JP2016031260A - Load drive circuit abnormality information notification apparatus and abnormality diagnosis apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load drive circuit abnormality information notification apparatus and an abnormality diagnosis apparatus capable of performing preliminary diagnostic processing of an abnormality diagnosis circuit and abnormality diagnostic processing of a load drive circuit.SOLUTION: When a first switching circuit 12 switches a voltage to a second reference voltage and outputs the second reference voltage to a comparator 14 as a first input voltage and a second switching circuit 13 switches a voltage to first and second threshold voltages and outputs the first and second threshold voltages to the comparator 14 as a second input voltage, a circuit 17 notifies a microcomputer 5 of an operation performed by the comparator 14 and operations performed by the first switching circuit, the second switching circuit, and the comparator 14 are preliminarily diagnosed. If it is determined that the operations are normal, the circuit 17 notifies the microcomputer 5 of information indicating whether an abnormality occurs on the basis of a comparison result of the comparator 14 to correspond to each of on and off drive control signals of a load 4 when the first switching circuit switches a voltage to a first reference voltage or a proportional voltage thereof and outputs the first reference voltage or the proportional voltage thereof to the comparator 14 as the first input voltage and the second switching circuit 13 switches a voltage to the first and second threshold voltages and outputs the first and second threshold voltages to the comparator 14 as the second input voltage.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an abnormality information notification device and an abnormality diagnosis device for detecting connection abnormality of a load drive circuit.

  The abnormality diagnosis device is configured, for example, in an electronic control unit (ECU) of the fuel injection control device. For example, an electromagnetic coil of a solenoid as a load may cause an abnormality such as a load open due to disconnection, a short circuit to a ground line, or a short circuit to a power supply line depending on some unexpected event. For this reason, the electronic control unit has a function of detecting an abnormality (see, for example, Patent Document 1).

  The technique described in Patent Document 1 includes an index voltage output circuit that outputs an index voltage that is an intermediate voltage between a power supply voltage and a ground voltage to the output terminal of the driver IC, a reference voltage generation circuit that generates a reference voltage, A disconnection detection circuit comprising a window comparator that compares the divided voltage of the output terminal voltage with a reference voltage and outputs a disconnection detection signal is provided, thereby detecting disconnection of the electromagnetic coil.

JP 2008-11347 A

  According to the technique described in Patent Document 1, since a window comparator is configured, at least two or more comparators are required to configure the abnormality presence / absence determining means. This undesirably increases the circuit scale. In addition, when various abnormality diagnosis circuits such as a comparator are operating abnormally, it is impossible to obtain a normal diagnosis result.

  An object of the present invention is to provide a load drive that enables pre-diagnosis processing of various circuits used for abnormality diagnosis and abnormality diagnosis processing of a load drive circuit while reducing the circuit scale by using only one comparator. An object of the present invention is to provide a circuit abnormality information notification device and abnormality diagnosis device.

According to the first aspect of the present invention, a load drive that drives a load connected in series to the switch element and connected to the second power supply line in response to applying a drive control signal to the switch element connected to the first power supply line. It is intended for a circuit abnormality information notification device.
According to the first aspect of the present invention, the comparator compares the first input voltage applied to the first input terminal with the second input voltage applied to the second input terminal, and outputs a comparison result. The reference voltage generation circuit generates a first reference voltage and a second reference voltage.
The threshold voltage generation circuit generates first and second threshold voltages. At this time, the threshold voltage generation circuit generates first and second threshold voltages that satisfy a condition in which the second threshold voltage is lower than the second reference voltage and the first threshold voltage is higher than the second reference voltage.

  The first switching circuit switches and outputs the first and second reference voltages of the reference voltage generation circuit to the switching comparator as a first input voltage, and the second switching circuit switches the first and second threshold voltages of the threshold voltage generation circuit. Are switched and output as the second input voltage. When the switch element energizes the load, the first switching circuit switches the voltage input to the first power line or its proportional voltage to the comparator as the first input voltage, and when the switch element energizes the load. The first reference voltage of the reference voltage generation circuit is applied to the node between the load and the switch element, and the first switching circuit switches and outputs the applied voltage or its proportional voltage to the comparator as the first input voltage. The notification means is means for notifying information indicating the presence or absence of abnormality based on the switching state of the first switching circuit, the switching state of the second switching circuit, and the comparison result of the comparator.

  When the switch element is energized to turn on the load, the first switching circuit switches and outputs the voltage input to the first power line connected through the switch element or its proportional voltage to the comparator as the first input voltage. The reference voltage generation circuit applies the first reference voltage to the node between the load and the switch element when the load is turned off by the first switching circuit, and the first switching circuit switches the applied voltage or its proportional voltage to the comparator as the first input voltage. In response to the output, the notification means notifies information for detecting an abnormality.

  In a state where the first switching circuit switches and outputs the second reference voltage to the comparator as the first input voltage and the second switching circuit switches and outputs the first and second threshold voltages to the comparator as the second input voltage. When the notifying means notifies the operation of the comparator, the operations of the first switching circuit, the second switching circuit, and the comparator are diagnosed in advance.

  At the time of this diagnosis on the condition that the pre-diagnosis result of the operation of the first switching circuit, the second switching circuit, and the comparator is determined to be normal, the first switching circuit is the first reference voltage or a proportion thereof. The notification means drives the load while the voltage is switched and output to the comparator as the first input voltage and the second switching circuit is switching and outputting the first and second threshold voltages to the comparator as the second input voltage. Information indicating the presence / absence of abnormality is notified based on the comparison result of the comparator corresponding to each of the on / off drive control signals of the drive control signal to be performed. Then, the presence or absence of abnormality can be determined outside. As a result, it can be configured using only one comparator, and the circuit scale can be reduced. In addition, it is possible to perform pre-diagnosis processing of various circuits used for abnormality diagnosis and abnormality diagnosis processing of the load drive circuit.

Electrical configuration diagram of an abnormality diagnosis device for a load drive circuit schematically showing the first embodiment Circuit configuration diagram schematically showing the inside of the buffer amplifier (A) is an electrical configuration diagram schematically showing an internal configuration example of the determination circuit, (b) is a table schematically showing an example of the signal state of each node of the determination circuit and an abnormality determination content of the determination means. Timing chart showing the details of the pre-diagnosis process (when normal) Flow chart conceptually showing the flow of operation of the abnormality diagnosis device (A) (b) is a timing chart schematically showing the contents of the pre-diagnosis process (at the time of abnormality) Timing chart schematically showing the contents of this diagnostic process (High-side drive: Normally when the load is turned off) Signal status of each node during this diagnostic process ((a) normal, (b) power supply short circuit, (c) ground short circuit) Timing chart schematically showing the contents of this diagnosis process (High-side drive: Normally when the load is energized) Timing chart schematically showing the contents of this diagnosis process (High-side drive: Normally when the load is energized) Signal status of each node during this diagnostic process ((a) Normal, (b) Open error, (c) Ground short circuit) Timing chart schematically showing signal state of each node in mask period Electrical configuration diagram of an abnormality diagnosis device for a load drive circuit schematically showing a second embodiment Table schematically showing signal status of each node of determination circuit and abnormality determination example of determination means Timing chart schematically showing the contents of this diagnosis process (low-side drive: usually when the load is turned off) Timing chart schematically showing the contents of this diagnostic process (low-side drive: normally when the load is energized) Timing chart schematically showing the contents of this diagnostic process (low-side drive: normally when the load is energized) Timing chart schematically showing signal state of each node in mask period

  Hereinafter, some embodiments of an abnormality information notification device and an abnormality diagnosis device for a load drive circuit will be described. In the following embodiments, portions having the same function or similar functions between the embodiments are denoted by the same reference numerals and description thereof is omitted.

(First embodiment)
1 to 12 show a first embodiment. FIG. 1 schematically shows an electrical configuration of an abnormality diagnosis device for a load drive circuit. The load drive circuit 1 is provided, for example, in an electronic control unit (ECU) mounted on a vehicle (not shown). A battery voltage VB is supplied to the vehicle from a battery (not shown) between a power terminal 2 as a power line and a ground 3 as another power line. The load drive circuit 1 drives and controls the load 4 according to the driving state of the vehicle using the battery voltage VB and the power supply voltage Vcc generated based on the voltage VB.

  The load driving circuit 1 is configured by connecting a microcomputer (hereinafter referred to as a microcomputer: equivalent to a judging means) 5, a gate driver 6, and a switch element 7, and a load 4 by a battery voltage VB supplied to the switch element 7. High side drive. The load 4 is an inductive load such as a solenoid or an electromagnetic coil of an injector, but the type of load is not limited. Although FIG. 1 shows an example of high-side driving, the present invention can be similarly applied to low-side driving as will be described later.

  The microcomputer 5 generates a load driving command signal (PWM signal) and outputs it to the gate driver 6. The gate driver 6 applies a drive control signal (on / off drive control signal) to the switch element 7 in response to a command signal input from the microcomputer 5. The switch element 7 is composed of, for example, a P-channel MOSFET, and is turned off when the drive control signal is “H”, and turned on when the drive control signal is “L”. Energize / disconnect the load 4. The power source terminal 2 of the battery voltage VB is connected to the source of the MOSFET, and the load 4 is connected between the drain of the MOSFET and the ground 3.

  An integrated circuit device 8 is connected to the load driving circuit 1. The integrated circuit device 8 operates as an abnormality information notification device, and constitutes the abnormality diagnosis device 9 of the load drive circuit 1 together with the microcomputer 5. The abnormality diagnosis device 9 includes a reference voltage generation circuit 10, a threshold voltage generation circuit 11, a first switching circuit 12, a second switching circuit 13, a comparator 14, a clock generation circuit 15, a latch circuit 16, a circuit 17, a controller 18, 19 and the microcomputer 5 described above are connected.

  The reference voltage generation circuit 10 includes a first reference voltage generation circuit 20 and a second reference voltage generation circuit 21. The first reference voltage generation circuit 20 generates the first reference voltage Vref1, and is composed of, for example, a resistance voltage dividing circuit, and outputs a stabilized reference voltage of about 2.5V, for example. The second reference voltage generation circuit 21 generates the second reference voltage Vref2, and is composed of, for example, a resistance voltage dividing circuit, and outputs a stabilized reference voltage of, for example, about 0.8 to 1.0V. The second reference voltage Vref2 of the second reference voltage generation circuit 21 is output to the first switching circuit 12.

  The threshold voltage generation circuit 11 includes voltage dividing resistors R1 to R3. These voltage dividing resistors R1 to R3 are connected in series between the supply node of the power supply voltage Vcc and the ground node and divide the power supply voltage Vcc at a predetermined ratio. The threshold voltage generation circuit 11 outputs the first threshold voltage Vth1 from the common connection node of the resistors R1 and R2, and outputs the second threshold voltage Vth2 (<Vth1) from the common connection node of the resistors R2 and R3. The second threshold voltage Vth2 is set in advance lower than the second reference voltage Vref2. The first threshold voltage Vth1 is set higher than the second reference voltage Vref2.

  The integrated circuit device 8 also includes a buffer amplifier 22 that outputs the first reference voltage Vref1 of the first reference voltage generation circuit 20 as a buffer. FIG. 2 shows a configuration example of the buffer amplifier 22. The buffer amplifier 22 has one input and two outputs, and has a configuration of high input impedance-low output impedance. The buffer amplifier 22 includes a voltage follower circuit 23 of an operational amplifier OP1 that operates by a power supply voltage Vcc in the first stage. The voltage follower circuit 23 receives the first reference voltage Vref1, and the subsequent circuit of the voltage follower circuit 23 uses the first output Vref11 and the second output Vref12 that are the same as or proportional to the first reference voltage Vref1 as the output of the buffer amplifier 22. To do. Thereby, even if an abnormality occurs in the subsequent circuit of the voltage follower circuit 23, the influence on the preceding circuit can be prevented.

  A current source 24, a diode-connected NMOS transistor 25, and a forward diode 26 are connected in series between the input node of the battery voltage VB and the output node of the voltage follower circuit 23. The gate of the output NMOS transistor 27 is connected to a common connection node between the current source 24 and the transistor 25. The drain of the transistor 27 is connected to the supply node of the battery voltage VB, and a resistor 28, a diode 29, and resistors 30, 31 are connected in series between the source of the transistor and the ground. Between the gate and source of the NMOS transistor 27, the drain gate of the NMOS transistor 32 is connected, and the source of the NMOS transistor 32 is connected to a common connection node between the resistor 28 and the anode of the diode 29. As a result, the NMOS transistor 27 is short-circuit protected.

  As shown in FIG. 1, the first output Vref11 of the buffer amplifier 22 is output to the common connection node N1 between the switch element 7 and the load 4 through the output terminal O1 of the integrated circuit device 2. The second output Vref12 of the buffer amplifier 22 is input to the first switching circuit 12. The first switching circuit 12 includes two sets of analog switches SW1 and SW2 for power interruption that are configured by combining, for example, a MOS transistor and a NOT gate. The first switching circuit 12 receives the second output Vref12 of the buffer amplifier 22 and the second reference of the second reference voltage generation circuit 21 in accordance with control signals φ1 and φ2 (on / off control signals) supplied from the circuit 17 through the controller 19. The voltage Vref2 is switched, and the selected reference voltage is switched and output to the first input terminal (non-inverting input terminal) of the comparator 14 as the first input voltage Vinp.

  The threshold voltage generation circuit 11 outputs the first threshold voltage Vth1 and the second threshold voltage Vth2 to the second switching circuit 13. The second switching circuit 13 includes, for example, two sets of analog switches SW3 and SW4 configured by combining MOS transistors and NOT gates. The second switching circuit 13 includes a first threshold voltage Vth1 and a second threshold voltage Vth2 generated by the threshold voltage generation circuit 11 in response to control signals φ3 and φ4 (on / off control signals) supplied from the circuit 17 through the controller 18. Are selectively output to the second input terminal (inverted input terminal) of the comparator 14 as the second input voltage Vinn.

  The comparator 14 compares the voltages applied to the first and second input terminals and outputs the voltage to the latch circuit 16 as a digital level. The clock generation circuit 15 generates a clock signal CLK of 40 [MHz], for example, and outputs the clock signal CLK to a configuration including the latch circuit 16, the circuit 17, and the controllers 18 and 19. The latch circuit 16 is composed of, for example, a D flip-flop, holds data and outputs Q according to the clock signal CLK supplied from the clock generation circuit 15.

  The Q output of the latch circuit 16 is given to the circuit 17. The gate driver 6 applies a drive control signal (on / off drive control signal) to the switch element 7 in response to a command signal input from the microcomputer 5, and this drive control signal is also input to the circuit 17 through the input terminal IN1. . The circuit 17 shows a form in which a drive control signal is input from the gate driver 6, but may be applied to a form in which an on / off command signal output from the microcomputer 5 is input as a drive control signal. The circuit 17 notifies the microcomputer 5 of data (information) indicating the presence / absence of abnormality according to the contents of the Q output of the latch circuit 16, and the circuit 17 is controlled by the controllers 18 and 19 as necessary. 12 and 13 are switched. The microcomputer 5 performs fail-safe processing (for example, immediately outputs an off command signal to the gate driver 6 and stops the load drive control) when information indicating that an abnormality exists is notified from the circuit 17.

  FIG. 3A shows a configuration example of the circuit 17. The circuit 17 includes a controller 40, latch circuits 41 and 42, a communication interface circuit 43, and a NOT gate 44. The latch circuits 41 and 42 are configured by D flip-flops, for example. The communication interface circuit 43 is configured using, for example, an SPI (Serial Peripheral Interface) bus.

  The Q output of the latch circuit 16 is input to the D terminal of one latch circuit 41 and is also input to the D terminal of the other latch circuit 42 via the NOT gate 44. Accordingly, the Q output of the latch circuit 16 is complementarily input to the D inputs of the one and other latch circuits 41 and 42.

  The controller 40 in the circuit 17 receives the clock signal CLK from the clock generation circuit 15 and the drive control signal from the gate driver 6. The controller 40 outputs control signals φ5 and φ6 to the clock terminals of one and the other latch circuits 41 and 42 in accordance with these input signals. The control signals φ5 and φ6 are complementary signals, and the Q outputs of the latch circuits 41 and 42 are input to the communication interface circuit 43. The communication interface circuit 43 outputs the outputs of the latch circuits 41 and 42. The output result of the circuit 17 is output to the microcomputer 5 by serial communication.

  The operation of the above configuration will be described. First, in order to facilitate understanding, a basic operation of the buffer amplifier 22 will be described. For example, when the ignition switch is turned on, the battery voltage VB is input to the ECU. When power is turned on, power supply voltages VB and Vcc are supplied to each circuit. When the microcomputer 5 outputs an off command signal to the gate driver 6, the gate driver 6 applies an off drive control signal (“H”) to the switch element 7. Then, the first output Vref11 of the buffer amplifier 22 is given to the common connection node N1 between the switch element 7 and the load 4.

  When the threshold voltages Vt1 of the transistors 25 and 27 in the buffer amplifier 22 shown in FIG. 2 are configured to coincide with each other, and the voltage drop due to the resistor 28 becomes a substantially negligible voltage, the buffer amplifier 22 outputs the first output Vref11. , A voltage substantially equal to the first reference voltage Vref1 is output. The first reference voltage Vref1 is lower than the battery voltage VB and higher than the ground voltage, and the first output Vref11 is the same.

  When the resistance value ratio between the resistors 30 and 31 is set to 2: 1, the buffer amplifier 22 uses, for example, one third of the voltage Vref11 / 3 of the first output Vref11 as the first reference voltage Vref1. Output as 2-output Vref12. The second output Vref12 of the buffer amplifier 22 is set in advance to a voltage lower than the first threshold voltage Vth1 output from the threshold voltage generation circuit 11 and higher than the second threshold voltage Vth2. The above-described resistance value ratio is set to 2: 1. However, if this voltage condition is satisfied, the resistance value ratio is not limited to this and can be changed as appropriate. If the switch element 7 is off, the buffer amplifier 22 outputs the same voltage as or proportional to the first reference voltage Vref1 output from the first reference voltage generation circuit 20 as the first output Vref11 and the second output Vref12. .

  On the other hand, when the microcomputer 5 outputs an ON command signal to the gate driver 6, the gate driver 6 applies an ON drive control signal (“L”) to the switch element 7. Then, a voltage close to the battery voltage VB is applied to the common connection node N1 between the switch element 7 and the load 4, and this battery voltage VB is input from the output side of the buffer amplifier 22 through the output terminal O1 of the integrated circuit device 8. Will be. In this case, the battery voltage VB is applied to the resistors 30 and 31 by the backflow preventing action of the diode 29 shown in FIG. Therefore, the buffer amplifier 22 outputs a voltage that is approximately one third of the battery voltage VB as the second output Vref12. In this way, the buffer amplifier 22 operates.

  FIG. 4 schematically shows a flowchart of a pre-diagnosis process (self-diagnosis process) when the power is turned on and an abnormality determination process when the load is driven. FIG. 5 schematically shows a timing chart so that the overall operation flow after power-on can be easily understood.

  For example, when an ignition switch (not shown) is turned on, the battery voltage VB is input to the load driving circuit 1 or the like (the integrated circuit device 8). The load driving circuit 1 or the like (the integrated circuit device 8) detects the increase in the input voltage of the battery voltage VB, and the controller 19 sets the control signals φ1 and φ2 to the “L” and “H” levels, respectively, of the first switching circuit 12. Output to switches SW1 and SW2. Further, the controller 18 complementarily outputs “H” and “L” to the switches SW3 and SW4 of the second switching circuit 13 in synchronization with the generation timing of the clock signal CLK (T1 in FIG. 4). period).

  For example, during the period (φ1, φ2) = (“L”, “H”), (φ3, φ4) = (“H”, “L”) (period T1a), the first input terminal of the comparator 14 is connected. The second reference voltage Vref2 is input as the first input voltage Vinp, and the first threshold voltage Vth1 is input as the second input voltage Vinn to the second input terminal of the comparator 14.

  In this state, when the clock generation circuit 15 synchronously outputs the pulse of the clock signal CLK to the latch circuit 16, the latch circuit 16 holds the D input at the pulse input timing of the clock signal CLK and outputs the held data to the circuit 17. Is done. Here, the second reference voltage Vref2 generated by the second reference voltage generation circuit 21 is set lower than the first threshold voltage Vth1.

  Therefore, when the second switching circuit 13 selectively switches and outputs the first threshold voltage Vth1 as the second input voltage Vinn to the comparator 14, the comparator 14, the first switching circuit 12, and the second switching circuit 13 operate normally. If so, the Q output of the latch circuit 16 becomes “L”. However, if the above circuit is not operating normally, the Q output becomes “H”.

  After that, during the period of (φ1, φ2) = (“L”, “H”), (φ3, φ4) = (“L”, “H”) (period T1b), the second input of the comparator 14 The second threshold voltage Vth2 is input to the terminal as the second input voltage Vinn.

  In this state, when the clock generation circuit 15 synchronously outputs the pulse of the clock signal CLK to the latch circuit 16, the latch circuit 16 holds the D input at the pulse input timing of the clock signal CLK and outputs it to the circuit 17. Here, the second reference voltage Vref2 generated by the second reference voltage generation circuit 21 is set higher than the second threshold voltage Vth2. Therefore, if the comparator 14, the first switching circuit 12, and the second switching circuit 13 are operating normally, the Q output of the latch circuit 16 becomes “H” (see the period T1b in FIG. 4; S1 in FIG. 5). However, if the above circuit is not operating normally, the Q output becomes “L”.

  Similarly, in the subsequent periods (φ1, φ2) = (“L”, “H”), (φ3, φ4) = (“H”, “L”), the circuit described above may operate normally. For example, the Q output of the latch circuit 16 becomes “L” (see the period T1c in FIG. 4; S1 in FIG. 5).

  Conversely, when these conditions are not satisfied, as shown in FIG. 6A, the Q output of the latch circuit 16 as described above exhibits an abnormal value ("L" level sustained). As shown in FIG. 6B, the Q output of the latch circuit 16 may indicate an abnormal value ("H" level sustained).

  Since the controller 40 of the circuit 17 switches the control signals φ5 and φ6 in a complementary manner in accordance with the clock input timing of the clock signal CLK and inputs the clock to the latch circuits 41 and 42, the Q output of the latch circuit 16 alternately changes in level. If so (for example, “L” “H” “L” within the period T1), the latch circuits 41 and 42 are at the same level (“L” “L” “L” or “H” “H” “H”). ) To the communication interface circuit 43.

  FIG. 3B schematically shows an outline of communication processing between the determination circuit and the microcomputer and normality / abnormality determination processing. In FIG. 3B, the relationship between the output O of the communication interface circuit 43 and the contents of normal / abnormal determination is stored in the internal memory (not shown) as a table. .

  When the communication interface circuit 43 continuously inputs the same level (“L” or “H”), the communication interface circuit 43 serially communicates with the microcomputer 5 using the signal “000” or “111” corresponding to this as an output O. This pre-diagnosis process is a process that the microcomputer 5 executes with the command signal turned off, and as shown in FIG.

  Conversely, as shown in FIG. 6A or 6B, when the Q output of the latch circuit 16 indicates an abnormal value, the latch circuits 41 and 42 output different levels to the communication interface circuit 43. As a result, the communication interface circuit 43 outputs a signal (for example, “010”, “101”) corresponding to this level, so that the microcomputer 5 is abnormal (for example, ground short circuit, power supply short circuit) in the pre-diagnosis process. It can be judged. In this case, the microcomputer 5 will not see the transition to the normal operation (S2 in FIG. 5).

  As a result of the pre-diagnosis process (self-diagnosis process), when the pre-diagnosis process is normally passed, the load driving circuit 1 drives the load 4 on and off (S3 to S9 in FIG. 5). During this time, abnormality detection and abnormality determination processing (main diagnosis processing) is performed (S4 and S7 in FIG. 5). This abnormality detection process (main diagnosis process) is a process that is performed in parallel when the load 4 is turned on or off.

  In the normal operation, when the load drive circuit 1 drives the load 4, when the drive control signal is OFF (YES in S3 in FIG. 5), the controller 40 of the circuit 17 causes the controller 19 to control the control signals (φ1, φ2). ) = (“H”, “L”). At this time, the second output Vref12 of the buffer amplifier 22 is output to the first input terminal of the comparator 14 through the first switching circuit 12.

  The switching timing of the second switching circuit 13 by the controller 19 is different from each other in the same cycle as the pulse generation cycle of the clock signal CLK of the clock generation circuit 15. Thus, the first and second threshold voltages Vth1 and Vth2 of the threshold voltage generation circuit 11 are supplied to the second input terminal of the comparator 14 in a complementary manner. The latch circuit 16 holds the D input at the generation timing of the clock signal CLK.

  Hereinafter, the normal control when the load 4 is turned off, the normal control when the load is turned on, and the control when an abnormality is detected are described separately. Normally, when the load 4 such as a solenoid or an energization coil of the injector is normally driven, the common connection node N1 between the switch element 7 and the load 4 is opened or disconnected depending on some external factor. 4 may be short-circuited, or the switch element 7 may be short-circuited to the ground. In preparation for such a case, an abnormality presence / absence determination unit and an abnormality determination unit are provided. The operation in this case will be described.

<Normal control when power is off>
An abnormality detection operation while the microcomputer 5 outputs an off command signal to the gate driver 6 and the gate driver 6 applies the off drive control signal to the switch element 7 to turn off the power supply to the load 4 will be described. As shown in FIG. 1, when the microcomputer 5 instructs the load 4 to turn off, the first output Vref11 of the buffer amplifier 22 is output to the common connection node N1 between the switch element 7 and the load 4.

  As shown in FIG. 7, the circuit 17 causes the controller 18 to send the control signals φ3 and φ4 to the control signal φ3 and φ4 at a timing different from the pulse generation timing of the clock signal CLK and in the same cycle as the clock signal CLK. Complementary output is performed at the H and L levels. The latch circuit 16 holds the D input and outputs Q in synchronization with the clock signal CLK.

  Here, the second output (proportional voltage) Vref12 (= Vref11 / 3 = Vref1 / 3) of the buffer amplifier 22 is set in advance so as to be lower than the first threshold voltage Vth1 and higher than the second threshold voltage Vth2. . Therefore, if the operation is normal, the control signals φ3 and φ4 are periodically switched, so that the Q output of the latch circuit 16 alternately changes to “H” and “L” according to the clock input timing (FIG. 7). (See period Ta1).

  At this time, the controller 40 of the circuit 17 switches the control signals φ5 and φ6 in a complementary manner in synchronization with the Q output of the latch circuit 16 according to the clock input timing of the clock signal CLK, and inputs the clock to the latch circuits 41 and 42. (Refer to FIG. 12 for the waveforms of φ5 and φ6). Therefore, “H” is always input to the two inputs of the communication interface circuit 43. Therefore, the communication interface circuit 43 outputs “1” continuously (for example, “11”) to the microcomputer 5.

  That is, if the circuit 17 detects that the Q output of the latch circuit 16 changes alternately, the microcomputer 5 is notified that it is operating normally. FIG. 8A schematically shows the control signals φ1, φ2, φ3, φ4 and signal changes of the nodes at this time in a timing chart.

<Control action when power supply short circuit is detected when power is off>
For example, a case where some abnormality occurs and the node N1 is short-circuited to the power supply terminal 2 of the battery voltage VB will be described. When the node N1 is short-circuited to the power supply terminal 2 of the power supply voltage VB, the voltage of the node N1 rises rapidly and substantially matches the battery voltage VB. This is due to a malfunction of the gate drive driver.

  In this case, a voltage VB / 3 that is one third of the battery voltage VB is input to the first input terminal of the comparator 14 through the resistors 30 and 31 in the buffer amplifier 22. As a result, the comparator 14 outputs a constant level (“H”) regardless of changes in the control signals φ3 and φ4. In this case, the controller 40 of the circuit 17 causes the control signals (φ5, φ6) = (“H”, “L”), (“L”, “H”) to be continuously input to the clocks of the latch circuits 41, 42. Is input to the communication interface circuit 43 as (Q1, Q2) = (“H” “L”). Since the communication interface circuit 43 notifies the microcomputer 5 of the signal “10” corresponding to this level, the microcomputer 5 can determine that there is an abnormality and determine that there is a power supply short circuit abnormality as shown in FIG. .

  That is, when the circuit 17 detects twice that the Q output of the latch circuit 16 is the constant level “H”, the microcomputer 5 is notified of the abnormality, and in particular, the power supply short-circuit abnormality is notified. Become. In this case, the microcomputer 5 can determine whether the node N1 or the node of the first or second output Vref11 or Vref12 of the buffer amplifier 22 is short-circuited. FIG. 8B schematically shows control signals φ1, φ2, φ3, φ4 and signal changes at each node when the power supply is short-circuited.

  When the circuit 17 detects that the Q output of the latch circuit 16 is “H” twice, the circuit 17 sets the control signals (φ3, φ4) = (“H”, “L”) (period Tb1 in FIG. 7). reference). This setting is for waiting for and detecting the timing when the voltage drops again in consideration of the malfunction of the gate drive process depending on some influence.

  If the voltage Vo or the like at the node N1 falls again as a result of waiting for this re-falling timing, the first input voltage Vinp at the first input terminal of the comparator 14 may become less than the first threshold voltage Vth1. In this case, the output of the comparator 14 becomes “L”, and the Q output becomes “L” at the next clock generation timing. In this case, since the input signal has returned to the normal state described above, the circuit 17 returns to the normal state described above. Control is performed (see period Tc1 in FIG. 7).

<Control action when a ground short circuit is detected when the load 4 is turned off>
For example, a case where some abnormality occurs and the node N1 is short-circuited to the ground when the load 4 is turned off will be described. When the node N1 is short-circuited to the ground, the voltage of the node N1 drops rapidly and substantially matches the ground potential. As this cause, it is considered that both terminals of the load 4 are short-circuited.

  In this case, the ground potential is input to the first input terminal of the comparator 14 through the resistors 30 and 31 in the buffer amplifier 22. As a result, the comparator 14 outputs a constant level (“L”) regardless of changes in the control signals φ3 and φ4. When the circuit 17 detects that the Q output of the latch circuit 16 is “L” at least a plurality of times (twice) as a constant level, the Q outputs of the latch circuits 41 and 42 in the circuit 17 are “L” and “H”. Output in order of level. Then, the communication interface circuit 43 of the circuit 17 outputs a signal “01” corresponding to this level to notify the microcomputer 5 that it is abnormal, and in particular, is notified that it is a ground short circuit abnormality. . In this case, the microcomputer 5 side can determine whether the node N1 or the node of the first or second output Vreff11 or Vref12 of the buffer amplifier 22 is short-circuited to the ground. FIG. 8C schematically shows each control signal φ1, φ2, φ3, φ4 and each signal change when the ground is short-circuited.

  When the circuit 17 detects “L” twice in succession, the controller 18 sets the control signal (φ3, φ4) = (“L”, “H”) (see the period Td1 in FIG. 7). This setting is for waiting and detecting the timing when the voltage at the node N1 rises again as described above. As a result of waiting, if the voltage at the energized node N1 rises again, the voltage at the node N1 rises again, and the first input voltage Vinp at the first input terminal of the comparator 14 may exceed the second threshold voltage Vth2 (FIG. Not shown). In this case, the output of the comparator 14 becomes “H”, the Q output becomes “H” at the next clock generation timing, and the circuit 17 performs the above-described normal control because the input signal has returned to the above-described normal state. (See period Ta1 or Tc1 in FIG. 7).

  Next, the control operation when energization is turned on will be described. As will be described below, the outputs of the control signals φ1 to φ4 in the abnormality determination process at the time of energization off and at the time of energization are different from each other. A mask period (see, for example, the period Tz in FIGS. 7, 9, and 10) for changing the signal output process is provided, which will be described later.

<Normal control operation when power is on>
An abnormality detection operation while the microcomputer 5 outputs an ON command signal to the gate driver 6 and the gate driver 6 turns on the switch element 7 to turn on the load 4 will be described. As shown in FIG. 9, when the microcomputer 5 outputs an ON command signal to the load 4, a voltage substantially close to the battery voltage VB is passed through the switch element 7 at the common connection node N <b> 1 between the switch element 7 and the load 4. Given. When an ON drive control signal is given from the gate driver 6, the circuit 17 fixes the control signals (φ3, φ4) = (“H”, “L”) by the controllers 40, 18.

  The second output Vref12 of the buffer amplifier 22 is set in advance so as to be lower than the first threshold voltage Vth1 and higher than the second threshold voltage Vth2. Accordingly, if the control signals φ3 and φ4 are “H” and “L”, respectively, a constant level “H” is output according to the input timing of the clock signal CLK if the operation is normal (FIG. 9). (See period Ta2, period Ta3 in FIG. 10). In the circuit 17, when the Q output of the latch circuit 16 is a constant level “H”, the latch circuit 41 outputs “H” to Q 1, and the latch circuit 42 outputs “L” to Q 2. “10” is continuously output, and the microcomputer 5 is notified of normal operation as shown in FIG. FIG. 11A schematically shows the control signals φ1, φ2, φ3, φ4 and signal changes of the nodes at this time in a timing chart.

<Control action when open (open) is detected when power is on>
For example, a case where some abnormality occurs and the energization node N1 to the load 4 is opened (opened) due to the influence of disconnection or the like will be described with reference to FIG. When the node N1 is opened, the output terminal O1 of the integrated circuit device 8 and the first and second outputs of the buffer amplifier 22 are disconnected. Then, the buffer amplifier 22 independently generates the voltage Vref1, and the voltage Vref1 / 3 that is one third of the voltage Vref1 is output to the first input terminal of the comparator 14 through the first switching circuit 12 (period of FIG. 9). (See Vinp in the second half of Ta2.) When the input voltage Vinp at the first input terminal becomes lower than the first threshold voltage Vth1, the comparator 14 outputs “L” to the D input of the latch circuit 16 (see timing Ta2a in FIG. 9). As a result, the latch circuit 16 outputs “L” as the Q output at the next clock input timing.

  When the latch circuit 16 outputs “L” as Q, the circuit 17 alternately sets the control signals (φ3, φ4) to “H” and “L” through the controllers 40 and 18 (see the period Tb2 in FIG. 9). This is performed to determine the type of abnormality.

  In the circuit 17, when the control signal (φ3, φ4) = (“L”, “H”), the second switching circuit 13 switches and outputs the second threshold voltage Vth2 to the second input terminal of the comparator. Then, the comparator 14 outputs “H” as a result of comparison with the second threshold voltage Vth2. Therefore, the latch circuit 16 outputs “H” as the Q output at the next clock input timing.

  In the circuit 17, when the control signal (φ3, φ4) = (“H”, “L”), the second switching circuit 13 switches and outputs the first threshold voltage Vth1 to the second input terminal of the comparator. Then, the comparator 14 outputs “L” as a result of comparison with the first threshold voltage Vth1. Therefore, the latch circuit 16 outputs “L” as the Q output at the next clock input timing. That is, when the input voltage of the first input terminal of the comparator 14 is kept substantially constant at Vref1 / 3 and is held between the first threshold voltage Vth1 and the second threshold voltage Vth2, the latch circuit 16 Q is output alternately between “H” and “L”.

  When the latch circuit 16 alternately outputs “H” and “L” with Q, the latch circuit 41 outputs “H” to Q1 and the latch circuit 42 outputs “H” to Q2 within the circuit 17, so that the communication interface circuit 43 outputs “11”, and as shown in FIG. 3B, the microcomputer 5 is notified of an open abnormality. On the microcomputer 5 side, it can be specified that the load connection node N1 is open according to the influence of disconnection or the like. If the microcomputer 5 determines that there is an abnormality, for example, it outputs an off command signal to the gate driver 6, and the gate driver 6 outputs an off drive control signal and stops the drive process to perform the fail safe process (timing in FIG. 9). See Tb2a). FIG. 11B schematically shows control signals φ1, φ2, φ3, φ4 and signal changes at each node when open detection is performed.

<Control action when ground short circuit is detected when power is on>
For example, a case where some abnormality occurs and the energization node N1 to the load 4 is short-circuited to the ground will be described with reference to FIG. When the node N1 is short-circuited to the ground, the voltage of the node N1 drops rapidly and substantially matches the ground potential. In this case, the ground potential is input to the first input terminal of the comparator 14 through the resistors 30 and 31 in the buffer amplifier 22. When the input voltage Vinp at the first input terminal of the comparator 14 becomes lower than the first threshold voltage Vth1, “L” is output to the D input of the latch circuit 16 (see timing Ta3a in FIG. 10). As a result, the latch circuit 16 outputs “L” as the Q output at the next clock input timing.

  When the latch circuit 16 outputs “L” as Q, the circuit 17 alternately sets the control signals (φ3, φ4) to “H” and “L” through the controllers 40 and 18 as described above (period Tb0 in FIG. 10). reference). This is performed to determine the type of abnormality.

  In the circuit 17, when the control signal (φ3, φ4) = (“L”, “H”), the second switching circuit 13 switches and outputs the second threshold voltage Vth2 to the second input terminal of the comparator. When the energization node N1 to the load 4 is short-circuited to the ground, the ground potential is input to the first input terminal of the comparator 14 (see Vinp at timing Tb3b in FIG. 10), and therefore the comparator 14 has the second threshold voltage Vth2. “L” is output as a result of the comparison. Therefore, the latch circuit 16 continuously outputs “L” as the Q output at the next clock input timing.

That is, when the input voltage Vinp at the first input terminal of the comparator 14 is kept substantially constant at the ground potential, the latch circuit 16 outputs Q at a constant level “L”.
When the latch circuit 16 outputs Q at a constant level “L” continuously, the latch circuit 41 outputs “L” to Q1 and the latch circuit 42 outputs “H” to Q2 in the circuit 17, so that the communication interface The circuit 43 outputs “01”, and as shown in FIG. 3B, the microcomputer 5 is notified of the ground short circuit abnormality. If the microcomputer 5 determines that there is an abnormality, for example, it outputs an off command signal to the gate driver 6, and the gate driver 6 outputs an off drive control signal and stops the drive process to perform the fail safe process (timing in FIG. 10). See Tb3c). FIG. 11 (c) schematically shows signal changes at each control signal φ1, φ2, φ3, φ4 and each node when a ground short circuit is detected.

  As described above, when the circuit 17 detects “L” as the Q output of the latch circuit 16 once, the circuit 17 sets the control signal (φ3, φ4) = (“L”, “H”). After such setting, the voltage at the node N1 may rise again, and the first input voltage Vinp at the first input terminal of the comparator 14 may return beyond the first threshold voltage Vth1 (not shown).

  In this case, the output of the comparator 14 becomes “H”, and the Q output becomes “H” at the next clock generation timing. On the other hand, even if the circuit 17 detects “H” only once, it will be determined as an open abnormality when it becomes “L” next time. In this case, the determination circuit detects “H” twice in succession. In this case, it is determined that the normal operation has been restored, and the above-described normal control is performed. The circuit 17 determines that it is operating normally by detecting “H” twice or more, and performs the above-described normal control. This can also be done.

Hereinafter, a mode for masking the switching period between energization on and energization off will be described.
<About mask period>
As described above, the circuit 17 serving as the notification means, the abnormality presence / absence determination means (the microcomputer 5 and the circuit 17) 100, and the abnormality determination means (the microcomputer 5) when the load 4 is turned on and when the load 4 is turned off. Although the circuit 17) 100 can be configured in common, there is a difference in abnormality presence / absence determination conditions and abnormality determination conditions (such as output of control signals φ1 to φ4) by the circuit 17 and the microcomputer 5. Therefore, as shown in FIG. 12, a mask period Tz is preferably provided in a switching period between energization on and energization off.

  When a drive control signal is transmitted from the gate driver 6 and the circuit 17 receives a timing at which the drive control signal changes from on to off or from off to on, the circuit 17 compares the comparison result of the comparator 14 for a predetermined time from the timing. The Q output of the latch circuit 16 is masked (S3a, S3b, S6a, S6b shown in FIG. 5). FIG. 12 schematically shows the operation of the circuit 17 when the drive control signal transitions from on to off. As shown in FIG. 12, when the microcomputer 5 gives an off command signal or an on command signal to the gate driver 6, the gate driver 6 outputs an off drive control signal or an on drive control signal to the switch element 7 as a drive control signal. .

  In a steady state in which the gate driver 6 drives the switch element 7 on (period Ton in FIG. 12) or in a steady state in which the gate driver 6 drives the switch element 7 off (period Toff in FIG. 12), the circuit 17 The controller 40 sequentially outputs control signals φ5 and φ6 in synchronization with the input timing of the signal CLK.

  While the controller 40 continues to output the control signals φ5 and φ6, the Q output of the latch circuit 16 becomes the Q1 output of the latch circuit 41, and the negative signal of the Q output of the latch circuit 16 becomes the Q2 output of the latch circuit 42. The Q1 output and Q2 output are input to the communication interface circuit 43. The communication interface circuit 43 outputs a signal corresponding to the Q1 output and Q2 output to the microcomputer 5.

  However, as described above, the abnormality determination condition differs between when the energization is on and when the energization is off. That is, for example, when the energization is on, the second switching circuit 13 normally performs the abnormality determination process by continuously switching and outputting the first threshold voltage Vth1 of the threshold voltage generation circuit 11, whereas when the energization is off, The second switching circuit 13 switches and outputs the first and second threshold voltages Vth1 and Vth2 of the threshold voltage generation circuit 11 to perform abnormality determination processing. For this reason, there is a possibility that an abnormality determination result may be mistaken in a transition period in which the switch element 7 is switched from on-drive to off-drive or a transition period in which the switch element 7 is switched from off-drive to on-drive. Therefore, in the present embodiment, a mask period Tz for abnormality determination processing is provided.

  When the microcomputer 5 gives an OFF command signal to the gate driver 6 in the ON state of the switch element 7, the gate driver 6 outputs an OFF drive control signal to the switch element 7. At this time, the gate driver 6 outputs an off drive control signal to the circuit 17. When receiving the off drive control signal (timing Tz1), the controller 40 of the circuit 17 stops outputting the control signals φ5 and φ6 for a predetermined period (for example, 1000 μsec: including transition period) Ty. This predetermined period Ty is set to a time sufficiently including the voltage fluctuation time of each node N1 when the load 4 is switched from energization on to energization off.

  For this reason, the controller 40 does not output the control signals φ5 and φ6 to the latch circuits 41 and 42, and the latch circuits 41 and 42 do not supply the output of the latch circuit 16 to the microcomputer 5. Although the output of the communication interface circuit 43 is given to the microcomputer 5, during the predetermined period Ty, the microcomputer 5 invalidates the output of the circuit 17 and does not use it for the abnormality determination process.

  On the other hand, when the gate driver 6 outputs an off drive control signal to the switch element 7, the switch element 7 is turned off. Then, the voltage at the node N1 decreases. At this time, the lowest voltage at which the node N1 decreases is the first reference voltage Vref1 of the first reference voltage generation circuit 20. At this time, the second output Vref12 of the buffer amplifier 22 drops to Vref1 / 3. Therefore, the input voltage Vinp at the first input terminal of the comparator 14 straddles the first threshold voltage Vth1 (see timing Tz2 in FIG. 12).

  The circuit 17 sets the control signals φ3 and φ4 to be alternately switched between “L” and “H” by the controllers 40 and 18 at a timing set in advance so as to exceed the timing Tz2 (see timing Tz3 in FIG. 12). . Then, the second switching circuit 13 switches and outputs the first threshold voltage Vth1 and the second threshold voltage Vth2 alternately.

  When a time Tx (<Ty) set shorter than the predetermined period Ty has elapsed since the OFF drive control signal was given, the circuit 17 outputs a clear signal / CLR to each of the latch circuits 41 and 42, and the OFF drive control signal When a predetermined period Ty elapses after the signal is given, the control signals φ5 and φ6 are sequentially re-output from the control signal φ6. Then, the Q2 output of the latch circuit 42 first becomes “H”, and then the Q1 output of the latch circuit 41 becomes “H”, and the communication interface circuit 43 sends the signal “11” when the normal energization is off to the microcomputer 5. Finally output. Thereby, misrecognition of the abnormality determination process can be prevented. Although the configuration from energization on to energization off is shown, the configuration from energization off to energization on is substantially the same, and the description thereof is omitted.

<Summary>
As described above, according to the present embodiment, the integrated circuit device 8 that notifies at least abnormality information can be configured using only one comparator, and the circuit scale can be reduced. In addition, it is possible to perform pre-diagnosis processing of various circuits used for abnormality diagnosis and abnormality diagnosis processing of the load drive circuit.

  Further, when the circuit 17 receives the timing at which the drive control signal changes from on to off or from off to on, the circuit 17 masks the comparison result of the comparator 14 for a predetermined period Ty from the timing. Information notification of the presence / absence of abnormality based on the comparison result of the comparator 14 is invalidated, and it is possible to prevent an erroneous determination of abnormality when the drive control signal changes from on to off and from off to on.

  When the load 4 is turned off, the reference voltage generation circuit 10 applies the first reference voltage Vref1 to the node N1 through the buffer amplifier 22, and the first switching circuit 12 applies the proportional voltage Vref12 of the first reference voltage to the comparator 14. The second switching circuit switches the first and second threshold voltages Vth1 and Vth2 of the threshold voltage generation circuit 11 to the second input terminal of the switching comparator 14 while switching and outputting the first input voltage to the first input terminal. When the second switching circuit 13 switches and outputs the first and second threshold voltages Vth1 and Vth2 of the threshold voltage generation circuit 11, the circuit 17 is normal if the comparison result of the comparator 14 changes alternately. Is notified, and when the comparison result of the comparator 14 does not change alternately and is at a certain level, information indicating that there is an abnormality is notified. Therefore, the presence or absence of abnormality can be notified, and the presence or absence of abnormality can be determined on the microcomputer 5 side.

  At this time, the circuit 17 is connected to the switch element 7 and the load on the condition that the comparison result of the comparator 14 is the same level corresponding to the applied voltage of the power supply line (for example, the power supply terminal 2 and the ground 3) when the comparison result is a constant level. Since the information indicating that the common connection node N1 with the power supply line 4 is short-circuited to the corresponding power supply line (power supply terminal 2, ground 3) is notified, the microcomputer 5 side can determine the type of the abnormality.

  When the load 4 is turned on, the first switching circuit 12 switches and outputs the proportional voltage VB / 3 of the battery voltage VB applied to the power supply terminal 2 to the first input terminal of the comparator 14 as the first input voltage. The second switching circuit 13 switches the first and second threshold voltages Vth1 and Vth2 of the threshold voltage generating circuit 11, and switches and outputs the second input voltage to the second input terminal of the comparator 14. At this time, the circuit 17 notifies information indicating that it is normal when the comparison result of the comparator 14 is a constant level “H” on the applied potential side of the battery voltage VB applied to the power supply terminal 2, and otherwise it is abnormal. Notify the information that it is. For this reason, the presence or absence of this abnormality can be determined on the microcomputer 5 side.

  When the comparison result of the comparator 14 changes alternately when the second switching circuit 13 switches and outputs the first and second threshold voltages Vth1 and Vth2 as the second input voltage of the comparator 14, the circuit 17 Information indicating that the common connection node N1 or the like of the load 4 is open is notified, and if the comparison result of the comparator 14 is a constant level “L” on the ground 3 side, information indicating that the ground is short-circuited is notified. Therefore, the type of abnormality can be determined on the microcomputer 5 side.

(Second Embodiment)
13 to 18 show a second embodiment. Although 1st Embodiment showed the example applied to the high side drive, 2nd Embodiment shows the example applied to the low side drive. The same parts as those in the previous embodiment are denoted by the same reference numerals and the description thereof is omitted. As shown in FIG. 13, the load 4 and the switch element 107 are connected in series between the supply terminal of the battery voltage VB and the ground. The switch element 107 is configured by, for example, an N channel type MOS transistor. The output of the buffer amplifier 22 is given to the common connection node N101 between the load 4 and the switch element 107. Other configurations are almost the same as those in the above-described embodiment, but the abnormality determination processing content on the microcomputer 5 side is stored in the memory in the microcomputer 5 as shown in FIG.

  The operation of the above configuration will be described below. Since the pre-diagnosis process is the same as that of the first embodiment, the description thereof is omitted. FIG. 15 schematically shows normal control when power is turned off and control processing when an abnormality occurs.

<Normal control when power is off>
An abnormality detection operation while the microcomputer 5 outputs an off command signal to the gate driver 6 and the gate driver 6 drives the switch element 107 off and turns off the load 4 will be described. As shown in FIG. 15, when the microcomputer 5 instructs to turn off the power supply to the load 4, the first output of the first reference voltage Vref1 is supplied to the common connection node N101 between the switch element 107 and the load 4 through the buffer amplifier 22. Vref11 is output.

  In the circuit 17, the controller 18 switches and outputs the control signals φ 3 and φ 4 in a complementary manner at a timing different from the pulse generation timing of the clock signal CLK and at the same cycle as the cycle of the clock signal CLK. The latch circuit 16 holds the D input and outputs Q in synchronization with the clock signal CLK.

  The second output Vref12 of the first reference voltage Vref1 is set in advance so as to be lower than the first threshold voltage Vth1 and higher than the second threshold voltage Vth2. Therefore, if the operation is normal, the control signals φ3 and φ4 are switched over time, so that the Q output of the latch circuit alternately changes to “H” and “L” according to the clock input timing (FIG. 15). (See period Ta4). When the circuit 17 detects that the Q output of the latch circuit 16 changes alternately, the communication interface circuit 43 continuously outputs the signal “0” or “1” corresponding thereto, so that the microcomputer 5 operates normally. Can be determined.

<Control action when ground short circuit is detected when power is off>
For example, a case where some abnormality occurs and the energization node N101 to the load 4 is short-circuited to the ground will be described. When the node N101 is short-circuited to the ground, the voltage at the node N101 drops rapidly and substantially matches the ground potential. In this case, the ground potential is input to the first input terminal of the comparator 14 through the resistors 30 and 31 in the buffer amplifier 22. As a result, the comparator 14 outputs a constant level (“L”) regardless of changes in the control signals φ3 and φ4, and the latch circuit 16 outputs Q of “L” (see period Tb4 in FIG. 15).

  When the latch circuit 16 outputs a certain level “L” as Q, the latch circuit 41 outputs “L” as Q1 and the latch circuit 42 outputs “H” as Q2 within the circuit 17, so that the communication interface circuit 43 “01” is output, and as shown in FIG. 14, the microcomputer 5 is notified of a ground short circuit abnormality. The microcomputer 5 can specify that the first or second output Vref11 or Vref12 of the node N101 or the buffer amplifier 22 is short-circuited to the ground.

  The circuit 17 sets the control signal (φ3, φ4) = (“L”, “H”) when “L” is continuously detected twice for the Q output of the latch circuit 16. This setting is a setting for waiting when, for example, some malfunction during gate driving occurs, and is provided for waiting and detecting the timing when the output voltage Vo rises again. If the voltage at the node N101 rises again as a result of waiting, the first input voltage Vinp at the first input terminal of the comparator 14 may exceed the second threshold voltage Vth2 (see timing Tb4a). In this case, the output of the comparator 14 becomes “H”, and the Q output becomes “H” at the next generation timing of the clock signal CLK. In this case, the circuit 17 notifies the microcomputer 5 of information that the normal operation has been restored. Then, the above-described normal control is performed (see period Tc4 in FIG. 15).

<Control action when power supply short circuit is detected when power is off>
For example, the case where some abnormality occurs and the energization node N101 to the load 4 is short-circuited to the supply terminal of the battery voltage VB will be described. When the node N101 is short-circuited to the supply terminal of the battery voltage VB, the voltage of the node N101 increases rapidly and substantially matches the battery voltage VB. In this case, a voltage VB / 3 that is one third of the battery voltage VB is input to the first input terminal of the comparator 14 through the resistors 30 and 31 in the buffer amplifier 22. As a result, the comparator 14 outputs a constant level (“H”) regardless of changes in the control signals φ3 and φ4.

  When the circuit 17 detects that the Q output of the latch circuit 16 is the constant level “H” twice or more, the latch circuit 41 outputs “H” to the Q1 in the circuit 17 and the latch circuit 42 “L”. Therefore, the communication interface circuit 43 outputs “10”, and as shown in FIG. 14, the microcomputer 5 is notified of a power supply short circuit abnormality (see period Td4 in FIG. 15). The microcomputer 5 can specify that the first or second output Vref11, Vref12 of the node N101 or the buffer amplifier 22 is short-circuited.

  When the circuit 17 detects “H” twice as the Q output of the latch circuit 16, the circuit 17 sets the control signals (φ3, φ4) = (“H”, “L”). This setting is for waiting and detecting the timing when the output voltage drops again. As a result of the standby, the voltage at the node N101 may drop again, and the first input voltage Vinp at the first input terminal of the comparator 14 may be less than the first threshold voltage Vth1 (not shown). In this case, the output of the comparator 14 becomes “L”, and the Q output of the latch circuit 16 becomes “L” at the next clock generation timing. In this case, the circuit 17 notifies the microcomputer 5 that the normal operation has been restored. The above-described normal control is performed.

Next, a control operation when energization is turned on will be described.
<Normal control operation when power is on>
The abnormality detection operation while the microcomputer 5 outputs an ON command signal to the gate driver 6 and the gate driver 6 controls the switch element 107 to be ON and the energization to the load 4 is ON will be described. As shown in FIG. 12, when the microcomputer 5 gives an ON command, a ground potential is supplied to the common connection node N <b> 101 between the switch element 107 and the load 4 through the switch element 107. When the ON drive control signal is given from the gate driver 6, the circuit 17 fixes the control signals (φ3, φ4) = (“L”, “H”) by the controllers 40 and 18.

  The second output Vref12 of the buffer amplifier 22 is set in advance so as to be lower than the first threshold voltage Vth1 and higher than the second threshold voltage Vth2. Accordingly, if the control signals φ3 and φ4 are “L” and “H”, respectively, a constant level “L” is output according to the input timing of the clock signal CLK if the operation is normal (FIG. 16). (See period Ta4). In the circuit 17, when the Q output of the latch circuit 16 is a certain level “L”, the latch circuit 41 outputs “L” to Q1, and the latch circuit 42 outputs “H” to Q2, so that the communication interface circuit 43 “01” is continuously output, and the microcomputer 5 is notified of normal operation as shown in FIG.

<Control action when open (open) is detected when power is on>
For example, a case where some abnormality occurs and the energization node N101 to the load 4 is opened (opened) due to the effect of disconnection or the like will be described. When the node N101 is opened, the output terminal O1 of the integrated circuit device 8 and the first and second outputs of the buffer amplifier 22 are disconnected. Then, the buffer amplifier 22 independently generates the voltage Vref1 and inputs the voltage Vref1 to the first input terminal of the comparator 14 through the first switching circuit 12 (see Vinp in the second half of the period Ta5 in FIG. 16).

  When the input voltage Vinp at the first input terminal becomes higher than the second threshold voltage Vth2, the comparator 14 outputs “H” to the D input of the latch circuit 16 (see timing Ta5a in FIG. 16). As a result, the latch circuit 16 outputs “H” as the Q output at the next clock input timing.

  When the latch circuit 16 outputs “H” as Q, the circuit 17 alternately sets the control signals (φ3, φ4) to “H” and “L” through the controllers 40 and 18 (see the period Tb5 in FIG. 16). This is performed to determine the type of abnormality.

  In the circuit 17, when the control signal (φ3, φ4) = (“H”, “L”), the second switching circuit 13 switches and outputs the first threshold voltage Vth1 to the second input terminal of the comparator. Then, the comparator 14 outputs “L” as a result of comparison with the first threshold voltage Vth1. Therefore, the latch circuit 16 outputs “L” as the Q output at the next clock input timing.

  In the circuit 17, when the control signal (φ3, φ4) = (“L”, “H”), the second switching circuit 13 switches and outputs the second threshold voltage Vth2 to the second input terminal of the comparator. Then, the comparator 14 outputs “H” as a result of comparison with the second threshold voltage Vth2. Therefore, the latch circuit 16 outputs “H” as the Q output at the next clock input timing. That is, when the input voltage of the first input terminal of the comparator 14 is kept substantially constant at Vref1 / 3 and is held between the first threshold voltage Vth1 and the second threshold voltage Vth2, the latch circuit 16 Q is output alternately between “H” and “L”.

  When the latch circuit 16 alternately outputs “L” and “H” with Q, the latch circuit 41 outputs “L” to Q1 and the latch circuit 42 outputs “L” to Q2 within the circuit 17, so that the communication interface circuit 43 outputs “00”, and as shown in FIG. 14, the microcomputer 5 is notified of an open abnormality. On the microcomputer 5 side, it can be specified that the load connection node N101 is open according to the influence of disconnection or the like. If the microcomputer 5 determines that there is an abnormality, for example, it outputs an off command signal to the gate driver 6, and the gate driver 6 outputs an off drive control signal and stops the drive process to perform the fail safe process (timing in FIG. 16). See Tb5a).

<Control action when power supply is short-circuited when energized>
For example, a case where some abnormality occurs and the power supply node N101 to the load 4 is short-circuited to the power source will be described. When the node N101 is short-circuited to the power supply, the voltage at the node N101 increases rapidly and substantially matches the battery voltage VB. In this case, a voltage VB / 3 that is one third of the battery voltage VB is input to the first input terminal of the comparator 14 through the resistors 30 and 31 in the buffer amplifier 22. When the input voltage Vinp at the first input terminal of the comparator 14 becomes higher than the second threshold voltage Vth2, “H” is output to the D input of the latch circuit 16 (see timing Ta6a in FIG. 17). As a result, the latch circuit 16 outputs “H” as the Q output at the next clock input timing.

  When the latch circuit 16 outputs “H” as Q, the circuit 17 alternately sets the control signals (φ3, φ4) to “H” and “L” through the controllers 40 and 18 as described above (period Tb0 in FIG. 17). reference). This is performed to determine the type of abnormality.

  In the circuit 17, when the control signal (φ3, φ4) = (“H”, “L”), the second switching circuit 13 switches and outputs the first threshold voltage Vth1 to the second input terminal of the comparator. When the power supply node N101 to the load 4 is short-circuited to the power source, the battery 14 is supplied with a voltage close to the battery voltage VB or VB (see Vinp at timing Tb6a in FIG. 17). “H” is output as a result of comparison with one threshold voltage Vth1. Therefore, the latch circuit 16 continuously outputs “H” as the Q output at the next clock input timing.

That is, when the input voltage Vinp at the first input terminal of the comparator 14 is kept substantially constant at the battery voltage VB, the latch circuit 16 continuously outputs Q at a constant level “H”.
When the latch circuit 16 outputs Q at a constant level “H” continuously, the latch circuit 41 outputs “H” Q1 and the latch circuit 42 outputs “L” Q2 within the circuit 17. The circuit 43 outputs “10”, and as shown in FIG. 14, the microcomputer 5 is notified of a power supply short circuit abnormality. If the microcomputer 5 determines that there is an abnormality, for example, it outputs an off command signal to the gate driver 6, and the gate driver 6 outputs an off drive control signal and stops the drive process (timing in FIG. 17). See Tb6c).

  As described above, when the circuit 17 detects “H” as the Q output of the latch circuit 16 once, the circuit 17 sets the control signals (φ3, φ4) = (“H”, “L”). After such a setting, the voltage at the node N101 may drop again, and the first input voltage Vinp at the first input terminal of the comparator 14 may return beyond the second threshold voltage Vth2 (not shown).

  In this case, the output of the comparator 14 becomes “L”, and the Q output becomes “L” at the next clock generation timing. On the contrary, even if the circuit 17 detects “L” only once, when it becomes “H” next time, it is notified that there is an open abnormality. In this case, the circuit 17 continues to “ When "L" is detected, it is determined that the normal operation is restored, and the above-described normal control is performed. That is, the circuit 17 determines that it is operating normally by detecting “L” twice or more, and performs the normal control described above. This can also be done.

  Also in this embodiment, the notification means 17, the abnormality presence / absence determination means 100, and the abnormality determination means 100 can be configured to be shared between when the load 4 is energized and when the load 4 is energized, but the circuit 17 and the microcomputer 5 Since there is a difference in the abnormality presence / absence determination condition and the abnormality determination condition (such as the output of the control signals φ1 to φ4), it is preferable to provide a mask period Tz as shown in FIG.

  For example, when the energization is on, the second switching circuit 13 normally performs the abnormality determination process by continuously switching and outputting the second threshold voltage Vth2 of the threshold voltage generation circuit 11, whereas when the energization is off, The two switching circuit 13 switches and outputs the first and second threshold voltages Vth1 and Vth2 of the threshold voltage generation circuit 11 to perform abnormality determination processing. For this reason, there is a possibility that an abnormality determination result may be mistaken in a transition period in which the switch element 107 is switched from on-drive to off-drive or a transition period in which the switch element 107 is switched from off-drive to on-drive. Therefore, in the present embodiment, a mask period Tz for abnormality determination processing is provided.

  When the microcomputer 5 gives an off command signal to the gate driver 6 while the switch element 107 is on, the gate driver 6 outputs an off drive control signal to the switch element 107. At this time, the gate driver 6 outputs an off drive control signal to the circuit 17. When receiving the off drive control signal (timing Tz1), the controller 40 of the circuit 17 stops outputting the control signals φ5 and φ6 for a predetermined period (for example, 1000 μsec: including transition period) Ty. The predetermined period Ty is set to a time sufficiently including the voltage fluctuation time of each node N1 when the load 4 is switched from energization on to energization off.

  For this reason, the controller 40 does not output the control signals φ5 and φ6 to the latch circuits 41 and 42, and the latch circuits 41 and 42 do not supply the output of the latch circuit 16 to the microcomputer 5. Although the output of the communication interface circuit 43 is given to the microcomputer 5, during the predetermined period Ty, the microcomputer 5 invalidates the output of the circuit 17 and does not use it for the abnormality determination process.

  On the other hand, when the gate driver 6 outputs an off drive control signal to the switch element 107, the switch element 107 is turned off. Then, the voltage of the node N101 increases. At this time, the highest voltage at which node N101 rises is battery voltage VB. At this time, the second output Vref12 of the buffer amplifier 22 rises to VB / 3. Therefore, the input voltage Vinp at the first input terminal of the comparator 14 straddles the second threshold voltage Vth2 (see timing Tz2 in FIG. 12).

  The circuit 17 sets the control signals φ3 and φ4 to be alternately switched between “L” and “H” by the controllers 40 and 18 at a timing set in advance so as to exceed the timing Tz2 (see timing Tz3 in FIG. 18). . Then, the second switching circuit 13 switches and outputs the second threshold voltage Vth2 and the first threshold voltage Vth1 alternately.

  When a time Tx (<Ty) set shorter than the predetermined period Ty has elapsed since the OFF drive control signal was given, the circuit 17 outputs a clear signal / CLR to each of the latch circuits 41 and 42, and the OFF drive control signal When a predetermined period Ty elapses after the signal is given, the control signals φ5 and φ6 are sequentially re-output from the control signal φ5. Then, the Q1 output of the latch circuit 41 first becomes “H”, and then the Q2 output of the latch circuit 42 becomes “H”, and the communication interface circuit 43 sends the signal “11” when the normal energization is off to the microcomputer 5. Finally output. Thereby, misrecognition of the abnormality determination process can be prevented.

As described above, even when the low-side drive is performed as in the present embodiment, the same operational effects as those of the above-described embodiment can be obtained.
In particular, when the load 4 is turned on, the second switching circuit 13 generates the threshold voltage while the first switching circuit 12 switches and outputs the ground potential of the ground 3 to the first input terminal of the comparator 14 as the first input voltage. The first and second threshold voltages Vth1 and Vth2 of the circuit 11 are switched and switched and output as a second input voltage to the second input terminal of the comparator 14. At this time, the circuit 17 notifies information indicating that it is normal when the comparison result of the comparator 14 is a constant level “L” on the ground potential side of the ground 3, and notifies information indicating that it is abnormal otherwise. To do. For this reason, the microcomputer 5 can determine the presence or absence of this abnormality.

  When the comparison result of the comparator 14 changes alternately when the second switching circuit 13 switches and outputs the first and second threshold voltages Vth1 and Vth2 as the second input voltage of the comparator 14, the circuit 17 Information indicating that the common connection node N1 or the like of the load 4 is open is notified, and if the comparison result of the comparator 14 is a constant level “H” on the battery voltage VB side on the power supply terminal 2 side, it indicates that the power supply is short-circuited. Notify information. For this reason, the microcomputer 5 can determine the type of this abnormality.

  In the drawings, 1 is a load drive circuit, 2 is a battery voltage power supply terminal (first power supply line, second power supply line), 3 is ground (second power supply line, first power supply line), 4 is a load, and 5 is a micro. Computer (judgment means), 7, 107 switch elements, 8 integrated circuit device (abnormal information notification device), 9 abnormal diagnosis device, 10 reference voltage generation circuit, 11 threshold voltage generation circuit, 12 first switch A circuit, 13 is a second switching circuit, 14 is a comparator, and 17 is a circuit (notification means).

Claims (7)

In response to applying a drive control signal to the switch element (7; 107) connected to the first power supply line (2; 3), the switch element is connected in series to the second power supply line (3; 2). Load driving circuit for driving the load (4)
A comparator (14) comprising a first input terminal and a second input terminal, for comparing a first input voltage applied to the first input terminal with a second input voltage applied to the second input terminal and outputting a comparison result; ,
A reference voltage generation circuit (10) for generating a first reference voltage (Vref1) and a second reference voltage (Vref2);
A circuit for generating first and second threshold voltages (Vth1, Vth2), wherein the second threshold voltage (Vth2) is lower than the second reference voltage (Vref2) and the first threshold voltage (Vth1) is the first threshold voltage (Vth1). A threshold voltage generation circuit (11) for generating first and second threshold voltages satisfying a condition higher than two reference voltages (Vref2);
A switching state of the first switching circuit (12) for switching and outputting the first and second reference voltages of the reference voltage generation circuit as a first input voltage to the comparator, and first and second threshold voltages of the threshold voltage generation circuit A switching state of the second switching circuit (13) that switches and outputs the comparator as a second input voltage, and a notification means (17) for notifying information indicating the presence or absence of abnormality based on the comparison result of the comparator; With
The notification means includes
When the switch element is energized to the load, the first switching circuit supplies the voltage input to the first power supply line (2; 3) connected through the switch element or the proportional voltage to the comparator. When the switch element outputs a switch as one input voltage and the switch element is turned off, the reference voltage generation circuit applies the first reference voltage (Vref1) to a node (N1; N101) between the load and the switch element. The first switching circuit notifies the comparator of the applied voltage or its proportional voltage as the first input voltage to notify the information for detecting an abnormality,
The first switching circuit switches and outputs the second reference voltage to the comparator as a first input voltage, and the second switching circuit switches and outputs the first and second threshold voltages to the comparator as a second input voltage. In this state, the operation of the first switching circuit, the second switching circuit, and the comparator is pre-diagnosed by notifying the operation of the comparator,
At the time of the main diagnosis on the condition that the pre-diagnosis result of the operation of the first switching circuit, the second switching circuit, and the comparator is determined to be normal, the first switching circuit is the first reference In the state where the voltage or its proportional voltage is switched and output to the comparator as the first input voltage and the second switching circuit is switching and outputting the first and second threshold voltages to the comparator as the second input voltage, An abnormality information notification device for a load drive circuit, wherein information indicating presence / absence of an abnormality is notified based on a comparison result of the comparator corresponding to each of the on / off drive control signals of the drive control signal for driving a load. In the load drive circuit abnormality information notification device according to claim 1,
The notification means includes
When a timing at which the drive control signal for driving the load changes from on to off or from off to on is masked for a predetermined period from the timing and based on the comparison result of the comparator during the predetermined period An abnormality information notifying device for a load driving circuit, wherein information notification of presence / absence of abnormality by the notifying means is invalidated. In the load drive circuit abnormality information notification device according to claim 1 or 2,
A proportional voltage (Vref12) of the first reference voltage is set between the first threshold voltage and the second threshold voltage;
When the load is turned off by the switch element,
The reference voltage generation circuit applies a first reference voltage (Vref1) to a node between the load and the switch element, and the first switching circuit supplies a proportional voltage of the first reference voltage to the comparator as the first input voltage. The second switching circuit switches the first and second threshold voltages of the threshold voltage generation circuit as a second input voltage to the comparator,
When the second switching circuit switches and outputs the first and second threshold voltages as the second input voltage of the comparator,
The notification means notifies information indicating that the comparator is normal if the comparison result of the comparator changes alternately, and indicates that the information is abnormal when the comparison result of the comparator does not change alternately and is at a constant level. A device for notifying abnormality information of a load driving circuit, characterized by: In the load drive circuit abnormality information notification device according to claim 3,
The notification means includes
Common connection between the switch element and the load, provided that the comparison result of the comparator is at a constant level and is at the same level corresponding to the applied voltage of the first power supply line or the second power supply line An abnormality information notification device for a load driving circuit, characterized in that a node notifies information corresponding to a short circuit to the corresponding first power supply line or second power supply line. In the load drive circuit abnormality information notification device according to claim 1 or 2,
A proportional voltage (Vref12) of the first reference voltage is set between the first threshold voltage and the second threshold voltage;
When the load is energized by the switch element,
While the first switching circuit switches and outputs the proportional voltage of the voltage input to the first power supply line or the second power supply line to the comparator as the first input voltage, the second switching circuit generates the threshold voltage. Switching the first and second threshold voltages of the circuit to the comparator as a second input voltage,
When the second switching circuit switches and outputs the first and second threshold voltages as the second input voltage of the comparator, the notifying means outputs a comparison result of the comparator on the applied potential side of the first power supply line. A load drive circuit abnormality information notification device that notifies that information is normal if it is at a certain level, and notifies information that it is abnormal otherwise. In the load drive circuit abnormality information notification device according to claim 5,
When the comparison result of the comparator changes alternately when the second switching circuit switches and outputs the first and second threshold voltages as the second input voltage of the comparator,
The notifying means notifies information indicating that a common connection node of the switch element and the load is open, and if the comparison result of the comparator is a constant level on the applied potential side of the second power supply line, An abnormality information notification device for a load driving circuit, which notifies information indicating that a short circuit has occurred in two power supply lines.   When the information is notified from the abnormality information notifying device (8) according to any one of claims 1 to 6, the apparatus includes a determination means (5) for determining presence / absence of abnormality based on the information. Abnormality diagnosis device.

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