JP2011069642A - Voltage detection circuit - Google Patents

Abstract

A voltage detection circuit that prevents erroneous detection due to noise is provided.
A second voltage V2 obtained by dividing a first voltage VDD input to a voltage terminal 12 is compared with a reference voltage Vref1, and a comparator 11 that outputs a comparison result is connected to the voltage terminal 12, and is While the switching circuit 14 that switches the voltage VDD is off, the latch circuit 15 that passes the signal S1 indicating the comparison result according to the logic value of the clock signal CLK, and between the voltage terminal 12 and the reference potential GND A voltage dividing circuit 12 that is connected and selects a voltage dividing ratio according to the output S3 of the latch circuit 15 and outputs a voltage obtained by dividing the first voltage VDD by the selected voltage dividing ratio to the comparator 11 as a second voltage V2. Are provided.
[Selection] Figure 1

Description

  The present invention relates to a voltage detection circuit.

  In a conventional voltage detection circuit, a CR filter including a capacitor and a resistor is connected to a voltage terminal in order to prevent erroneous detection due to noise or the like. In this voltage detection circuit, if the time constant of the CR filter is too small with respect to noise, the effect of suppressing the noise is reduced and there is a risk of erroneous detection. If it is too large, the response is delayed and the timing for detecting the voltage is delayed. There's a problem. In addition, since the area occupied by the capacitor is large, there is a problem that it is difficult to integrate the capacitor on a semiconductor chip.

  On the other hand, a power supply voltage detection circuit having hysteresis to prevent erroneous detection due to noise or the like is known (for example, see Patent Document 1).

  In this power supply voltage detection circuit, a power supply voltage detection circuit that compares a power supply voltage input to a power supply terminal with a reference voltage and outputs a detection signal; a control circuit that detects a time of the detection signal and outputs a set signal; A signal generation circuit that receives a set signal and outputs a reset signal, and a latch circuit that operates according to the set signal and the reset signal and outputs an initialization signal for an internal circuit.

  By performing the hysteresis control, the operation signal is not simultaneously input to the reset signal input terminal and the set signal input terminal of the latch circuit, thereby preventing erroneous detection of the latch circuit and chattering of the reset signal.

  However, this power supply voltage detection circuit has a problem that when the power supply voltage rises or falls at an arbitrary slew rate, the voltage detection operation cannot be performed correctly due to fluctuations in the power supply voltage, noise exceeding the hysteresis width, or the like.

JP 2000-165221 A

  The present invention provides a voltage detection circuit that prevents erroneous detection due to noise.

  The voltage detection circuit of one embodiment of the present invention compares a second voltage obtained by dividing the first voltage input to the voltage terminal with a reference voltage, and outputs a comparison result, and is connected to the voltage terminal. A latch circuit that passes a signal indicating the comparison result according to a logic value of a clock signal while the switching circuit that switches the first voltage is off, and is connected between the voltage terminal and a reference potential. A voltage dividing circuit that selects a voltage dividing ratio according to the output of the latch circuit and outputs a voltage obtained by dividing the first voltage by the selected voltage dividing ratio to the comparator as the second voltage. It is characterized by doing.

  According to the present invention, a voltage detection circuit that prevents erroneous detection due to noise can be obtained.

1 is a circuit diagram showing a voltage detection circuit according to Embodiment 1 of the present invention. The figure which shows the rise / fall characteristic of the voltage which concerns on Example 1 of this invention. The figure which shows the relationship between the voltage which concerns on Example 1 of this invention, and the output of a comparator. 1 is a circuit diagram showing a voltage conversion circuit according to Embodiment 1 of the present invention. 3 is a timing chart showing the operation of the voltage detection circuit according to the first embodiment of the present invention. The circuit diagram which shows the voltage detection circuit which concerns on Example 2 of this invention. 9 is a timing chart showing the operation of the voltage detection circuit according to the second embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  The voltage detection circuit according to this embodiment will be described with reference to FIGS. 1 is a circuit diagram showing a voltage detection circuit according to the present embodiment, FIG. 2 is a diagram showing a rising / falling characteristic of a voltage, FIG. 3 is a diagram showing a relationship between a voltage and an output of a comparator, and FIG. FIG. 5 is a timing chart showing the operation of the voltage detection circuit.

  As shown in FIG. 1, the voltage detection circuit 10 of the present embodiment includes a second voltage V2 obtained by dividing the power supply voltage (first voltage) VDD input to the voltage terminal 12 by the comparator 11 using the voltage dividing circuit 13; Compared with the reference voltage Vref1, the output signal (comparison result) S1 of the comparator 11 is set according to the logical value of the clock signal CLK gated by the drive signal VDR that drives the switching circuit 14 that switches the power supply voltage VDD. The latch circuit 15 is configured to pass or hold.

  The comparator 11 is a so-called current mirror type differential amplifier including, for example, a pair of first N channel MOS transistor and second N channel MOS transistor and a current mirror circuit having a first P channel MOS transistor and a second P channel MOS transistor. .

  In the comparator 11, the gate of the first N-channel MOS transistor is the inverting input terminal (−) to which the reference voltage Vref1 is input, and the gate of the second N-channel MOS transistor is the non-inverting input terminal (to which the second voltage V2 is input). +). A connection node between the drain of the first P-channel MOS transistor and the drain of the first N-channel MOS transistor is an output terminal.

  The comparator 11 outputs a high level output signal S1 to the output terminal when the second voltage V2 is higher than the reference voltage Vref1, and outputs a low level to the output terminal when the second voltage V2 is lower than the reference voltage Vref1. The signal S1 is output.

  The voltage terminal 12 is connected to an external power source (not shown). A voltage dividing circuit 13 and a switching circuit 14 are connected to the voltage terminal 12.

  FIG. 2 is a diagram showing rising and falling characteristics of the power supply voltage VDD. As shown in FIG. 2, for example, when the external power supply is powered on at time t1, the power supply voltage VDD rises according to a predetermined slew rate 21, reaches a predetermined voltage VH at time t2, and reaches a predetermined voltage at time t3. It is maintained at Vc, and the power supply voltage VDD falls according to a predetermined slew rate 22 at time t4, reaches a predetermined voltage VL lower than the voltage VH at time t5, and becomes zero at time t6.

  The rising slew rate 21 and the falling slew rate 22 are arbitrary, but are shown here as straight lines for convenience. The voltage Vc, the voltage VH, and the voltage VL are, for example, 50V, 35V, and 30V, respectively.

  The voltage dividing circuit 13 includes first to third resistors R1, R2, and R3 connected in series, and a switch 16, for example, an N-channel MOS transistor, connected in parallel to the third resistor R3.

  One end of the first resistor R1 is connected to the voltage terminal 12, and one end of the third resistor R3 is connected to the reference potential GND. A second voltage V2 is output from a connection node N1 between the first resistor R1 and the second resistor R2.

By turning on or off the switch 16, the first voltage division ratio R2 / (R1 + R2) or the second voltage division ratio (R2 + R3) / (R1 + R2 + R3) can be selected.
When the second voltage V2 when the switch 16 is on is V2on and the second voltage V2 when the switch 16 is off is V2off, V2on and V2off are respectively expressed by the following equations.

V2on = VDD × R2 / (R1 + R2) (1)
V2off = VDD × (R2 + R3) / (R1 + R2 + R3) (2)
The second voltage V2 referred to in this specification is a generic term for the second voltage V2on and the second voltage V2off.

  FIG. 3 is a diagram showing the relationship between the power supply voltage VDD and the output of the comparator 11. In the initial state, it is assumed that the switch 16 is in an off state and the power supply voltage VDD is zero.

  As shown in FIG. 3, when the power is turned on, the power supply voltage VDD rises from zero and reaches VH = Vref1 (R1 + R2 + R3) / (R2 + R3), the output signal S1 of the comparator 11 changes from Low to High. At this time, the switch 16 is turned on as will be described later. Thereafter, whenever the power supply voltage VDD is higher than the voltage VH, the output signal S1 of the comparator 11 continues to maintain the High level.

  Next, when the power supply voltage VDD falls from the predetermined voltage Vc and reaches VL = Vref1 (R1 + R2) / R2, the output signal S1 of the comparator 11 changes from High to Low. Thereafter, whenever the power supply voltage VDD is lower than the voltage VL, the output signal S1 of the comparator 11 maintains the low level.

  The voltage dividing circuit 13 and the comparator 11 constitute a comparison circuit having hysteresis with respect to the power supply voltage VDD.

  FIG. 4 is a circuit diagram showing the switching circuit 14. As shown in FIG. 4, the switching circuit 14 is, for example, a synchronous rectification type DC-DC converter. In the DC-DC converter, the output stage 30 is turned on / off by the drive signal VDR, and the on period of the output stage 30 is changed in accordance with changes in the load and the power supply voltage VDD.

  As a result, a DC voltage controlled by PWM (Pulse Width Modulation) is generated, and the DC voltage is smoothed and output to the internal circuit (not shown) as the third voltage V3. The internal circuit is a logic circuit driven with a low voltage, for example.

  The output stage 30 is a P-channel MOS transistor connected to the power supply voltage VDD, and is included in the IC. The diode 32 is connected between the output stage 30 and the reference potential GND, and is connected to the outside of the IC. A smoothing circuit including an inductor L and a capacitor C is connected to the output terminal LX.

  The diode 32 is, for example, a Schottky diode having a low forward voltage, and is provided to discharge energy stored in the inductor L as a regenerative current while the output stage 30 is turned off.

  The operational amplifier 33 outputs a reference signal Ver for feedback control so that the feedback voltage Vf obtained by dividing the third voltage V3 by the resistors R4 and R5 is equal to the reference voltage Vref2.

  The comparator 34 compares the repetitive signal Vchop, for example, a triangular wave and the reference signal Ver, and outputs a control signal P1 that turns on the output stage 30 during a period in which the repetitive signal Vchop is higher than the reference signal Ver.

  The control signal P1 is converted into a current by the V / I converter 35 and transmitted, converted into a voltage again by the I / V converter 36, and input to the gate of the output stage 30 as the drive signal VDR.

  In the NOR circuit 17 shown in FIG. 1, the clock signal CLK is input to one input terminal, and the drive signal VDR is input to the other input terminal. The clock signal CLK is gated with the drive signal VDR. The NOR circuit 17 sets the output signal S2 to High when both the clock signal CLK and the drive signal VDR are Low, and otherwise sets the output signal S2 to Low.

  The latch circuit 15 is, for example, a D-type flip-flop, and allows the output signal S1 of the comparator 11 to pass at a timing when the output signal S2 of the NOR circuit 17 changes from Low to High. Otherwise, the passed output signal S1 Is held as an output signal S3.

  Further, the output signal S3 of the latch circuit 15 is output to the gate of the N-channel MOS transistor which is the switch 16.

  Next, the operation of the voltage detection circuit 10 will be described in detail. FIG. 5 is a timing chart showing the operation of the voltage detection circuit 10.

  As an initial state, the power supply voltage VDD decreases according to the falling slew rate 22. The output stage 30 of the switching circuit 14 is off, and the power supply voltage VDD indicates a voltage 41 that is higher than the voltage VL. The output signal S3 of the latch circuit 15 is High, and the switch 16 is in an on state.

  The clock signal CLK and the drive signal VDR have the same period T, respectively. For example, the rising edge of the clock signal CLK is synchronized with the falling edge of the drive signal VDR.

  As shown in FIG. 5, at time t1, when the drive signal VDR becomes High and the output stage 30 is turned on, a large current flows instantaneously to charge the capacitor C, and the power supply voltage VDD drops below the voltage 41. As a result, a spike 42 is generated.

  When the power supply voltage VDD temporarily falls below the voltage VL due to the spike 42, that is, when the second voltage V2off falls below the reference voltage Vref1, the output signal S1 of the comparator 11 becomes Low. Due to the fluctuation of the spike 42, the chattering 45 may occur in the output signal S1 of the comparator 11.

  After the output stage 30 is switched, the power supply voltage VDD settles to a voltage 43 lower than the voltage 41 due to a voltage drop due to a wiring resistance such as a wire from the voltage terminal 12 to the output stage 30. The voltage 43 is higher than the voltage VL, and at this time, the output signal S1 of the comparator 11 becomes High.

  Next, when the drive signal VDR becomes Low at time t2 and the output stage 30 is turned off, the power supply voltage VDD instantaneously increases from the voltage 43 due to the energy stored in the inductor L, and a spike 44 is generated.

  When the current flowing through the output stage 30 becomes zero, voltage drop due to wiring resistance such as a wire from the voltage terminal 12 to the output stage 30 disappears, and the power supply voltage VDD settles to a voltage 41 a higher than the voltage 43.

  Since the power supply voltage VDD is generally in a falling state, the voltage 41a is lower than the voltage 41. The voltage 41a is larger than the voltage VL, and at this time, the output signal S1 of the comparator 11 maintains High.

  Next, when the clock signal CLK becomes Low at time t3, the output signal S2 of the NOR circuit 17 becomes High.

  When the output signal S2 becomes High, the latch circuit 15 passes the output signal S1 of the comparator 11. Since the output signal S3 of the latch circuit 15 is high in the initial state, the output signal S3 remains high and remains unchanged at this time.

  Thereafter, since the switching circuit 14 repeats the above-described operation according to the drive signal VDR, spikes 42 and spikes 44 are periodically generated in the power supply voltage VDD.

  Next, the period from time t4 to time t6 is the same as that from time t1 to time t3, and the description thereof is omitted.

  Next, when the drive signal VDR becomes High at time t7 and the output stage 30 is turned on, a spike 42b is generated in the power supply voltage VDD. Due to the spike 42b, the power supply voltage VDD falls below the voltage VL, and the output signal S1 of the comparator 11 becomes Low. Chattering 45b occurs due to fluctuation of the spike 42b.

  After the output stage 30 switches, the power supply voltage VDD settles to a voltage 43b that is lower than the voltage 41b when the output stage 30 is off. The voltage 43b is smaller than the voltage VL, and at this time, the output signal S1 of the comparator 11 is kept low.

  Next, at time t8, when the drive signal VDR becomes Low and the output stage 30 is turned off, a spike 44b is generated in the power supply voltage VDD. As a result, since the power supply voltage VDD temporarily becomes higher than the voltage VL, the output signal S1 of the comparator 11 temporarily becomes High, and chattering 46 is generated according to the fluctuation of the spike 44b.

  Next, when the clock signal CLK becomes Low at time t9, the output signal S2 of the NOR circuit 17 becomes High. As a result, the latch circuit 15 passes the output signal S1 of the comparator 11, and the output signal S3 becomes Low. At this time, it is detected for the first time that the power supply voltage VDD is lower than the voltage VL.

  When the output signal S3 becomes Low, the switch 16 is turned off, so that the second voltage V2 is represented by the voltage V2on thereafter.

  Accordingly, the timings (t3, t6, t9) at which the latch circuit 15 passes the output signal S1 of the comparator 11 are spikes 42, 44 when the drive signal VDR becomes High or Low and the output circuit 30 is turned on or off. From the voltage terminal 12 to the output stage 30 during the timing (t1, t2, t4, t5, t7, t8) and while the output stage 30 is on (t1-t2, t4-t5, t7-t9) A period in which a voltage drop due to a wiring resistance such as a wire occurs can be avoided.

  As described above, in the voltage detection circuit 10 of the present embodiment, the drive signal VDR that drives the output stage 30 of the switching circuit 14 is used to distribute the power supply voltage VDD while the output stage 30 is off. The level of the power supply voltage VDD is detected based on the comparison result obtained by comparing the compressed second voltage V2 and the reference voltage Vref1.

  As a result, the level of the power supply voltage VDD can be accurately detected without being affected by the spikes 42 and 44 generated when the output stage 30 is turned on or off and the voltage drop due to the wiring resistance. Therefore, a voltage detection circuit that prevents erroneous detection due to noise can be obtained.

  Here, the case where the power supply voltage VDD decreases according to the falling slew rate 22 has been described, but the same applies to the case where the power supply voltage VDD increases according to the rising slew rate 21, without being affected by spikes and voltage drops. The level of the power supply voltage VDD can be accurately detected.

  Although the case where the switching circuit 14 is a DCDC converter has been described, a driver IC such as a motor driver or an FPD (Flat Panel Driver) that supplies a large current to the load may be used.

  The voltage detection circuit according to this embodiment will be described with reference to FIGS. FIG. 6 is a circuit diagram showing the voltage detection circuit, and FIG. 7 is a timing chart showing the operation of the 6 voltage detection circuit. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. This embodiment is different from the first embodiment in that the timing for passing the output signal of the comparator is delayed.

  That is, as shown in FIG. 6, in the voltage detection circuit 60 of this embodiment, a counter 61 is connected between the NOR circuit 17 and the latch circuit 15 in order to delay the output signal S2 by τ. Yes. The pulse signal OSC is input to the input terminal of the counter 61, and the output signal S2 of the NOR circuit 17 is input to the control terminal.

  When the output signal S2 becomes High, the counter 61 starts counting the pulse signal OSC. When the count value reaches the full count, the counter 61 outputs the carry signal S4 from the output terminal to the latch circuit 15, clears the count value, Continue counting. When the counter 61 is in the full count state, the carry signal S4 is kept high.

  When the output signal S2 becomes Low, the counter 61 stops counting and clears the count value and the carry signal S4.

  Next, the operation of the voltage detection circuit 60 will be described in detail. FIG. 7 is a timing chart showing the operation of the voltage detection circuit 60. In FIG. 7, the time t1 to the time t9 excluding the times t3a, t3b, t6a, t6b, t9a, and t9b are the same as the times t1 to t9 shown in FIG.

As shown in FIG. 7, when the output signal S2 of the NOR circuit 17 becomes High at time t3, the counter 61 starts counting the pulse signal OSC.
Next, when the count value reaches the full count (γ) at time t3a between time t3 and time t4, the counter 61 sets the carry signal S4 to High, clears the count value at time t3b, and repeats counting.

  When the carry signal S4 becomes High, the latch circuit 15 passes the output signal S1 of the comparator 11. Since the output signal S3 of the latch circuit 15 is High in the initial state, the output signal S3 does not change at this time, and remains High.

  Thus, the timing at which the output signal S1 of the comparator 11 passes through the latch circuit 15 changes from t3 to t3a, and the capture time of the latch circuit 15 can be delayed by the time τ required for the counter 61 to perform a full count.

  Next, since the drive signal VDR becomes High at time t4, the output signal S2 of the NOR circuit 17 becomes Low, the counter 61 stops counting, and clears the count value.

  The period from time t6 to time t7 is the same as that from time t3 to time t4, and the description thereof is omitted.

Next, when the output signal S2 of the NOR circuit 17 becomes High at time t9, the counter 61 starts counting the pulse signal OSC.
Next, when the count value reaches the full count (γ) at time t9a, the carry signal S4 becomes High, and the latch circuit 15 passes the output signal S1 of the comparator 11. As a result, the output signal S3 of the latch circuit 15 becomes Low. At this time, it is detected for the first time that the power supply voltage VDD is lower than the voltage VL.

  When the slew rate 22 of the fall of the power supply voltage VDD is small, the output signal S1 of the comparator 11 may chatter at time t9 due to fluctuations in the power supply voltage VDD.

  By providing the delay time τ, the output signal S1 of the comparator 11 when the power supply voltage VDD is stabilized can be passed. This function enables accurate voltage detection when a voltage drop due to a wiring resistance such as a wire from the voltage terminal 12 to the output stage 30 occurs.

  As described above, the voltage detection circuit of this embodiment delays the timing of detecting the power supply voltage VDD by τ while the output stage 30 of the switching circuit 14 is off. There is an advantage that erroneous detection due to fluctuation can be prevented.

10, 60 Voltage detection circuit 11, 34 Comparator 12 Voltage terminal 13 Voltage divider circuit 14 Switching circuit 15 Latch circuit 16 Switch 17 NOR circuit 21, 22 Slew rate 30 Output stage 32 Diode 33 Operational amplifier 35 V / I conversion circuit 36 I / V conversion circuit 42, 44 Spike 45, 46 Chattering 61 Counter VDD Power supply voltage (first voltage)
V2, V3 Second and third voltages Vref1, Vref2 Reference voltage VDR Drive signal R1 First resistor R2 Second resistor R3 Third resistor R4, R5 Resistor L Inductor C Capacitors S1, S2, S3 Output signal S4 Carry signal CLK Clock signal Vf Feedback signal Ver Reference signal Vchop Repeat signal OSC Pulse signal

Claims (5)

A comparator that compares the second voltage obtained by dividing the first voltage input to the voltage terminal with the reference voltage, and outputs a comparison result;
A latch circuit connected to the voltage terminal and passing a signal indicating the comparison result according to a logic value of a clock signal while a switching circuit for switching the first voltage is off;
The voltage terminal is connected between the voltage terminal and a reference potential, and a voltage division ratio is selected according to the output of the latch circuit, and a voltage obtained by dividing the first voltage by the selected voltage division ratio is used as the second voltage. A voltage dividing circuit for outputting to the comparator;
A voltage detection circuit comprising:   The voltage detection circuit according to claim 1, wherein a spike is generated in the first voltage when the switching circuit is turned on or off. The voltage dividing circuit has one end connected to the voltage terminal, a second resistor connected in series to the first resistor, and a second resistor connected in series, and one end connected to a reference potential. A third resistor and a switch connected in parallel to the third resistor,
The switch is turned on or off according to the output of the latch circuit, the first voltage division ratio or the second voltage division ratio is selected, and the second voltage is output from the connection node of the first resistor and the second resistor. The voltage detection circuit according to claim 1.   While the switching circuit is off, the pulse signal starts counting according to the logic value of the clock signal. When the count value reaches a predetermined count value, a carry signal is output to the latch circuit, and the latch The voltage detection circuit according to claim 1, further comprising a counter that delays a timing at which the circuit passes the signal indicating the comparison result.   5. The voltage detection circuit according to claim 4, wherein the counter is a programmable counter, and the predetermined count value is set in advance according to a slew rate of rising and falling of the first voltage.

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