JP2015017033A - Semiconductor multilayer structure, and semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor multilayer structure including a GaOsubstrate and a nitride semiconductor layer that is hardly peeled from the GaOsubstrate and has high crystal quality, and to provide a semiconductor element containing the semiconductor multilayer structure.SOLUTION: A semiconductor multilayer structure includes in an embodiment a β-GaO-based substrate, a GaN-based buffer layer formed on the β-GaO-based substrate, and a nitride semiconductor layer formed on the GaN-based buffer layer. The semiconductor multilayer structure has a difference of 0.2° or less between a maximum value and a minimum value of the angle difference Δθ=θ-θs in the plane in the measurement range of from -22 mm to 22 mm distant from the center in the plane, wherein θs is an offset angle of the principal plate of the β-GaO-based substrate to a predetermined reference direction and θ is a tilting angle of the principal plane of the nitride semiconductor layer to a predetermined reference plane.

Description

  The present invention relates to a semiconductor multilayer structure and a semiconductor element.

Conventionally, a light emitting diode having a Ga ₂ O ₃ substrate and a GaN layer formed on the Ga ₂ O ₃ substrate via a GaN buffer layer is known (see, for example, Patent Document 1). According to Patent Document 1, a GaN buffer layer and a GaN layer are grown on a Ga ₂ O ₃ substrate whose main surface is a surface inclined at an angle of 2 ° to 4 ° from the (100) plane.

JP 2010-183026 A

Since the (100) plane of the Ga ₂ O ₃ crystal is a strong cleavage plane, a crystal layer is formed on the (100) plane or a Ga ₂ O ₃ substrate whose principal plane is a plane slightly inclined from the (100) plane. When epitaxial growth is performed, the crystal layer may be peeled off from the Ga ₂ O ₃ substrate.

Accordingly, an object of the present invention is to provide a semiconductor laminated structure having a Ga ₂ O ₃ substrate and a nitride semiconductor layer having a high crystal quality and a low risk of peeling from the Ga ₂ O ₃ substrate, and the semiconductor laminated structure It is providing the semiconductor element containing this.

  In order to achieve the above object, one embodiment of the present invention provides a semiconductor stacked structure according to [1] to [3].

[1] A β-Ga ₂ O ₃ based substrate, a GaN based buffer layer formed on the β-Ga ₂ O ₃ based substrate, and a nitride semiconductor layer formed on the GaN based buffer layer. An offset angle of the main surface of the β-Ga ₂ O ₃ based substrate with respect to a predetermined reference direction is θs, and an inclination angle of the main surface of the nitride semiconductor layer with respect to the predetermined reference surface is When θ is set, the difference between the maximum value and the minimum value of the angle difference Δθ determined by θ−θs = Δθ is within 0.2 ° in the measurement range of −22 mm to 22 mm with the center in the surface as the origin. A semiconductor laminated structure.

[2] The semiconductor stacked structure according to [1], wherein a difference between an in-plane maximum value and a minimum value of the angle difference Δθ is greater than 0.0 °.

[3] The semiconductor multilayer structure according to [1] or [2], wherein the GaN-based buffer layer is GaN formed in a film shape or an island shape.

  Moreover, in order to achieve the above object, another aspect of the present invention provides the semiconductor element of [4].

[4] A semiconductor element comprising the semiconductor multilayer structure according to any one of [1] to [3].

According to the present invention, a semiconductor stacked structure having a Ga ₂ O ₃ substrate and a nitride semiconductor layer having a high crystal quality and a low risk of peeling from the Ga ₂ O ₃ substrate, and the semiconductor stacked structure are included. A semiconductor element can be provided.

FIG. 1 is a vertical cross-sectional view of the semiconductor multilayer structure according to the first embodiment. Figure 2 is a conceptual diagram showing the orientation relationship between the _β-Ga 2 _{O 3} and the unit cell of the crystal, _β-Ga 2 _{O 3} principal surface of the substrate. FIGS. 3A to 3C are schematic views showing the relationship between the offset angle θs of the main surface of the β-Ga ₂ O ₃ substrate and the inclination angle θ of the main surface of the nitride semiconductor layer. FIG. 4 is a schematic diagram of a cross section of a semiconductor stacked structure that is orthogonal to the (−201) plane of the β-Ga ₂ O ₃ substrate and parallel to the [010] direction. FIGS. 5A and 5B show the in-plane of the semiconductor multilayer structure having a difference Δθ between the offset angle θs of the main surface of the β-Ga ₂ O ₃ substrate and the inclination angle θ of the main surface of the nitride semiconductor layer. It is a graph showing distribution. FIG. 6 is a graph showing variation in Δθ for each semiconductor stacked structure. FIGS. 7A and 7B are graphs showing variations in crystal quality of the nitride semiconductor layer for each semiconductor stacked structure. 8A to 8D show nitride semiconductors when the inclination angle θ of the main surface of the nitride semiconductor layer is 0.14 °, 0.25 °, 0.45 °, and 0.63 °, respectively. It is a photograph showing the state of the main surface of the layer. FIG. 9A is a photograph showing the state of the main surface of the nitride semiconductor layer when the buffer layer made of GaN is used, and FIG. 9B is the case where the buffer layer made of AlN is used. 4 is a photograph showing the state of the main surface of a nitride semiconductor layer. FIG. 10 is a vertical cross-sectional view of an LED element according to the second embodiment.

[First Embodiment]
(Structure of semiconductor laminated structure)
FIG. 1 is a vertical sectional view of a semiconductor multilayer structure 1 according to the first embodiment. Semiconductor laminated structure 1, _β-Ga 2 _{O 3} substrate 2, _β-Ga 2 _{O 3} and the buffer layer 3 formed on the main surface 2a of the substrate 2, _β-Ga 2 O through the buffer layer 3 ₃ having a nitride semiconductor layer 4 formed on the main surface 2a of the substrate 2.

The β-Ga ₂ O ₃ substrate 2 is made of β-Ga ₂ O ₃ crystal. The β-Ga ₂ O ₃ substrate 2 may contain a conductivity type impurity such as Si. The thickness of the β-Ga ₂ O ₃ substrate 2 is, for example, 400 μm.

The principal surface 2a of the β-Ga ₂ O ₃ substrate 2 is a surface inclined with an offset angle θs in the [102] direction with respect to the (−201) plane, that is, a normal vector whose normal vector is the (−201) plane. As a reference, the surface is inclined at an offset angle θs in the [102] direction.

  The offset angle θs is preferably −0.4 ° or more and 0.2 ° or less, and more preferably −0.2 ° or more and 0.0 ° or less.

Figure 2 is a conceptual diagram illustrating a unit cell of the _β-Ga 2 _{O 3} crystal, the orientation relationship between the main surface 2a of the _β-Ga 2 _{O 3} substrate 2. 2 represents an offset angle in the [102] direction from the (−201) plane. In FIG. 2, it is assumed that the offset angle in the [010] direction from the (−201) plane is 0 °.

A unit cell 2b in FIG. 2 is a unit cell of a β-Ga ₂ O ₃ crystal. The β-Ga ₂ O ₃ crystal has a β-gallia structure belonging to a monoclinic system, and a typical lattice constant of the β-Ga ₂ O ₃ crystal not containing impurities is a ₀ = 12.23Å, b ₀ = 3.04 cm, c ₀ = 5.80 cm, α = γ = 90 °, β = 103.7 °. Here, a ₀ , b ₀ , and c ₀ represent axis lengths in the [100] direction, [010] direction, and [001] direction, respectively.

The buffer layer 3 is made of GaN crystal. The buffer layer 3 may be formed in an island shape on the β-Ga ₂ O ₃ substrate 2 or may be formed in a film shape. The buffer layer 3 may contain a conductivity type impurity such as Si. The thickness of the buffer layer 3 is, for example, about 4 to 96 nm.

The buffer layer 3 is formed, for example, by epitaxially growing a GaN crystal on the main surface 2a of the β-Ga ₂ O ₃ substrate 2 at a growth temperature of about 450 to 530 ° C.

The nitride semiconductor layer 4 is made of Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) crystal, and in particular, a high quality crystal is obtained. It is preferable that the GaN crystal is easily formed (y = 1, x = z = 0). The thickness of the nitride semiconductor layer 4 is, for example, 5 μm. The nitride semiconductor layer 4 may contain a conductivity type impurity such as Si.

The nitride semiconductor layer 4 is, for example, Al _x Ga _y In _z N (0 ≦ x ≦ 1) at a growth temperature of about 1000 ° on the main surface 2a of the β-Ga ₂ O ₃ substrate 2 via the buffer layer 3. 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) The crystal is formed by epitaxial growth.

  The main surface 4a of the nitride semiconductor layer 4 is a surface inclined at an inclination angle θ with respect to the (002) plane. The smaller the absolute value of the inclination angle θ, the smaller the surface roughness of the main surface 4a of the nitride semiconductor layer 4.

  Since the unevenness of the main surface 4a of the nitride semiconductor layer 4 causes a leak in the semiconductor element including the semiconductor multilayer structure 1, the surface roughness of the main surface 4a of the nitride semiconductor layer 4 can be reduced by reducing the surface roughness. Can be reduced.

FIGS. 3A to 3C are schematic diagrams showing the relationship between the offset angle θs of the main surface 2 a of the β-Ga ₂ O ₃ substrate 2 and the inclination angle θ of the main surface 4 a of the nitride semiconductor layer 4. . 3A to 3C is a plane parallel to the [102] direction orthogonal to the (−201) plane of the β-Ga ₂ O ₃ substrate 2.

As shown in FIG. 3A, when the main surface 2a of the β-Ga ₂ O ₃ substrate 2 has no offset angle θs (θs = 0 °), the main surface 4a of the nitride semiconductor layer 4 is Inclination from the (002) plane at a predetermined inclination angle θ.

As shown in FIG. 3B, when the main surface 2a of the β-Ga ₂ O ₃ substrate 2 has an offset angle θs and the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4 decreases, the nitride The surface roughness of the main surface 4a of the semiconductor layer 4 is reduced.

As shown in FIG. 3C, by providing the main surface 2a of the β-Ga ₂ O ₃ substrate 2 with an appropriate offset angle θs, the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4 is set. It can be close to 0 °. Thereby, the surface roughness of main surface 4a of nitride semiconductor layer 4 can be effectively reduced.

Specifically, the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4 when the offset angle θs of the main surface 2a of the β-Ga ₂ O ₃ substrate 2 is −0.4 ° or more and 0.2 ° or less. Can be within a numerical range of −0.4 ° to 0.4 °, which is close to 0 °, and the offset angle θs of the main surface 2a of the β-Ga ₂ O ₃ substrate 2 is −0.2 ° to 0.2 °. When the angle is 0 ° or less, the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4 can be within a numerical range of −0.2 ° or more and 0.2 ° or less, which is closer to 0 °.

FIG. 4 is a schematic diagram of a cross section of the semiconductor multilayer structure 1 orthogonal to the (−201) plane of the β-Ga ₂ O ₃ substrate 2 and parallel to the [010] direction. Here, the [010] direction is a direction orthogonal to the [102] direction in the (−201) plane.

In the cross section shown in FIG. 4, the (−201) plane of the β-Ga ₂ O ₃ substrate 2 and the (002) plane of the nitride semiconductor layer 4 are substantially parallel. Therefore, in order to reduce the surface roughness by bringing the major surface 4a of the nitride semiconductor layer 4 closer to the (002) plane, the (−201) plane of the major surface 2a of the β-Ga ₂ O ₃ substrate 2 is used as a reference. The offset angle in the [010] direction is preferably in the range of −0.4 ° to 0.4 ° centered on 0 °, and is −0.2 ° to 0.2 °. More preferably within the range.

(Evaluation of semiconductor laminated structure)
Below, the evaluation result of the semiconductor laminated structure 1 is shown. In this evaluation, a nitride semiconductor layer 4 made of GaN crystal was used. Further, a buffer layer 3 made of GaN or AlN having a thickness of 48 nm was used.

FIGS. 5A and 5B show a semiconductor multilayer structure having a difference Δθ between the offset angle θs of the main surface 2 a of the β-Ga ₂ O ₃ substrate 2 and the inclination angle θ of the main surface 4 a of the nitride semiconductor layer 4. It is a graph showing distribution in 1 surface. 5A shows the distribution of Δθ when the buffer layer 3 made of GaN is used, and FIG. 5B shows the distribution of Δθ when the buffer layer 3 made of AlN is used.

Here, if the angle formed by the (−201) plane of the β-Ga ₂ O ₃ substrate 2 and the (002) plane of the nitride semiconductor layer 4 is Δθ, the relationship between Δθ, θ, and θs is Δθ = θ− It is represented by θs.

  5A and 5B represents the position in the X direction or Y direction in the plane of the semiconductor multilayer structure 1. Here, the mark ◯ plotted in FIGS. 5A and 5B represents a measured value on a line passing through the center in the plane of the semiconductor multilayer structure 1 and parallel to the [010] direction. The measured value on a line parallel to the [102] direction passing through the center in the plane of the semiconductor multilayer structure 1 is represented. The center of the surface of the semiconductor multilayer structure 1 is the origin of the measurement position.

  5A and 5B, in the case where the buffer layer 3 made of GaN is used, the variation in Δθ in the plane of the semiconductor multilayer structure 1 is smaller than in the case where the buffer layer 3 made of AlN is used. It shows that the nitride semiconductor layer 4 having a uniform offset angle in the plane is formed.

  FIG. 6 is a graph showing variation in Δθ for each semiconductor multilayer structure 1. FIG. 6 shows the cumulative relative frequency distribution of Δθ. 6 represents the cumulative relative frequency distribution of Δθ in the semiconductor multilayer structure 1 using the buffer layer 3 made of GaN, and the mark □ represents the semiconductor multilayer structure using the buffer layer 3 made of AlN. The cumulative relative frequency distribution of Δθ in the body 1 is represented. In addition, the value of Δθ of each semiconductor multilayer structure 1 is measured at the center position in the plane.

  FIG. 6 shows that when the buffer layer 3 made of GaN is used, the variation in Δθ for each semiconductor multilayer structure 1 is smaller than when the buffer layer 3 made of AlN is used.

  FIGS. 7A and 7B are graphs showing variations in the crystal quality of the nitride semiconductor layer 4 for each semiconductor multilayer structure 1. 7A shows the cumulative relative frequency distribution of the half-value width of the X-ray rocking curve of the (002) plane of the nitride semiconductor layer 4, and FIG. 7B shows the X of the (101) plane of the nitride semiconductor layer 4. Represents the cumulative relative frequency distribution of the full width at half maximum of the line rocking curve.

  The marks ◯ plotted in FIGS. 7A and 7B represent the cumulative relative frequency distribution of the half width of the X-ray rocking curve in the semiconductor multilayer structure 1 using the buffer layer 3 made of GaN. 4 represents the cumulative relative frequency distribution of the half width of the X-ray rocking curve in the semiconductor multilayer structure 1 using the buffer layer 3 made of AlN.

  FIGS. 7A and 7B show the case where the buffer layer 3 made of GaN is used and the semiconductor layered structure 1 having a crystal quality of the nitride semiconductor layer 4 as compared with the case where the buffer layer 3 made of AlN is used. This shows that the crystal quality of the nitride semiconductor layer 4 is improved, although the variation in the thickness does not change much.

5A and 6 that Δθ in the case of using the buffer layer 3 made of GaN is distributed in a range of approximately 0.0 or more and 0.2 ° or less. Therefore, by setting the offset angle θs of the main surface 2a of the β-Ga ₂ O ₃ substrate 2 to −0.4 ° or more and 0.2 ° or less, the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4 is − It can fall within the numerical range of 0.4 ° or more and 0.4 ° or less. Further, by setting the offset angle θs of the main surface 2a of the β-Ga ₂ O ₃ substrate 2 to −0.2 ° or more and 0.0 ° or less, the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4 is − It can be in the numerical range of 0.2 ° or more and 0.2 ° or less.

  8A to 8D show nitriding when the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4 is 0.14 °, 0.25 °, 0.45 °, and 0.63 °, respectively. 3 is a photograph showing the state of the main surface 4a of the physical semiconductor layer 4;

  8A to 8D show that the step bunching that appears on the main surface 4a of the nitride semiconductor layer 4 increases as the tilt angle θ increases. Although step bunching is hardly confirmed on the main surface 4a of the nitride semiconductor layer 4 shown in FIGS. 8A and 8B, the nitride semiconductor layer 4 shown in FIGS. Step bunching can be clearly confirmed on the main surface 4a.

  From FIGS. 8A to 8D, it is estimated that the step bunching can be clearly confirmed when the inclination angle θ is larger than about 0.4 ° (less than −0.4 °). Further, when the inclination angle θ is about −0.2 ° or more and 0.2 ° or less, it is presumed that the step bunching becomes smaller and the smooth surface is obtained as the observation with the optical microscope becomes difficult.

  FIG. 9A is a photograph showing the state of the main surface 4a of the nitride semiconductor layer 4 when the buffer layer 3 made of GaN is used, and FIG. 9B shows the buffer layer 3 made of AlN. 4 is a photograph showing the state of the main surface 4a of the nitride semiconductor layer 4 when used.

  9A and 9B show hillocks observed on the main surface 4a of the nitride semiconductor layer 4 when the buffer layer 3 made of GaN is used, compared to when the buffer layer 3 made of AlN is used. It shows that the shape of the convex portion is greatly reduced.

Specifically, hillock density of the main surface 4a of the nitride semiconductor layer 4 is less than one per 1 cm ² in the case of using the buffer layer 3 made of GaN, the case of using the buffer layer 3 made of AlN 1 cm ² The number was 10 ² to 10 ³ per unit.

  The generation of hillocks is hardly affected by the inclination angle θ of the main surface 4a of the nitride semiconductor layer 4, but the surface flatness can be further improved by reducing the hillock density using the buffer layer 3 made of GaN. Can be improved.

[Second Embodiment]
(Structure of semiconductor element)
2nd Embodiment is a form about the semiconductor element containing the semiconductor laminated structure 1 of 1st Embodiment. Hereinafter, an LED element will be described as an example of the semiconductor element.

FIG. 10 is a vertical cross-sectional view of the LED element 10 according to the second embodiment. The LED element 10 includes a β-Ga ₂ O ₃ substrate 11, a buffer layer 12 on the β-Ga ₂ O ₃ substrate 11, an n-type cladding layer 13 on the buffer layer 12, and light emission on the n-type cladding layer 13. Layer 14, p-type cladding layer 15 on light-emitting layer 14, contact layer 16 on p-type cladding layer 15, p-side electrode 17 on contact layer 16, and buffer layer of β-Ga ₂ O ₃ substrate 11. 12 and an n-side electrode 18 on the opposite surface.

  In addition, the side surface of the laminate including the buffer layer 12, the n-type cladding layer 13, the light emitting layer 14, the p-type cladding layer 15, and the contact layer 16 is covered with an insulating film 19.

Here, the β-Ga ₂ O ₃ substrate 11, the buffer layer 12, and the n-type cladding layer 13 are the β-Ga ₂ O ₃ substrate 2 and the buffer layer that constitute the semiconductor multilayer structure 1 of the first embodiment. 3 and nitride semiconductor layer 4 respectively. The thicknesses of the β-Ga ₂ O ₃ substrate 11, the buffer layer 12, and the n-type cladding layer 13 are, for example, 400 μm, 48 nm, and 5 μm, respectively.

  The light emitting layer 14 is composed of, for example, a three-layer multiple quantum well structure and a GaN crystal film having a thickness of 10 nm thereon. Each multiple quantum well structure includes a GaN crystal film having a thickness of 8 nm and an InGaN crystal film having a thickness of 2 nm. The light emitting layer 14 is formed, for example, by epitaxially growing each crystal film on the n-type cladding layer 13 at a growth temperature of 750 ° C.

The p-type cladding layer 15 is, for example, a GaN crystal film having a thickness of 150 nm and containing Mg having a concentration of 5.0 × 10 ¹⁹ / cm ³ . The p-type cladding layer 15 is formed, for example, by epitaxially growing a GaN crystal containing Mg on the light emitting layer 14 at a growth temperature of 1000 ° C.

The contact layer 16 is, for example, a GaN crystal film having a thickness of 10 nm and containing Mg having a concentration of 1.5 × 10 ²⁰ / cm ³ . The contact layer 16 is formed, for example, by epitaxially growing a GaN crystal containing Mg on the p-type cladding layer 15 at a growth temperature of 1000 ° C.

In the formation of the buffer layer 12, the n-type cladding layer 13, the light emitting layer 14, the p-type cladding layer 15, and the contact layer 16, TMG (trimethylgallium) gas as the Ga material, TMI (trimethylindium) gas as the In material, Si (C ₂ H ₅ ) ₂ SiH ₂ (diethylsilane) gas can be used as the raw material, Cp ₂ Mg (biscyclopentadienylmagnesium) gas can be used as the Mg raw material, and NH ₃ (ammonia) gas can be used as the N raw material.

The insulating film 19 is made of an insulating material made of SiO ₂ or the like, and is formed by sputtering, for example.

The p-side electrode 17 and the n-side electrode 18 are electrodes that are in ohmic contact with the contact layer 16 and the β-Ga ₂ O ₃ substrate 11, respectively, and are formed by, for example, a vapor deposition apparatus.

LED element 10 has, on _β-Ga 2 _{O 3} substrate 11 in the wafer state, the buffer layer 12, n-type cladding layer 13, the light emitting layer 14, p-type cladding layer 15, the contact layer 16, p-side electrodes 17, and n After the side electrodes 18 are formed, they are obtained by dicing them into, for example, a 300 μm square chip size.

The LED element 10 is, for example, an LED chip that extracts light from the β-Ga ₂ O ₃ substrate 11 side, and is mounted on a can-type stem using Ag paste.

Since the n-type cladding layer 13 of the LED element 10 is formed on the β-Ga ₂ O ₃ substrate 11 whose main surface is a surface inclined at a special offset angle, as shown in the first embodiment. The surface roughness is small and the crystal quality is excellent. The light emitting layer 14, the p-type cladding layer 15, and the contact layer 16 formed by epitaxial crystal growth on the n-type cladding layer 13 having excellent crystal quality also have excellent crystal quality. For this reason, the LED element 10 is excellent in leak characteristics and reliability.

(Effect of embodiment)
According to the first and second embodiments, Al _x Ga _y In _{z is} interposed via a buffer layer made of GaN on a β-Ga ₂ O ₃ substrate whose principal surface is a plane inclined from the (−201) plane. N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, 0.ltoreq.z.ltoreq.1, x + y + z = 1) is obtained by epitaxially growing a nitride semiconductor layer with a small surface roughness of the main surface and high crystal quality. Can be obtained.

  Further, by using such a nitride semiconductor layer, it is possible to form a semiconductor element that suppresses the occurrence of leakage current and has excellent reliability.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the invention. For example, in the second embodiment, an LED element is given as an example of a semiconductor element including the semiconductor multilayer structure of the first embodiment. However, the semiconductor element is not limited to this, and a transistor Other elements such as may be used.

  Moreover, said embodiment does not limit the invention which concerns on a claim. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

1 ... semiconductor _{stack, 2 ... β-Ga 2 O} 3 substrate, 3 ... buffer layer, 4 ... nitride semiconductor layer, 10 ... LED element

Claims (4)

a β-Ga ₂ O ₃ based substrate;
A GaN buffer layer formed on the β-Ga ₂ O ₃ substrate;
A nitride semiconductor layer formed on the GaN-based buffer layer;
A semiconductor multilayer structure comprising:
When the offset angle of the main surface of the β-Ga ₂ O ₃ based substrate with respect to a predetermined reference direction is θs and the inclination angle of the main surface of the nitride semiconductor layer with respect to the predetermined reference surface is θ, θ−θs = A semiconductor laminated structure in which a difference between an in-plane maximum value and a minimum value of an angle difference Δθ determined by Δθ is within 0.2 ° in a measurement range of −22 mm to 22 mm with the center in the plane as an origin.   2. The stacked semiconductor structure according to claim 1, wherein a difference between an in-plane maximum value and a minimum value of the angle difference Δθ is greater than 0.0 °.   3. The semiconductor multilayer structure according to claim 1, wherein the GaN-based buffer layer is GaN formed in a film shape or an island shape.   The semiconductor element containing the semiconductor laminated structure of any one of Claims 1-3.