JP2014207328A - Semiconductor light-emitting device - Google Patents

Abstract

A semiconductor light emitting device capable of improving crystal quality in a light emitting layer that emits light having a peak emission wavelength of 500 nm or more. In a light emitting diode including a group III nitride semiconductor layer 3 that emits light having a peak emission wavelength of 500 nm or more and includes a light emitting layer having an InxGa1-xN (x = 0.18 to 0.23) layer. The surface (growth surface) 3a of group III nitride semiconductor layer 3 is a surface inclined at an off angle θ of 0.3? Or more in the off direction of the m-axis [1-100] with respect to c-plane {0001}. . [Selection] Figure 3

Description

  The present invention relates to a semiconductor light emitting device (light emitting diode, laser diode, etc.) using a group III nitride semiconductor.

Conventionally, in a group III nitride semiconductor light emitting device having a light emitting layer (active layer) sandwiched between an n-type layer and a p-type layer, the nitride semiconductor layer is supported for the purpose of improving the crystal quality of the nitride semiconductor layer. It is known to provide an off-angle on a substrate.
For example, Patent Document 1 discloses that a nitride semiconductor layer, an n-type AlInGaN layer, an active layer, a carrier block layer made of p-type AlInGaN, a p-type on a substrate having an off angle at least in the a-axis direction with respect to the m-plane. It is disclosed that a p-type contact layer made of AlInGaN and p-type AlInGaN is arranged in this order.

JP 2012-49337 A

  However, the optimum values of the plane orientation and off-angle of the main surface of the substrate vary depending on the composition of the nitride semiconductor layer on which the crystal is grown. Therefore, for example, even when a light emitting layer having a peak emission wavelength of 500 nm or more is grown on a substrate described in Patent Document 1, it is difficult to improve the crystal quality. In addition, it cannot be said that a technique for improving the crystal quality of a light emitting layer that generates light having a peak emission wavelength of 500 nm or more has been established yet.

Therefore, an object of the present invention is to provide a semiconductor light emitting device capable of improving the crystal quality in a light emitting layer that generates light having a peak emission wavelength of 500 nm or more.
Another object of the present invention is to provide a semiconductor light emitting device capable of improving the light emission efficiency by improving the crystal quality of the light emitting layer.

In order to achieve the above object, an invention according to claim 1 is made of a group III nitride semiconductor and emits light sandwiched between at least an n-type layer, a p-type layer, and the n-type layer and the p-type layer. A light-emitting layer that emits light having a peak emission wavelength of 500 nm or more, and In _x Ga _1-x N (x = 0.18 to 0.30) layer, and the growth surface of the group III nitride semiconductor layer is a surface inclined at an off angle of 0.3 ° or more with respect to the c-plane.

According to this configuration, since the growth surface of the group III nitride semiconductor layer is inclined with an off angle of 0.3 ° or more with respect to the c-plane, the In _x Ga ₁ is grown during the growth of the group III nitride semiconductor layer. _-x N a (x = 0.18~0.23) can be grown with good crystalline quality. Thus, it is possible to improve the crystal quality of the _{In x Ga 1-x N (} x = 0.18~0.23) emission layer having a layer. As a result, the light emission efficiency of the semiconductor light emitting device can be improved.

According to a second aspect of the present invention, the growth surface of the group III nitride semiconductor layer is a surface inclined at an off angle of 0.3 ° or more in at least the m-axis direction with respect to the c-plane. preferable. Further, as in the invention described in claim 3, it is preferable that an off angle in the a-axis direction of the growth surface of the group III nitride semiconductor layer with respect to the c-plane is 0 °.
According to a fourth aspect of the present invention, the semiconductor light emitting device further includes a hexagonal substrate having a main surface inclined at an off angle of 0.3 ° or more with respect to the c-plane, and the group III nitride semiconductor 4. The semiconductor light emitting element according to claim 1, wherein the layer is a layer that is crystal-grown on the main surface of the substrate. 5.

According to this configuration, since the main surface of the substrate is inclined with an off angle of 0.3 ° or more with respect to the c-plane, the substrate is inclined with an off-angle of 0.3 ° or more with respect to the c-plane. The group III nitride semiconductor layer having the grown surface can be easily crystal-grown.
The invention according to claim 5 is the semiconductor light emitting element according to claim 4, wherein the substrate is a sapphire substrate.

According to this configuration, the group III nitride semiconductor layer having the light emitting layer with improved light emission efficiency can be formed on the sapphire substrate. Further, it is not necessary to use a special substrate, and an inexpensive sapphire substrate is sufficient, so that the manufacturing cost can be reduced.
The invention according to claim 6 is the semiconductor light emitting element according to any one of claims 1 to 5, wherein an off angle of the growth surface of the group III nitride semiconductor layer is 0.35 ° or more. .

According to this configuration, the light emission efficiency of the semiconductor light emitting element can be further improved.
Preferably, the light emitting layer has a multiple quantum well structure in which quantum well layers made of InGaN and barrier layers made of GaN are alternately stacked at a predetermined period. .
The invention according to claim 8, wherein the semiconductor light emitting device further includes an intermediate buffer layer having a superlattice structure in which InGaN layers and GaN layers are alternately stacked at a predetermined period as a base layer of the light emitting layer. The semiconductor light-emitting device according to any one of Items 1 to 7.

According to this configuration, when the light emitting layer is crystal-grown from the n-type layer or p-type layer side, the intermediate buffer layer is grown prior to the growth of the light emitting layer, so that the lattice size at the start of the light emitting layer growth can be increased. Change can be moderated. Therefore, introduction of lattice defects into the stress relaxation layer can be reduced.
The invention according to claim 9 is the semiconductor light-emitting element according to any one of claims 1 to 6, wherein the light-emitting layer generates light having a peak emission wavelength in a range of 500 nm to 550 nm. .

  According to this configuration, a semiconductor light emitting element having a light emitting layer that efficiently generates green light can be provided.

FIG. 1 is a schematic cross-sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a unit cell having a sapphire crystal structure. FIG. 3 is an enlarged view of a main part of the sapphire substrate and the group III nitride semiconductor layer of FIG. FIG. 4 is a schematic diagram for explaining a configuration of a processing apparatus for growing each layer constituting the group III nitride semiconductor layer. FIG. 5 is a graph showing the relationship (main wavelength 525 nm) between the EL intensity and the off angle of a sapphire single crystal wafer. FIG. 6 is a graph showing the relationship (main wavelength 525 nm) between the back surface output and the off angle of the sapphire single crystal wafer. FIG. 7 is a graph showing the relationship (main wavelength 470 nm) between the back surface output and the off angle of the sapphire single crystal wafer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention.
A light-emitting diode 1 as an example of a semiconductor light-emitting device of the present invention has a device body configured by growing a group III nitride semiconductor layer 3 having a group III nitride semiconductor multilayer structure on a sapphire substrate 2. Yes.

  The group III nitride semiconductor layer 3 includes, in order from the sapphire substrate 2 side, an n-type low-temperature GaN buffer layer 31 and an n-type GaN contact layer 32 as an example of the n-type layer of the present invention, an intermediate buffer layer 33, a light emitting layer 34, In addition, the p-type AlGaN electron blocking layer 35 and the p-type GaN contact layer 36 are stacked as an example of the p-type layer of the present invention. The III-nitride semiconductor layer 3 is selectively removed (for example, etched) from the p-type GaN contact layer 36 to a depth at which the n-type GaN contact layer 32 is exposed so that the cross section is substantially rectangular. Is formed. The n-type GaN contact layer 32 has a lead portion 5 drawn from one side of the group III nitride semiconductor layer 3 in the lateral direction along the surface of the sapphire substrate 2.

A p-type electrode (anode electrode) 6 is joined to the surface of the p-type GaN contact layer 36, and an n-type electrode (cathode electrode) 7 is joined to the lead portion 5 of the n-type GaN contact layer 32. ing. Thus, a light emitting diode structure is formed.
The sapphire substrate 2 is bonded to a support substrate (wiring substrate) 8. Wirings 9 and 10 are formed on the surface of the support substrate 8. The p-type electrode 6 and the wiring 9 are connected by a bonding wire 11, and the n-type electrode 7 and the wiring 10 are connected by a bonding wire 12. Further, although not shown, the structure of the light emitting diode 1 and the bonding wires 11 and 12 are sealed with a transparent resin such as an epoxy resin, thereby forming a package of the light emitting diode 1 (diode package). Yes.

The n-type low-temperature GaN buffer layer 31 is composed of, for example, an undoped (undoped dopant) GaN layer grown at a wafer temperature of 400 ° C. to 700 ° C. The layer thickness is preferably several tens of nm.
The n-type GaN contact layer 32 is made of, for example, an n-type GaN layer to which silicon is added as an n-type dopant. The layer thickness is preferably 3 μm or more, specifically 3 μm to 7 μm. The doping concentration of silicon is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

The intermediate buffer layer 33 has a superlattice structure in which, for example, an InGaN layer doped with silicon (for example, about 4 nm thick) and a GaN layer (for example, about 2 nm thick) are alternately stacked in a predetermined cycle (for example, about 5 cycles). Yes. In this embodiment, the InGaN layer is a layer represented by In _z Ga _1-z N (z = 0.01 to 0.05), and the GaN layer is a layer that does not contain In at all. The GaN layer may contain some In in a range smaller than the In composition ratio (z) of the InGaN layer of the intermediate buffer layer 33.

  The light emitting layer 34 generates light having a peak emission wavelength of 500 nm or more, and preferably generates light having a peak emission wavelength in the range of 500 nm to 550 nm. Here, the peak emission wavelength refers to the wavelength of the light having the highest intensity (main peak) among the light emitted from the light emitting layer 34, and is a wavelength corresponding to the peak value of the spectrum distribution of the emitted light. is there. Therefore, even if the peak of the noise level appears in addition to the maximum peak in the spectrum distribution, the peak emission wavelength of the noise level is not included in the “peak emission wavelength” in this embodiment.

The light emitting layer 34 includes, for example, a silicon-doped InGaN layer 14 (quantum well layer: about 3 nm thick, for example) and a GaN layer 13 (barrier layer: about 14 nm thick) alternately for a predetermined period (for example, 8 periods (eight pairs (eight pairs)). About)) It has a stacked multiple quantum well (MQW) structure. In this embodiment, the InGaN layer 14 is a layer represented by In _x Ga _1-x N (x = 0.18 to 0.23), and the GaN layer 13 is a layer that does not contain In at all. The In composition ratio (x) in the InGaN layer 14 is 0.18 (18%) to 0.23 (23%) in this embodiment, but is 0.18 (18%) to 0.30 (30). %). In this embodiment, the plurality of InGaN layers 14 have a constant In composition ratio (x) in the stacking direction of the group III nitride semiconductor layer 3. For example, the In composition ratios (x) of the eight InGaN layers 14 may all be 0.2 (20%). Moreover, the total thickness (total thickness) of the light emitting layer 34 is, for example, 60 nm to 150 nm.

The plurality of InGaN layers 14 may be stacked in the order in which the In composition ratio (x) changes in the stacking direction of the group III nitride semiconductor layer 3. For example, the layers may be stacked in the order in which the In composition ratio (x) increases or decreases as the distance from the sapphire substrate 2 increases.
Further, the light emitting layer 34 has a GaN final barrier layer 15 (for example, about 10 nm thick) between the multiple quantum well structure composed of the InGaN layer 14 and the GaN layer 13 and the p-type AlGaN electron blocking layer 35. The GaN final barrier layer 15 is made of, for example, an undoped (undoped dopant) GaN layer.

The p-type AlGaN electron blocking layer 35 is made of, for example, an AlGaN layer to which magnesium as a p-type dopant is added. The layer thickness is preferably 3 nm or more, specifically 5 nm to 30 nm. The doping concentration of magnesium is, for example, about 3 × 10 ¹⁹ cm ⁻³ .
The p-type GaN contact layer 36 is made of, for example, a GaN layer to which magnesium as a p-type dopant is added at a high concentration. The layer thickness is preferably 0.1 μm or more, specifically 0.2 μm to 0.5 μm. The doping concentration of magnesium is, for example, about 10 ²⁰ cm ⁻³ . The surface of the p-type GaN contact layer 36 forms the surface 3a of the group III nitride semiconductor layer 3, and this surface 3a is a mirror surface. The surface 3a is a light extraction side surface from which light generated in the light emitting layer 34 is extracted.

  The p-type electrode 6 and the n-type electrode 7 are films composed of, for example, a Ti layer and an Al layer. A transparent electrode for anode contact may be formed between the p-type electrode 6 and the p-type GaN contact layer 36 over almost the entire surface 3 a of the group III nitride semiconductor layer 3. Such a transparent electrode can be composed of, for example, a transparent thin metal layer composed of a Ni layer and an Au layer, a ZnO layer, or the like.

  The sapphire substrate 2 is a substrate made of a sapphire single crystal having a polar surface (c-plane in this embodiment) as a main surface 2a. Specifically, the main surface 2a of the sapphire substrate 2 has an off-angle of 0.3 ° or more from the plane orientation of the polar plane, more preferably 0.3 ° or more in the m-axis direction, and still more preferably m-axis direction. The surface has an off angle of 0.3 ° to 0.5 °. Therefore, the main growth surface (surface 3a) of the group III nitride semiconductor layer 3 grown on the sapphire substrate 2 is the same as the main surface 2a of the sapphire substrate 2, that is, a polar surface (in this embodiment, c Surface). The thickness of the sapphire substrate 2 is preferably 600 μm or more, specifically, 650 μm to 1000 μm. In the light emitting diode 1, instead of the sapphire substrate 2, a hexagonal substrate such as a GaN substrate, a ZnO substrate, an AlN substrate, or a SiC substrate can be used.

FIG. 2 is a schematic diagram showing a unit cell having a sapphire crystal structure. FIG. 3 is an enlarged view of a main part of the sapphire substrate and the group III nitride semiconductor layer of FIG.
As shown in FIG. 2, the crystal structure of a sapphire single crystal can be approximated by a hexagonal system, and four oxygen (O) atoms are bonded to one aluminum (Al) atom. The four oxygen atoms are located at the four vertices of a regular tetrahedron in which an aluminum atom is arranged in the center. Of these four oxygen atoms, one aluminum atom is positioned in the + c axis [0001] direction with respect to the oxygen atom, and the other three oxygen atoms are on the −c axis [000-1] side with respect to the aluminum atom. positioned. Due to such a structure, in the sapphire single crystal, the polarization direction is along the c-axis.

  The c-axis is along the axial direction of the hexagonal column, and the plane (the top surface of the hexagonal column) having the c-axis as a normal is the c-plane {0001}. When the sapphire single crystal is cleaved by two planes parallel to the c plane, the + c axis side plane (+ c plane) becomes a crystal plane in which aluminum atoms are arranged, and the −c axis side plane (−c plane) contains oxygen atoms. It becomes a lined crystal plane. For this reason, the c-plane is called a polar plane because it exhibits different properties on the + c-axis side and the −c-axis side.

In addition, the directions passing through the apexes that are not adjacent to each other in the hexagonal column when viewed from directly above the + c plane and the + c axis are the a1 axis [1000], a2 axis [0100], and a3 axis [0010], respectively. ].
On the other hand, the side surfaces of the hexagonal columns are m-planes {10-10}, respectively, and the planes passing through a pair of ridge lines that are not adjacent to each other are a-planes {11-20}. Since these are crystal planes perpendicular to the c-plane and orthogonal to the polarization direction, they are nonpolar planes, that is, nonpolar planes. The direction perpendicular to the m-plane is the m-axis [1-100].

Furthermore, since the crystal plane inclined with respect to the c-plane (not parallel nor perpendicular) intersects the polarization direction obliquely, it has a slightly polar plane, that is, a semipolar plane (Semipolar plane). Plane). Specific examples of the semipolar plane are planes such as {10-11} plane and (10-13) plane as shown on the right side of FIG.
And as mentioned above, the main surface 2a of the sapphire substrate 2 is a surface inclined with an off angle θ of 0.3 ° or more in the m-axis [1-100] direction with respect to the c-plane {0001}. . Further, the off angles in the a1 axis [1000], a2 axis [0100], and a3 axis [0010] directions of the main surface 2a of the sapphire substrate 2 with respect to the c plane {0001} are 0 °.

  As shown in FIG. 3, the main surface 2a of the sapphire substrate 2 has a normal n direction that does not coincide with the c-axis [0001] axis direction, and the m-axis [1- 100] with an off angle θ of 0.3 ° or more. As shown in FIG. 2, the off-direction refers to a direction in which the normal line n of the sapphire substrate 2 is inclined with respect to the c-axis [0001], and the normal line n is projected from the c-axis [0001] onto the c-plane {0001} ( This is indicated by the direction of the projected vector. That is, in this embodiment, the direction of the projection vector of the normal line n coincides with the m axis [1-100].

  As a result, the sapphire substrate 2 has a flat terrace surface 16 composed of the c-plane {0001} and the terrace surface 16 generated by the inclination of the main surface 2a with respect to the c-plane {0001} (off angle θ). The step portion has a step surface 17 that is an m-plane {10-10} perpendicular to the m-axis [1-100]. The height of the step portion (step height h) corresponds to a layer 18 (bi-layer) of an Al—O pair in which oxygen atoms are bonded on one aluminum atom.

  The step surfaces 17 of the layers 18 are regularly arranged while maintaining the width w of the terrace surface 16 in the m-axis [1-100] axis direction. Further, the step line 19 serving as a step edge of the step surface 17 maintains a perpendicular relationship with the m-axis [1-100] direction (in other words, maintains a parallel relationship with the m-axis [1-100] direction). Then, they are arranged in parallel while taking the width w of the terrace surface 16.

The group III nitride semiconductor layer 3 is formed by crystal growth of each layer 18 in the lateral direction along the m-axis [1-100] direction while maintaining the terrace surface 16 and the step surface 17 of the sapphire substrate 2. Has been. The width of each layer 18 in the growth direction (step growth width S) can be expressed by t ₂ / sin θ using the thickness t ₂ of the group III nitride semiconductor layer 3. Further, the width (step advance width L) in the growth direction of each layer 18 on the surface 3a (epi-growth surface) of the group III nitride semiconductor layer 3 can be represented by t ₂ / tan θ. Further, the step growth width S can be approximated to the step progress width L. When the unit of the angle is radians, t ₂ / sin θ≈t ₂ / tan θ≈t ₂ / θ. The step growth width S increases with the thickness t ₂ of the group III nitride semiconductor layer 3.

FIG. 4 is a schematic diagram for explaining a configuration of a processing apparatus for growing each layer constituting the group III nitride semiconductor layer 3.
As shown in FIG. 4, a susceptor 22 including a heater 21 is disposed in the processing chamber 20 of the processing apparatus. The susceptor 22 is coupled to a rotation shaft 23, and the rotation shaft 23 is rotated by a rotation drive mechanism 24 disposed outside the processing chamber 20. Thus, by holding the wafer 25 to be processed on the susceptor 22, the temperature of the wafer 25 can be raised to a predetermined temperature in the processing chamber 20 and can be rotated. The wafer 25 is a sapphire single crystal wafer constituting the sapphire substrate 2 described above.

An exhaust pipe 26 is connected to the processing chamber 20. The exhaust pipe 26 is connected to exhaust equipment such as a rotary pump. As a result, the pressure in the processing chamber 20 is set to 1/10 atm to normal pressure (preferably about 1/5 atm), and the atmosphere in the processing chamber 20 is always exhausted.
On the other hand, a raw material gas supply path 40 for supplying a raw material gas toward the surface of the wafer 25 held by the susceptor 22 is introduced into the processing chamber 20. The source gas supply path 40 includes a nitrogen source pipe 41 for supplying ammonia as a nitrogen source gas, a gallium source pipe 42 for supplying trimethylgallium (TMG) as a gallium source gas, and trimethylaluminum as an aluminum source gas. An aluminum source pipe 43 for supplying (TMAl), an indium source pipe 44 for supplying trimethylindium (TMIn) as an indium source gas, and ethylcyclopentadienylmagnesium (EtCp ₂ Mg) as a magnesium source gas are supplied. A magnesium raw material pipe 45 and a silicon raw material pipe 46 for supplying silane (SiH ₄ ) as a silicon raw material gas are connected. Valves 51 to 56 are interposed in these raw material pipes 41 to 46, respectively. Each source gas is supplied together with a carrier gas composed of hydrogen, nitrogen, or both.

  In order to grow the group III nitride semiconductor layer 3 on the sapphire substrate 2, a sapphire single crystal wafer having a c-plane {0001} as a main surface is held on the susceptor 22 as a wafer 25. In this state, the valves 52 to 56 are closed, the nitrogen material valve 51 is opened, and the carrier gas and ammonia gas (nitrogen material gas) are supplied into the processing chamber 20. Furthermore, the heater 21 is energized, and the wafer temperature (substrate temperature) is raised to 1000 ° C. to 1100 ° C. (for example, about 1050 ° C.). As a result, the group III nitride semiconductor can be grown without causing the surface of the wafer 25 to become rough.

Next, after setting the wafer temperature to be 400 ° C. to 700 ° C., the nitrogen material valve 51 and the gallium material valve 52 are opened. Thus, ammonia and trimethylgallium are supplied from the source gas supply path 40 together with the carrier gas. As a result, a low temperature GaN buffer layer 31 made of an undoped GaN layer grows on the surface of the wafer 25.
Next, after waiting until the wafer temperature reaches 1000 ° C. to 1100 ° C., the nitrogen material valve 51, the gallium material valve 52, and the silicon material valve 56 are opened. As a result, ammonia, trimethylgallium and silane are supplied from the source gas supply path 40 together with the carrier gas. As a result, an n-type GaN contact layer 32 made of a GaN layer doped with silicon grows on the surface of the wafer 25.

  The next step is a step of forming the intermediate buffer layer 33. Specifically, the aluminum material valve 53 and the silicon material valve 56 are closed, and the superlattice structure is grown. The growth of the superlattice structure includes the steps of growing an InGaN layer by opening the nitrogen source valve 51, the gallium source valve 52 and the indium source valve 54 and supplying ammonia, trimethylgallium and trimethylindium to the wafer 25, The step of growing the undoped GaN layer is performed alternately by closing the valve 54 and opening the nitrogen source valve 51 and the gallium source valve 52 to supply ammonia and trimethylgallium to the wafer 25. it can. For example, a GaN layer is formed first, and an InGaN layer is formed thereon. Repeat this 5 times. When the intermediate buffer layer 33 is formed, the temperature of the wafer 25 is preferably 740 ° C. to 850 ° C. (for example, about 780 ° C.).

  The next step is a step of forming the light emitting layer 34. In the process of the light emitting layer 34, similarly to the intermediate buffer layer 33, the aluminum material valve 53 and the silicon material valve 56 are closed, and a multiple quantum well structure is grown. The growth of the multiple quantum well structure includes the steps of growing the InGaN layer 14 by opening the nitrogen source valve 51, the gallium source valve 52 and the indium source valve 54 and supplying ammonia, trimethylgallium and trimethylindium to the wafer 25; By alternately performing the step of growing the undoped GaN layer 13 by closing the indium source valve 54 and opening the nitrogen source valve 51 and the gallium source valve 52 to supply ammonia and trimethylgallium to the wafer 25. It can be carried out. For example, the GaN layer 13 is formed first, and the InGaN layer 14 is formed thereon. After this is repeated eight times, finally, the GaN final barrier layer 15 is formed on the InGaN layer 14. When the light emitting layer 34 is formed, the temperature of the wafer 25 is preferably set to 700 ° C. to 800 ° C., for example.

  Next, the p-type AlGaN electron blocking layer 35 is formed. That is, the nitrogen material valve 51, the gallium material valve 52, the aluminum material valve 53, and the magnesium material valve 55 are opened, and the other valves 54 and 56 are closed. As a result, ammonia, trimethylgallium, trimethylaluminum, and ethylcyclopentadienylmagnesium are supplied toward the wafer 25, and a p-type AlGaN electron blocking layer 35 made of an AlGaN layer doped with magnesium is formed. . When the p-type AlGaN electron blocking layer 35 is formed, the temperature of the wafer 25 is preferably set to 1000 ° C. to 1100 ° C. (for example, 1000 ° C.).

  Next, the p-type GaN contact layer 36 is formed. That is, the nitrogen material valve 51, the gallium material valve 52, and the magnesium material valve 55 are opened, and the other valves 53, 54, and 56 are closed. As a result, ammonia, trimethylgallium and ethylcyclopentadienylmagnesium are supplied toward the wafer 25, and a p-type GaN contact layer 36 composed of a GaN layer doped with magnesium is formed. When forming the p-type GaN contact layer 36, the temperature of the wafer 25 is preferably set to 1000 ° C. to 1100 ° C. (for example, 1000 ° C.).

  When the group III nitride semiconductor layer 3 is thus grown on the wafer 25, the wafer 25 is transferred to an etching apparatus, and the n-type GaN contact layer 32 is exposed by plasma etching, for example, as shown in FIG. A recess 4 is formed for the purpose. The recess 4 may be formed so as to surround the intermediate buffer layer 33, the light emitting layer 34, the p-type AlGaN electron blocking layer 35, and the p-type GaN contact layer 36 in an island shape, whereby the intermediate buffer layer 33, the light emitting layer 34, the p-type AlGaN electron blocking layer 35 and the p-type GaN contact layer 36 may be shaped into a mesa shape.

Next, the p-type electrode 6 and the n-type electrode 7 are formed by a metal vapor deposition apparatus using resistance heating or an electron beam. Thereby, the light emitting diode 1 structure shown in FIG. 1 can be obtained.
After such a wafer process, individual elements are cut out by cleaving the wafer 25, and the individual elements are connected to lead electrodes by die bonding and wire bonding, and then sealed in a transparent resin such as an epoxy resin. . Thus, a package of the light emitting diode 1 is manufactured.

As described above, according to the light emitting diode 1, as shown in FIG. 3, the growth surface 3a of the group III nitride semiconductor layer 3 is 0 in the m-axis [1-100] direction with respect to the c-plane {0001}. Inclined at an off angle θ of 3 ° or more. Thereby, the width w of the terrace surface 16 of the group III nitride semiconductor layer 3 can be made a size suitable for the migration distance of In atoms. Therefore, when the light emitting layer 34 is grown, the In atoms in In _x Ga _1-x N (x = 0.18 to 0.23) are optimal in the crystal lattice (hexagonal lattice) constituting the group III nitride semiconductor. Can be placed on any site. As a result, since the light emitting layer 34 can be grown with good crystal quality, the light emission efficiency of the light emitting diode 1 can be improved.

Further, according to this embodiment, the group III nitride semiconductor layer 3 having the light emitting layer 34 with improved light emission efficiency can be formed on the sapphire substrate 2 as described above. It is not necessary to use a special substrate, and an inexpensive sapphire substrate is sufficient, so that the manufacturing cost can be reduced.
In this embodiment, an intermediate buffer layer 33 having an InGaN layer represented by In _z Ga _1-z N (z = 0.01 to 0.05) is formed as a base layer of the light emitting layer 34. Therefore, when the light emitting layer 34 is crystal-grown on the sapphire substrate 2, the change in the lattice size at the start of the growth of the light emitting layer 34 is moderated by growing the intermediate buffer layer 33 prior to the growth of the light emitting layer 34. be able to. Therefore, introduction of lattice defects into the light emitting layer 34 can be reduced.

As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above-described embodiment, the off angle θ of the surface 3a (growth surface) of the group III nitride semiconductor layer 3 is 0.3 ° or more in the m-axis [1-100] direction with respect to the c-plane {0001}. For example, the off angle θ is 0.3 ° or more in the a1 axis [1000], a2 axis [0100] or a3 axis [0010] direction with respect to the c-plane {0001}. There may be.

In the above-described embodiment, an example in which the present invention is applied to a light-emitting diode has been described. However, the present invention can also be applied to other types of light-emitting elements such as a nitride semiconductor laser element.
In addition, various design changes can be made within the scope of matters described in the claims.

Next, the effect of the light emitting diode according to the present invention was confirmed by carrying out the following examples.
(1) Effect of Improving Luminous Efficiency in Green Light-Emitting Diode First, the off angle θ of the main surface 2a is 0.25 ° and 0.35 in the m-axis [1-100] direction with respect to the c-plane {0001}, respectively. The sapphire single crystal wafer 25 was cut out as follows. Then, the group III nitride semiconductor layer 3 was formed on the main surface 2a of each sapphire single crystal wafer 25 in accordance with the above-described embodiment. A sample 1 was obtained as a result.

On the other hand, a sapphire single crystal wafer 25 was cut out in an environment (temperature, apparatus, etc.) different from that of sample 1 so that the off-angle θ is as shown in FIG. Were Samples 2-4.
And the back surface output of these samples 1-4 was measured using the back surface prober (green light: main wavelength 515nm). The results are shown in FIG. In FIG. 5, the back surface output of Sample 1 with an off angle of 0.35 ° is set as a reference value 1.00, and the back surface outputs of other samples are shown as relative values with respect to the reference value.

According to FIG. 5, in both samples 1 to 4, when the sapphire off-angle θ is in the range of 0.3 ° or more, the back surface of the light emitting layer 34 generates green light (peak emission wavelength is 500 nm or more). It was found that the output can be improved. When comparing the sample 1 with an off angle of 0.25 ° and the sample 3 with an off angle of 0.65 °, the back surface output at the latter off angle of 0.65 ° is inferior. This is considered to be an error due to a difference in environment when manufacturing a sapphire single crystal wafer.
(2) Comparison of Luminous Efficiency between Green Light-Emitting Diode and Blue Light-Emitting Diode The off angle θ of the main surface 2a is 0.25 ° in the m-axis [1-100] direction with respect to the c-plane {0001}. The sapphire single crystal wafer 25 was cut out to be 35 °. Then, the group III nitride semiconductor layer 3 was formed on the main surface 2a of each sapphire single crystal wafer 25 in accordance with the above-described embodiment. A sample 5 was obtained as a result.

On the other hand, the sapphire single crystal wafer 25 is cut out in an environment (temperature, apparatus, etc.) different from that of the sample 5 so that the off angle θ is 0.25 ° and 0.35 °, and this sapphire single crystal wafer 25 is used. The obtained sample was designated as sample 6.
And the back surface outputs of these samples 5 and 6 were measured using a back surface prober (green light: main wavelength 525 nm, blue light: main wavelength 470 nm). The results are shown in FIG. 6 and FIG. 6 and 7, the back surface output of sample 5 with an off angle of 0.25 ° is set to a reference value 1.0, and the back surface outputs of other samples are shown as relative values with respect to the reference value.

According to FIG. 6 showing the result of green light, it was found that the back surface output can be improved by changing the sapphire off angle θ from 0.25 ° to 0.35 ° in both the samples 5 and 6. On the other hand, according to FIG. 7 showing the result of blue light, in both Samples 5 and 6, even when the sapphire off angle θ is changed from 0.25 ° to 0.35 °, no improvement in the back surface output is seen, rather a slight decrease It was observed.
That is, according to FIGS. 6 and 7, the effect obtained by setting the off angle θ of the main surface 2a of the sapphire single crystal wafer 25 to 0.3 ° or more with respect to the c-plane {0001} is that the peak emission wavelength is 500 nm. It was found that the characteristic change is not expected to be conspicuous in the wavelength range of blue light (440 nm to 470 nm).

DESCRIPTION OF SYMBOLS 1 Light emitting diode 2 Sapphire base 3 Group III nitride semiconductor layer 13 GaN layer 14 InGaN layer 31 n-type low-temperature GaN buffer layer 32 n-type GaN contact layer 33 Intermediate buffer layer 34 Light-emitting layer 35 p-type AlGaN electron blocking layer 36 p-type GaN contact layer

Claims (9)

A group III nitride semiconductor layer comprising a group III nitride semiconductor, comprising at least an n-type layer, a p-type layer, and a light-emitting layer sandwiched between the n-type layer and the p-type layer,
The light emitting layer emits light having a peak emission wavelength of 500 nm or more, and has an In _x Ga _1-x N (x = 0.18 to 0.30) layer.
A semiconductor light emitting element, wherein a growth surface of the group III nitride semiconductor layer is a surface inclined at an off angle of 0.3 ° or more with respect to the c-plane.   2. The semiconductor light emitting element according to claim 1, wherein the growth surface of the group III nitride semiconductor layer is a surface inclined at an off angle of 0.3 ° or more in at least the m-axis direction with respect to the c plane.   3. The semiconductor light-emitting device according to claim 1, wherein an off-angle in the a-axis direction of the growth surface of the group III nitride semiconductor layer with respect to the c-plane is 0 °. The semiconductor light emitting device further includes a hexagonal substrate having a main surface inclined at an off angle of 0.3 ° or more with respect to the c-plane,
The said group III nitride semiconductor layer is a semiconductor light-emitting device as described in any one of Claims 1-3 which is a layer by which crystal growth was carried out on the said main surface of the said board | substrate.   The semiconductor light emitting element according to claim 4, wherein the substrate is a sapphire substrate.   The semiconductor light-emitting device according to claim 1, wherein an off angle of the growth surface of the group III nitride semiconductor layer is 0.35 ° or more.   The light emitting layer has a multiple quantum well structure in which quantum well layers made of InGaN and barrier layers made of GaN are alternately stacked at a predetermined period. Semiconductor light emitting device.   The semiconductor light emitting device further includes an intermediate buffer layer having a superlattice structure in which InGaN layers and GaN layers are alternately stacked at a predetermined period as a base layer of the light emitting layer. The semiconductor light-emitting device described in 1.   The semiconductor light emitting element according to claim 1, wherein the light emitting layer emits light having a peak light emission wavelength in a range of 500 nm to 550 nm.

Images