JP2008288532A - Nitride semiconductor device - Google Patents
Nitride semiconductor device Download PDFInfo
- Publication number
- JP2008288532A JP2008288532A JP2007134680A JP2007134680A JP2008288532A JP 2008288532 A JP2008288532 A JP 2008288532A JP 2007134680 A JP2007134680 A JP 2007134680A JP 2007134680 A JP2007134680 A JP 2007134680A JP 2008288532 A JP2008288532 A JP 2008288532A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- well
- active layer
- barrier
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 52
- 230000004888 barrier function Effects 0.000 claims abstract description 94
- 239000000203 mixture Substances 0.000 claims abstract description 59
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 19
- 229910052738 indium Inorganic materials 0.000 claims abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000000969 carrier Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 48
- 229910002601 GaN Inorganic materials 0.000 description 37
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 37
- 239000007789 gas Substances 0.000 description 20
- 238000010438 heat treatment Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 238000005424 photoluminescence Methods 0.000 description 10
- 229910052594 sapphire Inorganic materials 0.000 description 9
- 239000010980 sapphire Substances 0.000 description 9
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 5
- 238000007689 inspection Methods 0.000 description 5
- 239000011777 magnesium Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 4
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Landscapes
- Led Devices (AREA)
Abstract
Description
本発明は、窒化物系半導体装置に係り、特にアルミニウムを含む活性層を有する窒化物系半導体装置に関する。 The present invention relates to a nitride semiconductor device, and more particularly to a nitride semiconductor device having an active layer containing aluminum.
例えば半導体レーザや発光ダイオード（ＬＥＤ）等に、III族窒化物半導体からなる発光素子が使用されている。III族窒化物半導体の例としては、窒化アルミニウム（ＡｌＮ）、窒化ガリウム（ＧａＮ）、窒化インジウム（ＩｎＮ）等がある。代表的なIII族窒化物半導体は、ＡｌxＩｎyＧａ1-x-yＮ（０≦ｘ≦１、０≦ｙ≦１、０≦ｘ＋ｙ≦１）で表される。 For example, a light emitting element made of a group III nitride semiconductor is used for a semiconductor laser, a light emitting diode (LED), or the like. Examples of group III nitride semiconductors include aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). A typical group III nitride semiconductor is represented by Al x In y Ga 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).
III族窒化物半導体を用いた発光素子は、例えば、基板上にｎ型のIII族窒化物半導体層、活性層（発光層）及びｐ型のIII族窒化物半導体層を順に積層した構造を有し、活性層で発生した光を外部に出力する。活性層として、井戸層（ウェル層）を、井戸層よりもバンドギャップの大きなバリア層（障壁層）でサンドイッチ状に挟んだ量子井戸(quantum well)構造が採用可能である（例えば、特許文献１参照。）。
従来の量子井戸構造の活性層を有する窒化物系半導体装置では、バリア層と井戸層との格子不整合に起因するピエゾ電界が、バリア層と井戸層の界面において積層方向に向かって発生する。特に、長波長の光を発生する発光素子では、一般にインジウム（Ｉｎ）の組成が大きいため、バリア層と井戸層との格子不整合が大きくなる。そのため、バリア層と井戸層の界面におけるピエゾ電界が増大して、電子と正孔（ホール）とが井戸層の両端に空間的に分離し、例えば半導体レーザの場合には、しきい値の上昇や発生効率（量子効率）の低下を引き起こすという問題があった。 In a nitride semiconductor device having a conventional quantum well structure active layer, a piezoelectric field due to lattice mismatch between the barrier layer and the well layer is generated in the stacking direction at the interface between the barrier layer and the well layer. In particular, in a light-emitting element that generates light having a long wavelength, since the composition of indium (In) is generally large, the lattice mismatch between the barrier layer and the well layer increases. Therefore, the piezoelectric field at the interface between the barrier layer and the well layer is increased, and electrons and holes are spatially separated at both ends of the well layer. For example, in the case of a semiconductor laser, the threshold value is increased. In addition, there is a problem that the generation efficiency (quantum efficiency) is reduced.
上記問題点を鑑み、本発明は、バリア層と井戸層との格子不整合に起因するピエゾ電界の増大を抑制可能な窒化物系半導体装置を提供する。 In view of the above problems, the present invention provides a nitride semiconductor device capable of suppressing an increase in piezo electric field caused by lattice mismatch between a barrier layer and a well layer.
本発明の一態様によれば、量子井戸構造を有する活性層を備えた窒化物系半導体装置であって、活性層が、ＡｌaＩｎbＧａ1-a-bＮ（０＜ａ≦１、０≦ｂ≦１）からなる複数のバリア層と、複数のバリア層間に配置された、ＡｌxＩｎyＧａ1-x-yＮ（０＜ｘ＜ａ、０≦ｙ＜１かつｙ＜ｂ）からなる井戸層とを備える窒化物系半導体装置が提供される。 According to one embodiment of the present invention, a nitride-based semiconductor device including an active layer having a quantum well structure, wherein the active layer includes Al a In b Ga 1-ab N (0 <a ≦ 1, 0 ≦ a plurality of barrier layers made of b ≦ 1) and a well made of Al x In y Ga 1-xy N (0 <x <a, 0 ≦ y <1 and y <b) disposed between the plurality of barrier layers A nitride-based semiconductor device comprising a layer is provided.
本発明によれば、バリア層と井戸層との格子不整合に起因するピエゾ電界の増大を抑制可能な窒化物系半導体装置を提供できる。 ADVANTAGE OF THE INVENTION According to this invention, the nitride type semiconductor device which can suppress the increase in a piezoelectric field resulting from the lattice mismatch of a barrier layer and a well layer can be provided.
次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。 Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
又、以下に示す実施の形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は、構成部品の材質、形状、構造、配置等を下記のものに特定するものでない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる。 Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.
（第１の実施の形態）
本発明の第１の実施の形態に係る窒化物半導体装置は、図１に示すように、量子井戸構造を有する活性層３を備え、活性層３は、ＡｌaＩｎbＧａ1-a-bＮ（０＜ａ≦１、０＜ｂ≦１）からなる第１及び第２のバリア層３１１、３１２と、第１及び第２のバリア層３１１、３１２間に配置された、ＡｌxＩｎyＧａ1-x-yＮ（０＜ｘ＜ａ、０≦ｙ＜１かつｙ＜ｂ）からなる井戸層３２とを有する。即ち、アルミニウム（Ａｌ）及びインジウム（Ｉｎ）の組成比は、井戸層３２より第１及び第２のバリア層３１１、３１２の方が高い。活性層３は、井戸層３２を、井戸層３２よりもバンドギャップの大きな第１のバリア層３１１と第２のバリア層３１２でサンドイッチ状に挟んだ量子井戸構造である。
(First embodiment)
As shown in FIG. 1, the nitride semiconductor device according to the first embodiment of the present invention includes an active layer 3 having a quantum well structure, and the active layer 3 includes Al a In b Ga 1-ab N ( Al x In y Ga 1 disposed between the first and second barrier layers 311 and 312 having 0 <a ≦ 1 and 0 <b ≦ 1) and the first and second barrier layers 311 and 312. and a well layer 32 made of -xy N (0 <x <a, 0 ≦ y <1 and y <b). That is, the composition ratio of aluminum (Al) and indium (In) is higher in the first and second barrier layers 311 and 312 than in the well layer 32. The active layer 3 has a quantum well structure in which the well layer 32 is sandwiched between the first barrier layer 311 and the second barrier layer 312 having a larger band gap than the well layer 32.
また、図１に示す窒化物半導体装置は、基板１、第１導電型の第１半導体層２と第２導電型の第２半導体層４とを備える。基板１には、例えばサファイア基板、シリコンカーバイド（ＳｉＣ）基板、或いはＧａＮ単結晶基板等が採用可能である。第１半導体層２は、基板１上に配置され、第１半導体層２、活性層３、第２半導体層４は、この順で基板１上に積層される。図１に示すように、活性層３の第１のバリア層３１１が、第１半導体層２上に配置され、活性層３の第２のバリア層３１２上に第２導電型の第２半導体層が配置される。第１半導体層２は、第１導電型のキャリアを活性層３に供給し、第２半導体層４は、第２導電型のキャリアを活性層３に供給する。 The nitride semiconductor device shown in FIG. 1 includes a substrate 1, a first conductive type first semiconductor layer 2, and a second conductive type second semiconductor layer 4. As the substrate 1, for example, a sapphire substrate, a silicon carbide (SiC) substrate, or a GaN single crystal substrate can be employed. The first semiconductor layer 2 is disposed on the substrate 1, and the first semiconductor layer 2, the active layer 3, and the second semiconductor layer 4 are stacked on the substrate 1 in this order. As shown in FIG. 1, the first barrier layer 311 of the active layer 3 is disposed on the first semiconductor layer 2, and the second conductivity type second semiconductor layer is formed on the second barrier layer 312 of the active layer 3. Is placed. The first semiconductor layer 2 supplies the first conductivity type carriers to the active layer 3, and the second semiconductor layer 4 supplies the second conductivity type carriers to the active layer 3.
以下では、第１導電型がｎ型であり、第２導電型がｐ型である場合を例示的に説明する。即ち、活性層３に、第１半導体層２から電子が供給され、第２半導体層４から正孔が供給される。供給された電子及び正孔が活性層３で再結合することにより、光が発生する。ただし、第１導電型をｐ型、第２導電型をｎ型としてもよいことは勿論である。 Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example. That is, electrons are supplied from the first semiconductor layer 2 and holes are supplied from the second semiconductor layer 4 to the active layer 3. Light is generated by the recombination of the supplied electrons and holes in the active layer 3. However, it goes without saying that the first conductivity type may be p-type and the second conductivity type may be n-type.
活性層３で発生する光の波長は、活性層３におけるＩｎの組成比を調整することによって、例えば４００ｎｍ〜５５０ｎｍに設定できる。図２に、活性層３の構造例を示す。図２に示した活性層３は、波長４７０ｎｍで発光する青色発光素子の活性層として採用される構造であり、第１のバリア層３１１及び第２のバリア層３１２がＡｌ0.37Ｉｎ0.25Ｇａ0.38Ｎからなり、井戸層３２がＡｌ0.09Ｉｎ0.19Ｇａ0.72Ｎからなる。ここで、第１のバリア層３１１及び第２のバリア層３１２の膜厚は、例えばそれぞれ７〜１６ｎｍ程度であり、井戸層３２の膜厚は、例えば３ｎｍ程度である。 The wavelength of light generated in the active layer 3 can be set to, for example, 400 nm to 550 nm by adjusting the composition ratio of In in the active layer 3. FIG. 2 shows a structural example of the active layer 3. The active layer 3 shown in FIG. 2 has a structure adopted as an active layer of a blue light emitting element that emits light at a wavelength of 470 nm, and the first barrier layer 311 and the second barrier layer 312 are Al 0.37 In 0.25 Ga 0.38 N. The well layer 32 is made of Al 0.09 In 0.19 Ga 0.72 N. Here, the film thicknesses of the first barrier layer 311 and the second barrier layer 312 are each about 7 to 16 nm, for example, and the film thickness of the well layer 32 is about 3 nm, for example.
また、図１に示した第１半導体層２は、基板１０上に配置された第１コンタクト層２１と、第１コンタクト層２１上に積層された超格子層２２を有する。例えば、第１コンタクト層２１は、膜厚１〜５μｍ程度の第１導電型（ｎ型）のＧａＮ層からなり、超格子層２２は、第１導電型のＡｌＩｎＧａＮ／ＡｌＧａＮ層からなる。超格子層２２は、格子定数差の大きいＡｌＩｎＧａＮ層とＡｌＧａＮ層の応力を緩和し、活性層３を成長させやすくするものであり、例えば、Ｓｉドーピング濃度が１〜５×１０18ｃｍ-3で膜厚１ｎｍ程度のＡｌ0.01Ｉｎ0.05ＧａＮ層と、同様のＳｉドーピング濃度で膜厚２ｎｍ程度のＧａＮ層とを交互に１０周期程度積層した構成が用いられる。 The first semiconductor layer 2 shown in FIG. 1 has a first contact layer 21 disposed on the substrate 10 and a superlattice layer 22 stacked on the first contact layer 21. For example, the first contact layer 21 is made of a first conductivity type (n-type) GaN layer having a thickness of about 1 to 5 μm, and the superlattice layer 22 is made of a first conductivity type AlInGaN / AlGaN layer. The superlattice layer 22 relieves stress between the AlInGaN layer and the AlGaN layer having a large difference in lattice constant and facilitates the growth of the active layer 3. For example, the Si lattice concentration is 1 to 5 × 10 18 cm −3 . A configuration is used in which Al 0.01 In 0.05 GaN layers with a thickness of about 1 nm and GaN layers with a thickness of about 2 nm are stacked alternately for about 10 periods at the same Si doping concentration.
第２半導体層４は、活性層３上に配置された電子ブロック層４１と、電子ブロック層４１上に積層された第２コンタクト層４２を有する。電子ブロック層４１は、活性層３からの電子の流出を防いで、活性層３における電子と正孔の再結合効率を高める。例えば、電子ブロック層４１は、膜厚２０ｎｍ程度の第２導電型（ｐ型）のＡｌＧａＮ層であり、第２コンタクト層４２は、膜厚０．２〜１μｍ程度の第２導電型ＧａＮ層である。 The second semiconductor layer 4 has an electron block layer 41 disposed on the active layer 3 and a second contact layer 42 stacked on the electron block layer 41. The electron blocking layer 41 prevents electrons from flowing out of the active layer 3 and increases the recombination efficiency of electrons and holes in the active layer 3. For example, the electron block layer 41 is a second conductivity type (p-type) AlGaN layer having a thickness of about 20 nm, and the second contact layer 42 is a second conductivity type GaN layer having a thickness of about 0.2 to 1 μm. is there.
更に、図１に示す窒化物半導体装置は、第１半導体層２に電圧を印加する第１電極１０１と、第２半導体層４に電圧を印加する第２電極１０２を備える。図１に示すように、第２半導体層４、活性層３、及び第１半導体層２の一部領域をメサエッチングして露出させた第１コンタクト層２１の表面に、第１電極１０１が配置される。第２電極１０２は、第２コンタクト層４２上に配置される。第１電極１０１は、例えばアルミニウム（Ａｌ）膜からなり、第２電極１０２は、例えばＡｌ膜、或いはパラジウム（Ｐｄ）−金（Ａｕ）合金膜からなる。そして、第１電極１０１は第１半導体層２に、第２電極１０２は第２半導体層４に、それぞれオーミック接続される。 Further, the nitride semiconductor device shown in FIG. 1 includes a first electrode 101 that applies a voltage to the first semiconductor layer 2 and a second electrode 102 that applies a voltage to the second semiconductor layer 4. As shown in FIG. 1, the first electrode 101 is disposed on the surface of the first contact layer 21 exposed by mesa etching in the second semiconductor layer 4, the active layer 3, and a partial region of the first semiconductor layer 2. Is done. The second electrode 102 is disposed on the second contact layer 42. The first electrode 101 is made of, for example, an aluminum (Al) film, and the second electrode 102 is made of, for example, an Al film or a palladium (Pd) -gold (Au) alloy film. The first electrode 101 is ohmically connected to the first semiconductor layer 2, and the second electrode 102 is ohmically connected to the second semiconductor layer 4.
図１は、活性層３が井戸層３２を１つだけ有する量子井戸構造である場合を例示的に表しているが、活性層３は、それぞれがバリア層で挟まれた複数の井戸層を有する多重量子井戸（ＭＱＷ)構造であってもよい。図３に、活性層３が３つの井戸層、即ち第１の井戸層３２１、第２の井戸層３２２及び第３の井戸層３２３を有する例を示す。図３に示す活性層３において、第１の井戸層３２１は第１のバリア層３１１と第２のバリア層３１２の間に配置され、第２の井戸層３２２は第２のバリア層３１２と第３のバリア層３１３の間に配置され、第３の井戸層３２３は第３のバリア層３１３と第４のバリア層３１４の間に配置される。第１のバリア層３１１は第１半導体層２上に配置され、第４のバリア層３１４上に第２半導体層４が配置される。 FIG. 1 exemplarily shows a case where the active layer 3 has a quantum well structure having only one well layer 32, but the active layer 3 has a plurality of well layers each sandwiched by barrier layers. A multiple quantum well (MQW) structure may be used. FIG. 3 shows an example in which the active layer 3 has three well layers, that is, a first well layer 321, a second well layer 322, and a third well layer 323. In the active layer 3 illustrated in FIG. 3, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer 322 includes the second barrier layer 312 and the second barrier layer 312. The third well layer 323 is disposed between the third barrier layer 313 and the fourth barrier layer 314. The first barrier layer 311 is disposed on the first semiconductor layer 2, and the second semiconductor layer 4 is disposed on the fourth barrier layer 314.
次に、第１のバリア層３１１及び第２のバリア層３１２と、井戸層３２の格子定数について説明する。以下において、活性層３に含まれるすべてのバリア層を総称して「バリア層３１」という。また、活性層３が複数の井戸層を含む多重量子井戸構造の場合に、それらの井戸層を総称する場合も単に「井戸層３２」という。 Next, the lattice constants of the first barrier layer 311 and the second barrier layer 312 and the well layer 32 will be described. Hereinafter, all barrier layers included in the active layer 3 are collectively referred to as a “barrier layer 31”. Further, when the active layer 3 has a multiple quantum well structure including a plurality of well layers, the well layers are also simply referred to as “well layers 32”.
ＡｌxＩｎyＧａ1-x-yＮからなる窒化物系半導体では、Ｉｎの組成比ｙが高くなると格子定数が増大し、Ａｌの組成比ｘが高くなると格子定数が減少する。したがって、ＡｌxＩｎyＧａ1-x-yＮからなる窒化物系半導体のＩｎとＡｌの組成比を調整することによって、Ｉｎの組成比ｙが互いに異なる２つの窒化物系半導体の格子定数を一致させることができる。即ち、活性層３のバリア層３１と井戸層３２の格子定数が一致するＩｎとＡｌの組成比の組み合わせを設定可能である。 In a nitride-based semiconductor composed of Al x In y Ga 1-xy N, the lattice constant increases as the In composition ratio y increases, and the lattice constant decreases as the Al composition ratio x increases. Therefore, by adjusting the composition ratio of In and Al in the nitride-based semiconductor composed of Al x In y Ga 1-xy N, the lattice constants of two nitride-based semiconductors having different In composition ratios y are matched. be able to. That is, it is possible to set a combination of In and Al composition ratios in which the lattice constants of the barrier layer 31 and the well layer 32 of the active layer 3 coincide.
図４に、窒化物系半導体の格子定数ｄとバンドギャップＥｇの関係を示す。図４にハッチングで示した領域が、ＡｌxＩｎyＧａ1-x-yＮからなる窒化物系半導体がとりうる格子定数ｄとバンドギャップＥｇの範囲である。図４において、点Ａは、窒化物系半導体がＡｌＮ、即ちｘ＝１且つｙ＝０の場合を示し、格子定数は０．３１１である。点Ｂは、窒化物系半導体がＧａＮ、即ちｘ＝０且つｙ＝０の場合を示し、格子定数は０．３１９である。点Ｃは、窒化物系半導体がＩｎＮ、即ちｘ＝０且つｙ＝１の場合を示し、格子定数は０．３５５である。 FIG. 4 shows the relationship between the lattice constant d of the nitride-based semiconductor and the band gap Eg. A hatched region in FIG. 4 is a range of a lattice constant d and a band gap Eg that a nitride-based semiconductor composed of Al x In y Ga 1-xy N can take. In FIG. 4, point A indicates that the nitride-based semiconductor is AlN, that is, x = 1 and y = 0, and the lattice constant is 0.311. Point B indicates that the nitride-based semiconductor is GaN, that is, x = 0 and y = 0, and the lattice constant is 0.319. Point C indicates that the nitride-based semiconductor is InN, that is, x = 0 and y = 1, and the lattice constant is 0.355.
図４において、格子定数ｄが一致し、且つ、バリア層３１のバンドギャップＥｇ（Ｂａｒｒｉｅｒ）が井戸層３２のバンドギャップＥｇ（ＷｅＬＬ）より大きくなるように、バリア層３１のＩｎとＡｌの組成比、及び井戸層３２のＩｎとＡｌの組成比をそれぞれ調整する。例えば、図４に示したように、格子定数がｄ１＝０．３２５の場合に、Ｅｇ１≦Ｅｇ（ＷｅＬＬ）＜Ｅｇ（Ｂａｒｒｉｅｒ）≦Ｅｇ２となるように、バリア層３１のＩｎとＡｌの組成比、及び井戸層３２のＩｎとＡｌの組成比を調整することによって、活性層３の量子井戸構造を維持しつつ、バリア層３１と井戸層３２の格子定数を一致させられる。 In FIG. 4, the composition ratio of In and Al in the barrier layer 31 is such that the lattice constants d match and the band gap Eg (Barrier) of the barrier layer 31 is larger than the band gap Eg (WeLL) of the well layer 32. And the composition ratio of In and Al in the well layer 32 are adjusted. For example, as shown in FIG. 4, when the lattice constant is d1 = 0.325, the composition ratio of In and Al in the barrier layer 31 is such that Eg1 ≦ Eg (WeLL) <Eg (Barrier) ≦ Eg2. By adjusting the composition ratio of In and Al in the well layer 32, the lattice constants of the barrier layer 31 and the well layer 32 can be matched while maintaining the quantum well structure of the active layer 3.
図５に、ＡｌxＩｎyＧａ1-x-yＮからなる窒化物系半導体のバンドギャップＥｇとＩｎの組成比ｙの関係を示す。なお、ＡｌxＩｎyＧａ1-x-yＮからなる窒化物系半導体のバンドギャップＥｇは、以下の式（１）を用いて算出される：
Ｅｇ =ｘ×Ｅｇ(AlN) ＋ｙ×Ｅｇ(InN)＋(1−x−y)×Ｅｇ(GaN)
−Ｃ×ｘ×(1−x−y)−Ｃ’×y×(1−x−y) ・・・（１）
式（１）で、ＡｌＮのバンドギャップＥｇ(AlN)＝６．２ｅＶ、ＩｎＮのバンドギャップＥｇ(InN)＝０．７７ｅＶ、ＧａＮのバンドギャップＥｇ(GaN)＝３．４ｅＶ、ボーイングパラメータＣ、Ｃ’＝２．６ｅＶである。
FIG. 5 shows the relationship between the band gap Eg and the In composition ratio y of the nitride-based semiconductor composed of Al x In y Ga 1-xy N. The band gap Eg of the nitride-based semiconductor composed of Al x In y Ga 1-xy N is calculated using the following formula (1):
Eg = x * Eg (AlN) + y * Eg (InN) + (1-x-y) * Eg (GaN)
-Cxx (1-x-y) -C'xyx (1-x-y) (1)
In equation (1), the band gap Eg (AlN) of AlN = 6.2 eV, the band gap Eg (InN) = 0.77 eV of InN, the band gap Eg (GaN) = 3.4 eV of GaN, the bowing parameters C, C '= 2.6 eV.
図５に示すように、バンドギャップＥｇが極小値となるＩｎの組成比ｙ０＝０．１７が存在する。したがって、井戸層３２のＩｎの組成比を０．１７に設定することによって、バリア層３１のＩｎの設定可能な組成比の自由度を高くできる。ただし、バリア層３１がＡｌaＩｎbＧａ1-a-bＮからなる窒化物系半導体であり、井戸層３２がＡｌxＩｎyＧａ1-x-yＮからなる井戸層である場合、ｙ＜ｂ、即ち井戸層３２よりバリア層３１のＩｎの組成比の方が大きい必要がある。そのため、井戸層３２のＩｎの組成比を０．１７に設定した場合、バリア層３１のＩｎの組成比を０．１７より大きく設定する。 As shown in FIG. 5, there is an In composition ratio y0 = 0.17 in which the band gap Eg becomes a minimum value. Therefore, by setting the In composition ratio of the well layer 32 to 0.17, the degree of freedom of the settable composition ratio of the barrier layer 31 can be increased. However, when the barrier layer 31 is a nitride semiconductor composed of Al a In b Ga 1-ab N and the well layer 32 is a well layer composed of Al x In y Ga 1-xy N, y <b, The In composition ratio of the barrier layer 31 needs to be larger than that of the well layer 32. Therefore, when the In composition ratio of the well layer 32 is set to 0.17, the In composition ratio of the barrier layer 31 is set to be larger than 0.17.
図５から、井戸層３２のＩｎの組成比を０．１５〜０．２とすることにより、バリア層３１のＩｎの組成比を０．２より大きく、かつバリア層３１と井戸層３２の格子定数が一致する値に設定して、バリア層３１と井戸層３２との格子不整合に起因するピエゾ電界の増大を抑制されると同時に、活性層３を量子井戸構造にできる。より好ましくは、井戸層３２のＩｎの組成比を０．１６〜０．１８とすることにより、バリア層３１のＩｎの設定可能な組成比の自由度が高くなり、バリア層３１のＩｎの組成比を０．１８より大きくする。 From FIG. 5, by setting the In composition ratio of the well layer 32 to 0.15 to 0.2, the In composition ratio of the barrier layer 31 is larger than 0.2, and the lattice of the barrier layer 31 and the well layer 32 is When the constants are set to coincide with each other, an increase in the piezoelectric field due to lattice mismatch between the barrier layer 31 and the well layer 32 is suppressed, and at the same time, the active layer 3 can have a quantum well structure. More preferably, by setting the In composition ratio of the well layer 32 to 0.16 to 0.18, the degree of freedom of the settable composition ratio of the barrier layer 31 is increased, and the In composition of the barrier layer 31 is increased. The ratio is greater than 0.18.
なお、活性層３が発生する光の所望の波長に応じて、バリア層３１及び井戸層３２のＩｎとＡｌの組成比が設定されるのは勿論である。図２に示した例では、バリア層３１のＡｌの組成比ａ＝０．３７、Ｉｎの組成比ｂ＝０．２５で、Ｅｇ（Ｂａｒｒｉｅｒ）＝３．１８である。そして、井戸層３２のＡｌの組成比ｘ＝０．０９、Ｉｎの組成比ｙ＝０．１９であり、Ｅｇ（Ｗｅｌｌ）＝２．６３である。なお、ＩｎＮの格子定数０．３５５、ＧａＮの格子定数０．３１９、ＡｌＮの格子定数０．３１１から得られる係数４．６６、−０．７９を用いて、ａ＝４．６６ｂ−０．７９、及びｘ＝４．６６ｙ−０．７９の関係式を用いている。既に述べたように、図２に示した組成比の活性層３は、波長４７０ｎｍの青色の光を発生する。 Of course, the composition ratio of In and Al in the barrier layer 31 and the well layer 32 is set according to the desired wavelength of light generated by the active layer 3. In the example shown in FIG. 2, the Al composition ratio a = 0.37, the In composition ratio b = 0.25, and Eg (Barrier) = 3.18 in the barrier layer 31. The Al composition ratio x = 0.09 of the well layer 32, the In composition ratio y = 0.19, and Eg (Well) = 2.63. Note that a = 4.66b−0.79 using coefficients 4.66 and −0.79 obtained from the lattice constant 0.355 of InN, the lattice constant 0.319 of GaN, and the lattice constant 0.311 of AlN. , And x = 4.66y−0.79. As already described, the active layer 3 having the composition ratio shown in FIG. 2 generates blue light having a wavelength of 470 nm.
以下に、図１に示した窒化物系半導体装置の製造方法の例を説明する。なお、以下に述べる窒化物系半導体装置の製造方法は一例であり、この変形例を含めて、これ以外の種々の製造方法により実現可能であることは勿論である。ここで、基板１にサファイア基板を適用するとする。サファイア基板のｒ面上にＧａＮを結晶成長させると、その成長面はａ面となり、ノンポーラ面を成長面とする窒化物系半導体装置が形成される。なお、サファイア基板のセミポーラ面上にＧａＮを結晶成長させると、この面が引き継がれてＧａＮの成長面もセミポーラ面となる。 An example of a method for manufacturing the nitride semiconductor device shown in FIG. 1 will be described below. The nitride semiconductor device manufacturing method described below is merely an example, and it is needless to say that the present invention can be realized by various other manufacturing methods including this modification. Here, it is assumed that a sapphire substrate is applied to the substrate 1. When GaN is crystal-grown on the r-plane of the sapphire substrate, the growth plane becomes the a-plane, and a nitride-based semiconductor device having a nonpolar plane as the growth plane is formed. When GaN is crystal-grown on the semipolar surface of the sapphire substrate, this surface is taken over and the GaN growth surface also becomes a semipolar surface.
製造方法としては、良く知られた有機金属気相成長（ＭＯＣＶＤ）法等でサファイア基板上にＧａＮを成長させる。例えば、基板１をサーマルクリーニングした後、基板温度を１０００°Ｃ程度に上げて、基板１のｒ面上に、シリコン（Ｓｉ）ドープの第１導電型（ｎ型）の第１コンタクト層２１を１〜５μｍ程度成長させる。第１コンタクト層２１は、第１電極１０１とのオーミックコンタクトを取るための低抵抗層であり、第１コンタクト層２１に、例えばｎ型ドーパントとしてのシリコン（Ｓｉ）イオンを、３×１０18ｃｍ-3程度の高濃度でドープする。 As a manufacturing method, GaN is grown on a sapphire substrate by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, after the substrate 1 is thermally cleaned, the substrate temperature is raised to about 1000 ° C., and the first contact layer 21 of the first conductivity type (n-type) doped with silicon (Si) is formed on the r surface of the substrate 1. Grow about 1-5 μm. The first contact layer 21 is a low-resistance layer for making ohmic contact with the first electrode 101. For example, silicon (Si) ions as an n-type dopant are added to the first contact layer 21 at 3 × 10 18 cm. Dope at high concentration of about -3 .
次に基板温度を７００℃〜８００℃に下げて、Ｓｉドープの超格子層２２、及び活性層３を順次形成する。超格子層２２は、既に説明したように、Ｓｉドーピング濃度が１〜５×１０18ｃｍ-3で膜厚１ｎｍ程度のＡｌ0.01Ｉｎ0.05ＧａＮ層と、同様のＳｉドーピング濃度で膜厚２ｎｍ程度のＧａＮ層とを交互に１０周期程度積層した構成が用いられる。活性層３の形成方法の詳細は後述する。 Next, the substrate temperature is lowered to 700 ° C. to 800 ° C., and the Si-doped superlattice layer 22 and the active layer 3 are sequentially formed. As described above, the superlattice layer 22 has an Al 0.01 In 0.05 GaN layer having a Si doping concentration of 1 to 5 × 10 18 cm −3 and a thickness of about 1 nm, and a Si doping concentration of about 2 nm. A configuration in which about 10 cycles of GaN layers are alternately stacked is used. Details of the method of forming the active layer 3 will be described later.
その後、基板温度を９５０℃〜１０００℃程度まで上げて、マグネシウム（Ｍｇ）ドープの電子ブロック層４１を形成し、次にＭｇドープのｐ型ＧａＮコンタクト層５を０．２〜１μｍ程度積層する。電子ブロック層４１は、例えば窒化アルミニウムガリウム（ＡｌＧａＮ）層に、５×１０18ｃｍ-3程度のドーピング濃度でｐ型ドーパントとしてＭｇをドープすることにより、ｐ型半導体として形成される。第２コンタクト層４２は、第２電極１０２とのオーミックコンタクトを取るための低抵抗層であり、ＧａＮ層にｐ型ドーパントとしてのマグネシウム（Ｍｇ）を、例えば３×１０19ｃｍ-3の高濃度でドープする。 Thereafter, the substrate temperature is raised to about 950 ° C. to 1000 ° C. to form a magnesium (Mg) -doped electron block layer 41, and then Mg-doped p-type GaN contact layer 5 is laminated by about 0.2 to 1 μm. The electron block layer 41 is formed as a p-type semiconductor by doping Mg as a p-type dopant with a doping concentration of about 5 × 10 18 cm −3 in an aluminum gallium nitride (AlGaN) layer, for example. The second contact layer 42 is a low resistance layer for making ohmic contact with the second electrode 102, and magnesium (Mg) as a p-type dopant is added to the GaN layer at a high concentration of 3 × 10 19 cm −3 , for example. Dope with.
次いで、第２コンタクト層４２〜第１コンタクト層２１の途中までを反応性イオンエッチング等によりメサエッチングして除去し、第１コンタクト層２１表面を露出させる。その後、露出した第１コンタクト層２１表面に第１電極１０１を蒸着により形成し、第２コンタクト層４２上に第２電極１０２を蒸着により形成する。 Next, the second contact layer 42 to the middle of the first contact layer 21 are removed by mesa etching by reactive ion etching or the like to expose the surface of the first contact layer 21. Thereafter, the first electrode 101 is formed on the exposed surface of the first contact layer 21 by vapor deposition, and the second electrode 102 is formed on the second contact layer 42 by vapor deposition.
次に、活性層３の形成方法を説明する。活性層３は、ＡｌaＩｎbＧａ1-a-bＮ（０＜ａ≦１、０≦ｂ≦１）からなるバリア層３１、ＡｌxＩｎyＧａ1-x-yＮ（０＜ｘ＜ａ、０≦ｙ＜１かつｙ＜ｂ）からなる井戸層３２を、交互に積層して形成する。 Next, a method for forming the active layer 3 will be described. The active layer 3 includes a barrier layer 31 made of Al a In b Ga 1-ab N (0 <a ≦ 1, 0 ≦ b ≦ 1), Al x In y Ga 1-xy N (0 <x <a, 0 Well layers 32 of ≦ y <1 and y <b) are alternately stacked.
具体的には、活性層３を形成する際の基板温度及び原料ガスの流量を調整しながら、バリア層３１と井戸層３２を交互に連続して成長させ、バリア層３１と井戸層３２が積層してなる活性層３が形成される。即ち、基板温度及び原料ガスの流量を調節することにより、バリア層３１及び井戸層３２のＩｎとＡｌの組成比を所定の値に調整しながら成長させて、井戸層３２よりバリア層３１のバンドギャップが大きく、かつ格子定数が一致するようにバリア層３１及び井戸層３２を形成する。図６に、図３に示した３つの井戸層３２を有する活性層３を形成する製造方法の例を示す。 Specifically, while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 3, the barrier layers 31 and the well layers 32 are grown alternately and continuously, and the barrier layers 31 and the well layers 32 are stacked. Thus formed active layer 3 is formed. That is, by adjusting the substrate temperature and the flow rate of the source gas, the barrier layer 31 and the well layer 32 are grown while adjusting the composition ratio of In and Al to a predetermined value. The barrier layer 31 and the well layer 32 are formed so that the gap is large and the lattice constants coincide with each other. FIG. 6 shows an example of a manufacturing method for forming the active layer 3 having the three well layers 32 shown in FIG.
図６に示す基板温度Ｔａで第１〜第４のバリア層３１１〜３１４が形成され、基板温度Ｔｂで第１〜第３の井戸層３２１〜３２３が形成される。即ち、基板温度がＴａに設定された時刻ｔ０〜ｔ１において第１のバリア層３１１が形成される。次いで、時刻ｔ１で基板温度がＴｂに設定され、時刻ｔ１〜時刻ｔ２において第１の井戸層３２１が形成される。その後も同様に、時刻ｔ２〜ｔ３において基板温度Ｔａで第２のバリア層３１２が形成され、時刻ｔ３〜時刻ｔ４において基板温度Ｔｂで第２の井戸層３２２が形成される。そして、時刻ｔ４〜ｔ５において基板温度Ｔａで第３のバリア層３１３が形成され、時刻ｔ５〜時刻ｔ６において基板温度Ｔｂで第３の井戸層３２３が形成される。最後に、時刻ｔ６〜ｔ７において基板温度Ｔａで第４のバリア層３１４が形成され、活性層３が完成する。 First to fourth barrier layers 311 to 314 are formed at the substrate temperature Ta shown in FIG. 6, and first to third well layers 321 to 323 are formed at the substrate temperature Tb. That is, the first barrier layer 311 is formed at times t0 to t1 when the substrate temperature is set to Ta. Next, the substrate temperature is set to Tb at time t1, and the first well layer 321 is formed from time t1 to time t2. Similarly, the second barrier layer 312 is formed at the substrate temperature Ta from time t2 to t3, and the second well layer 322 is formed at the substrate temperature Tb from time t3 to time t4. Then, the third barrier layer 313 is formed at the substrate temperature Ta from time t4 to t5, and the third well layer 323 is formed at the substrate temperature Tb from time t5 to time t6. Finally, at time t6 to t7, the fourth barrier layer 314 is formed at the substrate temperature Ta, and the active layer 3 is completed.
第１〜第４のバリア層３１１〜３１４を形成する場合は、原料ガスとして、トリメチルガリウム（ＴＭＧ）ガスを３００ｓｃｃｍ（standard cc/min）、トリメチルインジウム（ＴＭＩ）ガスを５ｓｃｃｍ、トリメチルアルミニウム（ＴＭＡ）ガスを７ｓｃｃｍ、アンモニア（ＮＨ3）ガスを２０ｓｌｍ（standard L/min）の流量でそれぞれ成膜用の処理装置に供給する。一方、第１〜第３の井戸層３２１〜３２３を形成する場合は、原料ガスとして、ＴＭＧガスを３００ｓｃｃｍ、ＴＭＩガスを２８０ｓｃｃｍ、ＴＭＡガスを２ｓｃｃｍ、ＮＨ3ガスを２０ｓｌｍ（standard L/min）の流量でそれぞれ処理装置に供給する。なお、ＴＭＧガスはＧａ原子の原料ガス、ＴＭＩガスはＩｎ原子の原料ガス、ＴＭＡガスはＡｌ原子の原料ガス、ＮＨ3ガスは窒素原子の原料ガスとして供給される。 When the first to fourth barrier layers 311 to 314 are formed, trimethylgallium (TMG) gas is 300 sccm (standard cc / min), trimethylindium (TMI) gas is 5 sccm, and trimethylaluminum (TMA) is used as a source gas. A gas is supplied at a flow rate of 7 sccm and ammonia (NH 3 ) gas at a flow rate of 20 slm (standard L / min), respectively, to a film forming processing apparatus. On the other hand, when forming the first to third well layers 321 to 323, TMG gas is 300 sccm, TMI gas is 280 sccm, TMA gas is 2 sccm, and NH 3 gas is 20 slm (standard L / min). Each is supplied to the processing apparatus at a flow rate. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, TMA gas is supplied as Al atom source gas, and NH 3 gas is supplied as nitrogen atom source gas.
なお、成長条件の一例を示せば、基板温度Ｔａを１０５０℃とし、基板温度Ｔｂを８００℃とした場合に、第１〜第４のバリア層３１１〜３１４がそれぞれ形成される時間、即ち基板温度がＴａに設定される時間ｍ１を５分とし、第１〜第３の井戸層３２１〜３２３がそれぞれ形成される時間、即ち基板温度がＴｂに設定される時間ｍ２を１分として、活性層３が形成される。このとき、第１〜第４のバリア層３１１〜３１４の膜厚はそれぞれ１０ｎｍとなり、第１〜第３の井戸層３２１〜３２３の膜厚はそれぞれ３ｎｍとなる。また、第１〜第４のバリア層３１１〜３１４のＡｌ及びＩｎの組成比は、それぞれＡｌ：Ｉｎ＝７：５であり、第１〜第３の井戸層３２１〜３２３のＡｌ及びＩｎの組成比は、それぞれＡｌ：Ｉｎ＝１：２である。 As an example of the growth conditions, when the substrate temperature Ta is 1050 ° C. and the substrate temperature Tb is 800 ° C., the time during which the first to fourth barrier layers 311 to 314 are formed, that is, the substrate temperature Is set to 5 minutes, and the time when the first to third well layers 321 to 323 are formed, that is, the time m2 when the substrate temperature is set to Tb is set to 1 minute. Is formed. At this time, the film thicknesses of the first to fourth barrier layers 311 to 314 are each 10 nm, and the film thicknesses of the first to third well layers 321 to 323 are each 3 nm. Further, the Al and In composition ratios of the first to fourth barrier layers 311 to 314 are Al: In = 7: 5, respectively, and the Al and In compositions of the first to third well layers 321 to 323 are respectively set. The ratios are Al: In = 1: 2, respectively.
次に、活性層３がＡｌを含む窒化物系半導体である利点について説明する。ＧａＮからなる発光素子等では、例えば、クラッド層にＡｌＧａＮやＧａＮ等が、コンタクト層にはＧａＮ等が用いられる。ＩｎＧａＮを含む活性層の結晶成長を行う場合、Ｉｎの蒸気圧が高いため、活性層の成長温度を６５０〜８００℃程度にする必要がある。しかし、活性層の成膜後にｐ型半導体層を成膜する場合は、ｐ型ＧａＮ層やｐ型ＡｌＧａＮ層の結晶品質を高めるために、一般に活性層の成長温度よりも２００℃〜３００℃高い温度となる１０００℃付近の成長温度でｐ型半導体層をエピタキシャル成長させており、成膜時間は通常１５〜６０分程度かかる。そのため、活性層を成長させた後、活性層上にｐ型のＧａＮ層等を成膜する場合、ＧａＮ層の成長温度が高いために、活性層が熱によるダメージを受け、発光特性が著しく悪化する。 Next, the advantage that the active layer 3 is a nitride-based semiconductor containing Al will be described. In a GaN light-emitting element or the like, for example, AlGaN or GaN is used for the cladding layer, and GaN or the like is used for the contact layer. When crystal growth of an active layer containing InGaN is performed, since the vapor pressure of In is high, the growth temperature of the active layer needs to be about 650 to 800 ° C. However, when the p-type semiconductor layer is formed after the active layer is formed, it is generally 200 ° C. to 300 ° C. higher than the growth temperature of the active layer in order to improve the crystal quality of the p-type GaN layer or the p-type AlGaN layer. The p-type semiconductor layer is epitaxially grown at a growth temperature around 1000 ° C., which is a temperature, and the film formation time usually takes about 15 to 60 minutes. For this reason, when a p-type GaN layer or the like is formed on the active layer after growing the active layer, the growth temperature of the GaN layer is high, so that the active layer is damaged by heat and the light emission characteristics are remarkably deteriorated. To do.
特に、４５０ｎｍ以上の長波長のＧａＮ系半導体発光素子を作製する場合、通常、井戸層のＩｎ組成比が１０％を超えるが、Ｉｎ組成比が高くなるほど、高温状態に置かれたＩｎが昇華して壊れやすくなり、発光効率が極端に低下する。更に、活性層が熱によるダメージを受け続けると、Ｉｎが分離して発光素子を形成するウェハが黒色化する場合もある。このように、井戸層のＩｎ組成比が１０％を超える場合には、ｐ型半導体層の成長温度が高いことにより、活性層が劣化して発光特性が著しく悪くなる。 In particular, when fabricating a GaN-based semiconductor light-emitting device having a long wavelength of 450 nm or more, the In composition ratio of the well layer usually exceeds 10%, but as the In composition ratio increases, In placed at a higher temperature sublimates. It becomes fragile and the luminous efficiency is extremely lowered. Furthermore, if the active layer continues to be damaged by heat, the wafer on which the In is separated and forms the light emitting element may be blackened. Thus, when the In composition ratio of the well layer exceeds 10%, the growth temperature of the p-type semiconductor layer is high, so that the active layer is deteriorated and the light emission characteristics are remarkably deteriorated.
しかし、井戸層のＩｎ組成比が１０％を超える活性層を有し、４５０ｎｍ以上の長波長の発光を行うＧａＮ系半導体発光素子においても、以下に説明するように、少なくとも井戸層にＡｌを添加したＡｌＩｎＧａＮを採用することによって活性層の耐熱性が向上する。そのため、活性層よりも後に成長させる半導体層の形成工程での加熱による活性層の劣化を抑制することができる。 However, even in a GaN-based semiconductor light-emitting device that has an active layer with an In composition ratio of the well layer exceeding 10% and emits light with a long wavelength of 450 nm or more, as described below, at least Al is added to the well layer. The heat resistance of the active layer is improved by adopting AlInGaN. Therefore, it is possible to suppress the deterioration of the active layer due to heating in the process of forming the semiconductor layer grown after the active layer.
図１に示した窒化物系半導体装置を製造する工程において、基板１上に超格子層２２を形成した後、既に説明した方法と同様に、活性層３としてＡｌＩｎＧａＮからなる井戸層３２とＡｌＧａＮからなるバリア層３１とを５周期形成した後、アニール処理を行ない、そのアニール温度（熱処理温度）とＡｌの組成比に依存して活性層３の表面が黒色化しているかどうかを検査した。なお、Ａｌの組成比は、井戸層３２とバリア層３１とで共通である。 In the process of manufacturing the nitride semiconductor device shown in FIG. 1, after forming the superlattice layer 22 on the substrate 1, the well layer 32 made of AlInGaN and the AlGaN as the active layer 3 are formed in the same manner as described above. After forming five periods of the barrier layer 31 to be formed, annealing treatment was performed, and it was examined whether the surface of the active layer 3 was blackened depending on the annealing temperature (heat treatment temperature) and the Al composition ratio. The Al composition ratio is common to the well layer 32 and the barrier layer 31.
図７は、上記検査のデータの一部を示すもので、活性層３表面の画像データを、縦軸を活性層３のＡｌ組成比（Ａｌ／Ｇａ供給比）、横軸を熱処理温度（アニール温度）として表示したものである。活性層３には、バリア層３１としてアンドープＧａＮ層を用い、井戸層３２のＩｎ組成比は２０％程度とし、各アニール温度での熱処理は窒素雰囲気中で行ない、熱処理時間は３０分とした。 FIG. 7 shows a part of the data of the above inspection. The image data on the surface of the active layer 3 is plotted, the vertical axis is the Al composition ratio (Al / Ga supply ratio) of the active layer 3, and the horizontal axis is the heat treatment temperature (annealing). Temperature). In the active layer 3, an undoped GaN layer was used as the barrier layer 31, the In composition ratio of the well layer 32 was about 20%, the heat treatment at each annealing temperature was performed in a nitrogen atmosphere, and the heat treatment time was 30 minutes.
また、活性層３にＡｌを添加したものと比較するために、活性層３を従来のＩｎＧａＮ／ＧａＮからなる活性層とし、超格子層２２をＩｎＧａＮ／ＧａＮからなる超格子層とした構成で、上記と同様の条件で熱処理を行った。なお、ＩｎＧａＮからなる井戸層３２のＩｎ組成比は上記同様２０％程度とした。活性層３を従来のＩｎＧａＮ／ＧａＮで形成した場合の検査結果は、図７の上側に示した。 Further, in order to compare with the active layer 3 added with Al, the active layer 3 is a conventional active layer made of InGaN / GaN, and the superlattice layer 22 is a superlattice layer made of InGaN / GaN. Heat treatment was performed under the same conditions as above. The In composition ratio of the well layer 32 made of InGaN was about 20% as described above. The inspection result when the active layer 3 is formed of conventional InGaN / GaN is shown on the upper side of FIG.
図７では、検査結果を分かりやすくするために、ウェハの黒色化が始まる境界線を点線で示した。図７からわかるように、従来のＡｌを含まないＩｎＧａＮ／ＧａＮからなる活性層３では、９５０℃以上でウェハの黒色化が見られる。しかし、ＡｌＩｎＧａＮ／ＡｌＧａＮからなる活性層３では、Ａｌ組成比が０．５％の場合、ウェハの黒色化が見られるのは熱処理温度が１０００℃以上の場合である。更にＡｌ組成比を増加させてＡｌ組成比が１．０％の場合には、１０５０℃の熱処理温度にならないと、ウェハは黒色化せず、１０００℃でも活性層３に問題は発生しない。Ａｌ組成比を２．０％まで増加させた場合は、Ａｌ組成比１．０％の場合とウェハの状態は変わらず、耐熱性で差は見られない。 In FIG. 7, in order to make the inspection result easy to understand, the boundary line where the blackening of the wafer starts is indicated by a dotted line. As can be seen from FIG. 7, in the conventional active layer 3 made of InGaN / GaN containing no Al, the wafer is blackened at 950 ° C. or higher. However, in the active layer 3 made of AlInGaN / AlGaN, when the Al composition ratio is 0.5%, the wafer is blackened when the heat treatment temperature is 1000 ° C. or higher. When the Al composition ratio is further increased and the Al composition ratio is 1.0%, the wafer does not become black unless the heat treatment temperature reaches 1050 ° C., and no problem occurs in the active layer 3 even at 1000 ° C. When the Al composition ratio is increased to 2.0%, the wafer state remains the same as when the Al composition ratio is 1.0%, and there is no difference in heat resistance.
図８は、フォトルミネセンス（ＰＬ）測定の結果を示す。図８の縦軸はＰＬ強度（任意単位）、横軸は熱処理温度である。図７に示した検査の場合と同様に、図１の構成でサファイア基板上に、活性層３としてＡｌＩｎＧａＮからなる井戸層３２とＡｌＧａＮからなるバリア層３１、又は、ＡｌＩｎＧａＮからなる井戸層３２とＧａＮからなるバリア層３１とを５周期程度形成した後、アニール温度を変化させて窒素雰囲気中で時間３０分間の熱処理を行ない、その後室温で発光スペクトル（ＰＬ強度分布）を測定し、各温度のＰＬ強度分布の積分値を求めた。 FIG. 8 shows the result of photoluminescence (PL) measurement. The vertical axis in FIG. 8 is the PL intensity (arbitrary unit), and the horizontal axis is the heat treatment temperature. As in the case of the inspection shown in FIG. 7, the well layer 32 made of AlInGaN and the barrier layer 31 made of AlGaN as the active layer 3 or the well layer 32 made of AlInGaN and the GaN on the sapphire substrate in the configuration shown in FIG. After forming the barrier layer 31 made of about 5 cycles, the annealing temperature is changed, heat treatment is performed for 30 minutes in a nitrogen atmosphere, and then the emission spectrum (PL intensity distribution) is measured at room temperature. The integrated value of the intensity distribution was obtained.
図８で、曲線Ａ１は、活性層３がＡｌＩｎＧａＮからなる井戸層３２とＡｌＧａＮからなるバリア層３１のＭＱＷ構造で、Ａｌの組成比が０．２５％の場合を示す。曲線Ａ２は、活性層３を従来構造としたもので、ＩｎＧａＮからなる井戸層３２及びＧａＮからなるバリア層３１のＭＱＷ構造の場合を示す。曲線Ａ３は、活性層３がＡｌＩｎＧａＮからなる井戸層３２及びＧａＮからなるバリア層３１のＭＱＷ構造で、Ａｌの組成比が１％の場合を示す。曲線Ａ４は、活性層３がＡｌＩｎＧａＮからなる井戸層３２及びＡｌＧａＮからなるバリア層３１のＭＱＷ構造で、Ａｌの組成比が１％の場合を示す。 In FIG. 8, a curve A1 shows a case where the active layer 3 has an MQW structure of the well layer 32 made of AlInGaN and the barrier layer 31 made of AlGaN, and the Al composition ratio is 0.25%. A curve A2 shows the case where the active layer 3 has a conventional structure and has an MQW structure of a well layer 32 made of InGaN and a barrier layer 31 made of GaN. A curve A3 shows a case where the active layer 3 has an MQW structure of the well layer 32 made of AlInGaN and the barrier layer 31 made of GaN, and the Al composition ratio is 1%. A curve A4 shows an MQW structure in which the active layer 3 is a well layer 32 made of AlInGaN and a barrier layer 31 made of AlGaN, and the Al composition ratio is 1%.
図８に示すように、活性層３を従来構造とした曲線Ａ２では、９５０℃の熱処理を行うと、ＰＬ強度が激減し、活性層３の劣化が見られる。これは、図７の結果とも対応している。一方、Ａｌの組成比が０．２５％の曲線Ａ１の場合は、９５０℃付近で良好なＰＬ強度を示し、１０００℃の熱処理でＰＬ強度が低下する。したがって、井戸層３２及びバリア層３１にＡｌを添加した曲線Ａ１の場合の方が、従来構造の活性層３を採用した曲線Ａ２の場合よりもＴ℃（図８では５０℃）耐熱性が向上する。また、曲線Ａ３の場合では井戸層３２にのみＡｌが１％添加されているが、１０００℃になるとＰＬ強度が低下しており、耐熱性は曲線Ａ１の場合とほとんど変わらないが、Ａｌ組成比の増加にともないＰＬ強度は低下する。一方、井戸層３２とバリア層３１の両方にＡｌを１％添加した曲線Ａ４では、図７を参照すればわかるように耐熱性は曲線Ａ１や曲線Ａ３の場合よりも向上するが、ＰＬ強度は曲線Ａ３の場合よりも低下する。 As shown in FIG. 8, in the curve A2 in which the active layer 3 has a conventional structure, when heat treatment at 950 ° C. is performed, the PL intensity is drastically reduced and the active layer 3 is deteriorated. This also corresponds to the result of FIG. On the other hand, in the case of the curve A1 in which the Al composition ratio is 0.25%, good PL strength is exhibited at around 950 ° C., and the PL strength is lowered by heat treatment at 1000 ° C. Therefore, the heat resistance of T.degree. C. (50.degree. C. in FIG. 8) is improved in the case of the curve A1 where Al is added to the well layer 32 and the barrier layer 31 than in the case of the curve A2 employing the conventional active layer 3. To do. Further, in the case of the curve A3, 1% Al is added only to the well layer 32. However, the PL strength decreases at 1000 ° C., and the heat resistance is almost the same as in the case of the curve A1, but the Al composition ratio As the value increases, the PL intensity decreases. On the other hand, in the curve A4 in which 1% of Al is added to both the well layer 32 and the barrier layer 31, the heat resistance is improved as compared with the curves A1 and A3 as shown in FIG. It is lower than in the case of the curve A3.
上記のように、図７、図８に示された検査結果から、活性層３にＡｌが少しでも添加されれば、活性層３の耐熱性が向上する。その結果、活性層３が成膜された後に、活性層３の成膜時の処理温度より高い温度でｐ型のＧａＮ層を成膜する場合でも、活性層３の熱によるダメージが低減され、発光特性の低下を抑制できる。 As described above, from the inspection results shown in FIG. 7 and FIG. 8, if Al is added to the active layer 3 even a little, the heat resistance of the active layer 3 is improved. As a result, even when the p-type GaN layer is formed at a temperature higher than the processing temperature at the time of forming the active layer 3 after the active layer 3 is formed, damage due to heat of the active layer 3 is reduced, It is possible to suppress a decrease in light emission characteristics.
以上に説明したように、本発明の実施の形態に係る窒化物系半導体装置によれば、ＩｎとＡｌの組成比を調整することによって、井戸層３２よりもバリア層３１のバンドギャップが大きいという関係の量子井戸構造を維持しつつ、Ｉｎの組成比が異なるバリア層３１と井戸層３２の格子定数を一致させることができる。その結果、バリア層３１と井戸層３２との格子不整合に起因するピエゾ電界の増大を抑制可能な窒化物系半導体装置を提供できる。更に、図１に示した窒化物系半導体装置の活性層３のバリア層３１及び井戸層３２がＡｌを含むため、活性層３の熱によるダメージが低減され、発光特性の低下を抑制できる。 As described above, according to the nitride semiconductor device according to the embodiment of the present invention, the band gap of the barrier layer 31 is larger than that of the well layer 32 by adjusting the composition ratio of In and Al. While maintaining the related quantum well structure, the lattice constants of the barrier layer 31 and the well layer 32 having different In composition ratios can be matched. As a result, it is possible to provide a nitride semiconductor device capable of suppressing an increase in piezo electric field due to lattice mismatch between the barrier layer 31 and the well layer 32. Furthermore, since the barrier layer 31 and the well layer 32 of the active layer 3 of the nitride-based semiconductor device shown in FIG. 1 contain Al, damage due to heat of the active layer 3 is reduced, and deterioration of the light emission characteristics can be suppressed.
＜変形例＞
本発明の実施の形態の変形例に係る窒化物系半導体装置は、図９に示すように、基板１の下に第１電極１０１が配置されることが、図１と異なる点である。その他の構成については、図１に示す第１の実施の形態と同様である。
<Modification>
The nitride semiconductor device according to the modification of the embodiment of the present invention is different from FIG. 1 in that the first electrode 101 is disposed under the substrate 1 as shown in FIG. Other configurations are the same as those of the first embodiment shown in FIG.
図９に示した窒化物系半導体装置では、基板１に導電性の第１導電型のＳｉＣ基板を採用し、ＧａＮ層を基板１上に結晶成長させ、第１電極１０１と第２電極１０２を対向するように配置したＬＥＤを構成できる。図１に示した窒化物系半導体装置の構成では、基板１にサファイア基板を採用した場合に、サファイア基板の熱伝導が約０．５Ｗ／（ｃｍ・Ｋ）と悪く、プリント基板上の金属配線等と接続するボンディングワイヤーも第１電極１０１側と第２電極１０２側の両方必要となる。しかし、図９に示した構造では、基板１にＳｉＣ基板を採用する場合に、熱伝導はサファイア基板の１０倍（約４．９Ｗ／（ｃｍ・Ｋ））と放熱性が良く、第１電極１０１を金属配線に直接ボンディングできるため、必要なボンディングワイヤーが第２電極１０２側の１本でよいという利点がある。その他の構成については、図１に示す実施の形態と同様である。 In the nitride-based semiconductor device shown in FIG. 9, a conductive first conductivity type SiC substrate is adopted as the substrate 1, a GaN layer is grown on the substrate 1, and the first electrode 101 and the second electrode 102 are formed. LEDs arranged so as to face each other can be configured. In the configuration of the nitride-based semiconductor device shown in FIG. 1, when a sapphire substrate is used as the substrate 1, the heat conduction of the sapphire substrate is poor at about 0.5 W / (cm · K), and the metal wiring on the printed circuit board. Bonding wires connected to the first electrode 101 and the second electrode 102 are also required. However, in the structure shown in FIG. 9, when a SiC substrate is adopted as the substrate 1, the heat conduction is 10 times that of the sapphire substrate (about 4.9 W / (cm · K)) and the heat dissipation is good. Since 101 can be directly bonded to the metal wiring, there is an advantage that a required bonding wire may be one on the second electrode 102 side. Other configurations are the same as those of the embodiment shown in FIG.
（その他の実施の形態）
上記のように、本発明は実施の形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art.
既に述べた実施の形態の説明においては、第２コンタクト層４２上に第２電極１０２を形成する例を示したが、第２コンタクト層４２上に例えばＺｎＯ電極等の透明電極を積層した後、第２電極１０２を形成するようにしても良い。この場合、ＧａドープＺｎＯ電極を、例えば分子線エピタキシ（ＭＢＥ）法やパルスレーザ堆積（ＰＬＤ）法によって、第２コンタクト層４２上に形成する。 In the description of the embodiment already described, the example in which the second electrode 102 is formed on the second contact layer 42 has been shown. However, after a transparent electrode such as a ZnO electrode is stacked on the second contact layer 42, The second electrode 102 may be formed. In this case, a Ga-doped ZnO electrode is formed on the second contact layer 42 by, for example, a molecular beam epitaxy (MBE) method or a pulsed laser deposition (PLD) method.
このように、本発明はここでは記載していない様々な実施の形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。 As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.
１…基板
２…第１半導体層
３…活性層
４…第２半導体層
５…コンタクト層
１０…基板
２１…第１コンタクト層
２２…超格子層
３１…バリア層
３２…井戸層
４１…電子ブロック層
４２…第２コンタクト層
１０１…第１電極
１０２…第２電極
DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... 1st semiconductor layer 3 ... Active layer 4 ... 2nd semiconductor layer 5 ... Contact layer 10 ... Substrate 21 ... 1st contact layer 22 ... Superlattice layer 31 ... Barrier layer 32 ... Well layer 41 ... Electron block layer 42 ... 2nd contact layer 101 ... 1st electrode 102 ... 2nd electrode
Claims (7)
前記活性層が、
ＡｌaＩｎbＧａ1-a-bＮ（０＜ａ≦１、０＜ｂ≦１）からなる複数のバリア層と、
前記複数のバリア層間に配置された、ＡｌxＩｎyＧａ1-x-yＮ（０＜ｘ＜１、０≦ｙ＜１）からなる井戸層
とを備え、アルミニウム（Ａｌ）及びインジウム（Ｉｎ）の組成比が、前記井戸層より前記バリア層の方が高いことを特徴とする窒化物系半導体装置。 A nitride semiconductor device comprising an active layer having a quantum well structure,
The active layer is
A plurality of barrier layers made of Al a In b Ga 1-ab N (0 <a ≦ 1, 0 <b ≦ 1);
A well layer made of Al x In y Ga 1-xy N (0 <x <1, 0 ≦ y <1) disposed between the plurality of barrier layers, and comprising aluminum (Al) and indium (In) A nitride-based semiconductor device, wherein the barrier layer is higher in composition ratio than the well layer.
前記活性層に第２導電型のキャリアを供給する第２半導体層
とを更に備えることを特徴とする請求項１乃至４のいずれか１項に記載の窒化物系半導体装置。 A first semiconductor layer that supplies carriers of a first conductivity type to the active layer;
The nitride-based semiconductor device according to claim 1, further comprising: a second semiconductor layer that supplies a carrier of a second conductivity type to the active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007134680A JP2008288532A (en) | 2007-05-21 | 2007-05-21 | Nitride semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007134680A JP2008288532A (en) | 2007-05-21 | 2007-05-21 | Nitride semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2008288532A true JP2008288532A (en) | 2008-11-27 |
Family
ID=40147935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007134680A Withdrawn JP2008288532A (en) | 2007-05-21 | 2007-05-21 | Nitride semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2008288532A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013008931A (en) * | 2011-06-27 | 2013-01-10 | Rohm Co Ltd | Semiconductor light-emitting element |
| JP2013516781A (en) * | 2010-01-05 | 2013-05-13 | ソウル オプト デバイス カンパニー リミテッド | Light emitting diode and manufacturing method thereof |
| KR20160112372A (en) * | 2015-03-19 | 2016-09-28 | 엘지이노텍 주식회사 | Uv light emitting device and lighting system |
| CN111095579A (en) * | 2017-09-12 | 2020-05-01 | 日机装株式会社 | Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor light emitting element |
| JP2021190684A (en) * | 2020-05-27 | 2021-12-13 | 日亜化学工業株式会社 | Light-emitting element and method for manufacturing light-emitting element |
| US11888089B2 (en) | 2020-05-27 | 2024-01-30 | Nichia Corporation | Light emitting element and method of manufacturing light emitting element |
-
2007
- 2007-05-21 JP JP2007134680A patent/JP2008288532A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013516781A (en) * | 2010-01-05 | 2013-05-13 | ソウル オプト デバイス カンパニー リミテッド | Light emitting diode and manufacturing method thereof |
| JP2013008931A (en) * | 2011-06-27 | 2013-01-10 | Rohm Co Ltd | Semiconductor light-emitting element |
| KR20160112372A (en) * | 2015-03-19 | 2016-09-28 | 엘지이노텍 주식회사 | Uv light emitting device and lighting system |
| KR102317473B1 (en) | 2015-03-19 | 2021-10-27 | 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 | Uv light emitting device and lighting system |
| CN111095579A (en) * | 2017-09-12 | 2020-05-01 | 日机装株式会社 | Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor light emitting element |
| CN111095579B (en) * | 2017-09-12 | 2023-06-27 | 日机装株式会社 | Nitride semiconductor light-emitting element and method for manufacturing nitride semiconductor light-emitting element |
| JP2021190684A (en) * | 2020-05-27 | 2021-12-13 | 日亜化学工業株式会社 | Light-emitting element and method for manufacturing light-emitting element |
| JP7328558B2 (en) | 2020-05-27 | 2023-08-17 | 日亜化学工業株式会社 | Light-emitting element and method for manufacturing light-emitting element |
| US11888089B2 (en) | 2020-05-27 | 2024-01-30 | Nichia Corporation | Light emitting element and method of manufacturing light emitting element |
| US12408484B2 (en) | 2020-05-27 | 2025-09-02 | Nichia Corporation | Light emitting element and method of manufacturing light emitting element |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4234101B2 (en) | Gallium nitride compound semiconductor device | |
| JP5995302B2 (en) | Manufacturing method of nitride semiconductor light emitting device | |
| CN101373806B (en) | Zinc-blende nitride semiconductor free-standing substrate, method for fabricating same, and light-emitting device employing same | |
| KR20100006548A (en) | Group iii nitride based semiconductor light emitting element and epitaxial wafer | |
| JPWO2008153130A1 (en) | Nitride semiconductor light emitting device and method for manufacturing nitride semiconductor | |
| WO2010100844A1 (en) | Nitride semiconductor element and method for manufacturing same | |
| CN104919604A (en) | Nitride semiconductor light emitting element | |
| JP6062966B2 (en) | Gallium nitride light emitting diode | |
| WO2011125449A1 (en) | Nitrogen compound semiconductor light emitting element and manufacturing method thereof | |
| WO2015146069A1 (en) | Light emitting diode element | |
| KR20090021849A (en) | Semiconductor light emitting device and manufacturing method thereof | |
| CN103165787A (en) | Semiconductor light-emitting device | |
| JP2014187159A (en) | Semiconductor light-emitting element | |
| JP2008288532A (en) | Nitride semiconductor device | |
| JP5388967B2 (en) | Semiconductor light emitting device | |
| JP5229048B2 (en) | Group III nitride semiconductor light emitting device and method of manufacturing the same | |
| JP2008118049A (en) | GaN-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE | |
| WO2008056632A1 (en) | GaN SEMICONDUCTOR LIGHT EMITTING ELEMENT | |
| WO2016038856A1 (en) | Semiconductor light emitting element, semiconductor light emitting element manufacturing method, and negative electrode forming method | |
| US9305773B2 (en) | Semiconductor device, nitride semiconductor wafer, and method for forming nitride semiconductor layer | |
| JP6323782B2 (en) | Semiconductor light emitting device and method for manufacturing semiconductor light emitting device | |
| CN103081138A (en) | Nitride semiconductor light-emitting element and manufacturing method therefor | |
| JP2009027022A (en) | Nitride semiconductor light-emitting element | |
| JP2015018840A (en) | Semiconductor light emitting device | |
| JP2008227103A (en) | GaN-BASED SEMICONDUCTOR LIGHT EMITTING ELEMENT |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20100803 |