JP2014090381A - Duty correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a duty correction circuit that enables a high speed operation by increasing a setup margin.SOLUTION: A duty correction circuit 10 for correcting a duty of input data includes a latch circuit 21 for receiving the input data and operatively delaying the input data in synchronism with a clock signal, and a combinational circuit (logic circuit 13) for performing a logical operation on the input data and a latch circuit output outputted from the latch circuit 21. The combinational circuit 13 performs a logical operation determined on the basis of the duty of the input data.

Description

  The present invention relates to a duty correction circuit that corrects the duty of a signal, and more particularly to speeding up a duty correction circuit.

Conventionally, a duty correction circuit has been proposed in which a signal having a desired duty is obtained by correcting the duty of the signal.
For example, the duty correction circuit 1 shown in FIG. 10 includes a flip-flop (FF 1) 11, a flip-flop (FF 2) 12, a logic circuit (OR) 13, and an inverter (INV) 14.

  The flip-flop 11 receives the input data DATA and the clock signal CK, operates using the clock signal CK as an operation clock, and outputs the input data DATA acquired in synchronization with the clock signal CK as the output signal FF1_out. The input data DATA is input data to the duty correction circuit 1. The flip-flop 11 has a role of eliminating delay by synchronizing the input data DATA with the clock signal CK.

The flip-flop 12 receives the output signal FF1_out of the flip-flop 11 and the inverted clock signal CK_B obtained by inverting the clock signal CK by the inverter 14, operates using the inverted clock signal CK_B as an operation clock, and is synchronized with the inverted clock signal CK_B. The output signal FF1_out captured in this manner is output as the output signal FF2_out.
The logic circuit 13 receives the output signal FF1_out of the flip-flop 11 and the output signal FF2_out of the flip-flop 12, calculates a logical sum of these, and outputs the calculation result as an output signal OUT1. This output signal OUT1 becomes an output signal from the duty correction circuit 1.

For example, Patent Document 1 and Patent Document 2 have been proposed as duty correction circuits including two flip-flops FF and a combinational circuit.
In the duty correction circuit 1 shown in FIG. 10, the clock signal CK and the clock inverted signal CK_B are input to the flip-flops 11 and 12, respectively, and the rising edge and the falling edge of the clock signal CK are used as triggers to input data DATA. Are two signals that are out of phase with each other and with a phase difference of 180 °. Then, the output signals FF1_out and FF2_out of the flip-flops 11 and 12 are input to the logic circuit 13 as a combinational circuit in the subsequent stage, and the logical circuit 13 calculates the logical sum of these two output signals FF1_out and FF2_out. The duty is adjusted.

As a specific example, a case where the duty of the input data DATA is corrected so that the duty is 50% will be described.
In FIG. 10, a logic circuit (OR) 13 that calculates a logical sum is used as the combinational circuit, but the combinational circuit can be selected as appropriate according to the input data DATA. For example, the input data DATA is a synchronization signal that is synchronized with a clock signal generated by a counter or a frequency divider that operates in synchronization with the clock signal CK, and the HIGH level section is equivalent to one clock compared to the LOW level section. In the case of a short signal, a combinational circuit that adds the output signals FF1_out and FF2_out of the flip-flops 11 and 12, such as a logic circuit (OR) 13, as shown in FIG. Further, for example, the input data DATA is a synchronization signal synchronized with the clock signal CK generated by a counter or a frequency divider that operates in synchronization with the clock signal CK, and the HIGH level interval is 1 compared with the LOW level interval. In the case of a signal that becomes longer by the clock, a combinational circuit that subtracts the output signals FF1_out and FF2_out of the flip-flops 11 and 12, such as a logical circuit (AND) that calculates a logical product, is used.

FIG. 11 shows a timing chart of each part when the duty is corrected to 50% in the duty correction circuit 1 shown in FIG.
11, (a) is the clock signal CK, (b) is the input data DATA, (c) is the output signal FF1_out of the flip-flop (FF1) 11, (d) is the output signal FF2_out of the flip-flop (FF2) 12, (E) is the output signal OUT1 of the logic circuit (OR) 13, that is, the duty correction circuit 1.

The input data DATA is a signal obtained by dividing the clock signal CK by 3. The HIGH level section is a signal corresponding to one clock of the clock signal CK, and the LOW level section is a signal corresponding to two clocks of the clock signal CK.
By inputting the input data DATA and the clock signal CK to the flip-flop 11, an output signal FF1_out obtained by delaying the input data DATA by one clock is obtained as shown in FIG. Further, by inputting the clock inverted signal CK_B and the output signal FF1_out of the flip-flop 11 to the flip-flop 12, as shown in FIG. 11D, the output signal FF2_out obtained by delaying the output signal FF1_out by 1/2 clock is obtained. obtain.

As a result, two signals that are two signals out of phase with respect to the input data DATA and that have a phase difference of 180 ° (πrad) and that are synchronized with the clock signal CK of the output signals FF1_out and FF2_out are obtained. Can do.
By inputting these output signals FF1_out and FF2_out to the logic circuit (OR) 13 and calculating the logical sum of them, an output signal OUT1 having a duty of 50% can be obtained as shown in FIG. it can.

JP 2002-290214 A US Pat. No. 6,998,882

  As shown in the timing chart of FIG. 11, in the conventional duty correction circuit 1, at the same time that the flip-flop 11 takes in the input data DATA at the rising edge of the clock signal CK, the output signal FF1_out of the flip-flop 11 is determined and immediately thereafter. Since the flip-flop 12 takes in the output signal FF1_out at the falling edge of the clock signal CK, that is, at the rising edge of the clock inversion signal CK_B, the flip-flops 11 and 12 have a relatively high speed of 1/2 or less of one cycle of the clock signal CK. Need to work. The reason will be described with reference to FIG.

FIG. 12 is an enlarged timing chart of a part of FIG.
12, (a) is the input data DATA, (b) is the clock signal CK, (c) is the output signal FF1_out of the flip-flop 11, and (d) is the clock inverted signal CK_B.
Note that “delay” in FIG. 12 represents a delay time of switching of the input data DATA or the output signal FF1_out with respect to switching of the clock signal CK and the clock inverted signal CK_B.

  As shown in the timing chart of FIG. 12, when a data delay (delay time delay) occurs in the input data DATA with respect to the rise of the clock signal CK at time t1, the flip-flop 11 causes the clock signal CK at time t3. The input data DATA is taken in at the rising edge. Therefore, the signal to be read as the input data DATA must reach the input terminal of the flip-flop 11 between the time when the input data DATA rises at time t2 and the rising edge of the clock signal CK at time t3.

The flip-flop 12 receives a signal to be read as the output signal FF1_out between the time when the output signal FF1_out of the flip-flop 11 rises at the time t4 and the rising edge of the clock signal CK, that is, the clock inverted signal CK_B, at the time t5. The input terminal of the flip-flop 12 must be reached.
In this way, the margin from when the value of the input data DATA, which is a signal synchronized with the clock signal CK, is determined at the time t2, until the flip-flop 11 reads the input data DATA at the rising edge at the time t3 of the clock signal CK. Time, that is, a section T1 from time t2 to time t3, and the rising edge of the clock signal at time t5 after the output signal FF1_out of the flip-flop 11 which is a signal synchronized with the clock signal CK is determined at time t4 The margin time until the flip-flop 12 reads the output signal FF1_out, that is, the section T2 from the time point t4 to the time point t5 is called a setup margin.

That is, in the method of the conventional duty correction circuit 1, as shown in FIG. 12, at the opposite phase edge immediately after the rising edge of the clock signal CK at time t3, that is, at the rising edge of the clock inverted signal CK_B at time t5. The flip-flop 12 needs to capture the output signal FF1_out of the flip-flop 11.
Therefore, the setup margin of the flip-flop 12 is a time obtained by further subtracting the delay time delay of the flip-flop 11 from the half cycle of the clock signal CK, that is, an interval from time t4 to time t5 in FIG. There is a problem that the operation with the clock signal CK is difficult.

Since such a setup margin becomes difficult to secure as the circuit speed increases, it is required to solve the shortage of the setup margin particularly in a high-speed operation IC.
In view of the above, the present invention has an object to provide a duty correction circuit capable of increasing the setup margin and increasing the speed.

  One aspect of the present invention is a duty correction circuit (for example, the duty correction circuit 10 in FIG. 1) that corrects the duty of input data, and the input data is input and operates in synchronization with a clock signal. A logic operation determined based on the correction content of the duty of the input data is performed on the input data and the output of the latch circuit output from the latch circuit, for example, the latch circuit 21 in FIG. A duty correction circuit including a combinational circuit (for example, the logic circuit 13 in FIG. 1).

Further, the input data is input, and a flip-flop (for example, flip-flop 11 in FIG. 1) that adjusts the phase of the input data to a signal synchronized with a clock signal is included, and the latch circuit adjusts the phase by the flip-flop. Later input data may be delayed.
Another aspect of the present invention is a duty correction circuit (for example, duty correction circuit 30 in FIG. 7) that corrects the duty of input data, which operates when the input data is input and in synchronization with the clock signal. A first latch circuit that delays data (for example, the latch circuit 31a in FIG. 7) and a first latch circuit output that is output from the first latch circuit are input and operate in synchronization with the clock signal. A second latch circuit (for example, latch circuit 31b in FIG. 7) that delays the circuit output, and a combinational circuit that performs a logical operation on the first latch circuit output and the second latch circuit output output from the second latch circuit (For example, the logic circuit 13 in FIG. 7), and the combinational circuit performs a logic operation determined based on the duty of the input data. It is the duty correction circuit according to claim.

The first latch circuit and the second latch circuit may constitute a flip-flop (for example, flip-flop 31 in FIG. 7).
The input data may comprise a counter, a frequency divider, or a shift register that operates in synchronization with the clock signal.
The input data may be data in which a HIGH level section is shorter by one clock of the clock signal than a LOW level section.

The combinational circuit may be a circuit that calculates a logical sum.
The input data may be data in which a HIGH level section is longer by one clock of the clock signal than a LOW level section.
The combinational circuit may be a circuit that calculates a logical product.

  According to the present invention, since each part constituting the duty correction circuit operates in synchronization with the clock signal, it is sufficient to ensure only the setup margin for the clock signal. As the setup margin for the clock signal, the clock signal and the clock signal obtained by inverting the clock signal are used. A longer section can be secured as a setup margin compared to the case of using an inverted signal. Therefore, the speed of the duty correction circuit can be increased. In addition, since the circuit scale of the latch circuit is smaller than that of other circuits such as flip-flops, for example, the circuit area can be reduced by using the latch circuit.

It is a block diagram which shows an example of the duty correction circuit which concerns on 1st Embodiment of this invention. It is an example of the timing chart which shows the waveform of each part of FIG. FIG. 3 shows the detailed timing of some waveforms in FIG. It is a block diagram which shows an example of the duty correction circuit which concerns on 2nd Embodiment of this invention. FIG. 5 is an example of a timing chart showing waveforms at various parts in FIG. 4. FIG. FIG. 6 shows the detailed timing of a part of the waveforms in FIG. It is a block diagram which shows an example of the duty correction circuit which concerns on 3rd Embodiment of this invention. It is an example of the timing chart which shows the waveform of each part of FIG. FIG. 9 shows the detailed timing of some of the waveforms in FIG. It is a block diagram which shows an example of the conventional duty correction circuit. It is an example of the timing chart which shows the waveform of each part of FIG. FIG. 12 shows the detailed timing of some waveforms in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In each figure referred in the following description, the same part as another figure is shown with the same code | symbol.

First, the first embodiment will be described.
FIG. 1 is a configuration diagram illustrating an example of a duty correction circuit 10 according to the first embodiment.
The duty correction circuit 10 according to the first embodiment includes a flip-flop (FF1) 11, a latch circuit (LATCH) 21, and a logic circuit (OR) 13.
The flip-flop 11 receives the input data DATA and the clock signal CK, takes in the input data DATA using the clock signal CK as an operation clock, and outputs FF1_out as its output.

The latch circuit 21 receives the output signal FF1_out of the flip-flop 11 and the clock signal CK, takes the output signal FF1_out using the clock signal CK as an operation clock, and outputs the output signal Latch_out as its output.
The logic circuit 13 receives the output signal FF1_out of the flip-flop 11 and the output signal Latch_out of the latch circuit 21, and outputs a logical sum of the output signal FF1_out and the output signal Latch_out as the output signal OUT10 of the duty correction circuit 10.

The flip-flop 11 has a role of eliminating delay by synchronizing the input data DATA with the clock signal CK.
As shown in FIG. 1, the duty correction circuit 10 according to the first embodiment is provided with a latch circuit 21 in place of the flip-flop (FF2) 12 and the inverter 14 in the conventional duty correction circuit 1 shown in FIG. . That is, the duty correction circuit 10 according to the first embodiment includes a flip-flop (FF2) 12 that takes in the output signal FF1_out of the flip-flop (FF1) 11 at the rising edge of the clock inversion signal CK_B in the conventional duty correction circuit 1. In contrast to using the flip-flop 12, the setup margin is secured by using the latch circuit 21 that reads the output signal FF1_out at the rising edge of the clock signal CK.

  In addition, the duty of the input data DATA is corrected by inputting the clock signal CK to the flip-flop 11 and the latch circuit 21 shown in FIG. 1 and inputting the clock signal so that the phase is shifted with respect to the input data DATA. Two signals FF1_out and Latch_out that are signals and have a phase difference of 180 ° are output, and logical operation is performed on these two output signals FF1_out and Latch_out by a logic circuit in the subsequent stage.

As a specific example, a case where the input data DATA is corrected so that the duty of the output signal OUT10 of the duty correction circuit 10 is 50% will be described.
FIG. 2 shows a timing chart of each part when the duty is corrected to 50% in the duty correction circuit 10 shown in FIG.
2, (a) is the clock signal CK, (b) is the input data DATA, (c) is the output signal FF1_out of the flip-flop 11, (d) is the output signal Latch_out of the latch circuit 21, and (e) is the duty correction. This is the output signal OUT10 of the circuit 10.

  The input data DATA is a synchronization signal synchronized with the clock signal CK, and the difference between the HIGH level section and the LOW level section is detected by a counter, a frequency divider, a shift register, or the like that operates at the clock signal CK before the duty correction circuit. It is made to be for one clock. Here, when the input data DATA is a signal obtained by dividing the clock signal CK by 3, the HIGH level section is a signal corresponding to one clock of the clock signal CK, and the LOW level section is a signal corresponding to two clocks of the clock signal CK. Will be described.

  Such input data DATA is input to the flip-flop 11, the output signal FF1_out of the flip-flop 11 is input to the latch circuit 21, and the clock signal CK is input to the flip-flop 11 and the latch circuit 21, so that FIG. An output signal FF1_out shown in (c) and an output signal Latch_out shown in FIG. 2 (d) are extracted as two signals having a phase shift with respect to the input data DATA and having a phase difference of 180 °. be able to.

Then, by calculating the logical sum of these output signals FF1_out and Latch_out by the logic circuit 13 shown in FIG. 1, the output signal OUT10 having a duty of 50% shown in FIG. 2E can be obtained.
Here, a setup margin in the duty correction circuit 10 having the circuit configuration shown in FIG. 1 is considered.

FIG. 3 is an enlarged timing chart of a part of FIG.
3, (a) is the input data DATA, (b) is the clock signal CK, (c) is the output signal FF1_out of the flip-flop FF1, and (d) is the clock signal CK.
Note that “delay” in FIG. 3 represents a delay time of switching of the input data DATA or the output signal FF1_out with respect to switching of the clock signal CK.

As shown in the timing chart of FIG. 3, assuming that a data delay of delay time delay occurs in response to the switching of the input data DATA with respect to the rising edge of the clock signal CK at time t11, the flip-flop 11 The input data DATA is taken in at the rising edge of the clock signal CK.
Therefore, the signal to be read as the input data DATA reaches the input terminal of the flip-flop FF1 between the time when the input data DATA is switched to the HIGH level at the time t12 and the rising edge of the clock signal CK at the time t13. There must be. That is, the setup margin is a section T11 from t12 to t13, which is a considerable time obtained by subtracting the delay time delay from one cycle of the clock signal CK.

On the other hand, in the latch circuit 21, a signal to be read as the output signal FF1_out is latched between the time when the output signal FF1_out of the flip-flop 11 is switched to the HIGH level at time t14 and the rising edge of the clock signal CK at time t15. The input terminal of the circuit 21 must be reached.
That is, the output signal FF1_out of the flip-flop 11 is changed from the time when the input data DATA is switched to the HIGH level at the time t14 when the data delay of the delay time delay has elapsed from the rising edge of the clock signal CK at the time t13. The setup margin is until the rising edge of the clock signal CK, and corresponds to a period T12 obtained by subtracting the delay time delay from one cycle of the clock signal CK. That is, the setup margin section T12 of the latch circuit 21 is equivalent to the setup margin section T11 of the flip-flop 11, and a time longer than the half cycle of the clock signal CK can be secured as the setup margin.

  Here, when the setup margin of each part in the conventional duty correction circuit 1 shown in FIG. 12 is compared with the setup margin of each part in the duty correction circuit 10 in the first embodiment shown in FIG. The margin section is the same for T1 (FIG. 12) and T11 (FIG. 3). However, in the conventional duty correction circuit 1, as shown in FIG. 12, the flip-flop 12 using the clock inversion signal CK_B has an input. When two signals that are out of phase with respect to the data DATA and are out of phase by 180 ° are extracted, the fetch timing of the output signal FF1_out of the flip-flop 11 is the rising edge at the time t5, that is, the clock signal CK. Done at the standing edge, setup merge Is the interval T2, in the duty correction circuit 10 according to the present embodiment, as shown in FIG. 3, the capture timing of the output signal FF1_out of the flip-flop 11 is the rising edge of the clock signal CK at time t15, that is, The setup margin of the latch circuit 21 is the section T12 having the same length as the setup margin (section T11) of the flip-flop 11 because the timing is the same as the rising edge of the clock signal CK as the data fetch timing in the flip-flop 11. That is, compared with the conventional duty correction circuit 1 using the flip-flop 12 as a circuit for extracting two signals whose phases are shifted from the input data DATA and whose phases are shifted by 180 ° of the clock signal. Thus, it can be seen that the duty correction circuit 10 shown in FIG. 1 using the latch circuit 21 can have a larger setup margin.

That is, since the duty correction circuit 10 shown in FIG. 1 can secure a longer section as a setup margin, the occurrence of a setup error can be suppressed even when the cycle of the clock signal CK is shortened. In other words, the speed of the duty correction circuit 10 can be increased.
Further, in the conventional duty correction circuit 1 shown in FIG. 10, when the delay time delay exceeds 1/2 cycle of the clock signal CK, the setup margin elapses in the flip-flop 12 that operates using the clock inversion signal CK_B as the operation clock. However, since it does not toggle, the desired output signal OUT1 cannot be obtained. However, in the duty correction circuit 10 using the latch circuit 21 shown in FIG. 1, even when the delay time delay exceeds 1/2 cycle of the clock signal CK, the output signal OUT10 is only trimmed by the delay time delay. Miggling occurs. Therefore, it is possible to avoid a malfunction of a circuit (not shown) that operates in response to the output signal OUT10 due to the output signal OUT10 not toggling.

As described above, each part of the duty correction circuit 10 shown in FIG. 1 operates using the clock signal CK as an operation clock at the time of duty correction. Therefore, the setup margin is about twice that of the conventional duty correction circuit 1 shown in FIG. That is, the speed is increased by about twice.
That is, when the duty correction circuit 1 uses the clock signal CK and the clock inverted signal CK_B as operation clocks as in the conventional case, data must be captured before the rising of the clock signal CK and the clock inverted signal CK_B. Since the setup margin for the rising edge of the clock inverted signal CK_B is shorter than the clock signal CK by 1/2 clock, it is necessary to secure sufficient setup margins for the two points of the clock signal CK and the clock inverted signal CK_B. However, in the above-described embodiment, each unit operates using the clock signal CK as an operation clock. Therefore, it is only necessary to secure a setup margin for the clock signal CK. The setup margin for the clock signal CK is relative to the rising edge of the clock inverted signal CK_B. A section longer than the setup margin by about the version clock can be secured. Therefore, the speed can be increased by about twice.
In general, a latch circuit has a smaller circuit scale than a flip-flop. Therefore, the circuit area can be reduced by using the latch circuit 21 instead of the flip-flop 12.

Next, a second embodiment of the present invention will be described.
FIG. 4 is a schematic configuration diagram illustrating an example of the duty correction circuit 20 in the second embodiment.
The duty correction circuit 20 in the second embodiment includes a latch circuit (LATCH) 21 and a logic circuit (OR) 13.
The latch circuit 21 receives the input data DATA and the clock signal CK, takes in the input data DATA using the clock signal CK as an operation clock, and outputs an output signal Latch_out as its output.
The logic circuit 13 receives the input data DATA and the output signal Latch_out of the latch circuit 21, calculates the logical sum of the input data DATA and the output signal Latch_out, and outputs the calculation result as the output signal OUT 20 of the duty correction circuit 20.

  Here, the duty correction circuit 20 in the second embodiment corrects a signal that is synchronized with the clock signal CK as the input data DATA and that has a relatively short delay time delay for switching the input data DATA. It is targeted. That is, the duty correction circuit 10 in the first embodiment requires the flip-flop 11 for eliminating the data delay as the input data DATA. In the second embodiment, the delay of the input data DATA is eliminated. There is no flip-flop to do.

That is, when the delay time delay of the input data DATA is short, it is not necessary to provide the flip-flop 11 for eliminating the data delay as shown in FIG. Therefore, the duty correction circuit 20 in the second embodiment does not include a circuit such as a flip-flop for eliminating the data delay of the input data DATA, as shown in FIG.
Instead of using the flip-flop 12 that takes the inverted signal CK_B of the clock signal CK as an operation clock and captures data at the rising edge of the clock inverted signal CK_B, as in the conventional duty correction circuit 1 shown in FIG. A setup margin is ensured by using a latch circuit 21 that captures data in synchronization with CK.

  In other words, the duty of the input data DATA is corrected by inputting the clock signal CK as the operation clock and the input data DATA to the latch circuit 21 shown in FIG. Two signals which are signals and have a phase difference of 180 ° are outputted, and the logical sum of the output signal Latch_out of the latch circuit 21 and the input data DATA is calculated by the logic circuit 13.

Specifically, consider a case where the input data DATA is corrected so that the duty of the output signal OUT20 of the duty correction circuit 20 is 50%.
FIG. 5 is a timing chart showing waveforms of respective parts of the duty correction circuit 20. 5, (a) is the clock signal CK, (b) is the input data DATA, (c) is the output signal Latch_out of the latch circuit 21, and (d) is the output signal of the duty correction circuit 20 which is the output of the logic circuit 13. OUT20.

The input data DATA is a synchronization signal synchronized with the clock signal CK, and the difference between the HIGH level section and the LOW level section is detected by a counter, a frequency divider, a shift register, or the like that operates at the clock signal CK before the duty correction circuit. It is made to be for one clock.
Here, it is assumed that the input data DATA is a signal obtained by dividing the clock signal CK by 3, the HIGH level section is one clock of the operation clock CK, and the LOW level section is a signal of two operation clocks. .

By inputting the input data DATA to the latch circuit 21 and the operation clock CK, an output signal having a phase difference of 180 ° with respect to the input data DATA from the latch circuit 21 as shown in FIG. 5C. Latch_out can be taken out.
Then, by calculating the logical sum of the input data DATA and the output signal Latch_out by the logic circuit 13, as shown in FIG. 5D, the output signal OUT20 having a duty of 50% can be adjusted.

FIG. 6 is an enlarged timing chart of a part of FIG. 6A shows input data DATA, and FIG. 6B shows a clock signal CK.
In FIG. 6A, delay represents a delay time of switching of the input data DATA with respect to switching of the clock signal CK. The delay time delay in the input data DATA is such a short time that the flip-flop 11 does not need to eliminate the delay by synchronizing the input data DATA with the operation clock CK.

  Considering the setup margin in the duty correction circuit 20 having the configuration shown in FIG. 4, the phase is shifted by the flip-flop 12 using the clock inversion signal CK_B as shown in the timing chart of each part of the conventional duty correction circuit 1 shown in FIG. When a signal shifted by 180 ° is taken out, the data fetching timing is performed at the falling edge of the operation clock CK, which is about the interval T2, whereas the duty correction circuit 20 in the second embodiment using the latch circuit 21 is used. Then, as shown in FIG. 6, the setup margin is a section T21, which is a section T21 having a length equivalent to the setup margin section T1 of the flip-flop 11 in the conventional duty correction circuit 1 shown in FIG. That is, the setup margin in the flip-flop 12 is the interval T2 as shown in FIG. 12 and is about half a cycle of the clock signal CK, while the duty correction circuit 20 in the second embodiment is shown in FIG. The setup margin in the latch circuit 21 is the section T21, which is about one cycle. Therefore, a larger setup margin can be obtained as compared with the case where the flip-flop 12 using the clock inversion signal CK_B is used. Therefore, the second embodiment can obtain the same operation effect as the first embodiment, and the flip-flop for eliminating the data delay corresponding to the input data DATA with a small data delay. Therefore, the circuit area can be reduced and the circuit area can be reduced.

Next, a third embodiment of the present invention will be described.
FIG. 7 is a circuit diagram illustrating an example of the duty correction circuit 30 according to the third embodiment.
The duty correction circuit 30 according to the third embodiment includes a flip-flop (FF) 31 and a logic circuit (OR) 13.
The flip-flop 31 has a two-stage configuration of a latch in which a first latch circuit (LATCH1) 31a and a second latch circuit (LATCH2) 31b are connected in two stages. The flip-flop 31 receives the clock signal CK as an operation clock and also receives input data DATA synchronized with the clock signal CK. The input data DATA is input to the first latch circuit 31a.

The first latch circuit 31a receives the input data DATA and the clock signal CK, takes the input data DATA at the falling edge of the clock signal CK using the clock signal CK as an operation signal, and outputs the output signal L1.
The second latch circuit 31b receives the output signal L1 of the first latch circuit 31a and the clock signal CK, takes the output signal L1 at the rising edge of the clock signal CK using the clock signal CK as an operation signal, and outputs the output signal L2. To do.

Output signals L 1 and L 2 of the first and second latch circuits 31 a and 31 b are input to the logic circuit 13 as internal signals of the flip-flop 31.
The logic circuit 13 calculates the logical sum of the internal signals L 1 and L 2 of the flip-flop 31, and the output is output as the output signal OUT 30 of the duty correction circuit 30.
That is, in the duty correction circuit 30, the duty of the input data DATA is corrected by the logic circuit 13 provided in the subsequent stage for the input data DATA and the output having a phase difference of 180 ° with respect to the input data DATA. The logic circuit 13 calculates a logical sum using the internal signals L1 and L2 of the flip-flop 31 as input signals, thereby correcting the duty.

Specifically, by inputting a clock signal CK as an operation clock to the first and second latch circuits 31a and 31b, the flip-flop 31 makes the phase difference 180 ° with respect to the input data DATA 2. Two internal signals L1 and L2 are output, and both are calculated by the logic circuit 13 in the subsequent stage, whereby an output signal OUT30 having a duty of 50% is obtained.
That is, the conventional duty correction circuit 1 shown in FIG. 10 uses the flip-flop 12 that uses the clock inversion signal CK_B and captures data at the rising edge of the clock inversion signal CK_B, whereas the duty in the third embodiment. The correction circuit 30 secures a setup margin by using the second latch circuit 31b that captures data at the rising edge of the operation clock CK.

As a specific example, a case where correction is performed so that the duty of the output signal OUT30 is 50% will be described.
FIG. 8 shows a timing chart of each part when the duty of the input data DATA is corrected to 50% in the duty correction circuit 30 shown in FIG.
8, (a) is the clock signal CK, (b) is the input data DATA, (c) is the output signal L1 of the first latch circuit 31a, (d) is the output signal L2 of the second latch circuit 31b, (e ) Is an output signal OUT30 of the logic circuit 13, which is an output signal of the duty correction circuit 30.

  The input data DATA is a synchronization signal synchronized with the clock signal CK, and the difference between the HIGH level section and the LOW level section is detected by a counter, a frequency divider, a shift register, or the like that operates at the clock signal CK before the duty correction circuit. It is made to be for one clock. Here, when the input data DATA is a signal obtained by dividing the clock signal CK by 3, the HIGH level section is a signal corresponding to one clock of the clock signal CK, and the LOW level section is a signal corresponding to two clocks of the clock signal CK. Will be described.

  The input data DATA and the clock signal CK are input to the flip-flop 31, the input data DATA is input to the first latch circuit 31a of the first stage connected in two stages, and the first latch circuit 31a and the second latch are input. By taking out the output signals L1 and L2 of the circuit 31b, two signals having a phase shift with respect to the input data DATA and a phase difference of 180 ° are obtained. Then, by calculating the logical sum of the output signals L1 and L2 having a phase difference of 180 ° by the logic circuit 13 shown in FIG. 7, the duty becomes 50% as shown in the output signal OUT30 shown in FIG. Adjustments can be made as follows.

In the second latch circuit 31b, the data capture period is the timing at which the clock signal CK switches from the LOW level to the HIGH level, and therefore the setup margin is considered as follows.
A setup margin in the duty correction circuit 30 shown in FIG. 7 will be described with reference to FIG. FIG. 9 is an enlarged view of a part of FIG. 7, where (a) is input data DATA, (b) is an output signal L1 of the first latch circuit 31a, and (c) is a clock signal CK.

  As shown in FIG. 9, since the input data DATA capture timing at the first latch circuit 31a is the rising edge of the clock signal CK, the first latch circuit 31a is at the rising edge of the clock signal CK at time t35. Captures input data DATA. Therefore, the setup margin of the first latch circuit 31a is a section T31 from when the input data DATA is determined at time t32 to when the clock signal CK rises at time t35.

  On the other hand, since the second latch circuit 31b is the falling edge of the clock signal CK, the second latch circuit 31b takes in the output signal L1 at time t36. Therefore, the setup margin of the second latch circuit 31b is from the time when the output signal L1 is determined at the time t34 to the falling edge of the clock signal CK at the time t36, with the falling edge of the clock signal CK at the time t33. It becomes section T32. That is, it is equivalent to the setup margin of the flip-flop 11 in the conventional duty correction circuit 1 shown in FIG.

  As shown in FIG. 9, the second latch circuit 31b in the subsequent stage in the flip-flop 31 operates at the falling edge of the operation clock CK, but the output signal L1 from the latch circuit 31a in the previous stage is the falling edge of the clock signal. Therefore, the setup margin is a section T32 obtained by subtracting the delay time delay of the first latch circuit 31a from one cycle of the clock signal CK.

While the setup margin of the flip-flop 12 of the conventional duty correction circuit 1 is the section T2, the setup margin of the second latch circuit 31b of the duty correction circuit 30 in the present invention is about one cycle of the clock signal CK. Therefore, it can be seen that a larger setup margin can be secured as compared with the case where the flip-flop 12 using the clock inversion signal CK_B is used.
Therefore, in the third embodiment, the same operational effect as that of the first embodiment can be obtained.

  In each of the above embodiments, the input data DATA is a signal obtained by dividing the clock signal CK by 3, the H section is a signal corresponding to one clock of the operation clock CK, and the L section is a signal corresponding to two clocks of the operation clock CK. The case where the input data DATA is corrected so that the DUTY is 50% has been described, but the present invention is not limited to this. The signal does not have to be divided by three, and is not limited to the case where the correction is made so that the DUTY is 50%. The input data DATA having other characteristics can be applied. If the input data DATA has a difference of one clock between the H section and the L section, it can be corrected to be an arbitrary DUTY.

  In that case, a logic circuit may be appropriately selected as a combinational circuit in accordance with the input data DATA. For example, the input data DATA is a synchronization signal synchronized with a clock signal generated by a counter, a frequency divider, a shift register, or the like that operates in synchronization with the clock signal CK, and the HIGH level interval is compared with the LOW level interval. When the signal is shortened by one clock, a combinational circuit for adding the output signals FF1_out and Latch_out of the flip-flop 11 and the latch circuit 21, such as a logic circuit (OR) 13, as shown in FIG. Is used. Further, for example, the input data DATA is a synchronization signal synchronized with the clock signal CK generated by a counter, a frequency divider, a shift register or the like that operates in synchronization with the clock signal CK, and the HIGH level section is compared with the LOW level section. When the signal is longer by one clock, a combinational circuit that subtracts the output signals FF1_out and Latch_out from the flip-flop 11 and the latch circuit 21, such as a logical circuit (AND) that calculates a logical product, is used. Use it.

1, 10, 20, 30 Duty correction circuit 11, 12 Flip flop 13 Logic circuit 14 Inverter 21 Latch circuit 31 Flip flop 31a First latch circuit 31b Second latch circuit

Claims (9)

A duty correction circuit for correcting the duty of input data,
A latch circuit that receives the input data and operates in synchronization with a clock signal to latch the input data;
A duty correction circuit comprising: a combinational circuit that performs a logical operation determined on the input data and a latch circuit output output from the latch circuit based on a correction content of a duty of the input data. The input data is input, and has a flip-flop that adjusts the phase of the input data to a signal synchronized with a clock signal,
2. The duty correction circuit according to claim 1, wherein the latch circuit delays the input data after phase adjustment by the flip-flop. A duty correction circuit for correcting the duty of input data,
A first latch circuit that receives the input data and operates in synchronization with the clock signal to delay the input data;
A second latch circuit that receives the first latch circuit output output from the first latch circuit and operates in synchronization with the clock signal to delay the first latch circuit output;
A combinational circuit that performs a logical operation on the first latch circuit output and the second latch circuit output output from the second latch circuit,
The duty correction circuit, wherein the combinational circuit performs a logical operation determined based on a duty of the input data.   4. The duty correction circuit according to claim 3, wherein the first latch circuit and the second latch circuit constitute a flip-flop.   5. The duty correction circuit according to claim 1, wherein the input data includes a counter, a frequency divider, or a shift register that operates in synchronization with the clock signal. 6.   6. The duty correction according to claim 1, wherein the input data is data in which a HIGH level section is shorter by one clock of the clock signal than a LOW level section. circuit.   The duty correction circuit according to claim 6, wherein the combinational circuit is a circuit that calculates a logical sum.   6. The duty correction according to claim 1, wherein the input data is data in which a HIGH level section is longer by one clock of the clock signal than a LOW level section. 7. circuit.   9. The duty correction circuit according to claim 8, wherein the combinational circuit is a circuit that calculates a logical product.

Images