JP2010118143A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable delay circuit capable of setting a predetermined delay time.
The variable delay circuit includes a first delay circuit, a second delay circuit, a detection circuit, and a selection circuit. The first delay circuit 6 is configured by cascading a plurality of first delay stages 6a, and receives an input signal at the first stage. The second delay circuit 7 is configured by cascading a plurality of second delay stages 7a identical to the first delay stage 6a, and receives the first timing signal at the first stage. The detection circuit 8 receives the second timing signal and obtains a delay timing signal having a transition edge adjacent to the transition edge of the second timing signal among the delay timing signals output from the second delay stages 7a. The selection circuit 9 selects a delay signal output from the first delay stage corresponding to the second delay stage that outputs the delay timing signal obtained by the detection circuit 8.
[Selection] Figure 2

Description

  The present invention relates to a variable delay circuit capable of setting a delay time to a predetermined value.

  The speed of semiconductor integrated circuits is constantly increasing due to the development of semiconductor manufacturing technology. In particular, the operating frequency of logic LSIs such as microcomputers has been improving year by year, and the difference from the operating frequency of memory LSIs such as DRAMs has been increasing. In order to reduce this gap, high-speed DRAMs such as EDO DRAM (Extended Data Output DRAM), SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate Synchronous DRAM), and Direct RDRAM (Rambus DRAM) have been developed.

  This type of high-speed DRAM makes it possible to read and write data to these memory cells at high speed by sequentially accessing memory cells connected to the same word line. DRAMs with a maximum operating frequency exceeding 100 MHz have been developed. The high-speed DRAM is often used for main memories of personal computers and workstations.

JP 9-46197 A

  By the way, this type of high-speed DRAM is used not only as a personal computer and a workstation, but also as a component of a microcomputer application product or the like. In that case, the operating frequency is determined according to the specifications of each product. For this reason, the operating frequency of the high-speed DRAM used for such an application may be 50 MHz or 75 MHz, for example, when the maximum operating frequency is 133 MHz. As described above, when the high-speed DRAM is operated at a frequency lower than the maximum operating frequency, the following problems occur.

  FIG. 31A shows the read timing when the period of the CLK signal is 20 ns (50 MHz). For example, after receiving an active command ACTV that activates a row address circuit, the SDRAM performs a read operation by receiving a read command RD that activates a column address circuit. In the following description, each command is referred to as an ACTV command, an RD command, or the like.

  In this SDRAM, the minimum time of tRCD (/ RAS to / CAS Delay time) is set to 18 ns. tRCD is the time from when an ACTV command is received until a column command such as an RD command is received. The minimum time of tCAC (/ CAS Accesses time from Clock) is 14 ns. tCAC is the time from when a column command is received until the read data is output. tRCD, tCAC, and tAC shown in FIG. 31 (b) are regulations necessary for correct operation of the SDRAM, and each value does not depend on the operating frequency in the same product. In the following description, the clock signal CLK is referred to as a CLK signal.

  When operating SDRAM at 50MHz, the minimum time of tRCD (18ns) is smaller than the period of CLK signal (20ns). Therefore, the SDRAM can accept the RD command at the rising edge (20 ns) of the CLK signal next to the CLK signal that accepted the ACTV command. tRCD is actually 20ns. Further, the minimum time of tCAC (14 ns) is shorter than the period of the CLK signal (20 ns). Therefore, the SDRAM outputs the read data QA0 after tCAC (14 ns) from the rising edge of the CLK signal that accepted the RD command. As a result, the access time tRAC (/ RAS Access time from Clock) from the reception of the ACTV command to the output of the read data QA0 is 34 ns (tCLK + tCAC).

  On the other hand, FIG. 31B shows the read timing when the period of the CLK signal is 13 ns (about 75 MHz). Here, the maximum time of tAC (Access time from Clock) is set to 6 ns. tAC is the time from the rising edge of the clock signal CLK until the read data is output.

  When operating SDRAM at 75 MHz, the minimum time of tRCD (18 ns) is longer than the period of the CLK signal (13 ns). Therefore, after receiving the ACTV command, the SDRAM receives the RD command at the rising edge (26 ns) of the second CLK signal. tRCD is actually 26ns. Further, the minimum time of tCAC (14 ns) is longer than the period of the CLK signal (13 ns). Therefore, the SDRAM outputs the read data QA0 after tAC (6 ns) from the rising edge of the CLK signal next to the CLK signal that has received the RD command. As a result, the access time tRAC becomes 45 ns (3 · tCLK + tAC).

  Thus, in the above read operation, the access time tRAC becomes longer when the frequency of the CLK signal is higher. That is, the higher the frequency of the CLK signal, the lower the data bus occupation rate. Here, the bus occupation ratio is a ratio at which valid data is transmitted on the data bus in a predetermined period. For this reason, if the bus occupancy is low, the performance of the entire system is degraded.

  FIG. 32A shows the precharge operation after the ACTV command when the cycle of the clock signal CLK is 20 ns (50 MHz). The precharge operation is an operation of charging a bit line to a predetermined potential and inactivating a row address circuit.

  In this SDRAM, the minimum time of tRAS (/ RAS active time) is 24 ns. tRAS is the time from when the ACTV command is received until the precharge command PRE is received. The minimum time of tRP (/ RAS Precharge time) is set to 10 ns. tRP is the time from when the PRE command is received until the next ACTV command is received. tRAS, tRP, and tDPL shown in FIG. 32 (b) are regulations necessary for correct operation of the SDRAM, and each value does not depend on the operating frequency for the same product.

  When the SDRAM is operated at 50 MHz, the minimum time of tRAS (24 ns) is longer than the period of the CLK signal (20 ns). Therefore, the SDRAM receives the PRE command at the rising edge (40 ns) of the second CLK signal after receiving the ACTV command. tRAS is actually 40ns. The SDRAM executes a precharge operation within a period of tRP (10 ns) after receiving the PRE command. Therefore, the cycle time tRC (/ RAS Cycle time) from acceptance of the ACTV command to acceptance of the next ACTV command is 60 ns (3 · tCLK).

  On the other hand, FIG. 32B shows a write operation involving a precharge operation when the cycle of the clock signal CLK is 20 ns (50 MHz). Here, the WRA command (WRite with Auto-precharge) is a command for causing the SDRAM to automatically execute the precharge operation after the write operation. The minimum time of tRCD is set to 18 ns, which is the same as the normal read command RD (FIG. 31) and write command WR (not shown). The minimum time of tDPL (Data-in to Precharge Lead time) is set to 10 ns. tDPL is the time from when the write data is received until the precharge command PRE is received.

  When the SDRAM is operated at 50 MHz, the minimum time (18 ns) of tRCD is shorter than the period (20 ns) of the CLK signal, as in FIG. Therefore, the SDRAM can accept the WRA command at the rising edge (20 ns) of the CLK signal next to the CLK signal that accepted the ACTV command.

  The SDRAM captures write data (not shown) at the same time as the WRA command, and writes the captured data into the memory cell within the tDPL period. Thereafter, the SDRAM executes a precharge operation within the period of tRP. The sum of tDPL and tRP is 20 ns, which is the same as one cycle of the CLK signal. Therefore, the next ACTV command can be received at the rising edge (40 ns) of the CLK signal next to the CLK signal that has received the WRA command. Therefore, the cycle time tRC (/ RAS Cycle time) from acceptance of the ACTV command to acceptance of the next ACTV command is 40 ns (2.tCLK).

  Thus, the cycle time tRC is shorter when the precharge operation is performed together with the write operation than when the precharge operation is performed alone. That is, there is a problem that the complicated operation becomes faster.

  FIG. 33 shows another timing of the precharge operation of the SDRAM. FIG. 33A shows the precharge operation after the ACTV command when the cycle of the clock signal CLK is 13 ns (75 MHz).

  When SDRAM is operated at 75 MHz, the minimum time of tRAS (24 ns) is longer than the period of the CLK signal (13 ns). Therefore, after receiving the ACTV command, the SDRAM receives the PRE command at the rising edge (26 ns) of the second CLK signal. tRAS is actually 26ns. The SDRAM executes a precharge operation within a period of tRP (10 ns) after receiving the PRE command. Therefore, the cycle time tRC (/ RAS Cycle time) from acceptance of the ACTV command to acceptance of the next ACTV command is 39 ns (3 · tCLK).

  On the other hand, FIG. 33B shows a write operation involving a precharge operation when the cycle of the clock signal CLK is 13 ns (75 MHz). When operating SDRAM at 75MHz, the minimum time of tRCD (18ns) is longer than the period of CLK signal (13ns). Therefore, after receiving the ACTV command, the SDRAM receives the WRA command at the rising edge (26 ns) of the second CLK signal. The SDRAM takes in write data (not shown) at the same time as the WRA command, and writes the fetched data into memory cells within the tDPL period. Thereafter, the SDRAM executes a precharge operation within the period of tRP. The sum of tDPL and tRP is 20 ns, which is greater than one period of the CLK signal. Therefore, after receiving the WRA command, the next ACTV command can be received at the rising edge (52 ns) of the second CLK signal. Therefore, the cycle time tRC (/ RAS Cycle time) from acceptance of the ACTV command to acceptance of the next ACTV command is 52 ns (4 · tCLK).

  At the timings of FIG. 32B and FIG. 33B, there is a problem that the higher the frequency of the CLK signal, the slower the write operation. As a result, also in the write operation, the bus occupancy becomes lower as the frequency of the CLK signal is higher.

  At the operation timing when the frequency is high (FIG. 33), the cycle time tRC for executing the precharge operation together with the write operation is longer than the cycle time tRC for executing the precharge operation alone. This is opposite to the operation timing when the frequency is low (FIG. 32). That is, the cycle time tRC required for each operation does not depend on the frequency level. For this reason, there is a problem that it is difficult to perform timing design when this type of high-speed DRAM mounted on a microcomputer application product or the like is operated at a frequency lower than the maximum operating frequency.

  An object of the present invention is to provide a variable delay circuit capable of setting a predetermined delay time.

  FIG. 1 is a block diagram showing the basic principle of a semiconductor integrated circuit related to the present invention. The semiconductor integrated circuit includes a plurality of memory cells MC connected to word lines, a row control circuit 1, a column control circuit 3, a command control circuit 2, and a timing adjustment circuit 4.

  In this semiconductor integrated circuit, when a read operation or a write operation of the memory cell MC is executed, first, the row control circuit 1 operates to activate a predetermined word line. Next, the command control circuit 2 receives the column operation command in synchronization with the clock signal and operates the column control circuit 3. Here, the timing adjustment circuit 4 has a function of making the delay time from the reception of the column operation command to the start of the operation of the column control circuit 3 variable. The column control circuit 3 receives the control of the timing adjustment circuit 4 and starts operation after a predetermined delay time from the reception of the column operation command. Then, the read operation or the write operation of the memory cell MC selected by the activation of the word line is executed.

  As described above, by delaying the operation of the column control circuit 3, it is possible to execute the read operation or write operation of the memory cell MC at the optimum timing according to the operation timing of the internal circuit without depending on the cycle of the clock signal. As a result, the number of command receptions per unit time increases, and the bus occupancy rate of read data and write data can be improved. Further, since the column control circuit 3 operates at an optimum timing according to the operation timing of the internal circuit, the read cycle time and the write cycle time can be shortened.

  In the semiconductor integrated circuit, the timing adjustment circuit 4 sets a predetermined delay time according to the latency. Here, the latency is the number of clocks from receipt of a column operation command to execution of a read operation or a write operation, and is set according to the frequency of the clock signal to be used. For this reason, the column control circuit 3 can execute the read operation and the write operation at the optimum timing according to the frequency of the clock signal.

  The timing adjustment circuit 4 only needs to change the delay time according to the latency, and is configured by a simple delay circuit or the like. Further, the semiconductor integrated circuit includes a plurality of memory cells connected to the bit line, a precharge circuit 5, a command control circuit 2, and a timing adjustment circuit 4.

  In this semiconductor integrated circuit, when executing a precharge operation for setting a bit line to a predetermined potential, first, the command control circuit 2 receives a precharge command in synchronization with a clock signal and operates the precharge circuit 5. Here, the timing adjustment circuit 4 has a function of making the delay time from the reception of the precharge command to the start of the operation of the precharge circuit 5 variable. The precharge circuit 5 receives the control of the timing adjustment circuit 4 and starts operation after a predetermined delay time from the reception of the precharge command. Then, a precharge operation is performed.

  In this way, by delaying the operation of the precharge circuit 5, the precharge operation can be executed at an optimum timing according to the operation timing of the internal circuit without depending on the cycle of the clock signal. As a result, the number of command receptions per unit time can be increased. Therefore, it is possible to improve the bus occupation ratio of read data and write data. Further, since the precharge circuit 5 operates at an optimal timing according to the operation timing of the internal circuit, the precharge cycle time can be shortened.

  In the method for controlling a semiconductor integrated circuit, when a read operation or a write operation of the memory cell MC is executed, first, the row control circuit 1 operates to activate a predetermined word line. Next, in response to the column operation command in synchronization with the clock signal, the column control circuit 3 operates. Here, the delay time from the reception of the column operation command to the start of the operation of the column control circuit 3 is made variable. Therefore, the operation of the column control circuit 3 is started after a predetermined delay time from the reception of the column operation command. Then, the read operation or the write operation of the memory cell MC selected by the activation of the word line is executed.

  As described above, by delaying the operation of the column control circuit 3, it is possible to execute the read operation or write operation of the memory cell MC at the optimum timing according to the operation timing of the internal circuit without depending on the cycle of the clock signal. As a result, the number of command receptions per unit time increases, and the bus occupancy rate of read data and write data can be improved. In addition, since the column control circuit 3 operates at an optimum timing according to the operation timing of the internal circuit, the read operation and the write operation can be executed at high speed.

  FIG. 2 is a block diagram showing the basic principle of the present invention. The variable delay circuit includes a first delay circuit 6, a second delay circuit 7, a detection circuit 8, and a selection circuit 9. The first delay circuit 6 is configured by cascading a plurality of first delay stages 6a, and receives an input signal at the first stage. The second delay circuit 7 is configured by cascading a plurality of second delay stages 7a identical to the first delay stage 6a, and receives the first timing signal at the first stage.

  The detection circuit 8 receives the second timing signal and obtains a delay timing signal having a transition edge adjacent to the transition edge of the second timing signal among the delay timing signals output from the second delay stages 7a. The selection circuit 9 selects a delay signal output from the first delay stage corresponding to the second delay stage that outputs the delay timing signal obtained by the detection circuit 8.

  As a result, the input signal can be delayed by the time from the transition edge of the first timing signal to the transition edge of the second timing signal. Further, the delay time of the input signal can be adjusted by operating the detection circuit 8 as necessary. That is, power consumption can be reduced by controlling the detection frequency of the detection circuit 8 from the outside.

  In the variable delay circuit of the present invention, the input signal can be delayed by the time from the transition edge of the first timing signal to the transition edge of the second timing signal. Power consumption can be reduced by controlling the detection frequency of the detection circuit from the outside.

It is a block diagram which shows the basic principle of the semiconductor integrated circuit relevant to this invention. It is a block diagram which shows the basic principle of this invention. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit and a semiconductor integrated circuit control method related to the present invention; FIG. 4 is a circuit diagram illustrating the timing adjustment circuit of FIG. 3. FIG. 4 is a circuit diagram showing another timing adjustment circuit of FIG. 3. FIG. 5 is a timing diagram illustrating a read operation and a precharge operation of the SDRAM according to the first embodiment. FIG. 6 is a timing chart showing another example of the SDRAM read operation and precharge operation in the first embodiment. FIG. 5 is a timing diagram illustrating a precharge operation of the SDRAM according to the first embodiment. FIG. 6 is a timing chart showing another example of the SDRAM precharge operation in the first embodiment. FIG. 6 is a timing diagram illustrating a write operation involving a precharge operation of the SDRAM according to the first embodiment. FIG. 10 is a timing diagram illustrating another example of a write operation involving a precharge operation of the SDRAM according to the first embodiment. FIG. 5 is a timing chart showing a write operation and a precharge operation of the SDRAM in the first embodiment. FIG. 6 is a timing chart showing a burst read operation of the SDRAM in the first embodiment. It is a block diagram which shows 2nd Embodiment of the control method of the semiconductor integrated circuit and semiconductor integrated circuit relevant to this invention. FIG. 10 is a timing chart showing a burst read operation of the SDRAM in the second embodiment. It is a block diagram which shows 3rd Embodiment of the semiconductor integrated circuit relevant to this invention and the control method of a semiconductor integrated circuit, and one Embodiment of the variable delay circuit of this invention. FIG. 17 is a circuit diagram showing the timing control circuit of FIG. 16. FIG. 17 is a timing chart showing an operation of the timing control circuit of FIG. 16. FIG. 17 is a circuit diagram illustrating the timing adjustment circuit of FIG. 16. FIG. 20 is a timing chart showing the operation of the timing adjustment circuit of FIG. 19. FIG. 10 is a timing diagram illustrating a burst read operation of an SDRAM according to a third embodiment. FIG. 10 is a timing diagram illustrating a precharge operation of an SDRAM according to a third embodiment. FIG. 10 is a timing chart showing another example of the SDRAM precharge operation in the third embodiment. FIG. 10 is a timing diagram illustrating a write operation and a precharge operation of an SDRAM according to a third embodiment. FIG. 10 is a timing chart showing another example of the SDRAM precharge operation in the third embodiment. It is a block diagram which shows 4th Embodiment of the semiconductor integrated circuit relevant to this invention, the control method of a semiconductor integrated circuit, and one Embodiment of the variable delay circuit of this invention. FIG. 27 is a timing diagram illustrating an operation of the timing adjustment circuit of FIG. 26. FIG. 10 is a timing diagram illustrating a burst read operation of an SDRAM according to a fourth embodiment. It is a circuit diagram which shows another example of a timing adjustment circuit. FIG. 30 is a timing diagram illustrating an operation of the timing adjustment circuit of FIG. 29. FIG. 10 is a timing diagram showing a conventional SDRAM read operation. FIG. 10 is a timing diagram illustrating a precharge operation of a conventional SDRAM. It is a timing diagram which shows another example of the precharge operation | movement of the conventional SDRAM.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the signal line shown with the thick line in each drawing has shown that it is comprised by multiple pieces. A part of the circuit to which the thick line is connected is composed of a plurality of elements.

  FIG. 3 shows a first embodiment of a semiconductor integrated circuit and a method for controlling the semiconductor integrated circuit related to the present invention. The semiconductor integrated circuit of this embodiment is formed as an SDRAM on a silicon substrate using a CMOS process technology. The semiconductor integrated circuit includes an input / output control unit 10, a chip control unit 12, and a memory core unit 14.

  The input / output control unit 10 includes a plurality of input buffers 16a, 16b, and 16c, and latches 18a and 18b. The input buffer 16a receives the command signal CMD and outputs the received signal as an internal command signal ICMD. The input buffer 16b receives a clock signal CLK from the outside and outputs the received signal as an internal clock signal ICLK. The input buffer 16c receives the address signal AD and outputs the received signal as the internal address signal IAD.

  The latch 18a captures the internal command signal ICMD in synchronization with the internal clock signal ICLK, and outputs the captured signal as a latch command signal LCMD. The latch 18b captures the internal address signal IAD in synchronization with the internal clock signal ICLK, and outputs the captured signal as the latch address signal LAD. In the following description, each signal name may be abbreviated such that “command signal CMD” is “CMD signal” and “clock signal CLK” is “CLK signal”.

  The chip control unit 12 includes a command decoder 20, a timing adjustment circuit 22, a timing control circuit 24, a RAS latch 26, a CAS latch 28, a burst latch 30, a burst address generator 32, predecoders 34 and 36, a burst control circuit 38, a timing Adjustment circuits 40 and 42 and a timing control circuit 44 are provided.

  The command decoder 20 corresponds to the command control circuit 2 shown in FIG. The RAS latch 26, the predecoder 34, and the timing control circuit 24 correspond to the row control circuit 1 shown in FIG. The CAS latch 28, burst latch 30, burst address generator 32, predecoder 36, and timing control circuit 44 correspond to the column control circuit 3 shown in FIG.

  The command decoder 20 receives the latch command signal LCMD, decodes the command, and generates command signals ACT, RW, PCH, etc. for controlling the basic operation of the chip. Here, the ACT signal is generated when the CMD signal for activating the word line is supplied. The RW signal is generated when a CMD signal corresponding to a read operation and a write operation is supplied. The RW signal is a signal corresponding to the column operation command shown in FIG. The PCH signal is generated when the CMD signal corresponding to the precharge operation is supplied. The PCH signal is a signal corresponding to the precharge command shown in FIG.

  The timing adjustment circuit 22 receives the latency signal CL and the PCH signal, delays the PCH signal according to the latency signal CL, and outputs the delayed signal as a delayed precharge signal PCH2. Here, the latency signal CL corresponds to a CAS latency value set in a mode register (not shown) or the like. CAS latency is the number of clocks of the CLK signal from receiving a read command to outputting read data. In this embodiment, the CAS latency is set to “1” when a 50 MHz CLK signal is used, and at this time, the CL signal becomes L level. When using a 75 MHz CLK signal, the CAS latency is set to “2”. At this time, the CL signal becomes H level.

  The timing control circuit 24 receives the PCH2 signal and the auto precharge signal APCH from the timing control circuit 44, and outputs row timing signals RTIM1 and RTIM2 for controlling a row address system circuit.

  The RAS latch 26 takes in the row address signal out of the LAD signal in synchronization with the RTIM1 signal, and outputs the taken signal as the row address signal RASAD. The CAS latch 28 captures the LAD signal in synchronization with the timing signal EXTPZ from the timing adjustment circuit 40, and outputs the captured signal as the column address signal CASAD.

  The burst latch 30 captures the burst address BAD in synchronization with the timing signal INTPZ from the timing adjustment circuit 42, and outputs the captured signal as a CASAD signal. The burst address generator 32 receives the CASAD signal, increments the received address signal by 1, and outputs it as a BAD signal.

  The predecoder 34 receives the RASAD signal, generates a decode signal, and outputs this decode signal to the row decoder 48 of the memory core unit 14. The predecoder 36 receives the CASAD signal, generates a decode signal, and outputs the decode signal to the column decoder 52 of the memory core unit 14. The burst control circuit 38 takes in the RW signal in synchronization with the ICLK signal and outputs the burst control signal BCN.

  The timing adjustment circuit 40 receives the CL signal and the RW signal, delays the RW signal according to the CL signal, and outputs the delayed signal as the timing signal EXTPZ. The timing adjustment circuit 42 receives the CL signal and the BCN signal, delays the BCN signal according to the CL signal, and outputs it as a timing signal INTPZ. Here, the EXTPZ signal is generated based on an externally supplied command signal, and the INTPZ signal is generated based on an internally generated burst control signal BCN. The timing control circuit 44 receives the timing signals EXTPZ and INTPZ, and outputs an auto precharge signal APCH and a column timing signal CTIM1.

  The memory core unit 14 includes a memory cell unit 46 having a plurality of memory cells MC, a row decoder 48, a sense amplifier 50, and a column decoder 52. The memory core unit 14 has a bit line and a precharge circuit (not shown). The row decoder 48 has a function of receiving a RTIM2 signal and a predecode signal from the predecoder 34 and activating a word line (not shown) connected to the memory cell. The column decoder 52 has a function of receiving a CTIM1 signal and a predecode signal from the predecoder 36 and controlling a column switch (not shown) connected to the bit line. The sense amplifier 50 amplifies data transmitted from the memory cell MC via the bit line, and outputs the amplified signal to the output circuit.

  FIG. 4 shows details of the timing adjustment circuit 22. The timing adjustment circuit 22 includes delay circuits 54 and 56 and a combinational circuit 58. The delay circuit 54 is configured by arranging four CR time constant circuits 54b between six inverters 54a connected in cascade. The delay circuit 56 is configured by arranging two CR time constant circuits 56b between four cascaded inverters 56a. The CR time constant circuits 54b and 56b include, for example, a diffusion resistor and a MOS capacitor in which the source and drain of nMOS are connected to the ground line VSS. The delay circuits 54 and 56 both receive the PCH signal and output the delayed signal to the combinational circuit 58.

  The combinational circuit 58 includes two-input NAND gates 58a and 58b that connect the outputs of the delay circuit 54 and the delay circuit 56, respectively, and a two-input NAND gate 58c that outputs the logical sum of the outputs of the NAND gates 58a and 58b as a PCH2 signal. And an inverter 58d. The NAND gate 58a is supplied with the inverted logic of the CL signal via the inverter 58d. A CL signal is supplied to the NAND gate 58b. The combinational circuit 58 delays the received PCH signal by the delay circuit 54 when the CL signal is at the L level and outputs it as a PCH2 signal, and delays the received PCH signal by the delay circuit 56 when the CL signal is at the H level. This circuit outputs as a PCH2 signal. In this embodiment, the PCH2 signal is delayed by 4 ns with respect to the PCH signal when the CL signal is at the L level, and is delayed by 2 ns with respect to the PCH signal when the CL signal is at the H level.

  FIG. 5 shows details of the timing adjustment circuits 40 and 42. The timing adjustment circuits 40 and 42 include a delay circuit 60 and a combination circuit 58. In the delay circuit 60, a plurality of CR time constant circuits 60b are arranged between an even number of cascade-connected inverters 60a. The CR time constant circuit 60b includes, for example, a diffusion capacitor and a MOS capacitor in which an nMOS source and drain are connected to a ground line VSS. The delay circuit 60 receives the PCH signal and outputs the delayed signal to the combinational circuit 58.

  The timing adjustment circuits 40 and 42 output the received PCH signal as the PCH2 signal without delay when the CL signal is at the L level, and the received PCH signal is output by the delay circuit 60 when the CL signal is at the H level. This is a circuit for delaying and outputting as a PCH2 signal. In this embodiment, when the CL signal is at the H level, the timing adjustment circuits 40 and 42 delay the EXTPZ signal (or INTPZ signal) by 5 ns with respect to the RW signal (or BCN signal).

  Next, the operation of the SDRAM described above will be described. FIG. 6 shows the SDRAM read operation and precharge operation when the period of the CLK signal is 20 ns (50 MHz). In this embodiment, the minimum time of tRCDEX that is an external specification is set to 13 ns, and the minimum time of tRCDIN that is an internal specification is set to 18 ns. Here, the external specification is a value that must be observed by a user who uses the SDRAM, and the internal specification is an ability value of the chip. Further, the minimum time of tCAC and the minimum time of tRP are set to 14 ns and 10 ns, respectively, which are the same as the conventional one. In the case of 50 MHz, since the CAS latency is “1”, the CL signal is set to the L level.

  First, the latches 18a and 18b shown in FIG. 3 take in the ACTV command and the row address signal AD (AR0) in synchronization with the rising edge of the CLK signal (ICLK signal), respectively, and the latch command signal LCMD and the latch address signal LAD. (FIG. 6 (a)). The command decoder 20 receives the LCMD signal and activates the PCH signal. Then, the timing control circuit 24, the RAS latch 26, and the predecoder 34 operate to activate the row decoder. The minimum time (13 ns) of tRCDEX is smaller than the period of the CLK signal (tCK = 20 ns). Therefore, the SDRAM can accept the RD command at the rising edge (20 ns) of the CLK signal next to the CLK signal that accepted the ACTV command.

  The latches 18a and 18b take in the RD command and the column address signal AD (AC0) in synchronization with the rising edge (20 ns) of the CLK signal (ICLK signal), and output them as the latch command signal LCMD and the latch address signal LAD ( FIG. 6 (b)). In response to the RD command, the command decoder 20 activates the RW signal (FIG. 6 (c)).

  The timing adjustment circuit 40 shown in FIG. 5 receives the RW signal and outputs the received signal as an EXTPZ signal without delay (FIG. 6 (d)). The CAS latch 28 shown in FIG. 3 takes in the LAD signal in synchronization with the EXTPZ signal and outputs the taken signal as the CASAD signal (FIG. 6 (e)). Then, the timing control circuit 44 and the predecoder 36 operate to activate the column decoder. Thereafter, the data read from the memory cell MC is amplified by the sense amplifier 50 and output as read data DOUT0 from the data input / output terminal DQ via the output circuit (FIG. 6 (f)). As a result, the access time tRAC from the acceptance of the ACTV command to the output of the read data DOUT0 is 34 ns (tCLK + tCAC), which is the same as the conventional one. The latches 18a and 18b take in the PRE command in synchronization with the rising edge (40 ns) of the next CLK signal. In response to the PRE command, the command decoder 20 activates the PCH signal (FIG. 6 (g)).

  The timing adjustment circuit 22 shown in FIG. 4 delays the PCH signal by 4 ns and outputs it as a PCH2 signal (FIG. 6 (h)). The timing control circuit 24 receives the PCH2 signal and controls the precharge operation. The precharge operation is executed within a period of tRP (10 ns). Therefore, the SDRAM can fetch the next ACTV command in synchronization with the rising edge (60 ns) of the next CLK signal.

  FIG. 7 shows the SDRAM read operation and precharge operation when the period of the CLK signal is 13 ns (75 MHz). The minimum time of tRCDEX (13 ns), the minimum time of tRCDIN (18 ns), and the minimum time of tRP (10 ns) are the same as in FIG. The maximum time for tAC is 6 ns. In the case of 75 MHz, since the CAS latency is “2”, the CL signal is set to the H level.

  First, as in FIG. 6, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. The minimum time (13 ns) of tRCDEX is the same as the period (13 ns) of the CLK signal. Therefore, the SDRAM can accept the RD command at the rising edge (13 ns) of the CLK signal next to the CLK signal that accepted the ACTV command.

  Similarly to FIG. 6, the SDRAM activates the RW signal in response to the RD command (FIG. 7 (a)). The timing adjustment circuit 40 shown in FIG. 5 receives the RW signal, delays the received signal by 5 ns, and outputs it as an EXTPZ signal (FIG. 7B). By delaying the EXTPZ signal by 5 ns by the timing adjustment circuit 40, tRCDIN (18 ns) larger than one period (tCK = 13 ns) of the CLK signal can be satisfied. Thereafter, as in FIG. 6, the read data DOUT0 is output (FIG. 7 (c)).

  As a result, the access time tRAC from the reception of the ACTV command to the output of the read data DOUT0 is 32 ns (tCLK + tCAC), which is 13 ns faster than the prior art. Since tRAC is shortened, the data bus occupancy rate is greatly improved. That is, the performance of a system using SDRAM is improved.

  The SDRAM receives the PRE command in synchronization with the next rising edge (26 ns) of the CLK signal and activates the PCH signal (FIG. 7 (d)). The timing adjustment circuit 22 shown in FIG. 4 delays the PCH signal by 2 ns and outputs it as a PCH2 signal (FIG. 7 (e)). The timing control circuit 24 receives the PCH2 signal and controls the precharge operation. The precharge operation is executed within a period of tRP (10 ns). For this reason, the SDRAM can receive the next ACTV command in synchronization with the rising edge (39 ns) of the next CLK signal. The reason why the PCH2 signal is delayed by 4 ns and 2 ns will be described with reference to FIGS.

  FIG. 8 shows the precharge operation of the SDRAM when the period of the CLK signal is 20 ns (50 MHz). In this embodiment, the minimum time of tRASEX that is an external specification is set to 20 ns, and the minimum time of tRASIN that is an internal specification is set to 24 ns. First, as in FIG. 6, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG.

  The minimum time (20 ns) of tRASEX is the same as the period (20 ns) of the CLK signal. Therefore, the SDRAM can accept the PRE command at the rising edge (20 ns) of the CLK signal next to the CLK signal that accepted the ACTV command. As in FIG. 6, the SDRAM receives the PRE command and activates the PCH signal (FIG. 8 (a)).

  The timing adjustment circuit 22 shown in FIG. 4 receives the PCH signal, delays the received signal by 4 ns, and outputs it as a PCH2 signal (FIG. 8B). By delaying the PCH2 signal by 4 ns by the timing adjustment circuit 22, tRASIN (24 ns) larger than one period (tCK = 20 ns) of the CLK signal can be satisfied. Thereafter, as in FIG. 6, the timing control circuit 24 receives the PCH2 signal and controls the precharge operation. The precharge operation is executed within a period of tRP (10 ns). For this reason, the SDRAM can receive the next ACTV command in synchronization with the rising edge (40 ns) of the next CLK signal. As a result, the cycle time tRC from the reception of the ACTV command to the reception of the next ACTV command is 40 ns (2 · tCLK), which is one clock shorter than the conventional one.

  FIG. 9 shows the precharge operation of the SDRAM when the period of the CLK signal is 13 ns (75 MHz). Note that the minimum times of tRASEX and tRASIN are set to 20 ns and 24 ns, respectively, as in FIG.

  First, as in FIG. 6, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. The minimum time (20 ns) of tRASEX is shorter than two periods (26 ns) of the CLK signal. Therefore, the SDRAM can accept the PRE command at the rising edge (26 ns) of the second CLK signal from the CLK signal that accepted the ACTV command. As in FIG. 6, the SDRAM receives the PRE command and activates the PCH signal (FIG. 9 (a)).

  The timing adjustment circuit 22 shown in FIG. 4 delays the PCH signal by 2 ns and outputs it as a PCH2 signal (FIG. 9B). For this reason, the activation timing of the PCH2 signal satisfies tRASIN (24 ns). Thereafter, as in FIG. 6, the timing control circuit 24 receives the PCH2 signal and controls the precharge operation. The precharge operation is executed within a period of tRP (10 ns). The precharge operation is completed by the next rising edge (39 ns) of the CLK signal. For this reason, the SDRAM can receive the next ACTV command in synchronization with the rising edge (39 ns) of the next CLK signal. As a result, the cycle time tRC (/ RAS Cycle time) from the reception of the ACTV command to the reception of the next ACTV command is 39 ns (3 · tCLK), which is the same as the conventional case, although the timing adjustment circuit 22 is added.

  FIG. 10 shows a write operation accompanied by a precharge operation of the SDRAM when the period of the CLK signal is 20 ns (50 MHz). In this embodiment, the minimum time of tDPL is 10 ns. Note that tDPL is defined from the rising edge of the CLK signal, and tDPLIN, which is an effective value from the rising edge of the EXTPZ signal, is 7 ns. In FIG. 10, a description will be given using tDPLIN.

  First, as in FIG. 6, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. The minimum time (18 ns) of tRCDEX is smaller than the period of the CLK signal (tCK = 20 ns). Therefore, the SDRAM can accept the WRA command at the rising edge (20 ns) of the CLK signal next to the CLK signal that accepted the ACTV command. Then, the SDRAM captures the WRA command, the write address (AC0), and the write data (DIN0) in synchronization with the rising edge (20 ns) of the CLK signal (ICLK signal). The command decoder 20 receives the WRA command and activates the RW signal (FIG. 10 (a)).

  The timing adjustment circuit 40 shown in FIG. 5 outputs the RW signal as an EXTPZ signal without delay (FIG. 10B). The CAS latch 28 shown in FIG. 3 takes in the LAD signal in synchronization with the EXTPZ signal and outputs the taken signal as the CASAD signal (FIG. 10 (c)). Then, the timing control circuit 44 and the predecoder 36 operate to activate the column decoder. Thereafter, write data DIN0 is written into the memory cell MC.

  The SDRAM starts a precharge operation after tDPLIN (7 ns) from the rising edge of the EXTPZ signal. The precharge operation is executed within a period of tRP (10 ns). Therefore, the SDRAM can fetch the next ACTV command in synchronization with the rising edge (40 ns) of the next CLK signal. As a result, the cycle time tRC from the reception of the ACTV command to the reception of the next ACTV command is 40 ns (2 · tCLK), which is the same as the conventional one.

  FIG. 11 shows a write operation involving a precharge operation of the SDRAM when the period of the CLK signal is 13 ns (75 MHz). First, as in FIG. 6, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. The minimum time (13 ns) of tRCDEX is the same as the period (13 ns) of the CLK signal. Therefore, the SDRAM can accept the WRA command at the rising edge (13 ns) of the CLK signal next to the CLK signal that accepted the ACTV command.

  Similarly to FIG. 10, the SDRAM captures the WRA command, the write address (AC0), and the write data (DIN0) in synchronization with the rising edge (13 ns) of the CLK signal (ICLK signal). The SDRAM activates the RW signal in response to the WRA command (FIG. 11 (a)).

  The timing adjustment circuit 40 shown in FIG. 5 receives the RW signal, delays the received signal by 5 ns, and outputs it as an EXTPZ signal (FIG. 11 (b)). By delaying the EXTPZ signal by 5 ns by the timing adjustment circuit 40, tRCDIN (18 ns) can be satisfied as in FIG.

  Thereafter, as in FIG. 10, the timing control circuit 44 and the predecoder 36 operate, the column decoder is activated, and the write data DIN0 is written into the memory cell MC. The SDRAM starts a precharge operation after tDPLIN (7 ns) from the rising edge of the EXTPZ signal. The precharge operation is executed within a period of tRP (10 ns). Therefore, the SDRAM can fetch the next ACTV command in synchronization with the rising edge (39 ns) of the next CLK signal.

  As a result, the cycle time tRC from the reception of the ACTV command to the reception of the next ACTV command is 39 ns (3 · tCLK), which is one clock shorter than the conventional one. As a result, the bus occupancy rate is greatly improved, and the performance of a system using SDRAM is improved.

  FIG. 12 shows the SDRAM write operation and precharge operation when the period of the CLK signal is 13 ns (75 MHz). The timing until the rising edge of the third CLK signal (26 ns) is the same as the timing of FIG. The SDRAM receives the PRE command in synchronization with the rising edge (26 ns) of the CLK signal and activates the PCH signal (FIG. 12 (a)).

  The timing adjustment circuit 22 shown in FIG. 4 receives the PCH signal, delays the received signal by 2 ns, and outputs it as a PCH2 signal (FIG. 12B). By delaying the PCH2 signal by 2 ns by the timing adjustment circuit 40, tDPLIN (7 ns) can be satisfied (FIG. 12 (c)).

  Thereafter, the timing control circuit 24 receives the PCH2 signal and controls the precharge operation. The precharge operation is executed within a period of tRP (10 ns). For this reason, the SDRAM can receive the next ACTV command in synchronization with the rising edge (39 ns) of the next CLK signal. That is, the cycle time tRC is 39 ns (3 · tCLK), which is the same as in FIG.

  FIG. 13 shows a burst read operation of the SDRAM when the period of the CLK signal is 13 ns (75 MHz). Until the EXTPZ signal is activated, the timing is the same as that in FIG.

  The burst control circuit 38 shown in FIG. 3 receives the H level of the RW signal and is activated for a time corresponding to the burst length, which is the number of times the read data is output continuously. The burst length is set in advance in a mode register or the like (not shown). In this example, the burst length is set to “2”. Then, the burst control circuit 38 activates the burst control signal BCN by one less than the burst length in synchronization with the CLK signal (FIG. 13 (a)).

  The CAS latch 28 shown in FIG. 3 takes in the LAD signal in synchronization with the EXTPZ signal and outputs the taken signal as the CASAD signal (FIG. 13 (b)). Then, the timing control circuit 44 and the predecoder 36 operate to activate the column decoder. Thereafter, the data read from the memory cell MC is amplified by the sense amplifier 50 and output as read data DOUT0 (FIG. 13 (c)). Also, the burst address generator 32 shown in FIG. 3 receives the CASAD signal (AC0), increments the received address signal by 1, and outputs it as a bank address signal BAD (AC1) (FIG. 13 (d)).

  The timing adjustment circuit 42 receives the BCN signal, delays the received signal by 5 ns, and outputs it as an INTPZ signal (FIG. 13 (e)). The burst latch 30 takes in the BAD signal in synchronization with the INTPZ signal and outputs it as the CASAD signal (AC1) (FIG. 13 (f)). The timing control circuit 44 receives the INTPZ signal and outputs a timing signal CTIM1. Then, the column decoder corresponding to the CASAD signal (AC1) is activated, and the data read from the memory cell MC is output as read data DOUT1 (FIG. 13 (g)).

  The SDRAM receives a PRE command and executes a precharge operation in synchronization with the rising edge (39 ns) of the second CLK signal from the RD command. Further, the next ACTV command is accepted in synchronization with the rising edge (52 ns) of the next CLK signal. The operation timing of each circuit by the PRE command is the same as that in FIG.

  As described above, in the semiconductor integrated circuit and the semiconductor integrated circuit control method according to the present invention, the timing adjustment circuit 40 determines the delay time from the reception of the column address command (RD, WRA) to the start of the operation of the column address circuit. , 42. The timing adjustment circuit 22 controls the delay time from the reception of the precharge command (PRE) to the start of the precharge operation. Therefore, in a clock synchronous SDRAM or the like, a read operation, a write operation, or a precharge can be executed at an optimum timing according to the operation timing of the internal circuit without depending on the cycle of the clock signal. As a result, the number of command receptions per unit time increases, and the bus occupancy rate of read data and write data can be improved.

  Since the column address system circuit operates at an optimal timing according to the operation timing of the internal circuit, the read cycle time, write cycle time, and precharge cycle time can be shortened. In addition, the timing adjustment circuits 22, 40, and 42 change the delay time according to the latency. For this reason, the read operation and the write operation can be executed at an optimum timing according to the frequency of the clock signal using the delay time. The timing adjustment circuits 22, 40, and 42 can be configured with simple delay circuits.

  Since the delay circuits 54 and 56 are formed in the timing adjustment circuit 22, a predetermined delay time can be easily set only by switching the delay circuits 54 and 56. Similarly, since the delay circuit 60 is formed in the timing adjustment circuits 40 and 42, a predetermined delay time can be easily set depending on whether or not the delay circuit 60 is used.

  FIG. 14 shows a second embodiment of the semiconductor integrated circuit and the method for controlling the semiconductor integrated circuit according to the present invention. The same circuits as those described in the first embodiment are denoted by the same reference numerals, and detailed description of these circuits is omitted. In this embodiment, the chip control unit 62 includes a timing adjustment circuit 64, a latch 66, and a burst control circuit 68 in place of the timing adjustment circuits 40 and 42 and the burst control circuit 38 of the chip control unit 12 of the first embodiment. Have. Other configurations are the same as those in the first embodiment.

  The timing adjustment circuit 64 receives the CL signal and the ICLK signal, delays the ICLK signal according to the CL signal, and outputs it as a delayed internal clock signal ICLKD. The latch 66 captures the RW signal in synchronization with the ICLKD signal and outputs the captured signal as the EXTPZ signal. The burst control circuit 68 is activated in response to the H level of the EXTPZ signal, and outputs the ICLKD signal as the INTPZ signal by one less than the burst length. Next, the operation of the SDRAM in the second embodiment will be described.

  FIG. 15 shows the burst read timing of the SDRAM when the period of the CLK signal is 13 ns (75 MHz). Timing specifications such as the minimum time (13 ns) of tRCDEX are the same as those in the first embodiment. In the case of 75 MHz, since the CAS latency is “2”, the CL signal is set to the H level. First, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. The timing adjustment circuit 64 delays the CLK signal (ICLK signal) by about 5 ns and outputs it as an ICLKD signal (FIG. 15A).

  Next, the SDRAM activates the RW signal in response to the RD command (FIG. 15 (b)). The latch 66 captures the RW signal in synchronization with the rising edge of the ICLKD signal, and outputs the captured signal as the EXTPZ signal for a period of about half a clock (FIG. 15 (c)). In this way, by delaying the ICLKD signal by about 5 ns with respect to the CLK signal by the timing adjustment circuit 64, tRCDIN (18 ns) larger than one period (tCK = 13 ns) of the CLK signal can be satisfied. Thereafter, as in FIG. 6 of the first embodiment, read data DOUT0 is output (FIG. 15 (d)).

  The burst control circuit 68 is activated by the H level of the EXTPZ signal, and outputs the ICLKD signal as the INTPZ signal by one less than the burst length. In this example, since the burst length is set to “2”, the INTPZ signal is activated once (FIG. 15 (e)). Thereafter, the burst latch 30 and the burst address generator 32 operate, and burst read is executed at the same timing as in FIG. 13 (FIG. 15 (f)).

  The SDRAM receives a PRE command and executes a precharge operation in synchronization with the rising edge (39 ns) of the second CLK signal from the RD command. Further, the next ACTV command is accepted in synchronization with the rising edge (52 ns) of the next CLK signal. The operation timing of each circuit by the PRE command is the same as that in FIG.

  Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Further, in this embodiment, a latch 66 that takes in the command signal RW in synchronization with the delayed internal clock signal ICLKD is provided. Since the EXTPZ signal and the INTPZ signal are generated in synchronization with the ICLKD signal, the timing shift is minimized. Therefore, the timing accuracy of the row address system circuit can be improved. Further, since the timing adjustment circuit 64 can be shared as a delay element for generating the EXTPZ signal and the INTPZ signal, the circuit scale can be reduced.

  FIG. 16 shows a semiconductor integrated circuit, a third embodiment of the semiconductor integrated circuit control method related to the present invention, and an embodiment of the variable delay circuit of the present invention. The same circuits as those described in the first embodiment are denoted by the same reference numerals, and detailed description of these circuits is omitted. In this embodiment, the chip control unit 70 is different from the chip control unit 12 of the first embodiment. The input control unit 12 and the memory core unit 14 are the same as those in the first embodiment.

  The chip controller 70 includes a command decoder 20, a RAS controller 72, a CAS controller 74, timing control circuits 76 and 78, a RAS latch 26, a CAS latch 28, a burst latch 30, a burst address generator 32, and predecoders 34 and 36. And timing control circuits 82 and 44.

  The RAS control unit 72 receives the command signal PCH from the command decoder 20, the row timing signal RTIM3 from the timing control circuit 76, and the row timing signal RTIM5 from the timing control circuit 78, and sends a delayed precharge signal PCHD2 to the timing control circuit 76. Is output. The CAS control unit 74 receives the ICLK signal, the RW signal from the command decoder 20, the timing signal CLKA from the timing control circuit 82, and the row timing signal RTIM4 from the timing control circuit 76, and outputs timing signals EXTPZ and INTPZ. Yes.

  The timing control circuit 76 receives the delayed precharge signal PCHD and the auto precharge signal APCH, and outputs row timing signals RTIM1, RTIM2, RTIM3, and RTIM4 that control the circuit of the row address system. Here, the RTIM3 signal is a timing signal that changes to L level after the elapse of time tRASIN, which is an actual value of the internal circuit. RTIM4 is a timing signal that changes to the L level after the time tRCDIN, which is the actual value of the internal circuit, has elapsed. The timing control circuit 78 receives the RTIM4 signal, delays the received signal by a time corresponding to tDPL, and outputs it as a timing signal RTIM5.

  The timing control circuit 82 receives the ICLK signal, the ACT signal, and the CL signal, and outputs timing signals CLKA, CLKB, and CLKD. The RAS control unit 72 includes a latch 86, a pulse generation circuit 88, a timing adjustment circuit 90, a switch SW1, an AND gate 72a, and OR gates 72b and 72c.

  The latch 86 captures the PCH signal and outputs the captured signal as a latch command signal LPCH. The signal fetched into the latch 86 is reset when the reset command RST receives the delayed command signal PCHDA (H level) from the AND gate 72a. The pulse generation circuit 88 is a circuit that outputs the H pulse signal PLS2 in response to the falling edge of the RTIM6 signal. The timing adjustment circuit 90 receives the PCH2 signal, the CLKD signal, and the RTIM6 signal, and outputs a delayed command signal PCHDB.

  The switch SW1 has a function of setting the PCH2 signal to the ground level when the RTIM6 signal is at the H level and transmitting the PCH signal as the PCH2 signal when the RTIM6 signal is at the L level. The switch SW1 is formed of, for example, a CMOS transmission gate that receives the RTIM6 signal at the gate. The AND gate 72a outputs a logical product of the LPCH signal and the PLS2 signal as a delayed command signal PCHDA. The OR gate 72b outputs a logical sum of the PCHDA signal and the PCHDB signal as a delayed precharge signal PCHD. The OR gate 72c outputs a logical product of the RTIM3 signal and the RTIM5 signal as a RTIM6 signal.

  The CAS control unit 74 includes a burst control circuit 38, a latch 92, a pulse generation circuit 94, timing adjustment circuits 96 and 98, a switch SW2, AND gates 74a and 74b, and an OR gate 74c. The burst control circuit 38 takes in the RW signal in synchronization with the ICLK signal and outputs the burst control signal BCN. The latch 92 takes in the command signal RW1 and outputs the taken signal as a latch command signal LRW. The signal fetched into the latch 92 is reset when the H level EXTPZ signal is received at the reset terminal RST.

  The pulse generation circuit 94 is a circuit that receives the falling edge of the RTIM4 signal and outputs the H pulse signal PLS1.

  The timing adjustment circuit 96 receives the command signal RW2, the CLKA signal, and the RTIM4 signal, and outputs a timing signal EXTPBZ. The timing adjustment circuit 98 receives the burst control signal BCN, the timing signal CLKA, and the row timing signal RTIM1, and outputs a timing signal INTPZ.

  The switch SW2 has a function of setting the RW2 signal to the ground level when the CLKC signal is at the H level and transmitting the RW signal as the RW2 signal when the CLKC signal is at the L level. The switch SW2 is formed of, for example, a CMOS transmission gate that receives the CLKC signal at the gate. The AND gate 74a outputs a logical product of the RW signal and the RTIM4 signal as the RW1 signal. The OR gate 72c receives the output signal of the AND gate 74b and the EXPTBZ signal and outputs the EXTPZ signal.

  FIG. 17 shows details of the timing control circuit 82. The timing control circuit 82 includes cascaded D flip-flop circuits 82a, 82b, and 82c, an inverter array 82d in which two inverters are cascaded, OR gates 82e and 82f, and a selector 82g.

  The first-stage D flip-flop circuit 82a takes in the ACT signal in synchronization with the ICLK signal and outputs it as the command signal ACT2. The D flip-flop circuit 82b in the next stage takes in the ACT2 signal in synchronization with the ICLK signal and outputs it as the command signal ACT3. The D flip-flop circuit 82c at the final stage takes in the ACT3 signal in synchronization with the ICLK signal and outputs it as the command signal ACT4.

  The inverter row 82d receives the ACT2 signal and outputs the received signal as a CLKC signal. The OR gate 82e outputs the logical sum of the ACT2 signal and the ACT3 signal as the CLKA signal. The OR gate 82f outputs a logical sum of the ACT3 signal and the ACT4 signal as the timing signal CLKD0. The selector 82g is a circuit that outputs the CLKA signal as the CLKD signal when the CL signal is at the L level and outputs the CLKD0 signal as the CLKD signal when the CL signal is at the H level.

  FIG. 18 shows the operation timing of the timing control circuit 82. First, the SDRAM takes in the ACTV command in synchronization with the rising edge of the ICLK signal and activates the ACT signal (FIG. 18 (a)).

  The D flip-flop circuit 82a takes in the ACT signal and activates the ACT2 signal in synchronization with the rising edge of the ICLK signal (FIG. 18 (a)). Further, the activation of the ACT2 signal activates the CLKC signal and the CLKA signal (FIGS. 18C and 18D). Here, when the CL signal is at the L level, the CLKD signal is activated by the activation of the CLKA signal (FIG. 18 (e)).

  The D flip-flop circuit 82b takes in the ACT2 signal in synchronization with the rising edge of the ICLK signal and activates the ACT3 signal (FIG. 18 (f)). Here, when the CL signal is at the H level, the CLKD signal is activated by the activation of the ACT3 signal (FIG. 18 (g)). The D flip-flop circuit 82c takes in the ACT3 signal in synchronization with the rising edge of the ICLK signal and outputs the ACT4 signal (FIG. 18 (h)).

  The CLKC signal is activated for a period of about 1 clock from the rising edge of the CLK signal next to the ACTV command, and the CLKA signal is activated for a period of about 2 clocks from the rising edge of the CLK signal next to the ACTV command. The CLKD signal is activated for a period of approximately two clocks from the rising edge of the CLK signal next to the ACTV command or the rising edge of the second CLK signal after the ACTV command, depending on the level of the CL signal.

  FIG. 19 shows details of the timing adjustment circuits 90, 96, and 98. Since the timing adjustment circuits 90, 96, and 98 are the same circuit, the timing adjustment circuit 96 will be described here. The names of signals connected to the terminals of the timing adjustment circuits 90 and 98 are shown in parentheses. Further, although not shown in FIG. 16, the reset signal / RESET is a signal that is activated before the operation of the timing adjustment circuits 90, 96, and 98.

  The timing adjustment circuit 96 includes a plurality of cascade-connected delay setting units 100 and a NOR gate 102 that receives the output signal OUT of each delay setting unit 100. The delay setting unit 100 includes delay circuits 100a and 100b, a NAND gate 100c, a flip-flop circuit 100d, a NAND gate 100e, and a NOR gate 100f. Here, the delay setting unit 100 corresponds to the second delay circuit 7 and the first delay circuit 6 shown in FIG. The delay circuit 100a and the delay circuit 100b correspond to the second delay stage 7a and the first delay stage 6a shown in FIG. 2, respectively. The NAND gate 100c and the flip-flop circuit 100d correspond to the detection circuit 8 shown in FIG. The NAND gate 100e and the NOR gate 100f correspond to the selection circuit 9 shown in FIG.

  In the delay circuits 100a and 100b, a CR time constant circuit is disposed between two cascade-connected inverters. The CR time constant circuit includes, for example, a diffused resistor and a MOS capacitor in which the source and drain of nMOS are connected to the ground line VSS. The delay circuits 100a and 100b are the same circuit.

  Each delay setting unit 100 receives the RTIM4 signal at the NAND gate 100c. The delay circuit 100a receives the CLKA signal and outputs the delayed signal to the NAND gate 100c and the delay setting unit 100 in the next stage. The delay circuit 100b receives the RW2 signal and outputs the delayed signal to the NOR gate 100f and the delay setting unit 100 at the next stage.

  The flip-flop circuit 100d receives the / RESET signal at one input and the output of the NAND gate 100c at the other input. Further, the flip-flop circuit 100d connects the output on the side receiving the / RESET signal to the input of the NAND gate 100e in the previous stage, and connects the output on the side receiving the output of the NAND gate 100c to the input of its own NAND gate 100e. ing. The NAND gate 100e receives the output of its own flip-flop circuit 100d and the output of the next-stage flip-flop circuit 100d. The NOR gate 100f outputs an OUT signal.

  FIG. 20 shows the setting operation of the propagation delay time of the timing adjustment circuit 96. Note that the timing adjustment circuits 90 and 98 also operate at the same timing. First, the SDRAM activates the / RESET signal in response to the ACTV command. The flip-flop circuit 100d of each delay setting circuit 100 is reset in response to the / RESET signal. The output of each NAND gate 100e changes to the H level in response to the L level of the flip-flop circuit 100d and the H level of the next flip-flop circuit 100d (FIG. 20 (a)).

  The SDRAM starts the operation of the row address system circuit after receiving the ACTV command. The CLKA signal is activated in synchronization with the ICLK signal after the ACTV command (FIG. 20 (b)). Each delay circuit 100a receives the CLKA signal and sequentially transmits the delayed signal to the NAND gate 100c and the delay circuit 100a in the next stage (FIG. 20 (c)).

  NAND gate 100c inverts the signal received from delay circuit 100c and outputs it to flip-flop circuit 100d while the RTIM4 signal is at the H level. The flip-flop circuit 100d is set in response to the L level of the NAND gate 100c. By this setting, the flip-flop circuit 100d outputs an H level to its NAND gate 100e, and outputs an L level to the NAND gate 100e of the delay setting circuit 100 in the preceding stage (FIG. 20 (d)). The NAND gate 100e receives the H level from its own flip-flop circuit 100d and the L level from the next-stage flip-flop circuit 100d, and sequentially outputs L pulse signals (FIG. 20 (e)).

  After a predetermined time, the RTIM4 signal changes to the L level (FIG. 20 (f)). The NAND gate 100c is deactivated in response to the L level of the RTIM4 signal, and prohibits transmission of the delayed CLKA signal to the flip-flop circuit 100d. As a result, only the NOR gate 100f receiving the L level of the NAND gate 100e at this time is activated (FIG. 20 (g)). That is, the time difference between the transition edges of the CLKA signal and the RTIM4 signal is detected. The detection accuracy is less than the propagation delay time of one delay circuit 100a. For this reason, detection accuracy can be improved by reducing the time constant of the delay circuit 100a.

  Therefore, the RW2 signal transmitted to each delay circuit 100b is output as EXTP0Z from the NOR gate 102 after being delayed by the n delay circuits 100b. Since the delay circuits 100a and 100b are the same circuit, the propagation delay time of the n delay circuits 100b is the same as the time from the rising edge of the CLKA signal to the rising edge of the RTIM4 signal.

  The thick arrow in FIG. 19 indicates the RW2 signal when the CLKA signal is transmitted to the nth delay setting circuit 100 (n) and the RTIM4 signal changes to L level immediately after the nth flip-flop circuit 100d is set. The transmission path is shown. At this time, only the output of the NAND gate 100e of the delay setting circuit 100 (n) is at the L level, and one of the delay signals of the RW2 signal output from each delay circuit 100b is selected.

  Thus, the timing adjustment circuit 96 is a circuit that measures the time from the rising edge of the CLKA signal to the falling edge of the RTIM4 signal, delays the RW2 signal by this time, and outputs it as the EXTPBZ signal. The RTIM4 signal is a signal output corresponding to tRCDIN that is the actual value of the chip. For this reason, the RW2 signal is generated according to the actual tRCDIN that varies depending on the power supply voltage, temperature, and the like.

  Similarly, the timing adjustment circuit 90 is a circuit that measures the time from the rising edge of the PCH2 signal to the falling edge of the RTIM6 signal, delays the PCH2 signal by this time, and outputs it as a PCHD signal. The timing adjustment circuit 98 is a circuit that measures the time from the rising edge of the CLKA signal to the falling edge of the BCN signal, delays the BCN signal by this time, and outputs it as an INTPZ signal. Next, the operation of the SDRAM described above will be described.

  FIG. 21 shows a burst read operation of the SDRAM when the period of the CLK signal is 13 ns (75 MHz). Here, the operation of the CAS control unit 74 shown in FIG. 16 will be described in detail. When the period of the CLK signal is 13 ns, the burst length is set to “2”.

  First, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. Next, the timing control circuit 82 activates the CLKA signal and the CLKC signal in synchronization with the second CLK signal (13 ns) (FIGS. 21A and 21B). Further, the SDRAM activates the RW signal in response to the RD command (FIG. 21 (c)).

  Since the switch SW2 is connected to the ground line VSS while the CLKC signal is at the H level, the RW2 signal holds the L level (FIG. 21 (d)). The AND gate 74a receives the H level of the RW signal and the H level of the RTIM4 signal, and sets the RW1 signal to the H level (FIG. 21 (e)). The latch 92 captures the RW1 signal and outputs the captured signal as an LRW signal (FIG. 21 (f)).

  Here, after receiving the ACTV command, the timing adjustment circuit 96 measures the time from the rising edge of the CLKA signal to the falling edge of the RTIM4 signal (delay setting), as shown in FIG. At the same time, the timing adjustment circuits 90 and 98 perform delay setting in the same manner.

  Thereafter, the RTIM4 signal changes to the L level (FIG. 21 (g)). The pulse generation circuit 94 receives the L level of the RTIM4 signal and generates a PLS1 signal (FIG. 21 (h)). The AND gate 74b receives the H level of the LRW signal and the H level of the PLS1 signal, and sets the EXTPAZ signal to the H level (FIG. 21 (i)). The OR gate 74c outputs the EXTPAZ signal as an EXTPZ signal (FIG. 21 (j)). The latch 92 is reset in response to the H level of the EXTPZ signal and sets the LRW signal to the L level (FIG. 21 (k)). Thus, the EXTPZ signal for the first read operation after the ACTV command is generated from the RTIM4 signal.

  Next, the burst control circuit 38 outputs a BCN signal in synchronization with the ICLK signal (26 ns) (FIG. 21 (l)). The timing adjustment circuit 98 delays the BCN signal for a predetermined time and outputs it as an INTPZ signal (FIG. 21 (m)). Then, a burst read operation is executed in the same manner as in FIG.

  Next, the SDRAM receives the RD command in synchronization with the CLK signal (39 ns) and activates the RW signal (FIG. 21 (n)). The switch SW2 receives the L level of the CLKC signal and outputs the RW signal as the RW2 signal (FIG. 21 (o)). The timing adjustment circuit 96 delays the RW2 signal for a predetermined time and outputs it as the EXTPBZ signal (FIG. 21 (p)). The OR gate 74c outputs the EXTPBZ signal as the EXTPZ signal (FIG. 21 (q)). Then, a read operation is executed. Further, a burst read operation is executed (FIG. 21 (r)).

  FIG. 22 shows the precharge operation of the SDRAM when the period of the CLK signal is 20 ns (50 MHz). When the period of the CLK signal is 20 ns, the burst length is set to “1”. Here, the operation of the RAS control unit 72 shown in FIG. 16 will be described in detail.

  First, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. The timing control circuit 76 sets the RTIM4 signal to the L level after elapse of time of tRCDIN (in this example, 18 ns) that is the actual value of the internal circuit, and RTIM3 after elapse of time of tRASIN (in this example, 24 ns) that is the actual value of the internal circuit. The signal is set to L level (FIGS. 22A and 22B). The timing control circuit 78 delays tDPL (10 ns) from the slow signal of the RTIM4 signal and the CLKA signal and outputs the delayed signal as the RTIM5 signal (FIG. 22 (c)).

  The OR gate 72c outputs a logical sum of the RTIM3 signal and the RTIM5 signal as a RTIM6 signal (FIG. 22 (d)). That is, the RTIM6 signal is output in accordance with a signal having a late falling edge among the RTIM3 signal and the RTIM5 signal. On the other hand, the timing control circuit 82 activates the CLKA signal and the CLKD signal in synchronization with the second CLK signal (20 ns) (FIG. 22 (e)). Also, the SDRAM activates the PCH signal in response to the PRE command (FIG. 22 (f)).

  Here, the timing adjustment circuit 90 measures the time from the rising edge of the CLKD signal to the falling edge of the RTIM6 signal (delay setting) after receiving the ACTV command, similarly to the timing shown in FIG. Since the switch SW1 is connected to the ground line VSS while the RTIM6 signal is at the H level, the PCH2 signal holds the L level (FIG. 22 (g)).

  The latch 86 captures the PCH signal and outputs the captured signal as an LPCH signal (FIG. 22 (h)). The pulse generation circuit 88 receives the L level of the RTIM6 signal and generates a PLS2 signal (FIG. 22 (i)). The AND gate 72a receives the H level of the LPCH signal and the H level of the PLS2 signal, and sets the PCHDA signal to the H level (FIG. 22 (j)). The latch 86 is reset in response to the H level of the PCHDA signal and sets the LPCH signal to the L level (FIG. 22 (k)). The OR gate 72c outputs the PCHDA signal as a PCHD signal (FIG. 22 (l)). Then, a precharge operation is performed. As described above, when the PRE command is received by the next CLK signal after the ACTV command, the PCHD signal for performing the precharge operation is generated from the PCHDA signal.

  FIG. 23 shows another example of the SDRAM precharge operation when the period of the CLK signal is 20 ns (50 MHz). 23, the operation of the RAS control unit 72 shown in FIG. 16 will be described in detail. In this example, after receiving the ACTV command, the SDRAM receives the PRE command in synchronization with the second CLK signal (40 ns). The operations of symbols (a) to (d) in the figure are the same as those in FIG.

  The pulse generation circuit 88 generates the PLS2 signal in response to the L level of the RTIM6 signal (FIG. 23 (e)). At this time, since the PRE command is not supplied to the SDRAM, the latch 86 sets the LPCH signal to the L level. For this reason, the PCHDA signal is not activated (FIGS. 23 (f) and (g)).

  Thereafter, the SDRAM receives the PRE command in synchronization with the rising edge (40 ns) of the CLK signal and activates the PCH signal. The switch SW1 receives the L level of the RTIM6 signal and outputs the PCH signal as the PCH2 signal (FIG. 23 (h)). The timing adjustment circuit 90 delays the PCH2 signal for a predetermined time and outputs it as a PCHDB signal (FIG. 23 (i)). The OR gate 72b outputs the PCHDB signal as a PCHD signal (FIG. 23 (j)). Then, a precharge operation is performed. The latch 86 receives the activation of the PCH signal and sets the LPCH signal to the H level. However, since the PLS2 signal is not generated, the PCHDA signal is not activated (FIG. 23 (k)).

  FIG. 24 shows the SDRAM write operation and precharge operation when the period of the CLK signal is 13 ns (75 MHz). Here, the operation of the RAS control unit 72 shown in FIG. 16 will be described in detail. In this example, the SDRAM sequentially receives an ACTV command, a WR command, and a PRE command in synchronization with the CLK signal. Further, when the period of the CLK signal is 13 ns (75 MHz), the latency is set to “2”, so the CLKD signal becomes H level in synchronization with the rising edge of the second CLK signal (26 ns).

  Also, the timing adjustment circuit 90 measures the time from the rising edge of the CLKD signal to the falling edge of the RTIM5 signal (delay setting) as in FIG. Symbols (a)-(l) shown in the figure correspond to the symbols in FIG. 22, and each circuit operates in the same manner as in FIG.

  FIG. 25 shows another example of the SDRAM precharge operation when the period of the CLK signal is 13 ns (75 MHz). In this example, the SDRAM receives the PRE command in synchronization with the third CLK signal (39 ns) after receiving the ACTV command. Symbols (a) to (k) shown in the figure correspond to the symbols in FIG. 23, and each circuit operates in the same manner as in FIG.

  Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Furthermore, in this embodiment, the delay times of the timing adjustment circuits 96 and 98 are set using the RTIM4 signal that changes to the L level after tRCDIN, which is the actual value of the internal circuit. For this reason, the delay time can be set according to the operation timing of the actual row address system circuit that varies depending on the power supply voltage, temperature, and the like. Therefore, the column address system circuit can be operated at an optimum timing according to the operation timing of the row address system circuit.

  Since the delay time is set every time an ACTV command is received, the frequency of setting the delay time can be increased, and the column address system circuit can be operated with high accuracy. Each timing adjustment circuit obtains a time corresponding to the difference between transition edges of two signals (for example, CLKA signal and RTIM4 signal), and delays the input signal (for example, RW2 signal) by this time. Therefore, fluctuations in the operation timing of the internal circuit can be reliably reflected in the delay time of the input signal. Since the delay circuits 100a and 100b are the same, the difference between the transition edges of the two signals can be easily reflected in the delay time of the input signal.

  FIG. 26 shows a semiconductor integrated circuit related to the present invention, a fourth embodiment of the control method of the semiconductor integrated circuit, and an embodiment of the variable delay circuit of the present invention. The same circuits as those described in the first and third embodiments are denoted by the same reference numerals, and detailed description of these circuits is omitted. In this embodiment, the CAS control unit 104 is different from the CAS control unit 74 of the third embodiment. The other configuration is the same as that of the third embodiment.

  The CAS control unit 104 includes a timing adjustment circuit 106, pulse generation circuits 94 and 108, an OR gate 104 a, a latch 110, and a burst control circuit 68.

  The timing adjustment circuit 106 is the same circuit as the timing adjustment circuit 96 shown in FIG. The timing adjustment circuit 106 is a circuit that measures the time from the rising edge of the CLKA signal to the falling edge of the RTIM4 signal, delays the ICLK signal by this time, and outputs the delayed internal clock signal ICLKD.

  The pulse generation circuit 108 is the same circuit as the pulse generation circuit 94. The pattern generation circuit 108 outputs the H pulse signal CLKP in synchronization with the rising edge of the ICLKD signal. The OR gate 104a outputs the logical sum of the PLS1 signal and the CLKP signal as the H pulse signal PLS3. The latch 110 captures the RW signal in synchronization with the PLS3 signal, and outputs the captured signal as the EXTPZ signal. As in the second embodiment, the burst control circuit 88 is activated in response to the H level of the EXTPZ signal, and outputs the ICLKD signal as an INTPZ signal for a number of times less than the burst length.

  FIG. 27 shows the operation of the timing adjustment circuit 106. First, similarly to FIG. 20, the flip-flop circuit 100d of each delay setting circuit 100 shown in FIG. 19 is reset in response to the / RESET signal. The delay circuit 100b receives the ICLK signal or the output signal of the preceding delay circuit 100b and outputs a delayed signal (FIG. 27 (a)).

  Next, the CLKA signal is activated in synchronization with the ICLK signal after the ACTV command (FIG. 27 (b)). Each delay circuit 100a receives the CLKA signal and sequentially transmits the delayed signal to the NAND gate 100c and the delay circuit 100a in the next stage (FIG. 27 (c)). The NAND gate 100e sequentially receives the H level of its own flip-flop circuit 100d and the L level of the next-stage flip-flop circuit 100d, and outputs an L pulse signal (FIG. 27 (d)).

  Here, the outputs of the NAND gate 100e are both at the H level when the level of the delay signal of the ICLK signal output from each delay circuit 100b changes. For this reason, the output signal of the delay circuit 100b cannot pass through the NOR gate 100f, and the ICLKD signal is held at the H level (FIG. 27 (e)).

  After a predetermined time, the RTIM4 signal changes to L level, and for example, the output of the nth NAND gate 100e is fixed to L level (FIG. 27 (f)). By this fixing, the nth NOR gate 100f is activated, and the output signal of the delay circuit 100b is transmitted to the NOR gate 102.

  Thereafter, the ICLK signal is output as the ICLKD signal with a delay of the delay time set in the delay adjustment circuit 106 (FIG. 27 (g)).

  FIG. 28 shows a burst read operation of the SDRAM when the period of the CLK signal is 13 ns (75 MHz). Here, the operation of the CAS control unit 104 shown in FIG. 26 will be described in detail. First, the SDRAM receives the ACTV command and activates the row decoder 48 shown in FIG. Next, the timing control circuit 82 activates the CLKA signal in synchronization with the second CLK signal (13 ns) (FIG. 28 (a)). Further, the SDRAM activates the RW signal in response to the RD command (FIG. 28 (b)).

  As described above, the timing adjustment circuit 96 measures the time from the rising edge of the CLKA signal to the falling edge of the RTIM4 signal (delay setting). The timing adjustment circuit 96 outputs an ICLK signal delayed by a predetermined delay time after setting the delay (FIG. 28 (c)).

  The pulse generation circuit 94 receives the L level of the RTIM4 signal and generates a PLS1 signal (FIG. 28 (d)). The OR gate 104a outputs the PLS1 signal as a PLS3 signal (FIG. 28 (e)).

  The latch 110 captures the H level of the RW signal in synchronization with the PLS3 signal, and outputs the captured signal as an EXTPZ signal for a period of about half a clock (FIG. 28 (f)). Since the EXTPZ signal is at the L level when the PLS3 signal rises, the burst control circuit 68 holds the L level of the INTPZ signal (FIG. 28 (g)). Then, the first read operation is executed by the activation of the EXTPZ signal. Thus, the EXTPZ signal for the first read operation after the ACTV command is generated from the RTIM4 signal.

  Next, the pulse generation circuit 104 outputs the CLKP signal in synchronization with the rising edge of the ICLKD signal (FIG. 28 (h)). The OR gate 104a outputs the CLKP signal as a PLS3 signal (FIG. 28 (i)).

  The burst control circuit 68 is activated by the H level of the EXTPZ signal, and outputs the PLS signal as the INTPZ signal for a number of times less than the burst length. In this example, the burst length is set to “2”, and the INTPZ signal is activated once (FIG. 28 (j)). Since the RW signal is at the L level when the PLS3 signal rises, the latch 110 holds the L level of the EXTPZ signal (FIG. 28 (k)). Then, the burst read operation is executed by the activation of the INTPZ signal.

  Next, the SDRAM receives the RD command in synchronization with the rising edge (39 ns) of the CLK signal and activates the RW signal (FIG. 28 (l)). The pulse generation circuit 104 outputs the CLKP signal (FIG. 28 (m)), and the OR gate 104a outputs the PLS3 signal (FIG. 28 (n)). The latch 110 captures the H level of the RW signal in synchronization with the PLS3 signal, and outputs the captured signal as the EXTPZ signal for a period of about half a clock (FIG. 28 (o)).

  Then, the reading operation is executed by the activation of the EXTPZ signal. Thus, the EXTPZ signal for the second and subsequent read operations is generated from the ICLK signal. Further, the INTPZ signal is activated in synchronization with the next ICLKD signal, and a burst read operation is executed (FIG. 28 (p)).

  Also in the semiconductor integrated circuit of this embodiment, the same effects as those of the second and third embodiments described above can be obtained.

  In the above-described embodiment, an example in which each timing adjustment circuit sets a delay time every time it receives an ACTV command has been described. The present invention is not limited to such an embodiment. For example, the delay time may be set only when the power is turned on, or the delay time may be set according to an external request using a mode register or a control terminal. A delay time may be set during the refresh operation. Further, the delay time may be set when an ACTV command is received when the internal circuit is inactive. By doing in this way, the setting frequency of delay time falls and power consumption is reduced.

In the above-described embodiment, the example in which the present invention is applied to the SDRAM having one memory core unit 14 has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a multi-bank SDRAM having a plurality of memory core units 14. In this case, for example, in the first embodiment, timing adjustment circuits 40 and 42 are formed corresponding to the row address system circuit of each memory core unit 14 and the delay times of the EXTPZ signal and the INTPZ signal are controlled. Good. In the multi-bank configuration, when the timing adjustment circuits 40 and 42 are formed one by one in order to reduce the circuit scale, the delay time may be set as follows.
(A) A delay time is set only when the power is turned on.
(B) A delay time is set according to an external request. An external request can be received by writing a predetermined value in the mode register or by supplying a predetermined control signal to the control terminal. By using the mode register, the delay time can be set only when necessary. By using the control terminal, for example, the delay time can be set immediately when the power supply voltage fluctuates.
(C) A delay time is set during the refresh operation. Specifically, a delay time may be set when a refresh command is received. Also, the delay time may be set only when the first refresh command is received after the power is turned on.

  Said (a)-(c) may be applied independently and may be applied together. Further, since the frequency of setting the delay time is reduced in any form, power consumption can be reduced.

  Furthermore, the timing adjustment circuits 90, 96, and 98 used in the third embodiment described above are not limited to the circuit shown in FIG. Another example of the timing adjustment circuit is shown in FIG. This timing adjustment circuit includes an activation signal ENA generation circuit 112 and a plurality of cascaded delay setting units 114. The delay setting unit 114 includes the same delay circuit 100a, NAND gate 100c, flip-flop circuit 100d, three-input NAND gate 114a, and delay circuit 114b as in FIG. Here, each delay circuit 114b corresponds to the first delay stage 6a shown in FIG. The NAND gate 114a corresponds to the selection circuit 9 shown in FIG.

  In the generation circuit 112, an inverter, a CMOS transmission gate, and an AND circuit 112a are connected in series. In this generation circuit 112, the CMOS transmission gate takes in the inverted signal INV of the RTIM4 signal when the ICLK signal is at the L level. The fetched INV signal is held by a latch circuit (not shown). During the period when the INV signal is at the H level, the ICLK signal or RW2 signal supplied from the other input of the AND circuit 112a is output as the enable signal ENA.

  The NAND gate 114a of the delay setting unit 114 receives the enable signal ENA, the output of its own flip-flop circuit 100d, and the output of the subsequent flip-flop circuit 100d.

  In the delay circuit 114b, a CR time constant circuit is arranged between the NAND gate and the inverter. One input of the NAND gate is connected to the output of the NAND gate 114a, and the other input is connected to the output of the delay circuit 114b in the preceding stage (right side in the figure). Note that the input of the first-stage delay circuit 114b (not shown, but located on the right side of the figure) is fixed at the H level.

  Then, a delay clock signal CLKD or EXTPBZ signal delayed by a predetermined time is output from the delay circuit 114a (left side in the figure) of the delay setting unit 114 in the first stage. Signal names in parentheses are signal names corresponding to the timing adjustment circuits 96 and 98.

  FIG. 30 shows the setting operation of the propagation delay time when the ICLK signal is delayed in the timing adjustment circuit shown in FIG. Here, only timings different from those in FIG. 20 will be described. First, the CMOS transmission gate holds the inverted signal INV of the RTIM4 signal during the period when the ICLK signal is at the L level (FIG. 30A). Since the INV signal is at the L level when the ICLK signal rises, the ENA signal holds the L level (FIG. 30 (b)).

  Next, during the L level period of the ICLK signal, the RTIM4 signal changes to the L level, and the INV signal changes to the H level (FIG. 30 (c)). The AND circuit 112a is activated by the H level of the INV signal. Also, before the AND circuit 112a is activated, the propagation delay time is set in the same manner as in FIG. 20 (FIG. 30 (d)). The AND circuit 112a sets the ENA signal to the H level in response to the next rising edge of the ICLK signal (FIG. 30 (e)). Then, only the NAND gate 114a shown by shading in FIG. 29 is activated, and its output changes to L level (FIG. 30 (e)).

  As a result, the delay circuits 114b indicated by thick wavy lines in FIG. 29 are electrically connected in series. The ICLK signal is output as the CLKD signal with a delay of the total delay time (FIG. 30 (f)). That is, a propagation delay time is set. Here, when the signal supplied to the AND circuit 112a is the RW2 signal, the same waveforms as (o) and (p) shown in FIG. 21 are obtained.

  Further, in the above-described embodiments, the example in which the present invention is applied to the SDRAM has been described. However, the present invention is not limited to such an embodiment. For example, the present invention may be applied to a semiconductor memory such as DRAM or SRAM that operates in synchronization with a clock signal. Alternatively, the present invention may be applied to a system LSI incorporating a DRAM memory core. The semiconductor manufacturing process to which the present invention is applied is not limited to the CMOS process, and may be a Bi-CMOS process.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention. The present invention is not limited to this, and it is obvious that modifications can be made without departing from the present invention.

1 row control circuit 2 command control circuit 3 column control circuit 4 timing adjustment circuit 5 precharge circuit 6 first delay circuit 7 second delay circuit 8 detection circuit 9 selection circuit 6a first delay stage 7a second delay stage 10 input / output control Unit 12 Chip control unit 14 Memory core unit 16a, 16b, 16c Input buffer 18a, 18b Latch 20 Command decoder 22 Timing adjustment circuit 24 Timing control circuit 26 RAS latch 28 CAS latch 30 Burst latch 32 Burst address generator 34, 36 Predecoder 38 Burst control circuit 40, 42 Timing adjustment circuit 44 Timing control circuit 46 Memory cell part 48 Row decoder 50 Sense amplifier 52 Column decoder 54, 56 Delay circuit 58 Combinational circuit 60 Delay circuit 62 Chip control part 64 Timing Adjustment circuit 66 Latch 68 Burst control circuit 70 Chip control unit 72 RAS control unit 74 CAS control unit 76, 78 Timing control circuit 82 Timing control circuit 86 Latch 88 Pulse generation circuit 90 Timing adjustment circuit 94 Pulse generation circuit 96, 98 Timing adjustment circuit DESCRIPTION OF SYMBOLS 100 Delay setting part 100a, 100b Delay circuit 100e Flip-flop circuit 102 NOR gate 104 CAS control part 106 Timing adjustment circuit 108 Pulse generation circuit 110 Latch
ACT command signal
AD address signal
APCH Auto precharge signal
BCN burst control signal
CASAD column address signal
CL latency signal
CLK clock signal
CLKA, CLKC, CLKD timing signals
CLKP, PLS3 H pulse signal
CMD command signal
CTIM1 column timing signal
EXTPZ timing signal
EXTPAZ, EXTPBZ timing signal
IAD internal address signal
ICLK Internal clock signal
ICLKD Delay internal clock signal
ICMD internal command signal
INTPZ timing signal
LCMD Latch command signal
LPCH Latch command signal
LRW Latch command signal
MC memory cell
PCH command signal
PCH2 command signal
PCHD delayed precharge signal
PCHD2 delayed precharge signal
PCHDA, PCHDB Delay command signal
PLS1, PLS2 H pulse signal
RW command signal
RW1, RW2 command signal
RASAD address signal
RTIM1 and RTIM2 row timing signals
RTIM3, RTIM4, RTIM5, RTIM6 row timing signals
SW1, SW2 switch

Claims (1)

A first delay circuit having a plurality of first delay stages connected in cascade and receiving an input signal at the first stage;
A plurality of second delay stages identical to the first delay stage are cascaded, and a second delay circuit receiving the first timing signal at the first stage;
A detection circuit that receives a second timing signal and obtains the delay timing signal having a transition edge adjacent to a transition edge of the second timing signal among the delay timing signals output from the second delay stages;
A variable delay circuit comprising: a selection circuit that selects a delay signal output from the first delay stage corresponding to the second delay stage that outputs the delay timing signal obtained by the detection circuit.

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