JP2014078661A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

An object of the present invention is to improve the reliability of a semiconductor device having a capacitor.
Polysilicon films P1 and P2 extending in a second direction along a main surface of a semiconductor substrate SB and insulated from each other via an ONO film MF are alternately arranged in a first direction orthogonal to the second direction. A capacitor element CPD composed of the polysilicon films P1 and P2 is formed by arranging a plurality of them side by side. By embedding a polysilicon film P2 between the polysilicon films P1 adjacent in the first direction and not forming other conductor films constituting the capacitor element CPD on the polysilicon films P1 and P2, the capacitor element CPD and Align the height with other semiconductor elements.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device having a capacitive element.

  As an element used as a load capacitor of an oscillation circuit, there is a capacitive element having a structure in which an insulating film is interposed between conductor films. As a structure of the capacitive element, there is known a PIP (Poly-Insulator-Poly) capacitive element in which another polysilicon film is laminated on a polysilicon film through an insulating film in a direction perpendicular to the main surface of the semiconductor substrate. It has been.

  In addition, as one of the non-volatile memories, it has a FET (Field Effect Transistor) structure and stores information by accumulating charges in an ONO (Oxide Nitride Oxide) film formed between the gate electrode and the substrate. MONOS (Metal Oxide Nitride Oxide Semiconductor) memory is known. The MONOS memory has a split gate having a select gate electrode used for selecting a memory cell and a memory gate electrode formed adjacent to the select gate via an insulating film and used for storing information. There is a gate type non-volatile memory.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 5-22662) describes forming a nonvolatile memory device composed of two MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) arranged on a semiconductor substrate. Here, it is described that after two gate electrodes are formed on a semiconductor substrate, an insulating film is embedded between the gate electrodes. However, it is not suggested to use such a structure for a capacitor element, and since one of the two gate electrodes is a floating gate, the structure cannot be used as a capacitor element.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 6-232407) describes that two MOSFETs are connected in series to have the function of one MOSFET. Here, it is described that after two gate electrodes are formed on a semiconductor substrate, an insulating film is embedded between the gate electrodes. However, when an insulating film is embedded between the gate electrodes, the distance between the gate electrodes needs to be increased to some extent. Therefore, even if the structure formed by the method described in Patent Document 2 is applied to a capacitor, the capacitance is small. It will be a thing.

JP-A-5-226661 JP-A-6-232407

  On the semiconductor substrate, it is conceivable to form a semiconductor element such as an FET or a nonvolatile memory in addition to the capacitor element. However, when these multiple types of elements are mixedly mounted on the same substrate, due to the difference in height between the capacitive element and other elements such as FETs, Planarization becomes difficult, and problems such as deterioration of lithography accuracy occur.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment is configured such that a capacitive element is formed by a plurality of conductive films that extend along a main surface of a semiconductor substrate and are insulated from each other.

  According to one embodiment disclosed in the present application, the heights of elements on the same substrate can be made uniform, various problems in the process due to the difference in height can be avoided, and as a result, the reliability of the semiconductor device can be avoided. Can be improved.

1 is a plan layout showing a semiconductor device according to an embodiment of the present invention; It is sectional drawing which shows the semiconductor device which is one embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. FIG. 4 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 3. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. FIG. 10 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 9; FIG. 11 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 10; FIG. 12 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11; It is a plane layout which shows the modification of the semiconductor device which is one embodiment of this invention. It is a plane layout which shows the modification of the semiconductor device which is one embodiment of this invention. It is a plane layout which shows the modification of the semiconductor device which is one embodiment of this invention. It is sectional drawing which shows the modification of the semiconductor device which is one embodiment of this invention. It is sectional drawing which shows the semiconductor device which is a comparative example. It is sectional drawing which shows the manufacturing method of the semiconductor device which is a comparative example. FIG. 19 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 18;

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the following embodiments, even a plan view may be partially hatched to make the drawings easy to see.

  Note that the height in the present application refers to the distance from the main surface of the semiconductor substrate to the upper surface of the target film or element in a direction perpendicular to the main surface of the semiconductor substrate.

  In the semiconductor device of this embodiment, the reliability of a semiconductor device is improved by aligning the height of a capacitor formed over a semiconductor substrate with the height of another semiconductor element.

  The structure of the semiconductor device of this embodiment will be described below with reference to FIGS. FIG. 1 is a plan layout showing the semiconductor device of this embodiment, and FIG. 2 is a cross-sectional view showing the semiconductor device of this embodiment. 2 is a cross-sectional view taken along line AA in FIG. 1.

  In FIG. 1, a plurality of polysilicon films P1 (first conductor films) disposed on a semiconductor substrate (not shown) and extending in the second direction along the main surface of the semiconductor substrate, and extending in the second direction. 2 shows a planar layout of a capacitive element CPD composed of a plurality of polysilicon films P2 (second conductor films). As shown in FIG. 1, the polysilicon films P <b> 1 and P <b> 2 are alternately arranged in a direction orthogonal to the second direction and in the first direction along the main surface of the semiconductor substrate. That is, in the first direction, the polysilicon film P2 is disposed between the adjacent polysilicon films P1, and the polysilicon film P1 is disposed between the adjacent polysilicon films P2.

  A laminate in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked in this order from the polysilicon film P1 side to the polysilicon film P2 side between the side walls of the opposing polysilicon film P1 and the polysilicon film P2. An ONO film (first ONO film) MF, which is a film, is formed. Note that FIG. 1 does not show the shape of the ONO film MF.

  A contact plug CP, which is a conductor for supplying a predetermined potential to each of the polysilicon films P1 and P2, is connected to the upper surface of each of the polysilicon films P1 and P2. The contact plug CP is mainly made of, for example, a W (tungsten) film. Here, the contact plug CP is electrically connected to the upper surface of one end in the longitudinal direction (second direction) of each of the polysilicon films P1 and P2.

  In addition, a contact plug for supplying a potential to a semiconductor substrate (not shown) is provided beside the capacitive element CPD in the first direction. However, FIG. 1 does not show the contact plug CP shown in FIG. 2 that is provided beside the capacitive element CPD in the first direction and is electrically connected to the semiconductor substrate SB.

  As shown in FIGS. 1 and 2, the polysilicon film P2 at the end of the capacitive element CPD in the first direction is a film formed in a sidewall shape on the sidewall of the polysilicon film P1 via the ONO film MF. The width in the first direction is narrower than other polysilicon films P2.

  In the cross-sectional view shown in FIG. 2, the region where the MONOS memory Q1 is formed is shown on the left side of the drawing, the region where the capacitive element CPD is formed is shown in the center of the drawing, and the n-channel type low breakdown voltage MOSFET Q2 is formed on the right side of the drawing. Indicates the area. The MONOS memory Q1, the capacitive element CPD, and the low breakdown voltage MOSFET Q2 are all semiconductor elements provided on the same semiconductor substrate SB. The semiconductor substrate SB is made of, for example, single crystal silicon. The MONOS memory Q1 and the low breakdown voltage MOSFET Q2 are formed on a p-type well formed by implanting a p-type impurity (for example, B (boron)) on the upper surface of the semiconductor substrate SB. The capacitive element CPD is formed on an n-type well formed by implanting an n-type impurity (for example, arsenic (As)) on the upper surface of the semiconductor substrate SB.

  First, the MONOS memory Q1 shown on the left side of FIG. 2 will be described. In the left sectional view of FIG. 2, a control gate electrode CG is formed on the semiconductor substrate SB via a gate insulating film GF1. Memory gate electrodes MG are formed on the sidewalls on both sides of the control gate electrode CG via an ONO film (second ONO film) MF. The memory gate electrode MG is formed in a self-aligned manner and has a sidewall shape. An ONO film MF is interposed between the memory gate electrode MG and the semiconductor substrate SB, and is formed between the memory gate electrode MG and the semiconductor substrate SB, and between the memory gate electrode MG and the control gate electrode CG. The ONO film MF thus formed is integrally formed continuously. That is, the ONO film MF is formed so as to cover the side wall and the bottom surface of the memory gate electrode MG, and its cross-sectional shape is L-shaped.

  The ONO film MF is composed of a laminated film in which a silicon oxide film (first silicon oxide film) X1, a silicon nitride film N1, and a silicon oxide film (second silicon oxide film) X2 are formed in this order from the upper surface of the semiconductor substrate SB. . Accordingly, between the memory gate electrode MG and the control gate electrode CG adjacent to each other, the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 are formed in order from the control gate electrode CG side to the memory gate electrode MG side. ing. A side wall SW is formed in a self-aligned manner on the side wall of the memory gate electrode MG that is not adjacent to the control gate electrode CG. Each film thickness of the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 is, for example, 6 nm. Further, the width of the memory gate electrode MG in the first direction is, for example, 50 nm.

  The gate insulating film GF1 is an insulating film made of, for example, a silicon oxide film. The control gate electrode CG and the memory gate electrode MG are made of, for example, a polysilicon film. The silicon nitride film N1 is an insulating film that functions as a charge storage film when the MONOS memory Q1 is operated. The sidewall SW is an insulating film including, for example, a silicon oxide film.

  The upper surface of the semiconductor substrate SB immediately below the memory gate electrode MG and immediately below the control gate electrode CG is a region that becomes a channel region during the operation of the MONOS memory Q1, and the main surface of the semiconductor substrate SB has a first direction (FIG. 2). A pair of source / drain regions are formed so as to sandwich the channel region in a direction along the main surface of the semiconductor substrate SB. Each of the pair of source / drain regions includes an extension region EX which is an n-type semiconductor layer into which arsenic (As) is implanted, for example, and a semiconductor layer into which arsenic (As) is implanted at a higher concentration than the extension region EX, for example. And a diffusion layer DF. The extension region EX is formed in a region closer to the channel region than the diffusion layer DF with a junction depth shallower than that of the diffusion layer DF.

  Thus, the source / drain region has an LDD (Lightly Doped Drain) structure having the diffusion layer DF having a relatively high impurity concentration and the extension region EX having a lower impurity concentration than the diffusion layer DF. Here, the extension region EX is mainly formed on the upper surface of the semiconductor substrate SB immediately below the sidewall SW, and the diffusion layer DF is a semiconductor exposed from the memory gate electrode MG, the control gate electrode CG, the ONO film MF, and the sidewall SW. It is formed on the upper surface of the substrate SB.

  The MONOS memory Q1 includes a memory gate electrode MG for storage, a control gate electrode CG for selection, a silicon oxide film X1, a silicon nitride film N1, and a source / drain region, and is a split gate nonvolatile memory having the shape of a field effect transistor. Memory. The MONOS memory can store information by accumulating charges in the silicon nitride film N1 directly below the memory gate electrode MG. There are the following two methods for putting charge into and out of the silicon nitride film N1. One is a method of writing and erasing by putting electrons in and out with a tunnel current on the entire surface of the silicon nitride film N1 under the memory gate electrode MG, and the other is a method using hot carriers. FIG. 2 shows a structure in which the memory gate electrode MG is formed on the side walls on both sides of the control gate electrode CG. The ONO film MF for storing charges as information is formed on the memory gate on one side wall of the control gate electrode CG. It may be only the ONO film MF directly below the electrode MG, or may be each of the ONO film MF immediately below the memory gate electrode MG on both side walls of the control gate electrode CG.

  Next, the capacitive element CPD shown in the center of FIG. 2 will be described. In the central cross-sectional view of FIG. 2, a plurality of polysilicon films P1 formed via the insulating film IF1 are arranged side by side in the first direction on the semiconductor substrate SB. Further, a plurality of polysilicon films P2 formed via the ONO film MF are arranged side by side in the first direction on the semiconductor substrate SB. Each polysilicon film P1 is a film extending in the second direction (the depth direction in FIG. 2), and is a film in the same layer as the control gate electrode CG and a gate electrode GE described later. Each polysilicon film P2 is a film extending in the second direction, and is a film in the same layer as the memory gate electrode MG. The ONO film MF formed in the MONOS memory Q1 and the ONO film MF formed in the capacitor element CPD are the same layer.

  As described with reference to FIG. 1, the polysilicon films P1 and P2 are alternately arranged one by one in the first direction, and the ONO film MF is interposed between the adjacent polysilicon films P1 and P2. Yes. The ONO film MF is a laminated film in which a silicon oxide film X1, a silicon nitride film N1, and a silicon oxide film X2 are formed in this order from the upper surface of the semiconductor substrate SB. Accordingly, between the polysilicon films P1 and P2 adjacent to each other, a silicon oxide film X1, a silicon nitride film N1, and a silicon oxide film X2 are formed in order from the polysilicon film P1 side to the polysilicon film P2 side.

  Capacitance element CPD is constituted by polysilicon films P1 and P2 that are alternately arranged in the first direction and insulated from each other by ONO film MF. As will be described later, the capacitive element CPD can also constitute a capacitive element by generating a capacitance between the semiconductor substrate SB and the polysilicon film P1 or P2. That is, the capacitive element CPD has at least polysilicon films P1 and P2 on the semiconductor substrate SB, and is an element that can be used by generating a capacitance between the polysilicon films P1 and P2. It is an element that can obtain a larger capacitance by generating a capacitance with the substrate SB.

  Sidewall-shaped polysilicon films P2 formed in a self-aligned manner are formed at both ends of the capacitive element in the first direction. As will be described later, since the polysilicon film P2 and the memory gate electrode MG are the same film formed by self-aligning the same polysilicon film by the same etching process, the shapes thereof are the same. Yes.

  Therefore, the width of the memory gate electrode MG in the first direction, that is, the gate length of the memory gate electrode MG, and the width in the first direction of the sidewall-shaped polysilicon film P2 at the end of the capacitive element in the first direction are: It is the same size. As described above, when the width of the memory gate electrode MG in the first direction is 50 nm, the width of the sidewall-like polysilicon film P2 in the same direction is 50 nm. Similarly to the memory gate electrode MG, the bottom surface of the sidewall-like polysilicon film P2 at the end of the capacitive element CPD and the side wall of the polysilicon film P2 adjacent to the polysilicon film P1 are The ONO film MF having an L-shaped cross-sectional shape is continuously covered.

  In addition, the polysilicon film P2 other than the sidewall-like polysilicon film P2, that is, the polysilicon film P2 formed on the other side than the end of the capacitor element CPD in the first direction, is completely between the adjacent polysilicon films P1. It is formed so as to be buried, and has a rectangular shape in a cross section along the first direction. An ONO film MF formed continuously from the bottom surface of the polysilicon film P2 is formed between the rectangular polysilicon film P2 and the polysilicon film P1 adjacent to the polysilicon film P2. . Therefore, the side walls and the bottom surface of the polysilicon film P2 sandwiched between the two polysilicon films P1 are covered with the ONO film MF having a U-shaped cross-sectional shape.

  When a capacitive element is formed by separating a plurality of polysilicon films with an insulating film, for example, a silicon oxide film may be used as the insulating film, but here, the polysilicon film P1, with an ONO film MF interposed therebetween, may be used. By insulating P2 from each other, it is possible to form a capacitive element CPD having a high breakdown voltage and a large capacity. That is, since the silicon nitride film N1 constituting the ONO film MF has a higher dielectric constant than the silicon oxide film, the equivalent oxide thickness (EOT) is small. Therefore, when the equivalent oxide thickness of the ONO film MF is the same as when only the silicon oxide film is used as the insulating film, the physical thickness of the silicon nitride film N1 can be increased. Therefore, by insulating the polysilicon films P1 and P2 with the ONO film MF, the breakdown voltage between the polysilicon films P1 and P2 can be increased, and the capacitance of the capacitive element CPD can be prevented from decreasing. .

  Specifically, only the silicon oxide film having a thickness of 15 nm is used for the insulation between the polysilicons of the capacitor element, and the silicon oxide films X1, X2 having a thickness of 5 nm and the nitride having a thickness of 10 nm, respectively. The case where the ONO film MF made of the silicon film N1 is used will be compared. At this time, since the equivalent oxide thickness is almost the same in each case, the capacitance of the capacitive element does not change, but since the physical thickness is larger in the ONO film MF, the capacitive element using the ONO film MF is used. Has a high breakdown voltage.

  Here, the width in the first direction of each of the polysilicon film P1 and the polysilicon film P2 having the above-described rectangular cross section is, for example, 70 to 80 nm. The width in the first direction of the polysilicon film P2 formed between the adjacent polysilicon films P1 is not more than twice the width in the first direction of the sidewall-like polysilicon film P2.

  A side wall SW is formed in a self-aligned manner on one side wall of the above-described side wall-like polysilicon film P2 that is not adjacent to the polysilicon film P1. The sidewall SW is an insulating film including, for example, a silicon oxide film. Similar to the MONOS memory Q1, an extension region EX and a diffusion layer DF are formed on the upper surface of the semiconductor substrate SB next to the capacitive element CPD. The extension region EX and the diffusion layer DF are both n-type semiconductor layers, and the diffusion layer DF has a higher concentration of n-type impurities (for example, As (arsenic)) than the extension region EX.

  Since an n-type well is formed on the upper surface of the semiconductor substrate SB in the vicinity of the region where the capacitive element CPD is formed, unlike the MONOS memory Q1, the upper surface of the semiconductor substrate SB, the diffusion layer DF, and the extension A PN junction is not formed between the region EX. In the region where the capacitive element CPD is formed, a potential is supplied to the well on the upper surface of the semiconductor substrate SB via the contact plug CP, the silicide layer S1, the diffusion layer DF, and the extension region EX, thereby the semiconductor substrate SB. And a capacitance can be generated between the polysilicon films P1 and P2.

  The capacitive element CPD is a lateral capacitive element composed of a plurality of conductor films adjacent to each other in the direction along the main surface of the semiconductor substrate SB. That is, on the semiconductor substrate SB, the conductor film constituting the capacitive element CPD is not formed immediately above or directly below the polysilicon films P1 and P2. For this reason, the height of the capacitive element CPD is the same as the height of each of the MONOS memory Q1 and the low breakdown voltage MOSFET Q2.

  Next, the low voltage MOSFET Q2 shown on the right side of FIG. 2 will be described. In the cross-sectional view on the right side of FIG. 2, the gate electrode GE is formed on the semiconductor substrate SB via the gate insulating film GF2. The low breakdown voltage MOSFET Q2 has the same structure as the above-described MONOS memory Q1 except that the ONO film MF and the memory gate electrode MG are not provided. That is, the side wall of the gate electrode GE has a side wall SW, and the main surface of the semiconductor substrate SB next to the gate electrode GE in the first direction has an n-type semiconductor layer diffusion layer DF and extension region. Source / drain regions made of EX are formed.

  The low breakdown voltage MOSFET Q2 is a field effect transistor that includes the gate electrode GE and the source / drain regions and is driven at a lower voltage than a high breakdown voltage element such as the MONOS memory Q1. For example, the low breakdown voltage MOSFET Q2 is used for a logic circuit, a switching circuit, or the like in the core portion of the semiconductor device.

  A silicide layer S1 made of, for example, CoSi (cobalt silicide) is formed on the respective upper surfaces of the control gate electrode CG, the memory gate electrode MG, the polysilicon films P1 and P2, the gate electrode GE, and the diffusion layer DF. On the semiconductor substrate SB, an etching stopper film ES and an interlayer insulating film L1 are formed so as to cover the MONOS memory Q1, the capacitive element CPD, the low breakdown voltage MONOS memory Q2, and the silicide layer S1. The upper surface of the interlayer insulating film L1 has a flattened and uniform height above the formation regions of the MONOS memory Q1, the capacitive element CPD, and the low breakdown voltage MONOS memory Q2. That is, the distance between the upper surface of the interlayer insulating film L1 and the main surface of the semiconductor substrate SB is constant in any region where the MONOS memory Q1, the capacitive element CPD, or the low breakdown voltage MONOS memory Q2 is formed, and the interlayer insulating film L1. There is no unevenness or height difference on the upper surface of the plate.

  In the interlayer insulating film L1, contact holes are formed through the upper surface and lower surface of the interlayer insulating film L1 and the etching stopper film ES to expose the upper surface of each silicide layer S1. A main conductor film made of, for example, W (tungsten) is formed inside each of the plurality of contact holes via a barrier conductor film containing, for example, Ti (titanium), and the contact made of the barrier conductor film and the main conductor film. A plug CP is formed. The contact plug CP that completely fills the contact hole is formed to supply a predetermined potential to each of the control gate electrode CG, the memory gate electrode MG, the polysilicon films P1 and P2, the gate electrode GE, and the diffusion layer DF. Conductor. The etching stopper film ES is made of, for example, a silicon nitride film, and the interlayer insulating film L1 is made of, for example, a silicon oxide film.

  On the interlayer insulating film L1, an interlayer insulating film L2 made of, for example, a SiOC film which is a low-k film having a dielectric constant lower than that of the silicon oxide film is formed. The interlayer insulating film L2 includes a plurality of wiring grooves that penetrate from the upper surface to the lower surface of the interlayer insulating film L2 and expose the upper surface of the interlayer insulating film L1 and the upper surface of the contact plug CP. A wiring W1 mainly made of Cu (copper) is completely embedded.

  The wiring W1 includes a barrier conductor film containing, for example, Ta (tantalum) formed on the side wall and bottom surface of the wiring groove, and a Cu (copper) film formed in the wiring groove via the barrier conductor film. This is so-called single damascene wiring. The bottom of the wiring W1 is connected to the contact plug CP, and is connected to the control gate electrode CG, the memory gate electrode MG, the polysilicon films P1, P2, the gate electrode GE, and the diffusion layer DF via the contact plug CP. It has the role of supplying the potential.

  In a region not shown in FIG. 2, contact plugs CP and wirings W1 are formed on the polysilicon films P1, P2, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE via the silicide layer S1. Is formed. Although not shown, a wiring layer including a plurality of interlayer insulating films and a plurality of wirings embedded in grooves or holes formed in each of the plurality of interlayer insulating films on the wiring W1. Are stacked. In the present application, a layer including an interlayer insulating film and a wiring formed at the same height as the interlayer insulating film, such as the interlayer insulating film L2 and the wiring W1, is referred to as a wiring layer. The wiring layer is formed along the upper surface of the underlying interlayer insulating film L1.

  Although the semiconductor device according to the present embodiment has been described above, the MONOS memory Q1 does not have the structure having the memory gate electrode MG on the side walls on both sides of the control gate electrode CG as described above, but on the side walls on both sides of the control gate electrode CG. Of these, a structure without the ONO film MF and the memory gate electrode MG adjacent to one side wall may be employed. That is, as will be described later with reference to FIG. 16, the memory gate electrode MG may be formed on at least one side wall of the control gate electrode CG via the ONO film MF. In this case, a sidewall SW is formed on the side wall of the control gate electrode CG that is not in contact with the memory gate electrode MG.

  Further, the sidewall-like polysilicon films P2 at both ends of the capacitive element CPD in the first direction may be omitted. In this case, the polysilicon film P1 is formed on both ends of the capacitive element CPD in the first direction, and the sidewall SW is formed on the sidewall instead of the ONO film MF.

  In addition, here, the structure in which the capacitor element CPD is formed on the active region on the upper surface of the semiconductor substrate SB has been described. However, the capacitor element CPD is formed immediately above the element isolation region made of an insulating film formed on the upper surface of the semiconductor substrate SB. May be.

  The effects of the semiconductor device of this embodiment will be described below with reference to FIG. 17 showing a semiconductor device of a comparative example. FIG. 17 is a cross-sectional view showing a comparative semiconductor device including a MONOS memory and a capacitor element. The left side of the figure shows the MONOS memory, and the right side of the figure shows the capacitor element.

  When two types of conductor films that are close to each other via an insulating film are formed on a semiconductor substrate and a capacitor element that uses a capacitance generated between the conductor films is formed, the structure of the capacitor element is, for example, A conductor film extending in a direction along the main surface of the semiconductor substrate is formed on the semiconductor substrate, and a conductor film extending in a direction along the main surface of the semiconductor substrate is formed on the conductor film via an insulating film. Further formation is conceivable. The structure of such a comparative example is shown in FIG. Note that the MONOS memory Q1 shown on the left side of FIG. 17 has the same structure as the MONOS memory Q1 shown in FIG.

  As shown in FIG. 17, the capacitive element CPDa has polysilicon films P1a and P2a extending in a plane parallel to the main surface of the semiconductor substrate SB and extending in the lateral direction and the depth direction of the cross section of FIG. Yes. Directly above the polysilicon film P1a formed on the semiconductor substrate SB via the insulating film IF1, the polysilicon film P1a is formed via the ONO film MF composed of the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 that are sequentially stacked. A silicon film P2a is formed. As described above, the capacitive element CPDa of the comparative example is an element that generates a capacitance between the polysilicon films P1a and P2a that face each other in the direction (vertical direction) perpendicular to the main surface of the semiconductor substrate SB and are insulated from each other. is there.

  Thus, since the capacitive element CPDa has a laminated structure of conductor films, the height of the capacitive element, that is, the direction perpendicular to the major surface of the semiconductor substrate SB, the uppermost of the capacitive element CPDa from the main surface of the semiconductor substrate SB The distance to the upper surface is not the height from the main surface of the semiconductor substrate SB to the uppermost surface of the polysilicon film P1a, but the height from the main surface of the semiconductor substrate SB to the uppermost surface of the polysilicon film P2a. Here, there is a difference in distance H1 between the height of the upper surface of the polysilicon film P1a and the height of the polysilicon film P2a. Here, the height of the structure including the silicide layer S1 formed on the upper surface of the polysilicon film P2a is defined as the height of the polysilicon film P2a.

  The ONO film MF is continuously formed along each of the upper surface, the side wall, and the upper surface of the semiconductor substrate SB of the polysilicon film P1a. Similarly, the polysilicon film P2a is formed on the ONO film MF along each of the upper surface, the side wall, and the upper surface of the semiconductor substrate SB of the polysilicon film P1a. A sidewall SW is formed on the side wall of the polysilicon film P2a, and a contact plug CP is connected to the upper surface of the polysilicon film P2a next to the polysilicon film P1a via a silicide layer S1. A silicide layer S1 is also formed on the upper surface of the polysilicon film P2a immediately above the polysilicon film P1a.

  Here, the upper surface and the side wall of the polysilicon film P2a near the side wall of the polysilicon film P1a are covered with the side wall SW and the insulating film IF2, and the silicide layer S1 is not formed. In this way, the silicide layer S1 is prevented from being formed on a part of the surface of the polysilicon film P2a. In the region where the polysilicon film P2a is bent, that is, at the corner, the surface of the polysilicon film P2a is curved. This is because the formation of the silicide layer S1 in such a bent region causes a defect.

  The insulating film IF2 is made of, for example, a silicon oxide film, and continuously covers the upper surface of the end of the polysilicon film P2a above the polysilicon film P1a and the side wall of the polysilicon film P2a along the side wall of the polysilicon film P1a. Is formed. For example, when a resistance element made of a semiconductor layer in which an n-type or p-type impurity is implanted is formed on the main surface of the semiconductor substrate SB, the insulating film IF2 has a silicide layer formed on a part of the upper surface of the resistance element. In order to prevent the low efficiency of the resistance element from being lowered, the film is also used to cover a part of the upper surface of the resistance element.

  The capacitive element CPDa is covered with an etching stopper film ES and an interlayer insulating film L1, a plurality of contact plugs CP are formed through the interlayer insulating film, and the silicide layer S1 is formed on the polysilicon films P1a and P2a and the semiconductor substrate SB. It is electrically connected via. The polysilicon film P1a has a width longer than that of the polysilicon film P2a in the depth direction of FIG. 17, and an end portion thereof is exposed from the polysilicon film P2a in plan view. A silicide layer S1 (not shown) is formed on the upper surface of the exposed polysilicon film P1a, and a contact plug CP (not shown) is connected to the upper surface. Here, the silicide layer S1 is not formed on the upper surface of the polysilicon film P1a and in the region covered with the polysilicon film P2a.

  On the interlayer insulating film L1, an interlayer insulating film L2 and a wiring W1 are formed as in the semiconductor device shown in FIG. Although not shown, a wiring layer including a plurality of wirings is stacked on the wiring W1. Here, the height of the upper surface of the interlayer insulating film L1 covering the capacitive element CPDa on the right side in FIG. 17 is higher than the height of the upper surface of the interlayer insulating film L1 covering the left MONOS memory Q1 in FIG. The contact plugs that penetrate the interlayer insulating film L1 also have a difference in height (distance H2). For this reason, the same difference (distance H2) between the height of each of the interlayer insulating film L2 and the wiring W1 on the interlayer insulating film L1 occurs between the MONOS memory Q1 and the capacitor CPDa.

  This is because the etching stopper film ES and the interlayer insulating film L1 having the same film thickness are formed on each of the MONOS memory Q1 and the capacitive element CPDa whose height is higher than the MONOS memory Q1 by the distance H1. . After the formation of the interlayer insulating film L1, the upper surface thereof is planarized by using a CMP (Chemical Mechanical Polishing) method or the like. However, if the height difference of the upper surface of the interlayer insulating film L1 is too large, the interlayer insulating film L1 is subjected to a planarization process. It is difficult to completely planarize the upper surface of the semiconductor substrate SB in parallel with the main surface of the semiconductor substrate SB.

  As described above, since the polysilicon film P2a is formed on the polysilicon film P1a, the height of the element is higher in the capacitive element CPDa than in the MONOS memory Q1. Therefore, the height of the interlayer insulating films L1, L2, the contact plug CP, and the wiring W1 is higher in the region where the capacitive element CPDa is formed than in the region where the MONOS memory Q1 is formed. Although not shown, similarly, when a MOSFET such as the low breakdown voltage MOSFET Q2 shown in FIG. 2 is formed, the capacitive element CPDa is formed from the upper surface of the interlayer insulating film immediately above the region where the MOSFET is formed. The upper surface of the interlayer insulating film L1 immediately above the formed region is higher by the distance H2. It is conceivable that the distance H2 is smaller than the distance H1 due to the flattening step, but here, H1 and H2 are assumed to be the same size.

  If the upper surface of the interlayer insulating film L1 is not flattened for the above reason and unevenness occurs, the accuracy of the subsequent manufacturing process decreases and the difficulty increases. For example, since the height of the capacitive element CPDa is higher than the height of the MONOS memory Q1 or other MOSFET on the same semiconductor substrate SB, the film thickness of the interlayer insulating film L1 covering the vicinity of the capacitive element CPDa is increased. The vertical length of the contact hole that is formed in the vicinity of the capacitive element CPDa and exposes the semiconductor substrate SB is increased.

  In this case, if it is attempted to keep the diameter of the contact hole equal to the diameter of the contact hole in the vicinity of the MONOS memory Q1 or other MOSFET, the length in the vertical direction with respect to the diameter of the contact hole in the vicinity of the capacitive element CPDa. Becomes longer and it becomes difficult to form a contact hole by an etching method. If the contact hole is not properly formed, there is a problem in that the reliability of the semiconductor device is lowered due to, for example, poor conduction of the semiconductor element.

  Also, if a contact hole that is long in the vertical direction and has a small diameter is formed, it becomes difficult to form a barrier conductor film made of Ti (titanium) or the like on the side wall in the contact hole, and a tungsten film is embedded. Becomes difficult. When the formation failure of the film constituting the contact plug CP occurs in this way, problems such as the occurrence of a conduction failure of the semiconductor element or a lower breakdown voltage of the interlayer insulating film occur, and the reliability of the semiconductor device decreases.

  Further, with respect to the above problem, if the diameter of the contact hole is increased in accordance with the increase in the thickness of the interlayer insulating film L1 in the vicinity of the capacitive element CPDa, the diameter of the contact plug CP formed in the contact hole increases. Therefore, it becomes difficult to miniaturize the semiconductor device. Further, since the amount of metal necessary for forming the contact plug CP increases, there arises a problem that the manufacturing cost increases.

  Even if unevenness is not formed on the entire upper surface of the interlayer insulating film L1 and there is no difference in height, when a capacitor element having a structure in which conductor films are stacked is to be formed, the capacitor element CPDa and the interlayer insulating film L1 are formed. In order to maintain a withstand voltage with respect to the upper wiring, it is necessary to increase the thickness of the interlayer insulating film L1 to some extent. That is, if the height of the capacitive element CPDa is high, the film thickness of the interlayer insulating film L1 in the vicinity thereof must be increased. The length of the direction becomes longer. Therefore, if the diameter of the contact plug CP is not increased, there is a high possibility that a formation failure of the contact plug CP will occur. If the diameter of the contact plug CP is increased, it becomes difficult to miniaturize the semiconductor device, and the manufacturing cost is increased. An increasing problem arises.

  Further, when a difference in height occurs on the upper surface of the interlayer insulating film L1 as described above, lithography for forming a groove or a through hole in another interlayer insulating film (for example, the interlayer insulating film L2) formed on the interlayer insulating film L1. In the process, the entire surface of the photoresist film cannot be focused at the time of exposure, and there is a problem that the accuracy of lithography is lowered. That is, the processing accuracy of the insulating film or the wiring formed on the interlayer insulating film L1 having a height difference on the upper surface is lowered.

  Further, when the upper surface of the interlayer insulating film L1 is uneven as described above, a metal film is buried in the wiring trench formed in the interlayer insulating film (for example, the interlayer insulating film L2) thereover, and then on the interlayer insulating film When an unnecessary metal film is removed by a CMP method or the like to form a wiring (eg, wiring W1) made of a metal film that fills the wiring groove, there is a possibility that a short circuit may occur between the wirings. This is because, due to the unevenness, a difference in height also occurs in the interlayer insulating film formed on the interlayer insulating film L1, and as a result, the metal film remains in the recessed region on the upper surface of the interlayer insulating film, and should be insulated from each other. This is because the wirings are integrated and short-circuited via the metal film.

  The various problems described above occur because the height of the capacitive element CPDa having a structure in which conductor films are stacked is higher than the height of other MONOS memories Q1 or MOSFETs. Therefore, the occurrence of the above-described problem can be prevented if the heights of the capacitor element and the other semiconductor elements are uniform.

  Therefore, in this embodiment, instead of a structure in which conductor films are stacked in the vertical direction, a capacitor element having a plurality of conductor films adjacent to each other via an insulating film is formed in a direction along the main surface of the semiconductor substrate. Thus, the heights of the capacitive elements and the semiconductor elements such as the MONOS memory and the MOSFET on the same substrate are made uniform. That is, as shown in FIG. 2, no conductor film (for example, polysilicon film) constituting the capacitive element is formed above each of the polysilicon films P1 and P2 constituting the capacitive element CPD. The CPD is composed of polysilicon films P1 and P2 arranged via an insulating film (ONO film MF) in a direction (first direction) along the main surface of the semiconductor substrate SB.

  Therefore, the control gate electrode CG and the polysilicon film P1 which is the same layer as the gate electrode GE, the polysilicon film P2 buried between the plurality of polysilicon films P1, and the side walls of the polysilicon film P1 are self-aligned. The capacitive element CPD formed of the polysilicon film P2 formed in the same manner has the same height as the MONOS memory Q1 and the low breakdown voltage MOSFET Q2. Therefore, the height of the upper surface of the interlayer insulating film L1 formed on the semiconductor substrate SB so as to cover these semiconductor elements is uniform immediately above the respective formation regions of the respective semiconductor elements, which is a comparative example of FIG. As shown, there is no difference in height depending on the formation region of each semiconductor element.

  As a result, the film thickness of the interlayer insulating film L1 in the vicinity of the capacitive element CPD is equal to the film thickness of the interlayer insulating film L1 in the region where the MONOS memory Q1 or the low breakdown voltage MOSFET Q2 is formed. It is possible to prevent the formation of the contact hole and the contact plug CP from being difficult due to the film L1 being excessively thick. Therefore, the occurrence of a conduction failure of the contact plug CP can be prevented, and the reliability of the semiconductor device can be improved. Further, the diameter of the contact hole formed in the vicinity of the capacitive element CPD can be reduced according to the diameter of the contact plug in the vicinity of the MONOS memory Q1 or the low breakdown voltage MOSFET Q2, thereby facilitating the miniaturization of the semiconductor device. it can.

  Further, since the height of the capacitive element CPD is equal to that of other semiconductor elements, the thickness of the interlayer insulating film L1 on the semiconductor substrate SB is made thinner than that of the capacitive element having the laminated structure of the comparative example. However, the breakdown voltage between the capacitive element CPD and the wiring W1 thereon can be maintained. Accordingly, it is possible to prevent the interlayer insulating film L1 from being thickened and to prevent the contact plug CP from increasing in length in the vertical direction, and thus it is not necessary to increase the diameter of the contact plug CP.

  Further, since the upper surface of the interlayer insulating film L1 is uniform over the entire surface of the semiconductor substrate SB, the film formed on the interlayer insulating film L1 is processed due to the unevenness of the upper surface of the interlayer insulating film L1. It is possible to prevent the occurrence of the problem that the exposure accuracy of the photolithography is lowered or the problem that the wiring W1 is short-circuited. Thereby, the formation accuracy of the wiring layer is improved.

  As described above, in the present embodiment, it is possible to prevent the accuracy of the manufacturing process after the formation of the interlayer insulating film L1 from being lowered and the difficulty of the manufacturing process from being increased. Reliability can be improved.

  In the present embodiment, the capacitor element CPD is formed, and the distance between the adjacent polysilicon films P1 is not excessively separated, so that one polysilicon film P2 is formed between the adjacent polysilicon films P1. Embedded. When the adjacent polysilicon films P1 are largely separated from each other, sidewall-like polysilicon films P2 are formed on the sidewalls on both sides of each polysilicon film P1. It is possible to use as

  On the other hand, in the present embodiment, the area occupied by the capacitive element CPD on the semiconductor substrate SB can be reduced by bringing the polysilicon films P1 close to each other and filling the space with the polysilicon film P2. Accordingly, a capacitor element capable of generating a high capacitance can be formed with a small area, and thus the semiconductor device can be miniaturized.

  As shown in FIG. 17, the capacitive element CPDa shown in FIG. 17 and the capacitive element CPD shown in FIG. 2 are stored as long as the area occupied by the capacitive element in plan view is equal to that in the case where the conductor films are stacked. Capable capacity is equivalent. In an element that generates a capacitance by arranging conductor films extending in the second direction in the first direction, such as the capacitance element CPD of the present embodiment, the polysilicon film P1, This can be handled by changing the number of P2 or the length in the second direction.

  Further, since the space between the adjacent polysilicon films P1 is filled with the polysilicon film P2, the distance between the polysilicon films P1 in the first direction between the opposing ONO films MF is the sidewall-like polysilicon film in the same direction. The size needs to be not more than twice the width of P2.

  In the capacitive element CPDa of the comparative example shown in FIG. 17, since the silicide layer is not formed on the upper surface of the polysilicon film P1a covered with the polysilicon film P2a, the polysilicon film P1a has a high resistance. In this case, in a semiconductor device that requires high-speed operation, there arises a problem that the responsiveness of the capacitive element CPDa is deteriorated. This problem occurs because the capacitance element CPDa of the comparative example forms the silicide layer S1 in a state where the upper surface of the polysilicon film P1a is covered with the polysilicon film P2a.

  On the other hand, in the present embodiment, since the polysilicon films P1 and P2 alternately arranged in the first direction are formed as shown in FIG. 2, the upper surfaces of the respective polysilicon films constituting the capacitive element CPD are The silicide layer S1 can be formed in an exposed state. Therefore, the silicide layer S1 can be formed on the entire upper surfaces of the polysilicon films P1 and P2 constituting the completed capacitive element CPD, and the resistance of the polysilicon films P1 and P2 can be reduced. Thereby, even when high-speed operation is required, the responsiveness of the capacitive element CPD can be improved.

  Below, the manufacturing method of the semiconductor device of this Embodiment is demonstrated using FIGS. 3 to 12 are cross-sectional views illustrating the manufacturing process of the semiconductor device of the present embodiment. 3 to 12, a MONOS memory formation region (first region) 1A and a capacitor element formation region (second region) 1B are shown in order from the left side of the drawing.

  In FIG. 2, the case where the MOSFET Q2 is formed on the semiconductor substrate SB has been described. However, in the following description of the manufacturing process, description of the manufacturing process of the MOSFET used in the logic circuit or the like is omitted. In the semiconductor device of this embodiment, the low breakdown voltage MOSFET may be formed on the semiconductor substrate SB, and the manufacturing process uses a known method. The gate electrode of the low breakdown voltage MOSFET is formed of a film in the same layer as a polysilicon film P1 described later.

  First, as shown in FIG. 3, a semiconductor substrate SB made of, for example, single crystal silicon is prepared. Subsequently, a trench is formed in the main surface of the semiconductor substrate SB, and an element isolation region (not shown) is formed by embedding a silicon oxide film or the like in the trench. The element isolation region is, for example, STI (Shallow Trench Isolation) or LOCOS (Local Oxidization of Silicon), and is an insulating region formed to electrically insulate and isolate each semiconductor element on the semiconductor substrate. Thereafter, impurities are implanted into the main surface of the semiconductor substrate SB by an ion implantation method or the like to form a well (not shown). At this time, in the MONOS memory formation region 1A, a p-type well (for example, B (boron)) is implanted into the upper surface of the semiconductor substrate SB to form a p-type well. In the capacitive element formation region 1B, the semiconductor substrate SB An n-type well is formed by implanting an n-type impurity (for example, As (arsenic)) on the upper surface. Such placement is performed by using a photoresist film formed by photolithography as a mask.

  Next, as shown in FIG. 4, an insulating film IF1 and a polysilicon film P1 are sequentially formed on the main surface of the semiconductor substrate SB. The insulating film IF1 is made of, for example, a silicon oxide film, and the insulating film IF1 and the polysilicon film P1 are formed by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, an n-type impurity (for example, As (arsenic)) is implanted into part of the polysilicon film P1 by ion implantation using a photolithography technique.

  Thereafter, after a photoresist film pattern is formed on the polysilicon film P1 by photolithography, a part of the polysilicon film P1 and the insulating film IF1 is removed by a dry etching method using the photoresist film as a mask. Thus, the upper surface of the semiconductor substrate SB is exposed. Thereby, the control gate electrode CG made of the polysilicon film P1 and the gate insulating film GF1 made of the insulating film IF1 are formed in the MONOS memory forming region 1A.

  Further, by processing the polysilicon film P1 and the insulating film IF1 by the above-described dry etching method, on the semiconductor substrate SB in the capacitor element formation region 1B, the direction along the main surface of the semiconductor substrate SB is shown in FIG. A stacked pattern including a plurality of polysilicon films P1 extending in the depth direction (second direction) and the insulating film IF1 immediately below them is formed. In the capacitive element formation region 1B, the polysilicon film P1 and the insulating film are arranged in the direction (first direction) perpendicular to the extending direction (second direction) of the polysilicon film P1 and along the main surface of the semiconductor substrate SB. A plurality of the laminated patterns made of the film IF1 are formed.

  Next, as shown in FIG. 5, a silicon oxide film X1, a silicon nitride film N1, a silicon oxide film X2, and a polysilicon film P2 are sequentially formed on the entire main surface of the semiconductor substrate SB by using, for example, a CVD method. Form. Here, the thickness of each of the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 is 6 nm, and the thickness of the polysilicon film P2 is 50 nm. Thereby, the upper surface and the side walls of the pattern made of the insulating film IF1 and the polysilicon film P1 and the pattern made of the gate insulating film GF1 and the control gate electrode CG are covered with the silicon oxide film X1. The laminated film composed of the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 constitutes an ONO film MF.

  At this time, a pattern of a plurality of polysilicon films P1 is formed on the semiconductor substrate SB in the capacitor element formation region 1B, and the grooves between the adjacent polysilicon films P1 are formed of the silicon oxide film X1 and the silicon nitride film. It is filled with N1, silicon oxide film X2, and polysilicon film P2. Here, a case where a groove between adjacent polysilicon films P1 is completely filled with the silicon oxide film X1, the silicon nitride film N1, the silicon oxide film X2, and the polysilicon film P2 will be described. It does not have to be completely embedded. That is, a recess is formed on the upper surface of the buried polysilicon film P2 between adjacent polysilicon films P1, and the height of the bottom surface of the recess is lower than the height of the polysilicon film P1 sandwiching the recess. It may be formed.

  However, the height of the bottom surface of the concave portion, that is, the distance from the lowest upper surface of the ONO film MF between the adjacent polysilicon films P1 to the lowest upper surface of the polysilicon film P2 is a plurality in the first direction. The thickness of the polysilicon film P2 is larger than the thickness of the polysilicon film P2 formed along the upper surface of the semiconductor substrate SB outside the polysilicon film P1.

  This is because if the bottom surface of the concave portion is too low, the polysilicon film P2 is partially removed and the upper surface of the ONO film MF is exposed by an etching process described later with reference to FIG. This is because, since the polysilicon film P2 between the silicon films P1 is separated into two, it is important to avoid this, in order to facilitate miniaturization of the semiconductor device. That is, the polysilicon film P1 and the polysilicon film P2 become two types of conductor films that form a capacitive element in a later process, but the polysilicon film P2 between the polysilicon films P1 can be integrated without being separated. For example, a capacitive element with a smaller area can be formed without reducing the capacitance. Therefore, the etching process described later with reference to FIG. 6 reduces the distance between the polysilicon films P1 to such an extent that the ONO film MF between the polysilicon films P1 is not exposed. It is necessary to embed with P2.

  Next, as shown in FIG. 6, the polysilicon film P2 is partially removed using a dry etching method to expose the upper surface of the silicon oxide film X2. The polysilicon film P2 is etched back by anisotropic dry etching to leave the polysilicon film P2 only on the side walls of the control gate electrode CG and the polysilicon film P1. Thereby, the height of the upper surface of the polysilicon film P2 buried between the adjacent polysilicon films P1 is substantially the same as the height of the upper surface of the polysilicon film P1.

  At this time, the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 are formed on the side wall of the polysilicon film P1 in the capacitor element formation region 1B and not adjacent to the other polysilicon film P1. As a result, the polysilicon film P2 remains in a sidewall shape. That is, in the capacitive element formation region 1B, of the plurality of polysilicon films P1 arranged in the first direction, the sidewall of the outermost polysilicon film P1 that is not adjacent to the other polysilicon film P1. In this, a sidewall-like polysilicon film P2 is formed in a self-aligned manner. Similarly, in the MONOS memory formation region 1A, the memory gate electrode MG made of the sidewall-like polysilicon film P2 is formed on the side walls on both sides of the control gate electrode CG via the ONO film MF in a self-aligned manner.

  Note that the trench between the adjacent polysilicon films P1 in the capacitive element formation region 1B is still filled with the silicon oxide film X1, the silicon nitride film N1, the silicon oxide film X2, and the polysilicon film P2, and the trench The inner polysilicon film P2 does not have a sidewall shape. Thus, a capacitive element CPD composed of a plurality of polysilicon films P1 and P2 that are insulated from each other via the ONO film MF and alternately arranged in the first direction is formed in the capacitive element formation region 1B.

  An ONO film MF is interposed between the adjacent polysilicon films P1 and P2, and the polysilicon films P1 and P2 are insulated from each other. The capacitive element CPD is a PIP capacitive element formed by insulating a plurality of polysilicon films. The PIP capacitor element is an element that generates a capacitance between the adjacent polysilicon film P1 and polysilicon film P2, which are insulated from each other via the ONO film MF.

  Further, since the space between the adjacent polysilicon films P1 is filled with the polysilicon film P2, the distance between the polysilicon films P1 in the first direction between the opposing ONO films MF is the sidewall-like polysilicon film in the same direction. The size needs to be not more than twice the width of P2.

  Next, as shown in FIG. 7, by partially removing the ONO film MF using a wet etching method, the upper surface of the semiconductor substrate SB, the upper surface of the control gate electrode CG, and the upper surface of the polysilicon film P1 are exposed. . Thus, the ONO film MF is removed and the semiconductor substrate SB is exposed in a region not covered with the control gate electrode CG and the memory gate electrode MG polysilicon films P1 and P2. That is, the ONO film MF in other regions is removed while leaving the ONO film MF in contact with the side walls and the bottom surface of the control gate electrode CG and the memory gate electrode MG polysilicon films P1 and P2.

  Thereafter, the ONO film MF and the memory gate electrode MG on one side wall of the control gate electrode CG may be removed before performing the process described with reference to FIG. A case where the MONOS memory is formed while leaving the memory gate electrode MG on the side wall will be described.

  Next, as shown in FIG. 8, an n-type impurity (for example, As (arsenic)) is implanted into the upper surface of the semiconductor substrate SB at a relatively low concentration by using an ion implantation method. Thereby, the extension region EX is formed on the main surface of the semiconductor substrate SB in the MONOS memory forming region 1A. In the MONOS memory formation region 1A, an extension region EX is formed on the upper surface of the semiconductor substrate SB exposed beside the structure including the control gate electrode CG and the memory gate electrode MG that are in contact with each other via the ONO film MF.

  Thereafter, an insulating film is formed on the entire main surface of the semiconductor substrate SB using, for example, a CVD method, and then the insulating film is partially removed using a dry etching method to expose the upper surface of the semiconductor substrate SB. Thus, the sidewall SW made of the insulating film is formed. Sidewall SW is formed in a self-aligned manner on one exposed side wall of memory gate electrode MG and the side wall of capacitive element CPD. The material of the sidewall SW can be, for example, a silicon oxide film or a stacked film of a silicon nitride film and a silicon oxide film.

  Thereafter, using an ion implantation method, an n-type impurity (for example, As (arsenic)) is implanted into the upper surface of the semiconductor substrate SB at a higher concentration than the ion implantation performed for forming the extension region EX. Thereby, a diffusion layer DF having an impurity concentration higher than that of the extension region EX is formed on the main surface of the semiconductor substrate SB in the MONOS memory forming region 1A and the capacitive element forming region 1B. The diffusion layer DF is a semiconductor region that is deeper than the extension region EX.

  In the present embodiment, the MONOS memory formation region 1A and the extension region EX of the capacitor element formation region 1B are formed by a single ion implantation process, and the MONOS memory formation region 1A and the capacitor element formation region are formed by a single ion implantation process. A 1B diffusion layer DF is formed. However, in actuality, it may be considered that the extension region EX or the diffusion layer DF is formed by dividing the ion implantation process depending on the type of element or the conductivity type of the element.

  In the MONOS memory formation region 1A, the diffusion layer DF is formed on the structure including the control gate electrode CG and the memory gate electrode MG that are in contact with each other via the ONO film MF, and the upper surface of the semiconductor substrate SB exposed from the sidewall SW on the side wall. . In the capacitive element formation region 1B, the diffusion layer DF is formed on the upper surface of the semiconductor substrate SB exposed from the capacitive element CPD including the polysilicon films P1 and P2 that are in contact with each other via the ONO film and the sidewall SW on the sidewall.

  By forming the diffusion layer DF, a pair of source / drain regions including the extension region EX and the diffusion layer DF adjacent to the extension region EX are formed on the upper surface of the semiconductor substrate SB in the MONOS memory formation region 1A. The source / drain regions have an LDD structure including a diffusion layer DF having a relatively high impurity concentration and an extension region EX having an impurity concentration lower than that of the diffusion layer DF.

  Through the above steps, the control gate electrode CG, the memory gate electrode MG adjacent to the side wall of the control gate electrode CG via the ONO film MF, the control gate electrode CG, and the control gate electrode CG are formed on the semiconductor substrate SB in the MONOS memory formation region 1A. A MONOS memory Q1 having source / drain regions formed on the upper surface of the semiconductor substrate SB so as to sandwich the memory gate electrode MG is formed. The MONOS memory Q1 has at least a silicon oxide film X1 and a silicon nitride film N1 functioning as a charge storage film in the ONO film MF.

  Here, the height of the MONOS memory Q1 is the height of the upper surface of the control gate electrode CG, and the height of the capacitive element CPD is the height of the upper surface of the polysilicon film P1. Since the control gate electrode CG is a film in the same layer formed in the same process as the polysilicon film P1 in the capacitive element formation region 1B, the height of the MONOS memory Q1 and the height of the capacitive element CPD are the same.

  Next, as shown in FIG. 9, a silicide layer S1 is formed on the upper surfaces of the diffusion layer DF, the control gate electrode CG, the memory gate electrode MG, and the polysilicon films P1 and P2, using a known salicide technique. The silicide layer S1 is a conductive film made of, for example, cobalt silicide (CoSi). The silicide layer S1 is formed by forming a metal film such as Co (cobalt) on the semiconductor substrate SB and then reacting the metal film and the silicon film by heat treatment. At this time, since the upper surfaces of the polysilicon films P1 and P2 are both exposed from other insulating films or the like in the capacitor element formation region 1B, the metal film is formed in contact with the upper surfaces of the polysilicon films P1 and P2. By performing the heat treatment, a silicide layer S1 is formed on the entire upper surface of the polysilicon films P1 and P2.

  Thereafter, an etching stopper film ES made of, for example, a silicon nitride film and an interlayer insulating film L1 made of, for example, a silicon oxide film are sequentially formed on the entire upper surface of the semiconductor substrate SB by using a CVD method or the like. At this time, unevenness is formed on the upper surface of the interlayer insulating film L1 due to the presence or absence of an element formed on the upper surface of the semiconductor substrate SB or the height of the element. When the height difference between the elements is large, the height difference of the unevenness is also large. However, since the height of the MONOS memory Q1 and the height of the capacitive element CPD are the same as described above, the MONOS memory Q1 and the capacitive element are the same. The height of the upper surface of the interlayer insulating film L1 immediately above each CPD is the same.

  Next, as shown in FIG. 10, the upper surface of the interlayer insulating film L1 is polished and flattened by using, for example, a CMP method. As described above, when the difference in height between the plurality of elements formed on the semiconductor substrate SB is large, the difference in height of the unevenness formed on the upper surface of the interlayer insulating film L1 also increases. In this case, even if it is attempted to planarize the upper surface of the interlayer insulating film L1 by a CMP method or the like, there is a risk that a difference in height remains on the upper surface of the interlayer insulating film L1. In the present embodiment, since the height of the MONOS memory Q1 and the height of the capacitive element CPD are the same, the upper surface of the interlayer insulating film L1 above those semiconductor elements can be easily flattened.

  Next, as shown in FIG. 11, a plurality of contact holes penetrating the interlayer insulating film L1 and the etching stopper film ES are formed by using a photolithography technique and a dry etching method.

  In the MONOS memory formation region 1A, a plurality of contact holes penetrating the interlayer insulating film L1 and the etching stopper film ES are opened, so that the diffusion layer DF, the control gate electrode CG, and the silicide layer S1 above the memory gate electrode MG are formed. Expose the top surface. In the capacitor element formation region 1B, a plurality of contact holes penetrating the interlayer insulating film L1 and the etching stopper film ES are opened, so that the upper surfaces of the silicide layers S1 above the polysilicon films P1, P2 and the diffusion layer DF are exposed. Let In FIG. 11, the contact holes formed immediately above the polysilicon films P1, P2, the control gate electrode CG, and the memory gate electrode MG are not shown. These contact holes are formed in a region not shown in FIG.

  Subsequently, for example, a W (tungsten) film is buried in each of the plurality of contact holes via a barrier conductor film containing, for example, Ti (titanium), and an unnecessary conductive film on the interlayer insulating film L1 is removed. Thus, a contact plug (connection member) CP including the barrier conductor film and the tungsten film embedded in each contact hole is formed. Each of the plurality of contact plugs CP is a conductor formed to supply a predetermined potential to the diffusion layer DF, the control gate electrode CG, the memory gate electrode MG, and the polysilicon films P1 and P2.

  In a specific step of forming the contact plug CP, first, the barrier conductor film (not shown) is formed on the entire upper surface of the semiconductor substrate SB by using a sputtering method or the like, and the surface in the contact hole is formed with the barrier conductor film. cover. Thereafter, a tungsten film is formed on the semiconductor substrate SB by using a sputtering method or the like, and each of the plurality of contact holes is completely filled with the tungsten film. Subsequently, the upper surface of the interlayer insulating film L1 is exposed by removing the excess barrier conductor film and the tungsten film on the interlayer insulating film L1 by using a CMP method or the like. Thereby, the upper surfaces of the interlayer insulating film L1 and the tungsten film are flattened, and the contact plug CP made of the barrier conductor film and the tungsten film is formed in each contact hole.

  Next, as shown in FIG. 12, an interlayer insulating film L2 made of SiOC or the like is formed on the interlayer insulating film L1 by using, for example, a CVD method. Thereafter, a plurality of wiring trenches that penetrate the interlayer insulating film L2 and expose the upper surface of the contact plug CP are formed by using a photolithography technique and a dry etching method. Subsequently, each wiring groove is completely filled with a metal film formed by sputtering or electrolytic plating so as to cover the side wall and bottom surface of each wiring groove, and then the excess metal on the interlayer insulating film L2 is filled. By removing the film and exposing the upper surface of the interlayer insulating film L2, the wiring W1 made of the metal film left inside each wiring trench is formed.

  In a specific process of forming the wiring W1, first, as described above, after forming the interlayer insulating film L2 and a plurality of wiring grooves penetrating the interlayer insulating film L2, a sputtering method or the like is performed on the entire upper surface of the semiconductor substrate SB. For example, a barrier conductor film (not shown) containing Ta (tantalum) is formed, and the surface of each wiring groove and the interlayer insulating film L2 is covered with the barrier conductor film. Then, after forming a thin seed film made of Cu (copper) on the semiconductor substrate SB using a sputtering method, a Cu (copper) film serving as a main conductor film of the wiring W1 is formed using an electrolytic plating method. Then, each wiring groove is completely embedded. Subsequently, by removing the excess barrier conductor film and Cu (copper) film on the interlayer insulating film L2 using a CMP method or the like, the barrier conductor film, the seed film, and the main conductor film are formed in each wiring groove. A wiring W1 is formed.

  By the CMP process for forming the wiring W1, the upper surface of the interlayer insulating film L2 is exposed, and the upper surfaces of the interlayer insulating film L2 and the wiring W1 are planarized. In the subsequent process, a plurality of wiring layers including interlayer insulating films, wiring in the wiring trenches opened in the interlayer insulating films and vias in the via holes are stacked on the interlayer insulating film L2 to form upper layer wiring (illustrated). No) is completed, and the semiconductor device of this embodiment is completed. As described with reference to FIG. 1, the capacitive element CPD has a structure in which a plurality of polysilicon films P1 and P2 extending in the second direction are alternately arranged in the first direction, as described with reference to FIG.

  Since an n-type well is formed on the upper surface of the semiconductor substrate SB in the vicinity of the capacitive element formation region 1B, unlike the MONOS memory Q1, the upper surface of the semiconductor substrate SB, the diffusion layer DF, and the extension region EX No PN junction is formed between them. The semiconductor substrate SB is insulated from the polysilicon film P1 through the insulating film IF1, and is insulated from the polysilicon film P2 through the ONO film MF. Therefore, in the capacitive element formation region 1B, the potential is supplied to the well on the upper surface of the semiconductor substrate SB via the contact plug CP, the silicide layer S1, the diffusion layer DF, and the extension region EX. Capacitance can also be generated between one of the silicon films P1 and P2.

  Below, the effect of the manufacturing method of the semiconductor device of this Embodiment is demonstrated using the comparative example shown in FIGS. 18 and 19 are cross-sectional views for explaining a manufacturing process of a semiconductor device as a comparative example. 18 and 19, similarly to FIGS. 3 to 12, the MONOS memory formation region 1A is shown on the left side of the drawing, and the capacitive element formation region 1C is shown on the right side of the drawing. However, unlike FIGS. 3 to 12, in FIGS. 18 and 19, the MONOS memory formation region 1 </ b> A and the capacitor element formation region 1 </ b> C are not shown separately in the respective drawings, and the semiconductor substrate SB between the regions is not shown. A structure in which an element isolation region EI is formed on the upper surface is shown. Although not shown, other semiconductor elements such as MOSFETs are formed on the semiconductor substrate SB in addition to the MONOS memory.

  As a capacitive element formed on a semiconductor substrate, a capacitive element having a structure in which another conductor film is stacked on a conductor film via an insulating film in a direction perpendicular to the main surface of the semiconductor substrate can be considered. In this case, since the capacitive element has a structure in which a conductive film is further laminated on the conductive film, the height of the capacitive element is higher than other semiconductor elements such as MONOS memories or MOSFETs.

  As a comparative example, a manufacturing process in the case of forming a capacitor element having a laminated structure of conductor films and a MONOS memory will be described below.

  First, as shown in FIG. 18, the control gate is formed on the semiconductor substrate SB in the MONOS memory formation region 1A via the gate insulating film GF1 by performing the same process as that described with reference to FIGS. An electrode CG is formed, and a polysilicon film P1a is formed on the semiconductor substrate SB in the capacitor element formation region 1C via the insulating film IF1, and these are covered with the polysilicon film P2a.

  The semiconductor device of the comparative example is obtained by laminating a conductor film extending in a planar manner along the main surface of the semiconductor substrate SB on a conductor film extending in a planar shape along the main surface of the semiconductor substrate SB. Therefore, the polysilicon film P1a shown in FIG. 18 is formed not as a pattern extending in the position direction but as a pattern extending in a planar shape along the main surface of the semiconductor substrate SB.

  Further, the polysilicon film P2a formed (deposited) on the entire upper surface of the semiconductor substrate SB is not formed so as to be embedded between adjacent polysilicon films as in the present embodiment. It is formed along the upper surface and side wall of the silicon film P1a.

  Thereafter, a photoresist film PR1 that covers only the polysilicon film P2a in the capacitor element formation region 1C is formed by using a photolithography technique. Specifically, the photoresist film PR1 is continuously formed so as to cover the semiconductor substrate SB immediately above the polysilicon film P1a and in the vicinity of the polysilicon film P1a. However, a region (not shown) where a contact plug is connected to the upper surface of the polysilicon film P1a via a silicide layer in a later step is exposed from the photoresist film PR1. The photoresist film PR1 is formed to leave the polysilicon film P2a on the polysilicon film P1a.

  Next, as shown in FIG. 19, the etching process described with reference to FIG. 6 is performed using the photoresist film PR1 as a mask, so that the ONO film MF is interposed on the side wall of the control gate electrode CG in the MONOS memory formation region 1A. Then, the memory gate electrode MG is formed, the polysilicon film P2a around the capacitive element in the capacitive element forming region 1C is removed, and the surface of the ONO film MF is exposed. At this time, since the polysilicon film P2a covering the upper surface and the side wall of the polysilicon film P1a in the capacitor element formation region 1C is covered with the photoresist film PR1, it is not removed by the etching process. Subsequently, the photoresist film PR1 is removed. The subsequent steps are the same as those described with reference to FIGS. 7 to 10 to obtain the structure shown in FIG.

  That is, after the ONO film MF exposed from the polysilicon film P2a is removed, the extension region EX, the sidewall SW, and the diffusion layer DF are sequentially formed, followed by the etching stopper film ES and the interlayer insulating film L1, and then the interlayer The top surface of the insulating film L1 is planarized. As a result, the MONOS memory Q1 and the capacitive element CPDa formed of the polysilicon films P1a and P2a are formed.

  The MONOS memory Q1 shown in FIG. 19 has the same structure as the MONOS memory Q1 shown in FIG. 10, but the capacitive element CPDa in FIG. 19 is different from the capacitive element CPD in FIG. A polysilicon film P2a laminated thereover via an ONO film MF is provided. In FIG. 19, no silicide layer is formed on the upper surface of the polysilicon film P1a in the region covered with the polysilicon film P2a. A silicide layer S1 is formed on the upper surface of the polysilicon film P2a except for a region covered with the sidewall SW and the insulating film IF2. As described above, the insulating film IF2 is provided to prevent a defect from occurring due to the formation of a silicide layer on the surface in the vicinity of the corner of the polysilicon film P2a.

  At this time, the height of the capacitive element CPDa is higher than the height of the MONOS memory Q1 because the polysilicon film P2a and the ONO film MF are formed on the polysilicon film P1a. That is, as shown in FIG. 19, the height of the capacitive element CPDa is higher than the MONOS memory Q1 by the distance H1. For this reason, the upper surface of the interlayer insulating film L1 covering the upper portions of these semiconductor elements is higher immediately above the capacitor element CPDa than directly above the MONOS memory Q1, and the upper and lower surfaces of the interlayer insulating film L1 have irregularities having a large height difference. Is formed.

  It is difficult to planarize the upper surface of the interlayer insulating film L1 having such a shape. As shown in FIG. 19, even after the planarization step by polishing such as CMP, the MONOS memory forming region 1A and A step is formed on the upper surface of the interlayer insulating film L1 between the capacitor element formation region 1C and the upper surface of the interlayer insulating film L1 is not flat. This is because it is technically difficult to completely flatten the upper surface of the insulating film having large irregularities on the upper surface. That is, in the planarization step, it is difficult to improve the flatness of the surface after polishing unless the unevenness of the surface to be polished is reduced as much as possible by the CMP method or the like.

  At this time, a difference in height of the distance H3 occurs between the upper surface of the interlayer insulating film L1 between the MONOS memory formation region 1A and the capacitor element formation region 1C. The distance H3 is the same as or smaller than the distance H1. Here, it is assumed that the distance H3 is the same size as the distance H1.

  The height of the upper surface of the interlayer insulating film L1 in the capacitor element formation region 1C is higher even immediately above the vicinity of the polysilicon film P1a, except immediately above the region where the polysilicon films P1a and P2a overlap in plan view. Thus, there is a difference in the film thickness of the interlayer insulating film L1 between the MONOS memory formation region 1A and the capacitor element formation region 1C.

  Next, by performing the contact plug CP forming step and the wiring layer forming step on the interlayer insulating film L1 described with reference to FIGS. 11 and 12, the semiconductor device of the comparative example shown in FIG. 17 is completed. In order to form the interlayer insulating film L2 and the wiring W1 on the interlayer insulating film L1, the interlayer insulating film L2 and the wiring W1 also have a distance H2 between the region where the MONOS memory Q1 is formed and the region where the capacitive element CPDa is formed. A difference in height occurs. The distances H1, H2, and H3 are approximately the same size.

  As described above, when the upper surface of the interlayer insulating film L1 is not flattened and unevenness occurs, the accuracy of the subsequent manufacturing process decreases and the difficulty increases. That is, in the region where the capacitive element CPDa is formed, the vertical length of the contact hole that exposes the silicide layer S1 on the upper surface of the semiconductor substrate SB becomes long, and it becomes difficult to form the contact hole. In addition, if a contact hole that is long in the vertical direction and has a small diameter is formed, it becomes difficult to form a contact plug CP in the contact hole, which causes problems such as poor conduction of the semiconductor element or low breakdown voltage of the interlayer insulating film. As a result, the reliability of the semiconductor device decreases.

  Further, with respect to the above problem, if the diameter of the contact hole is increased in accordance with the increase in the thickness of the interlayer insulating film L1 in the vicinity of the capacitive element CPDa, the diameter of the contact plug CP formed in the contact hole increases. As a result, it is difficult to miniaturize the semiconductor device, and the manufacturing cost increases.

  Further, when a difference in level occurs on the upper surface of the interlayer insulating film L1 as described above, or for forming a groove or a through hole in another interlayer insulating film (for example, the interlayer insulating film L2) formed on the interlayer insulating film L1. In the lithography process, it is impossible to focus on the entire surface of the photoresist film at the time of exposure, which causes a problem that the accuracy of lithography is lowered. That is, the processing accuracy of the insulating film or the wiring formed on the interlayer insulating film L1 having a height difference on the upper surface is lowered. Even when a contact hole is opened in the interlayer insulating film L1, it is difficult to focus when exposing a photoresist film used as a mask to define the position of the contact hole and the shape of the opening. The above problem occurs.

  Further, if the upper surface of the interlayer insulating film L1 is uneven as described above, a plurality of metal films formed in the plurality of wiring grooves formed in the interlayer insulating film (for example, the interlayer insulating film L2) thereon may be short-circuited. There is.

  On the other hand, in the present embodiment, as shown in FIG. 12, different polysilicon films P1 and P2 are arranged in a direction along the upper surface of the semiconductor substrate SB and insulated from each other by the ONO film MF. The height of the capacitive element CPD composed of the films P1 and P2 is reduced. Since the PIP capacitor of this embodiment does not have a structure in which different polysilicon films are stacked in a direction perpendicular to the main surface of the semiconductor substrate, the height of the element can be reduced, and other memories can be used. The height of the element can be aligned with that of the element or FET. Accordingly, the upper surface of the interlayer insulating film L1 formed above the capacitor element CPD having the same height and the other semiconductor elements can be easily flattened. It is possible to prevent the reliability of the semiconductor device from being lowered due to the formation of the step on the upper surface, and to facilitate miniaturization of the semiconductor device.

  Specifically, the film thickness of the interlayer insulating film L1 in the vicinity of the capacitive element CPD is equal to the film thickness of the interlayer insulating film L1 in the region where the MONOS memory Q1 or the low breakdown voltage MOSFET Q2 is formed. It can be prevented that the formation of the contact hole and the contact plug CP is difficult due to the film thickness of the interlayer insulating film L1 being excessively thick. Therefore, the occurrence of a conduction failure of the contact plug CP can be prevented, and the reliability of the semiconductor device can be improved. Further, the diameter of the contact hole formed in the vicinity of the capacitive element CPD can be reduced according to the diameter of the contact plug in the vicinity of the MONOS memory Q1 or the low breakdown voltage MOSFET Q2, thereby facilitating the miniaturization of the semiconductor device. it can.

  Further, since the upper surface of the interlayer insulating film L1 is flat over the entire surface of the semiconductor substrate SB, the film formed on the interlayer insulating film L1 is processed due to the unevenness of the upper surface of the interlayer insulating film L1. The problem that the exposure accuracy of photolithography decreases, the problem that the exposure accuracy of photolithography when the contact hole is formed in the interlayer insulating film L1, or the problem that the wiring W1 is short-circuited can be prevented. Thereby, the formation accuracy of the wiring layer is improved.

  As described above, in the present embodiment, it is possible to prevent the accuracy of the manufacturing process after the formation of the interlayer insulating film L1 from being lowered and the difficulty of the manufacturing process from being increased. Reliability can be improved.

  Further, in the present embodiment, as described above, the distance between the adjacent polysilicon films P1 is not excessively separated, and one polysilicon film P2 is embedded between the adjacent polysilicon films P1, It is possible to reduce the area occupied by the capacitive element CPD on the semiconductor substrate SB. Accordingly, a capacitor element capable of generating a high capacitance can be formed with a small area, and thus the semiconductor device can be miniaturized.

  In the capacitive element CPDa of the comparative example shown in FIG. 17, since the silicide layer is not formed on the upper surface of the polysilicon film P1a covered with the polysilicon film P2a, the polysilicon film P1a has a high resistance, and the capacitance element CPDa There arises a problem that the responsiveness deteriorates.

  On the other hand, in the present embodiment, as shown in FIG. 12, the polysilicon films P1 and P2 alternately arranged in the first direction are formed, and the upper surfaces of the respective polysilicon films constituting the capacitor element CPD are exposed. Since the silicide layer S1 can be formed in this manner, the silicide layer S1 can be formed on the entire upper surfaces of the polysilicon films P1 and P2, and the responsiveness of the capacitive element CPD can be improved.

  As a structure of the capacitor element, after forming a conductor film on a semiconductor substrate via an insulating film, the conductor film is processed into a plurality of patterns using a photolithography technique, an etching method, or the like. A structure is conceivable in which charges are accumulated between the plurality of patterns insulated from each other by embedding an insulating film between them. However, the closer the distance between the conductor films constituting the capacitive element, the larger the amount of charge that can be accumulated, whereas the patterns processed using photolithography technology can reduce the distance between them. Therefore, it is difficult to form a capacitor with a large capacity.

  On the other hand, in the capacitive element CPD of the present embodiment shown in FIG. 12, after the polysilicon film P1 constituting the capacitive element CPD is formed, the ONO film MF, which is a thin insulating film for insulating the conductor films, is formed. Since the polysilicon film P2 is formed after that, the distance between the polysilicon films P1 and P2 can be reduced as compared with the case where one pattern is processed and separated as described above. Therefore, a plurality of conductor films that are closer to each other can be formed, so that the capacitance of the capacitor CPD can be increased.

  In addition, as described with reference to FIG. 18, when the capacitor elements CPDa are formed by stacking the polysilicon films P1a and P2a, in order to leave the polysilicon film P2a on the polysilicon film P1a, a photoresist film It is necessary to perform a step of covering the polysilicon film P2a with PR1 and a step of removing the photoresist film PR1 after removing a part of the polysilicon film P2a after the step. For this reason, in the manufacturing process of the semiconductor device of the comparative example described above, there is a problem that the manufacturing process increases in order to form the capacitive element.

  On the other hand, as described with reference to FIGS. 3 to 12, the capacitive element CPD can be formed by forming a conductor film on the side wall of the conductor film via the ONO film, similarly to the MONOS memory Q1. Therefore, it is possible to form the capacitive element CPD in accordance with the formation process of the MONOS memory Q1 without increasing unnecessary processes. Therefore, it is possible to prevent the manufacturing process of the semiconductor device from becoming complicated and increasing the manufacturing cost of the semiconductor device.

  Hereinafter, modified examples of the semiconductor device of this embodiment will be described with reference to FIGS. 13 to 15 are plan layouts showing modifications of the semiconductor device of the present embodiment. FIG. 16 is a cross-sectional view showing a modification of the semiconductor device of the present embodiment.

  In FIG. 1, as a planar layout of the capacitive element CPD, a plurality of polysilicon films P1, P2 extending in one direction are arranged in the first direction, and contact plugs are formed on the upper surfaces of the end portions of the respective polysilicon films P1, P2. Although a structure in which CPs are connected is shown, the capacitor element CPD of the present embodiment is not limited to such an arrangement, and may have a layout as shown in FIGS.

  The polysilicon film P1 constituting the capacitive element CPD which is one of the modifications of the present embodiment shown in FIG. 13 includes a pattern extending in the first direction and one side wall in the second direction of the pattern. A plurality of patterns extending in the second direction are arranged side by side in the first direction, and have a comb shape in which these patterns are integrated. The polysilicon film P2 is formed along the side wall of the polysilicon film P1 so as to surround the polysilicon film P1 in plan view, and the ONO film MF is interposed between the polysilicon films P1 and P2. The capacitance of the capacitive element CPD is generated between each of the polysilicon films P1 and P2 mainly extending in the second direction and alternately arranged in the first direction.

  The contact plug CP that feeds power to the polysilicon film P1 protrudes from the end pattern in the first direction out of the plurality of patterns of the polysilicon film P1 extending in the second direction to the outside of the capacitive element CPD in the first direction. In addition, they are connected to the upper surfaces of the two patterns (feeding portions). The two patterns (feeding portions) are arranged in the second direction, and a polysilicon film P2 is embedded between them.

  The contact plug CP that feeds power to the polysilicon film P2 is connected to the upper surface of the polysilicon film P2 that is embedded between the two patterns (feeding portions) that constitute the polysilicon film P1 that are adjacent in the second direction. ing. For example, a comb-shaped polysilicon film P1 is formed, formed along one side wall of a pattern extending in the first direction, and formed in a sidewall shape like the polysilicon film P2 extending in the first direction. It is difficult to accurately connect the contact plug CP to the upper surface of the narrow pattern.

  However, if the contact plug CP is connected to the polysilicon film P2 embedded between two adjacent patterns as described above, even if the contact plug CP formation position is displaced due to the accuracy of the exposure apparatus or the like, the displacement width Therefore, the contact plug CP can be reliably connected to the polysilicon film P2, and the reliability of the semiconductor device can be improved.

  Further, as shown in FIG. 13, if a power feeding portion for connecting the contact plug CP to the polysilicon films P1 and P2 is provided at the end of the capacitive element CPD, the plurality of power feeding portions extend in the second direction and extend in the first direction. The width of each pattern of the polysilicon films P1 and P2 arranged in the first direction can be reduced. Therefore, the degree of freedom in layout design of the polysilicon films P1 and P2 constituting the capacitive element CPD is improved.

  Further, the capacitive element CPD of the modification of the present embodiment shown in FIG. 14 has a polysilicon film extending around the polysilicon film P1 extending in the second direction and arranged in the first direction via the ONO film MF. The capacitive element CPD in which P2 is formed has a structure in which the end portion in the second direction of a part of the polysilicon film P1 is extended in the second direction from the adjacent polysilicon film P1. Since the polysilicon film P2 is buried between the adjacent polysilicon films P1, a plurality of polysilicon films P1 and P2 are alternately arranged in the first direction.

  The method of connecting the contact plug CP to the polysilicon film P1 is the same as that in FIG. However, the contact plug CP that feeds power to the polysilicon film P2 is adjacent to the polysilicon film P2 along the corner of the polysilicon film P1 having a rectangular shape in plan view, and adjacent to the polysilicon film P1, and in the second direction. The polysilicon film P1 having the extended pattern is connected to the upper surface of the polysilicon film P2 in the vicinity of the contact point with the polysilicon film P2 along the side wall in the first direction.

  In this way, the contact plug CP is connected to the polysilicon film P2 on the upper surface of the polysilicon film P2 in the vicinity of the corner of the polysilicon film P1, not between the opposing side walls of the adjacent polysilicon film P1. Wide area for Therefore, if the contact plug CP is connected to the region as described above, the contact plug CP can be more reliably connected to the polysilicon film P2 for the reason described with reference to FIG. In addition, since the shape of the polysilicon film P2 formed between the adjacent polysilicon films P1 can be prevented from being restricted to connect the contact plug CP, the degree of freedom in layout of the capacitor element CPD. Can be increased.

  Further, FIG. 15 shows, as one modified example of the capacitive element CPD of the present embodiment, patterns of two polysilicon films P1 extending in the second direction and adjacent in the second direction, and the respective polycrystals. A polysilicon film P2 formed so as to surround the periphery of the silicon film P1 with an ONO film MF is shown. A contact plug CP is connected to the upper surface of the polysilicon film P2 buried between the polysilicon films P1 adjacent in the second direction. Although not shown, a plurality of polysilicon films P1 may be arranged in the first direction. In this case, the polysilicon film P2 is also buried between the polysilicon films P1 adjacent in the first direction.

  In the capacitive element shown in FIG. 15, the shape of the polysilicon film P2 adjacent to the polysilicon film P1 in the first direction is the restriction for connecting the contact plug CP, as in the capacitive element of the modification shown in FIG. Therefore, the degree of freedom in the layout of the capacitor CPD can be increased.

  FIG. 16 shows a structure in which the ONO film MF and the memory gate electrode MG are provided only on one side wall of the control gate electrode CG, as a modification of the MONOS memory Q1 of the present embodiment. As described above, if the memory gate electrode MG and the ONO film MF are formed adjacent to one side wall of the control gate electrode CG, the MONOS memory Q1 can be used as a nonvolatile memory.

  In order to form such a structure, first, the steps described with reference to FIGS. 3 to 7 are performed, thereby forming the sidewall-like memory gate electrode MG on the side walls on both sides of the control gate electrode CG. Thereafter, the memory gate electrode MG on one side wall of the control gate electrode CG and the capacitor element formation region 1B are covered with a photoresist film, and then the other exposed memory gate electrode MG is removed by an etching method or the like. Then, the photoresist film may be removed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the case where an n-channel MOSFET is formed on a semiconductor substrate as shown in FIG. 2 has been described. However, the semiconductor element may be a p-channel MOSFET, and MIS (Metal Insulator Semiconductor) type FET may be used.

1A MONOS memory formation region 1B capacitive element formation region CG control gate electrode CP contact plug CPD, CPDa capacitive element EI element isolation region ES etching stopper film EX extension region GE gate electrode GF1, GF2 gate insulating film IF1, IF2 insulating films L1, L2 Interlayer insulating film MG Memory gate electrode MF ONO film N1 Silicon nitride films P1, P1a, P2, P2a Polysilicon film PR1 Photoresist film Q1 MONOS memory Q2 Low breakdown voltage MOSFET
S1 Silicide layer SB Semiconductor substrate DF Diffusion layer SW Side wall W1 Wiring X1, X2 Silicon oxide film

Claims (14)

A first conductor film formed on a semiconductor substrate;
A second conductor film adjacent to the first conductor film and insulated from the first conductor film in a first direction along the main surface of the semiconductor substrate;
A capacitive element including
Between the first conductor film and the second conductor film, a first silicon oxide film, a silicon nitride film, and a silicon oxide film formed in order from the side wall of the first conductor film toward the side wall of the second conductor film, and A semiconductor device in which a first ONO film including a second silicon oxide film is formed. On the semiconductor substrate, a gate electrode formed through a gate insulating film,
2. The semiconductor device according to claim 1, wherein a field effect transistor including a source / drain region formed on an upper surface of the semiconductor substrate beside the gate electrode is formed. On the semiconductor substrate, a selection gate electrode formed through a gate insulating film,
A memory gate electrode adjacent to the side wall of the select gate electrode via a second ONO film and formed on the semiconductor substrate via the second ONO film;
A non-volatile memory including a source / drain region formed on an upper surface of the semiconductor substrate beside the select gate electrode and the memory gate electrode;
The semiconductor device according to claim 1, wherein the second ONO film is a film in the same layer as the first ONO film. The selection gate electrode and the first conductor film are films of the same layer,
The semiconductor device according to claim 3, wherein the memory gate electrode and the second conductor film are films of the same layer.   The semiconductor device according to claim 3, wherein the capacitive element and the nonvolatile memory have the same height. The second conductive film at the end of the capacitive element in the first direction has a sidewall shape;
4. The semiconductor device according to claim 3, wherein a width in the first direction of the second conductor film at an end of the capacitive element in the first direction and a gate length of the memory gate electrode are the same size. The capacitor element and the nonvolatile memory are covered with an interlayer insulating film formed on the semiconductor substrate and having a flat upper surface.
The semiconductor device according to claim 3, wherein a wiring layer is formed on the interlayer insulating film along an upper surface of the interlayer insulating film.   2. The semiconductor device according to claim 1, wherein a plurality of the first conductor films and the second conductor films are alternately arranged in the first direction and extend in a second direction orthogonal to the first direction. . The width in the first direction of the second conductor film embedded between the first conductor films adjacent in the first direction is:
9. The size of the second conductor film having a sidewall shape formed at an end of the capacitive element in the first direction is not more than twice the width in the first direction. Semiconductor device. The capacitor element is covered with an interlayer insulating film formed on the semiconductor substrate and having a flat upper surface.
The semiconductor device according to claim 1, wherein a plurality of contact plugs penetrating the interlayer insulating film are formed.   2. The semiconductor device according to claim 1, wherein a conductor film constituting the capacitive element is not formed immediately above or immediately below each of the first conductor film and the second conductor film on the semiconductor substrate. (A1) preparing a semiconductor substrate;
(B1) forming a first conductor film on the semiconductor substrate via a first insulating film;
(C1) processing the first conductor film;
(D1) A first silicon oxide film, a silicon nitride film, a second silicon oxide film, and a second conductor film are sequentially stacked on the semiconductor substrate, and the first silicon oxide film, the silicon nitride film, and the second silicon oxide film are stacked. Forming an ONO film including:
(E1) The second conductor film is partially removed to expose the upper surface of the first conductor film and the upper surface of the ONO film, so that they are adjacent to each other in the first direction along the main surface of the semiconductor substrate. Forming a capacitive element including the insulated first conductor film and the second conductor film;
A method for manufacturing a semiconductor device, comprising: (F1) After the step (e1), a step of removing the exposed ONO film;
(G1) forming an interlayer insulating film covering the capacitive element on the semiconductor substrate;
(H1) planarizing the upper surface of the interlayer insulating film;
(I1) After the step (h1), forming a contact plug that penetrates the interlayer insulating film;
(J1) After the step (i1), forming a wiring layer on the interlayer insulating film;
The method of manufacturing a semiconductor device according to claim 12, further comprising: In the step (c1), a process of forming a selection gate electrode made of the first conductor film in the first region on the semiconductor substrate is performed.
The second region on the semiconductor substrate is processed to form a plurality of patterns of the first conductor film extending in the second direction perpendicular to the first direction in the first direction,
In the step (e1), by partially removing the second conductor film, a memory gate electrode made of the second conductor film is formed adjacent to the side wall of the selection gate electrode via the ONO film. ,
In the second region, the capacitor element including the first conductor film adjacent in the first direction and the second conductor film embedded therebetween is formed,
(F2) After the step (e1) and before the step (g1), impurities are implanted into the upper surface of the semiconductor substrate next to the selection gate electrode and the memory gate electrode, and source / By forming the drain region,
Forming a non-volatile memory having the select gate electrode, the memory gate electrode, the ONO film, and the source / drain regions;
The method of manufacturing a semiconductor device according to claim 13, further comprising:

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