JP2016165010A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to improve the reliability of a semiconductor device having a split gate type MONOS memory. An ONO film and a polysilicon film P2 are sequentially formed so as to fill a space between a polysilicon film P1 and a dummy gate electrode, and then the dummy gate electrode is removed. Thereafter, by polishing the upper surfaces of the polysilicon films P1 and P2, a memory gate electrode made of the polysilicon film P2 is formed on the side wall of the control gate electrode made of the polysilicon film P1 via the ONO film. As a result, a memory gate electrode having a highly uniform sidewall and a uniform film thickness is formed. [Selection] Figure 11

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a split gate nonvolatile memory.

  MONOS that stores information by accumulating electric charge in an ONO (Oxide Nitride Oxide) film formed between a gate electrode and a substrate, and having a FET (Field Effect Transistor) structure as one of nonvolatile memories (Metal Oxide Nitride Oxide Semiconductor) Memory is known. The MONOS memory has a split gate having a select gate electrode used for selecting a memory cell and a memory gate electrode formed adjacent to the select gate via an insulating film and used for storing information. There is a gate type non-volatile memory.

  Patent Document 1 (International Patent Publication WO2009 / 104688 pamphlet) describes a semiconductor layer that constitutes a memory gate electrode in an opening of a pattern that constitutes a control gate electrode in a step of forming a split gate type nonvolatile memory element. Is described as embedding. However, the formation of a dummy gate electrode (sacrificial pattern that does not remain in the completed semiconductor device) is not described here. Further, there is no description regarding the capacitive element.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2009-302269), in order to prevent damage to the ONO film due to ion implantation caused by reducing the height of the selection gate electrode and the memory gate electrode, It is described that an ONO film and a memory gate electrode are formed after forming a drain region.

International Patent Publication WO2009 / 104688 Pamphlet JP 2009-302269 A

  In a split gate type MONOS memory cell, it is conceivable to reduce the height of the selection gate electrode and the memory gate electrode in order to reduce the size of the semiconductor device. In this case, however, the shape required for the memory gate electrode is reduced. As a result, it becomes difficult to ensure, and the characteristics and reliability of the semiconductor device deteriorate.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device according to one embodiment forms a pattern of the second polysilicon film via the ONO film between the first polysilicon film and the dummy gate electrode, and then removes the dummy gate electrode, A memory gate electrode is formed on the side wall of the control gate electrode through the ONO film so that the side wall is highly perpendicular and the film thickness is uniform.

  According to one embodiment disclosed in the present application, the reliability of a semiconductor device can be improved.

It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 2; FIG. 4 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 3. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4. 6 is a plan layout illustrating a method for manufacturing the semiconductor device following FIG. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 5; FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a plan layout showing a method for manufacturing the semiconductor device following FIG. 8; FIG. FIG. 9 is a plan layout showing a method for manufacturing the semiconductor device following FIG. 8; FIG. FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. FIG. 12 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12; FIG. 14 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 13; FIG. 15 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 14; 16 is a plan layout illustrating the method for manufacturing the semiconductor device following FIG. 15. FIG. 16 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 15; FIG. 18 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 17; FIG. 19 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 18; FIG. 20 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 19; FIG. 21 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 20; FIG. 22 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 21; FIG. 23 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 22; 24 is a plan layout illustrating the method for manufacturing the semiconductor device following FIG. 23. 24 is a plan layout illustrating the method for manufacturing the semiconductor device following FIG. 23. FIG. 24 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 23; It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. FIG. 28 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 27; FIG. 29 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 28; FIG. 30 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 29; FIG. 31 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 30; It is sectional drawing which shows the manufacturing method of the semiconductor device which is a comparative example. It is sectional drawing which shows the manufacturing method of the semiconductor device which is a comparative example.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the following embodiments, even a plan view may be partially hatched to make the drawings easy to see.

(Embodiment 1)
The semiconductor device according to the present embodiment refines a MONOS memory cell, which is a split gate type nonvolatile memory cell formed on a semiconductor substrate, and improves the reliability of the semiconductor device.

  Below, the manufacturing method of the semiconductor device of this Embodiment is demonstrated using FIGS. 1 to 5, 7, 8, 11 to 15, 17 to 23, and 26 are cross-sectional views illustrating a manufacturing process of the semiconductor device of the present embodiment. 2 to 5, 7, 8, 11 to 15, 17 to 23, and 26, in order from the left side of the drawing, the MONOS memory formation region A 1, the power feeding portion formation region B 1, and the capacitor element formation region. C1 and the low breakdown voltage element formation region D1 are shown.

  6, FIG. 9, FIG. 16, and FIG. 25 show a planar layout of the capacitor element formation region in the semiconductor device during the manufacturing process. 10 and 24 show a planar layout of a power feeding portion forming region in the semiconductor device during the manufacturing process.

  First, as shown in FIG. 1, a semiconductor substrate SB made of, for example, single crystal silicon is prepared. Subsequently, a trench is formed in the main surface of the semiconductor substrate SB, and a silicon oxide film or the like is embedded in the trench, thereby forming an element isolation region EI. The element isolation region EI is, for example, STI (Shallow Trench Isolation). Thereafter, impurities are implanted into the main surface of the semiconductor substrate SB by an ion implantation method or the like to form a well (not shown). The depth at which the well is formed is deeper than the element isolation region EI.

  Next, as shown in FIG. 2, an insulating film IF and a polysilicon film P1 are sequentially formed on the main surface of the semiconductor substrate SB. The insulating film IF is made of, for example, a silicon oxide film, and the insulating film IF and the polysilicon film P1 are formed by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, an N-type impurity (for example, As (arsenic)) is implanted into part of the polysilicon film P1 by ion implantation using photolithography technology. Here, by performing ion implantation in a state where the polysilicon film P1 in the low breakdown voltage element formation region D1 is covered with the photoresist film PR1, the MONOS memory formation region A1, the power feeding portion formation region B1, and the capacitive element formation region C1 Impurity ions are implanted into the polysilicon film P1.

  Note that the MONOS memory formation region A1 and the low breakdown voltage element formation region D1 shown in FIG. 2 are the regions where the element isolation region EI was not formed in the process described with reference to FIG. This is an active region exposed from the region EI. In addition, the power supply portion formation region B1 and the capacitor element formation region C1 are regions in which the element isolation region EI is formed in the process described with reference to FIG.

  Next, as shown in FIG. 3, after removing the photoresist film PR1, a silicon nitride film N2 is formed (deposited) on the entire upper surface of the polysilicon film P1 using a CVD method or the like.

  Next, as shown in FIG. 4, after the pattern of the photoresist film PR2 is formed on the silicon nitride film N2 by the photolithography technique, the silicon nitride film N2, by the dry etching method using the photoresist film PR2 as a mask, By partially removing the polysilicon film P1 and the insulating film IF, the upper surface of the semiconductor substrate SB and the upper surface of the element isolation region EI are exposed. Thereby, the dummy gate electrode DP made of the polysilicon film P1 and the gate insulating film GF made of the insulating film IF are formed in the MONOS memory formation region A1.

  The polysilicon film P1 and the dummy gate electrode DP are provided adjacent to each other with a space therebetween. At this time, in the direction along the cross section of FIG. 4, that is, the direction in which the dummy gate electrode DP and the polysilicon film P1 are arranged, the width of the dummy gate electrode DP is, for example, 100 nm, and the width of the polysilicon film P1 is, for example, 60 nm. In the same direction, the width of the polysilicon film P2 buried between the dummy gate electrode DP and the polysilicon film P1 is, for example, 80 to 90 nm.

  Here, as shown in FIG. 4, in the MONOS memory formation region A1, when a plurality of patterns made of the insulating film IF arranged in the direction along the main surface of the semiconductor substrate SB are formed, an insulating film adjacent to one insulating film IF is formed. A pair of insulating films arranged so as to sandwich the insulating film IF is referred to as a gate insulating film GF. In the MONOS memory formation region A1, when a plurality of patterns made of the polysilicon film P1 aligned in the direction along the main surface of the semiconductor substrate SB are formed, the dummy gate electrode DP is formed between the adjacent polysilicon films P1. It is formed. At this time, in the MONOS memory formation region A1, the polysilicon film P1 is formed on the gate insulating film GF, and the dummy gate electrode DP is formed on the insulating film IF.

  That is, the insulating film IF is disposed between the adjacent gate insulating films GF, and the gate insulating film is interposed between the polysilicon films P1 formed in contact with the upper surfaces of the adjacent gate insulating films GF. A dummy gate electrode DP in contact with the upper surface of the film GF is formed. The dummy gate electrode DP is a sacrificial pattern that is removed in a later process and does not remain in a semiconductor device completed thereafter.

  Next, as shown in FIG. 5, after removing the photoresist film PR2, the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film are formed on the entire main surface of the semiconductor substrate SB by using, for example, the CVD method. X2 and the polysilicon film P2 are sequentially formed. Thereby, the upper surface and the side wall of the pattern formed of the laminated film of the insulating film IF, the polysilicon film P1, and the silicon nitride film N2 are covered with the silicon oxide film X1. Further, the upper surface and side walls of the pattern made of the laminated film of the insulating film IF, the dummy gate electrode DP, and the silicon nitride film N2 are covered with the silicon oxide film X1. Further, the upper surface and the side wall of the pattern made of the laminated film of the gate insulating film GF, the polysilicon film P1, and the silicon nitride film N2 are covered with the silicon oxide film X1. In the following, a laminated film composed of the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 may be simply referred to as an ONO film.

  At this time, a pattern of a plurality of polysilicon films P1 is formed on the semiconductor substrate SB, and the grooves between the adjacent polysilicon films P1 are formed in the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2. And completely filled with the polysilicon film P2. However, the portion between the polysilicon films P1 is not completely filled at a place where the distance between the polysilicon films P1 is large. The trench between the dummy gate electrode DP and the polysilicon film P1 is completely filled with the silicon oxide film X1, the silicon nitride film N1, the silicon oxide film X2, and the polysilicon film P2.

  Next, as shown in FIGS. 6 and 7, the polysilicon film P2 is partially removed using a dry etching method to expose the upper surface of the silicon oxide film X2. 6 is a plan layout of the semiconductor device during the manufacturing process, and the capacitor element formation region C1 in FIG. 7 shows a cross section taken along the line CC in FIG. That is, FIG. 6 is a planar layout showing a region where a capacitor element is formed in the semiconductor device of this embodiment. 6 crosses the five polysilicon films P1 and the six polysilicon films P2. In FIG. 7, in order to simplify the drawing, in the capacitor element formation region C1, The number of polysilicon films P1 and P2 is omitted.

  In FIG. 6, illustration of the silicon nitride film N2 and the ONO film on the polysilicon film P1 is omitted for easy understanding of the arrangement of the polysilicon films P1 and P2. Further, the ONO film on the element isolation region EI in the region not covered with the polysilicon films P1 and P2 is partially omitted.

  As shown in FIG. 7, the polysilicon film P2 immediately above the dummy gate electrode DP is removed. The height of the upper surface of the polysilicon film P2 buried between the adjacent polysilicon films P1 or between the adjacent polysilicon film P1 and the dummy gate electrode DP is determined by the silicon oxide on the silicon nitride film N2. The height is almost the same as the height of the upper surface of the film X2. At this time, the side region of the stacked film of the polysilicon film and the silicon nitride film N2 and the lateral region of the stacked film was not completely filled with the polysilicon film P2 in the film forming process described with reference to FIG. On the other side wall, a polysilicon film P2 is formed in a self-aligned manner in a sidewall shape via a silicon oxide film X1, a silicon nitride film N1, and a silicon oxide film X2.

  Note that the trench between the dummy gate electrode DP and the polysilicon film P1 remains completely filled with the silicon oxide film X1, the silicon nitride film N1, the silicon oxide film X2, and the polysilicon film P2. The film P2 does not have a sidewall shape.

  As shown in FIG. 6, in the capacitor element formation region, the polysilicon film P1 is disposed so as to be surrounded by the polysilicon film P2 formed on the element isolation region EI. Since the ONO film composed of the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 is formed between the polysilicon films P1 and P2, the polysilicon films P1 and P2 are insulated from each other.

  The pattern of the polysilicon film P2 surrounds two patterns of the polysilicon film P1. Of the two polysilicon film P1 patterns, one comb-shaped polysilicon film P1 pattern is used to generate capacitance between the polysilicon film P2 and extends in the other direction. The existing pattern of the polysilicon film P1 is provided in order to securely connect the contact plug (connection member) to the polysilicon film P2. The polysilicon film P1 provided for generating the capacitance includes a pattern extending in the first direction and a plurality of patterns extending in the second direction orthogonal to the first direction and arranged in the first direction. It has a comb shape. A polysilicon film P2 extending in the second direction is formed between the plurality of patterns extending in the second direction, and the polysilicon films P1 and P2 are alternately formed in the first direction. Yes. As described above, the polysilicon film P2 also has a comb shape including a plurality of patterns extending in the second direction.

  Next, as shown in FIG. 8, by using an isotropic dry etching method using a photoresist film PR3 formed on the semiconductor substrate SB by photolithography as a mask, an ONO film is interposed on the sidewall of the polysilicon film P1. Then, the polysilicon film P2 formed in a sidewall shape is removed. At this time, in the MONOS memory formation region A1, the polysilicon film P2 buried between the polysilicon film P1 and the dummy gate electrode DP is not removed because it is covered with the photoresist film PR3, but the polysilicon film P1. The side wall-like polysilicon film P2 is removed, and the surface of the silicon oxide film X2 is exposed.

  Further, since the power feeding portion forming region B1, the capacitive element forming region C1, and the low breakdown voltage element forming region D1 are covered with the photoresist film PR3, the sidewalls formed in the power feeding portion forming region B1 and the capacitive element forming region C1. A portion of the shaped polysilicon film P2 remains without being removed. However, even in the power supply portion forming region B1 and the capacitive element forming region C1, in the region not shown in FIG. 8, as shown in FIGS. 9 and 10 used later, in the etching process of FIG. There are also places where the sidewall-like polysilicon film P2 is removed by being exposed from PR3.

  Next, as shown in FIGS. 9, 10, and 11, after removing the photoresist film PR <b> 3, a part of the silicon oxide film X <b> 2 on the upper part of the ONO film and the silicon nitride film are formed using a wet etching method. By removing a part of N1, the surface of the silicon oxide film X1 is exposed.

  9 is a plan layout showing a capacitor element formation region in the semiconductor device in the manufacturing process, as in FIG. 6, and the capacitor element formation region C1 in FIG. 11 is a cross-sectional view taken along the line CC in FIG. It is. FIG. 10 is a plan layout showing a MONOS memory formation region and a MONOS memory power supply portion formation region in the semiconductor device during the manufacturing process. The MONOS memory formation area A1 in FIG. 11 is a cross section taken along the line AA in FIG. 10, and the power feeding part formation area B1 in FIG. 11 is a cross section taken along the line BB in FIG. In FIGS. 9 and 10, the silicon oxide film X1 and the silicon nitride film N2 on the polysilicon film P1 are not shown for easy understanding of the arrangement of the polysilicon films P1 and P2. Further, the silicon oxide film X1, the silicon nitride film N1, and the silicon oxide film X2 are not shown except those formed on the respective sidewalls of the polysilicon films P1 and P2.

  As shown in FIGS. 9, 10, and 11, in the region not covered with the polysilicon film P2, the silicon oxide film X2 and the silicon nitride film N1 are removed by the wet etching process, and the silicon oxide film X1 is exposed. doing. That is, the silicon oxide film X2 and the silicon nitride film N1 in other regions are removed while leaving the silicon oxide film X2 and the silicon nitride film N1 adjacent to the sidewall and the bottom of the polysilicon film P1.

  In the planar layouts shown in FIGS. 9 and 10, the side wall of a part of the polysilicon film P1 is covered only with the silicon oxide film X1, and is not covered with the polysilicon film P2, the silicon oxide film X2, and the silicon nitride film N1. . Similar to the polysilicon film P1, the side wall of the dummy gate electrode DP also includes a region that is not covered by the polysilicon film P2, the silicon oxide film X2, and the silicon nitride film N1.

  As described above, the regions of the sidewalls of the polysilicon film P1 and the dummy gate electrode DP that are not covered with the polysilicon film P2, the silicon oxide film X2, and the silicon nitride film N1 are dry-etched as described with reference to FIG. This is the region where the sidewall-like polysilicon film P2 has been removed by the process. Here, in the region from which the silicon oxide film X2 and the silicon nitride film N1 have been removed, the silicon oxide film X1 is left without being removed in the process described later with reference to FIG. Then, the photoresist film PR4 is removed thereafter to prevent the semiconductor substrate SB from being damaged.

  As shown in FIG. 9, among the comb-shaped polysilicon film P1, the polysilicon film P2 on the side wall of the pattern extending in the first direction is removed, and the side walls of the plurality of patterns extending in the second direction are removed. The polysilicon film P2 is not removed. Thus, only the polysilicon film P2 on the side wall of the pattern extending in the first direction is removed when the contact plug is connected to the comb-shaped polysilicon film P1, as will be described later. This is to prevent electrical conduction between the polysilicon film P1 and the polysilicon film P2 due to misalignment of connection locations or contact of a silicide layer.

  As shown in FIG. 10, the polysilicon films P1 and P2 and the dummy gate electrode DP extend in the same direction, and are arranged side by side in a direction orthogonal to the extending direction. The polysilicon film P1 in the MONOS memory formation region A1 shown in FIG. 11 and the polysilicon film P1 in the power feeding portion formation region B1 are integrally formed as shown in FIG. The polysilicon film P2 in the MONOS memory formation region A1 and the polysilicon film P2 in the power feeding portion formation region B1 are integrally formed as shown in FIG. However, the dummy gate electrode DP does not extend to the power feeding unit.

  In the formation region of the MONOS memory shown in FIG. 10, the dummy gate electrode DP is disposed so as to be sandwiched between the pair of polysilicon films P1 via the ONO film in the direction orthogonal to the extending direction. Further, the dummy gate electrode DP and the pair of polysilicon films P1 sandwiching the dummy gate electrode DP are arranged so as to be sandwiched between the pair of polysilicon films P1 in the same direction. An ONO film is interposed between the polysilicon film P1 and the polysilicon film P2. In the power feeding portion forming region B1 in FIG. 11, one of the pair of polysilicon films P1 and one of the pair of polysilicon films P2 are illustrated. The other polysilicon films P1 and P2 are not shown in FIG.

  In the region where the power feeding unit is formed, the pattern of the polysilicon film P2 surrounds the pattern of the isolated polysilicon film P1. As will be described later, this is a structure which is formed in a sidewall shape and is provided to securely connect the contact plug to the polysilicon film P2 having a small width.

  Next, as shown in FIG. 12, a pattern of a photoresist film PR4 is formed on the semiconductor substrate SB by photolithography. The photoresist film PR4 covers the power supply portion formation region B1, the capacitor element formation region C1, and the low breakdown voltage element formation region D1, and is a silicon oxide immediately above the dummy gate electrode DP (see FIG. 11) in the MONOS memory formation region A1. The upper surface of the film X1 is exposed. Specifically, the photoresist film PR4 covers the surfaces of the gate insulating film GF, the polysilicon films P1, P2, the silicon nitride films N1, N2, the silicon oxide films X1 and X2 in the MONOS memory formation region A1, and the dummy gate electrode. In this pattern, the upper surface of the silicon oxide film X1 directly above DP is exposed.

  Thereafter, the silicon oxide film X1 immediately above the dummy gate electrode DP, the silicon nitride film N2 immediately above the dummy gate electrode DP, and the dummy gate electrode DP are sequentially removed by an isotropic dry etching method. As a result, the side wall of the silicon oxide film X1 in contact with the side wall of the dummy gate electrode DP is exposed, and the insulating film IF immediately below the region where the dummy gate electrode DP is removed is exposed.

  Here, the silicon oxide film X1 and the silicon nitride film N1 constituting the ONO film between the region where the dummy gate electrode DP is formed and the polysilicon film P2 are removed by a more isotropic dry etching method. May be. The silicon nitride film N1 in the MONOS memory formation region A1 is an insulating film that becomes a charge storage film of a MONOS memory formed in a later process. In order to operate the MONOS memory, it is important to store charges in the silicon nitride film N1 immediately below the polysilicon film P2 to be a memory gate in a later process, but it is not directly below the polysilicon film P2 but on the side wall. If charges are accumulated or moved in the formed silicon nitride film N1, the characteristics or reliability of the MONOS memory may be degraded.

  Therefore, as described above, if the silicon oxide film X1 and the silicon nitride film N1 constituting the ONO film between the region where the dummy gate electrode DP is formed and the polysilicon film P2 are removed, the polysilicon film P2 is removed. It is possible to prevent electric charges from being accumulated in the silicon nitride film N1 other than the silicon nitride film N1 immediately below. However, in this embodiment, the silicon oxide films X1 and X2 and the silicon nitride film N1 constituting the ONO film between the region where the dummy gate electrode DP is formed and the polysilicon film P2 are left without being removed. A method for manufacturing a semiconductor device will be described.

  Next, as shown in FIG. 13, after removing the photoresist film PR4, the silicon oxide film X1 in other regions is removed, leaving the ONO film formed adjacent to the sidewall and bottom of the polysilicon film P2. Then, the main surface of the semiconductor substrate SB is exposed. As a result, the side walls of the polysilicon film P1 and the silicon nitride film N2 that are not adjacent to the polysilicon film P2 are exposed, and the upper surface of the silicon nitride film N2 is exposed. Further, the upper surface of the semiconductor substrate SB is exposed by simultaneously removing the insulating film IF immediately below the region where the dummy gate electrode DP is removed.

  As described above, in this embodiment, in the process described with reference to FIG. 12, the photoresist film PR4 is formed without removing the insulating film IF in the MONOS memory formation region A1 following the process of removing the dummy gate electrode DP. After the removal, the insulating film IF in the MONOS memory formation region A1 is removed together with a part of the silicon oxide film X1 in the step shown in FIG. By doing so, it is possible to prevent the substrate from being damaged by being exposed to a cleaning solution, an etching solution, or the like by the step of removing a part of the photoresist film PR4 and the silicon oxide film X1. .

  At this time, it is considered that the silicon oxide film X1 exposed on the side surface of the ONO film between the region where the dummy gate electrode DP (see FIG. 11) is formed and the polysilicon film P2 is also removed. In the following description, it is assumed that the silicon oxide film X1 remains without being removed. However, the silicon oxide film X1 may be removed.

  Thereafter, the gate insulating film GF made of the insulating film IF is formed by processing the silicon nitride film N2, the polysilicon film P1, and the insulating film IF in the low breakdown voltage element forming region D1 using a photolithography technique and a dry etching method. To do.

  Next, as shown in FIG. 14, a silicon nitride film is formed (deposited) on the entire upper surface of the semiconductor substrate SB using, for example, a CVD method, and then the silicon nitride film is partially removed by a dry etching method. The main surface of the semiconductor substrate SB is exposed. Thus, the offset spacer OS made of the silicon nitride film is formed in a self-aligned manner on the side walls of the respective structures on the semiconductor substrate SB.

  Specifically, in the MONOS memory formation region A1, a laminated film composed of the gate insulating film GF, the polysilicon film P1, and the silicon nitride film N2, and an ONO film and the polysilicon film P2 that are in contact with one side wall of the laminated film are formed. An offset spacer OS is formed on each of the side walls on both sides of the structure including the laminated film.

  In the power feeding part forming region B1 and the capacitive element forming region C1, a laminated film composed of the insulating film IF, the polysilicon film P1, and the silicon nitride film N2, and an ONO film and a polysilicon film P2 that are in contact with one side wall of the laminated film An offset spacer OS is formed on each of the side walls on both sides of the structure including the laminated film. In the power supply portion forming region B1, since the sidewall-like polysilicon film P2 is formed on one side wall of the structure, the offset spacer OS is formed on the sidewall of the sidewall-like polysilicon film P2. Is done. In the capacitor element formation region C1, since the sidewall-like polysilicon film P2 is formed on both side walls of the structure, the offset spacer OS is formed on the side wall of each sidewall-like polysilicon film P2. Is done.

  In the low breakdown voltage element formation region D1, offset spacers OS are formed on the sidewalls on both sides of the laminated film composed of the gate insulating film GF, the polysilicon film P1, and the silicon nitride film N2.

  Thereafter, an N-type impurity (for example, As (arsenic)) is implanted into the upper surface of the semiconductor substrate SB at a relatively low concentration by using an ion implantation method. Thus, the extension region EX is formed on the main surface of the semiconductor substrate SB in the MONOS memory formation region A1 and the low breakdown voltage element formation region D1. In the MONOS memory formation region A1, an extension region EX is formed on the upper surface of the semiconductor substrate SB exposed beside the structure including the polysilicon films P1 and P2 that are in contact with each other via the ONO film. Therefore, the extension region EX is also formed between the adjacent polysilicon films P2 and on the upper surface of the semiconductor substrate SB just below the region where the dummy gate electrode DP (see FIG. 11) was formed.

  In the low breakdown voltage element formation region D1, an extension region EX is formed on the upper surface of the semiconductor substrate SB exposed beside the polysilicon film P1. Note that the extension region EX is not formed in the element isolation region EI and the semiconductor substrate SB immediately below the element isolation region EI in the power feeding portion formation region B1 and the capacitor element formation region C1.

  Next, as shown in FIG. 15, an insulating film is formed on the entire main surface of the semiconductor substrate SB using, for example, a CVD method, and then the insulating film is partially removed using a dry etching method. By exposing the upper surface of the substrate SB, the sidewall SW made of the insulating film is formed. The sidewall SW is formed in a self-aligned manner on the side wall where the offset spacer OS is exposed. The material of the sidewall SW can be, for example, a silicon oxide film or a stacked film of a silicon nitride film and a silicon oxide film.

  Thereafter, using an ion implantation method, an N-type impurity (for example, As (arsenic)) is implanted into the upper surface of the semiconductor substrate SB at a higher concentration than the ion implantation step performed for forming the extension region EX. Thus, the diffusion layer SL having an impurity concentration higher than that of the extension region EX is formed on the main surface of the semiconductor substrate SB in the MONOS memory formation region A1 and the low breakdown voltage element formation region D1. The diffusion layer SL is a semiconductor region having a junction depth deeper than that of the extension region EX.

  In this embodiment, the MONOS memory formation region A1 and the extension region EX of the low breakdown voltage element formation region D1 are formed by a single ion implantation process, and the MONOS memory formation region A1 and the low breakdown voltage element are formed by a single ion implantation process. A diffusion layer SL in the formation region D1 is formed. However, in practice, the extension region EX or the diffusion layer SL may be formed by dividing the ion implantation process depending on the type of element or the difference between the N-type FET, the P-type FET, and the like.

  In the MONOS memory formation region A1, the diffusion layer SL is formed on the upper surface of the semiconductor substrate SB exposed from the structure including the polysilicon films P1 and P2 that are in contact via the ONO film, the offset spacer OS on the side wall of the structure, and the side wall SW. It is formed. Therefore, between the adjacent polysilicon films P2 and immediately below the region where the dummy gate electrode DP (see FIG. 11) is formed, the upper surface of the semiconductor substrate SB is also sandwiched between the extension regions EX. Diffusion layer SL is formed.

  In the low breakdown voltage element formation region D1, the diffusion layer SL is formed on the upper surface of the polysilicon film P1, the offset spacer OS on the sidewall of the polysilicon film P1, and the semiconductor substrate SB exposed beside the sidewall SW. Note that the diffusion layer SL is not formed in the element isolation region EI and the semiconductor substrate SB immediately below the element isolation region EI in the power feeding portion formation region B1 and the capacitor element formation region C1.

  By forming the diffusion layer SL, a source / drain region comprising the extension region EX and the diffusion layer SL adjacent to the extension region EX on the upper surface of the semiconductor substrate SB of each of the MONOS memory formation region A1 and the low breakdown voltage element formation region D1. Is formed. The source / drain regions have an LDD (Lightly Doped Drain) structure having a diffusion layer SL having a relatively high impurity concentration and an extension region EX having an impurity concentration lower than that of the diffusion layer SL.

  Here, a diffusion layer serving as a well power feeding portion may be formed on the upper surface (not shown) of the semiconductor substrate SB surrounding the capacitive element formation region C1. The well power feeding unit is a semiconductor region that is formed in an annular shape surrounding the element isolation region EI of the capacitive element formation region C1 in a plan view on the main surface of the semiconductor substrate SB, for example, and supplies a potential to the semiconductor substrate. The well power feeding portion can be formed by the same ion implantation process as that for forming the diffusion layer SL, or can be formed by performing another ion implantation process. The well power feeding unit will be described later with reference to FIG.

  Next, as shown in FIGS. 16 and 17, a silicide layer S1 is formed on the upper surface of the diffusion layer SL and the upper surface of the polysilicon film P2 by using a known salicide technique. FIG. 16 is a plan layout showing the semiconductor device in the manufacturing process, and the capacitor element formation region C1 of FIG. 17 shows a cross section taken along the line CC of FIG. In FIG. 16, the silicon nitride film N2 (see FIG. 17) on the polysilicon film P1 is not shown for easy understanding of the drawing.

  In FIG. 16, unlike FIG. 9, a silicide layer S1 is formed on the polysilicon film P2 (see FIG. 17). Note that the silicide layer S1 shown in FIG. 16 is removed by a polishing process described later.

  The silicide layer S1 shown in FIG. 17 is a conductive film made of, for example, cobalt silicide (CoSi). The silicide layer S1 is formed by forming a metal film such as Co (cobalt) on the semiconductor substrate SB and then reacting the metal film and the silicon film by heat treatment. At this time, since the upper surface of the polysilicon film P1 is covered with the silicon nitride film N2, the silicide layer S1 is not formed on the upper surface of the polysilicon film P1.

  Next, as shown in FIG. 18, an etching stopper film ES made of, for example, a silicon nitride film and an interlayer insulating film L1 made of, for example, a silicon oxide film are formed on the entire upper surface of the semiconductor substrate SB by using a CVD method or the like. Are sequentially formed.

  Next, as shown in FIG. 19, the upper surface of the structure on the semiconductor substrate SB is polished and retracted using, for example, a CMP (Chemical Mechanical Polishing) method. Specifically, the interlayer insulating film L1, the etching stopper film ES, the silicide layer S1, the silicon oxide films X1 and X2, the silicon nitride films N1 and N2, the polysilicon films P1 and P2, the offset spacer OS, and the sidewall SW are polished. . Thereby, the upper surface height of each polished film is equal to or lower than the upper surface height of the polysilicon film P2 before the polishing step and higher than the bottom surfaces of the polysilicon films P1 and P2. Flattened. As a result, the silicide layer S1 on the polysilicon film P2 is removed, and the upper surfaces of the polysilicon films P1 and P2 are exposed.

  By the above polishing process, in the MONOS memory formation region A1 and the power feeding portion formation region B1, the control gate electrode CG made of the polysilicon film P1 is formed, and the memory gate electrode MG made of the polysilicon film P2 is formed. Note that the control gate electrode CG and the memory gate electrode MG in the power supply portion formation region B1 are not conductive layers that function as gate electrodes of n-channel FETs (Field Effect Transistors) constituting a MONOS memory to be formed later. The control gate electrode CG and the memory gate electrode MG in the power feeding part formation region B1 are conductive layers used for supplying a predetermined potential to the control gate electrode CG and the memory gate electrode MG in the MONOS memory formation region A1.

  Thereby, in the MONOS memory formation region A1, a MONOS memory including the gate insulating film GF, the control gate electrode CG, the ONO film, the memory gate electrode MG, the extension region EX, and the diffusion layer SL is formed. The ONO film includes a silicon nitride film N1 that is a charge storage film that holds information, and silicon oxide films X1 and X2 for insulating the silicon nitride film N1 from the control gate electrode CG, the memory gate electrode MG, and the semiconductor substrate SB. Contains. The MONOS memory is a non-volatile memory that can store information by accumulating charges in the silicon nitride film N1 immediately below the memory gate electrode MG. There are two methods for putting charge into and out of the silicon nitride film N1, and one is writing and erasing by putting electrons into and out of the entire surface of the silicon nitride film N1 under the memory gate electrode MG with a tunnel current. The other is a method using a hot carrier.

  The MONOS memory has a split gate type structure having a memory gate electrode MG adjacent to the control gate electrode CG via an ONO film. In the MONOS memory formation region A1, a pair of MONOS memories are formed across the region where the dummy gate electrode DP (see FIG. 11) is formed. The pair of MONOS memories are formed on the semiconductor substrate SB between them. The source / drain regions (herein referred to as source regions) formed on the upper surface are shared.

  In addition, the above-described polishing step forms a power supply unit having the control gate electrode CG and the memory gate electrode MG that are insulated from each other via the ONO film in the power supply unit formation region B1. As described above, the power supply unit includes the control gate electrode CG and the memory gate electrode MG for supplying a predetermined potential to the control gate electrode CG and the memory gate electrode MG of the MONOS memory. A contact plug formed in a later step is connected to the upper surfaces of the control gate electrode CG and the memory gate electrode MG constituting the power feeding unit via a silicide layer (not shown).

  Further, by the polishing step, a PIP (Poly-Insulator-Poly) capacitive element made of polysilicon films P1 and P2 insulated from each other via the ONO film is formed in the capacitive element forming region C1. The PIP capacitor element can function as a capacitor element by generating a capacitance between the polysilicon film P1 and the polysilicon film P2 that are insulated from each other via the ONO film.

  As a structure of the capacitive element, it is conceivable to use a structure in which another polysilicon film is stacked on the polysilicon film through an insulating film in a direction perpendicular to the main surface of the semiconductor substrate. On the other hand, in the present embodiment, different polysilicon films P1 and P2 are arranged in a direction along the upper surface of the semiconductor substrate SB and insulated from each other by an ONO film, thereby forming a PIP capacitor element. Since the PIP capacitor of this embodiment does not have a structure in which different polysilicon films are stacked in a direction perpendicular to the main surface of the semiconductor substrate, the height of the element can be reduced, and other memories can be used. The height of the element can be aligned with that of the element or FET. Therefore, miniaturization of the semiconductor device can be facilitated. As described above, the heights of the upper surfaces of the polysilicon films P1 and P2 that constitute the PIP capacitor element and generate capacitance between them are the respective heights of the control gate electrode CG and the memory gate electrode MG constituting the MONOS memory. It is the same as the height of the upper surface.

  Next, as shown in FIG. 20, after the silicon oxide film X3 is formed on the entire upper surface of the semiconductor substrate SB by using, for example, the CVD method, the silicon oxide film X3 is processed by using the photolithography technique and the dry etching method. Then, the upper surface of the polysilicon film P1 in the low breakdown voltage element forming region D1 is exposed from the silicon oxide film X3. Thereafter, using a wet etching method using the silicon oxide film X3 as a mask, the polysilicon film P1 in the low breakdown voltage element forming region D1 is removed, and the gate insulating film GF immediately below the polysilicon film P1 is exposed. Here, the case where the wet etching method is used to avoid damage to the underlying film when the polysilicon film P1 is removed has been described. However, the polysilicon film P1 is removed by the dry etching method. It doesn't matter.

  Note that the thickness of the gate insulating film GF in the low breakdown voltage element formation region D1 may be increased by performing a heat treatment after removing the polysilicon film P1 in the low breakdown voltage element formation region D1.

  Next, as shown in FIG. 21, after the silicon oxide film X3 is removed by etching back or the like, for example, a sputtering method or the like is used to form, for example, titanium nitride (TiN), over the entire upper surface of the semiconductor substrate SB. A metal film made of aluminum (Al), tantalum nitride (TaN), or the like is formed. Thus, in the process described with reference to FIG. 20, the metal film is completely buried in the groove formed in the low breakdown voltage element formation region D1 in the region where the polysilicon film P1 is removed.

  Subsequently, by removing the excess metal film by using a CMP method or the like, each of the polysilicon films P1, P2, the control gate electrode CG, the memory gate electrode MG, the interlayer insulating film L1, and the etching stopper film ES. Expose the top surface. Thereby, the gate electrode G1 made of the metal film is formed on the gate insulating film GF in the low breakdown voltage element formation region D1. By the polishing process by the CMP method, the height of the upper surface of the gate electrode G1 is set to the height of the upper surfaces of the polysilicon films P1, P2, the control gate electrode CG, the memory gate electrode MG, the interlayer insulating film L1, and the etching stopper film ES. Is the same.

  As a result, an n-channel low breakdown voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) including the gate electrode G1, the diffusion layer SL, and the extension region EX is formed in the low breakdown voltage element formation region D1. The MOSFET is an element that is driven at a voltage lower than that of the MONOS memory and is used for switching in a logic circuit or the like.

  Next, as shown in FIG. 22, after the silicon oxide film X4 is formed on the entire upper surface of the semiconductor substrate SB using, for example, the CVD method, the silicon oxide film X4 is removed using the photolithography technique and the dry etching method. The upper surfaces of the control gate electrode CG and the memory gate electrode MG in the power feeding portion formation region B1 are exposed from the silicon oxide film X4. Thereafter, using a known salicide technique, a silicide layer S2 made of, for example, cobalt silicide (CoSi) is formed on the upper surfaces of the control gate electrode CG and the memory gate electrode MG in the power supply portion formation region B1. The silicide layers S1 and S2 have a contact resistance when electrically connecting a contact plug formed in a later process to the diffusion layer SL, the control gate electrode CG, the memory gate electrode MG, and the polysilicon films P1 and P2. This is a conductive layer provided for reduction.

  In the cross-sectional view shown in FIG. 22, the silicide layer S2 is not formed in the capacitor element formation region C1, but in the region not shown in FIG. 22, the capacitor element is configured as described later with reference to FIG. A silicide layer S2 is formed on the polysilicon films P1 and P2 to be formed. Further, since the control gate electrode CG and the memory gate electrode MG in the MONOS memory formation region A1 in FIG. 22 are supplied with potentials from the control gate electrode CG and the memory gate electrode MG in the power feeding portion formation region B1, the MONOS memory formation region No silicide layer S2 is formed on the upper surfaces of the control gate electrode CG and the memory gate electrode MG of A1.

  Next, as shown in FIG. 23, after the silicon oxide film X4 is removed, an interlayer insulating film L2 made of, for example, a silicon oxide film is formed on the entire upper surface of the semiconductor substrate SB by using a CVD method or the like. Thereby, the interlayer insulating film L1, the etching stopper film ES, the sidewall SW, the offset spacer OS, the control gate electrode CG, the memory gate electrode MG, the silicon oxide films X1 and X2, the silicon nitride film N1, the silicide layer S2, and the polysilicon film The upper surfaces of P1 and P2 are covered with an interlayer insulating film L2.

  Subsequently, a plurality of contact holes penetrating the interlayer insulating film L1 and a plurality of contact holes penetrating the interlayer insulating films L1, L2 and the etching stopper film ES are formed by using a photolithography technique and a dry etching method.

  In the MONOS memory formation region A1, the upper surface of the silicide layer S1 on the upper surface of the diffusion layer SL is exposed by opening a contact hole that penetrates the interlayer insulating films L1 and L2 and the etching stopper film ES. In the power supply portion formation region B1, a contact hole penetrating the interlayer insulating film L1 is opened to expose the upper surface of the silicide layer S2 on the upper surface of the control gate electrode CG, and the interlayer insulating films L1 and L2 and the etching stopper film ES are formed. By opening a penetrating contact hole, the upper surface of the silicide layer S2 on the upper surface of the memory gate electrode MG formed in a sidewall shape is exposed. The contact hole that exposes the silicide layer S2 on the sidewall-like memory gate electrode MG at the end of the power feeding portion is adjacent to the memory gate electrode MG and is surrounded by the memory gate electrode MG in plan view. The silicide layer S2 on the upper surface of each may be exposed.

  In the capacitor element formation region C1, in a region not shown in FIG. 23, a contact hole penetrating the interlayer insulating film L1 is opened to expose the upper surfaces of the polysilicon films P1 and P2. In the low breakdown voltage element formation region D1, the upper surface of the silicide layer S1 on the upper surface of the diffusion layer SL is exposed by opening a contact hole that penetrates the interlayer insulating films L1 and L2 and the etching stopper film ES. In a non-existing region, a contact hole penetrating the interlayer insulating film L1 is opened to expose the upper surface of the gate electrode G1.

  Next, as shown in FIGS. 24, 25 and 26, a contact plug (connection member) C2 mainly containing W (tungsten), for example, is formed inside each of the plurality of contact holes. The semiconductor device of the embodiment is completed. FIG. 24 is a plan layout showing the formation region of the MONOS memory and the formation region of the power feeding portion of the MONOS memory in the semiconductor device in the manufacturing process, as in FIG. The MONOS memory forming area A1 in FIG. 26 is a cross section taken along the line AA in FIG. 24, and the power feeding part forming area B1 in FIG. 26 is a cross section taken along the line BB in FIG. 25 is a plan layout showing a capacitor element formation region in the semiconductor device in the manufacturing process, as in FIGS. 6 and 9, and the capacitor element formation region C1 in FIG. It is a cross section in the -C line.

  Each of the plurality of contact plugs C2 is a conductor formed to supply a predetermined potential to the diffusion layer SL, the control gate electrode CG, the memory gate electrode MG, the polysilicon films P1 and P2, and the gate electrode G1.

  When forming the contact plug C2, first, a barrier metal film (not shown) is formed on the entire upper surface of the semiconductor substrate SB by using a sputtering method or the like, and the surface in the contact hole is covered with the barrier metal film. Thereafter, a tungsten film is formed by sputtering or the like, and each of the plurality of contact holes is completely buried. Subsequently, by using a CMP method or the like, the upper barrier metal film and the tungsten film on the interlayer insulating film L2 are removed to expose the upper surface of the interlayer insulating film L2, and the upper surfaces of the interlayer insulating film L2 and the tungsten film are exposed. By flattening, a contact plug C2 made of a barrier metal film and a tungsten film is formed in each contact hole.

  As shown in the power feeding part forming region B1 in FIG. 26, the contact plug C2 connected via the silicide layer S2 on the memory gate electrode MG formed in a sidewall shape is a control gate adjacent to the memory gate electrode MG. The electrode CG may be electrically connected via a silicide layer S2. The control gate electrode CG is not electrically connected to the control gate electrode CG in the MONOS memory formation region A1, and is surrounded by the memory gate electrode MG in plan view as shown in the power feeding section of FIG. Is electrically isolated.

  As described above, when the contact plug C2 is electrically connected to the memory gate electrode MG, the contact plug C2 is formed so as to cover the upper surface of the isolated control gate electrode CG because the memory gate electrode MG has a sidewall shape. This is due to the self-alignment. That is, since the area of the upper surface of the memory gate electrode MG, that is, the area in plan view, is small, it is difficult to connect the contact plug C2 only to the memory gate electrode MG accurately and reliably. Therefore, here, the control gate electrode CG electrically insulated from the MONOS memory is formed, and a wide contact plug C2 extending over the control gate electrode CG is formed on the memory gate electrode MG. The reliability of power supply to MG is increased.

  As shown in FIG. 25, such a configuration is also used at a location where the contact plug C2 is electrically connected to the polysilicon film P2 formed in a sidewall shape. In FIG. 25, in addition to the polysilicon films P1 and P2, a silicide layer S2 formed on each of the polysilicon films P1 and P2 is also illustrated. The contact plug C2 is electrically connected to the polysilicon film P1 or P2 immediately below the silicide layer S2 by being connected to the silicide layer S2.

  The contact plug C2 for supplying a potential to the polysilicon film P2 is insulated from the silicide layer S2 on the polysilicon film P2 and the polysilicon film P1 that generates capacitance in the PIP capacitor element. Is formed so as to straddle the silicide layer S2 immediately above the polysilicon film P1 (not shown) surrounded by. As a result, like the memory gate electrode MG (see FIG. 24) described above, the contact plug C2 can be reliably connected to the polysilicon film P2 formed in a sidewall shape and having a small width in plan view.

  As shown in FIG. 25, the regions other than the regions supplying power to the polysilicon films P1 and P2, that is, the regions adjacent to each other through the ONO film in order for the polysilicon films P1 and P2 to generate capacitance. The silicide layer S2 is not formed. This is because when the silicide layer S2 is formed on the polysilicon films P1 and P2, the polysilicon films P1 and P2 that are close to each other through the ONO film composed of the silicon oxide films X1 and X2 and the silicon nitride film N2 However, this is for avoiding a short circuit due to contact between the silicide layers S2 on the upper side. Therefore, in a region where a plurality of polysilicon films P1 extending in the second direction and a plurality of polysilicon films P2 extending in the second direction are alternately arranged in the first direction, that is, in a region where capacitance is generated, The silicide layer S2 is not formed on the silicon films P1 and P2 (see FIG. 22).

  A contact plug C2 for supplying a potential to the polysilicon film P1 is connected to a pattern extending in the first direction among the patterns of the polysilicon film P1, and the first direction of the polysilicon film P1 is connected to the pattern. A silicide layer S2 is formed between the contact plug C2 and the pattern extending to the contact plug C2.

  Here, in the step described with reference to FIG. 8, when a part of the polysilicon film P2 in the capacitor element formation region C1 in the region not shown in FIG. 8 is not removed, as shown in FIG. In the polysilicon film P1 having the shape, the polysilicon film P2 remains adjacent to the pattern extending in the first direction. In this case, when the silicide layer S2 is formed on the upper surface of the pattern extending in the first direction and the polysilicon film P2 adjacent thereto, the polysilicon films P1 and P2 are in contact with each other and the silicide layer S2 in the upper part thereof. There is a risk of short circuit. In order to avoid this, in this embodiment, in the process described with reference to FIG. 8, a part of the polysilicon film P2 in the capacitor element formation region C1 is removed to prevent a short circuit between the polysilicon films P1 and P2. Is possible. Further, when the contact plug C2 is connected on the comb-shaped polysilicon film P1, a short circuit between the polysilicon films P1 and P2 can be prevented due to the displacement of the contact hole formation.

  FIG. 25 shows a well power feeding portion WS formed on the upper surface of the semiconductor substrate SB in order to supply a potential to a well formed on the upper surface of the semiconductor substrate SB (not shown). The well power supply unit WS is formed by ion-implanting, for example, a P-type impurity (for example, B (boron)) into the upper surface of the semiconductor substrate SB so that the element isolation region EI in which the PIP capacitor element is formed is seen in a plan view. It is formed in an annular shape so as to surround it. A silicide layer S1 (not shown) is formed on the upper surface of the well power supply portion WS, and a contact plug C2 is formed on the well power supply portion WS via the silicide layer S1. By supplying a potential to the semiconductor substrate SB via the contact plug C2, the silicide layer S1, and the well power feeding portion WS, the potential of the semiconductor substrate SB below the PIP capacitor element can be fixed.

  As shown in FIG. 24, in the region where the MONOS memory is formed, unlike in FIG. 10, the dummy gate electrode DP is removed, and the semiconductor substrate SB immediately below the region where the dummy gate electrode DP is formed (FIG. 26). The diffusion layer SL constituting the source / drain regions is formed on the upper surface of the reference). In FIG. 24, the silicide layers S1 and S2 are not shown for easy understanding of the drawing. The silicide layer S2 is not formed on the upper surfaces of the memory gate electrode MG and the control gate electrode CG in the region constituting the MONOS memory. However, in the power supply portion, the silicide gate SMG and the control gate electrode CG A silicide layer S2 (not shown) is formed between the upper and lower contact plugs C2.

  The effects of the method for manufacturing the semiconductor device of the present embodiment will be described below.

  As shown in FIGS. 32 and 33, the split gate type MONOS memory has a structure in which a control gate electrode CGa is formed on a semiconductor substrate SB via a gate insulating film GF, and one or both of the side walls thereof are formed. In addition, it is conceivable to form the memory gate electrode MGa formed in a side wall shape in a self-aligned manner via the ONO film. The ONO film is a laminated film in which a silicon oxide film X1, a silicon nitride film N1, and a silicon oxide film X2 are sequentially formed. The silicon nitride film N1 is an insulating film that functions as a charge storage film of the MONOS memory.

  32 and 33 are sectional views showing a semiconductor device including a MONOS memory as a comparative example. Here, in addition to the control gate electrode CGa and the memory gate electrode MGa, a source / drain composed of a silicon nitride film N2 on the control gate electrode CGa, an extension region EX formed on the upper surface of the semiconductor substrate SB, and a diffusion layer SL. Shows the area. Note that the silicon nitride film N2 is not formed, and the height of the upper surface of the control gate electrode CGa may be equal to the heights of the uppermost surfaces of the ONO film and the memory gate electrode MGa.

  The memory gate electrode MGa shown in FIG. 32 and FIG. 33 is formed on the semiconductor substrate SB after forming a laminated film pattern composed of the control gate electrode CGa and the silicon nitride film N2 via the gate insulating film GF. An ONO film and a polysilicon film that cover the stacked film are formed (deposited) by a CVD method or the like, and then the polysilicon film is partially removed by a dry etching method. That is, a part of the polysilicon film remains in a side wall shape in a self-aligned manner on the side wall of the control gate electrode CGa, and the memory gate electrode MGa made of the polysilicon film is formed.

  In the comparative example, since the memory gate electrode MGa is formed in a sidewall shape, in the gate length direction of the control gate electrode CGa, the height of the upper surface of the memory gate electrode MGa increases as the distance from the side wall of the control gate electrode CGa increases. Lower. In this case, the lowest height (film thickness) of the end of the memory gate electrode MGa is L as shown in FIG. If the MONOS memory having the memory gate electrode MGa having such a shape is to be miniaturized, in the ion implantation process for forming the source / drain regions after the memory gate electrode MGa is formed, the impurity to be implanted becomes the memory gate. It penetrates the electrode MGa and is driven into the upper surface of the semiconductor substrate SB. In this case, since extra impurity ions are implanted into the upper surface of the semiconductor substrate SB, the characteristics of the MONOS memory, that is, information erasing characteristics, writing characteristics, and the like are changed, and the reliability of the semiconductor device is lowered.

  In order to prevent the penetration of impurity ions, the memory gate electrode MGa needs to have a predetermined height (film thickness) X, whereas the height of the memory gate electrode MGa is not constant, and the gate length direction The height (film thickness) L of one end is low. That is, in the semiconductor device of the comparative example shown in FIG. 32, the MONOS memory cannot be miniaturized while maintaining the height X necessary for preventing impurity ions from penetrating the memory gate electrode MGa.

  That is, even if an attempt is made to miniaturize the MONOS memory so that the height (film thickness) L of one end of the memory gate electrode MGa maintains the height (film thickness) X that can prevent the penetration of impurity ions, the memory gate Since the electrode MGa is formed in a self-aligned manner, the height of the uppermost surface of the memory gate electrode MGa is higher than the height L of the upper surface of one end portion. The height of the upper surface of the stacked film adjacent to the side wall of the memory gate electrode MGa via the ONO film, that is, the stacked film including the control gate electrode CGa is higher than the height L of the upper surface of the end portion of the memory gate electrode MGa. Get higher. For this reason, the height of the top surfaces of the memory gate electrode MGa and the stacked film adjacent to the memory gate electrode MGa cannot be lowered to such a level that the memory gate electrode MGa does not penetrate impurity ions.

  Thus, when trying to prevent the penetration of impurity ions, there is a problem that it is difficult to miniaturize the MONOS memory due to the memory gate electrode MGa having a sidewall shape.

  Further, as shown in FIG. 33, the shape of the memory gate electrode MGa formed in a self-alignment tends to extend in the direction away from the control gate electrode CGa so that the bottom is widened at the bottom. Becomes more prominent as the MONOS memory becomes finer. The characteristics and reliability of the MONOS memory are greatly influenced by the width of the memory gate electrode MGa in the gate length direction and its perpendicularity.

  Note that the term “perpendicularity” as used herein refers to a degree indicating how close the side walls of the memory gate electrode MGa are formed to the main surface of the semiconductor substrate SB. The higher the verticality of the sidewall of the memory gate electrode MGa, the easier it is to keep the characteristics of the MONOS memory constant and to maintain the reliability of the MONOS memory. That is, if the angle formed between the side wall of the memory gate electrode MGa and the side wall opposite to the side where the memory gate electrode MGa and the control gate electrode CGa are in contact with the semiconductor substrate SB is close to the vertical, the reliability of the semiconductor device Can be prevented from decreasing.

  However, as described above, when the MONOS memory is miniaturized, the bottom of the sidewall-like memory gate electrode MGa extends along the upper surface of the semiconductor substrate, and it becomes difficult to maintain the verticality. Further, since the sidewall-shaped memory gate electrode MGa becomes wider in the gate length direction as it approaches the lower surface from the upper surface, forming the memory gate electrode MGa while keeping the width constant is the same as the MONOS memory. The smaller the size, the more difficult it becomes. For this reason, if the MONOS memory is to be miniaturized, the sidewall-shaped memory gate electrode MGa is kept vertical, and the width in the gate length direction cannot be formed with a desired constant width. There is a risk that the reliability of the semiconductor device is lowered.

  In contrast, the present embodiment does not use a method of leaving a polysilicon film formed in a sidewall shape on the side wall of the control gate electrode as a memory gate electrode. In the present embodiment, as described with reference to FIGS. 5 and 7, the polysilicon film P2 embedded in the trench between the pattern of the polysilicon film P1 serving as the control electrode and the pattern of the dummy gate electrode DP is used. A memory gate electrode MG is formed (see FIG. 19). Thus, in the process shown in FIG. 7, the polysilicon film P2 formed in the side wall shape is removed and is not used as a gate electrode.

  The polysilicon film P2 formed in the trench as described above changes in height and width as the distance from the control gate electrode CGa is increased as in the memory gate electrode MGa (see FIG. 32) of the comparative example. The cross-sectional shape of the memory gate electrode MG is rectangular as shown in FIG.

  Therefore, in the manufacturing process of the semiconductor device of the present embodiment, the height of the upper surface of one memory gate electrode MG is constant in any region, and the width of the memory gate electrode MG in the gate length direction is set to any height. Also, the thickness can be constant, and the verticality of the side wall can be improved. That is, the thickness of one memory gate electrode MG does not decrease as the distance from the adjacent control gate electrode CG increases, and the thickness is uniform. Of the side walls of the memory gate electrode MG, the side wall not adjacent to the control gate electrode CG is formed perpendicular to the main surface of the semiconductor substrate SB.

  For this reason, even if the MONOS memory is miniaturized, the height of the memory gate electrode MG is not excessively lowered at the end thereof, and impurity ions are not formed in the ion implantation process performed when forming the source / drain regions. It is possible to prevent the memory gate electrode MG from penetrating. As a result, even if the MONOS memory is miniaturized, it is possible to prevent the characteristics of the MONOS memory from changing, so that the reliability of the semiconductor device can be improved.

  Further, the width of the memory gate electrode MG can be easily controlled by adjusting the distance between the polysilicon film P1 and the dummy gate electrode DP shown in FIG. Also, unlike the semiconductor device of the comparative example shown in FIG. 33, it is possible to prevent the bottom of the memory gate electrode MG from spreading in the gate length direction, so that it is possible to prevent the characteristics of the MONOS memory from changing. . Therefore, the control of the width of the memory gate electrode MG is facilitated, and the perpendicularity of the memory gate electrode MG can be improved, so that the characteristics of the MONOS memory, that is, the information erasing characteristics and the writing characteristics can be easily adjusted. Therefore, the reliability of the semiconductor device can be improved.

  In the semiconductor device formed by the manufacturing method of the present embodiment, the area required for one MONOS memory can be reduced to about half compared with the case where the memory gate electrode is formed in a sidewall shape.

  Further, in the present embodiment, as shown in FIG. 26, different polysilicon films P1 and P2 are used instead of a PIP capacitor element in which another polysilicon film is laminated on a polysilicon film via an insulating film. Capacitance elements are formed by arranging ONO films between the polysilicon films P1 and P2 in the direction along the upper surface of the SB. For this reason, as described above, the height of the PIP element can be reduced, and the height of the PIP element can be made equal to that of the FET used for the MONOS memory or the logic circuit, so that the semiconductor device can be miniaturized.

  The PIP capacitor element has a structure in which polysilicon films P1 and P2 are formed side by side in the direction along the upper surface of the semiconductor substrate SB, similarly to the MONOS memory. A capacitor element can be formed. Accordingly, the manufacturing process of the semiconductor device can be simplified and the throughput can be improved as compared with the case where the PIP capacitor element is formed by stacking another polysilicon film on the polysilicon film via the insulating film. Can do.

  An element that generates a capacitance by facing comb-shaped patterns facing each other like the PIP capacitance element of the present embodiment extends in the second direction and extends in the second direction, depending on the required capacitance. This can be dealt with by changing a plurality of patterns of the polysilicon films P1 and P2 alternately arranged, that is, the number or length of combs.

(Embodiment 2)
In the first embodiment, the semiconductor device manufacturing method including the step of polishing and removing the silicide layer S1 in the step described with reference to FIG. 19 has been described. In contrast, in the present embodiment, a method for manufacturing a semiconductor device when the silicide layer is not polished in the polishing step will be described below with reference to FIGS. 27 to 31 are cross-sectional views showing the semiconductor device in the manufacturing process for explaining the method for manufacturing the semiconductor device of the present embodiment.

  In the manufacturing process of the semiconductor device according to the present embodiment, first, the pattern including the polysilicon films P1 and P2 is formed on the semiconductor substrate SB by performing the steps shown in FIGS. Then, the dummy gate electrode DP (see FIG. 11) is removed.

  Next, as shown in FIG. 27, after removing the photoresist film PR4, the upper surface of the polysilicon film P2 exposed from the silicon oxide film X1 is selectively etched back and retracted using a dry etching method. Thus, grooves D2 to D4 are formed in the MONOS memory formation region A1, the power feeding portion formation region B1, and the capacitor element formation region C1, respectively. That is, the trench D2 is formed immediately above the polysilicon film P2 in the MONOS memory formation region A1, and the trench D3 is formed immediately above the polysilicon film P2 buried between the adjacent polysilicon films P1 in the power feeding portion formation region B1. Then, a trench D4 is formed immediately above the polysilicon film P2 buried between the adjacent polysilicon films P1 in the capacitive element formation region C1. The side walls of the silicon oxide film X2 are exposed on the side walls of the grooves D2 to D4, and the polysilicon film P2 is exposed on the bottom surfaces of the grooves D2 to D4.

  Also, the etch back causes the upper surface of the polysilicon film P2 formed in a sidewall shape to recede in the power supply portion formation region B1 and the capacitor element formation region C1.

  The height of the upper surface of the etched back polysilicon film P2 is, for example, equal to or higher than the upper surface of the polysilicon film P1. As a result, the height of the upper surface of the polysilicon film P2 is lower than the height of the upper surface of the ONO film composed of the silicon oxide film X2, the silicon nitride film N1, and the silicon oxide film X1 in contact with the side walls thereof.

  Next, the structure shown in FIG. 28 is obtained by performing the same processes as those described with reference to FIGS. That is, after removing the exposed silicon oxide film X1, the offset spacer OS, the extension region EX, the sidewall SW, and the diffusion layer SL are sequentially formed.

  However, unlike the first embodiment, the height of the upper surface of the polysilicon film P2 is lower than the height of the upper surface of the ONO film in contact with the side wall thereof, so that each of the grooves D2 to D4 immediately above the polysilicon film P2 is provided. A sidewall SW is formed on the sidewall via an offset spacer OS. Further, in the power feeding portion forming region B1 and the capacitive element forming region C1, a sidewall SW is formed on the sidewall of the silicon oxide film X2 immediately above the polysilicon film P2 formed in a sidewall shape via an offset spacer OS. Is done.

  As a result, the upper surface of the polysilicon film P2 in the MONOS memory formation region A1 and the upper surface of the polysilicon film P2 embedded between the adjacent polysilicon films P1 in the power feeding portion formation region B1 and the capacitor element formation region C1 are Since it is completely covered with the wall SW, it is not exposed on the semiconductor substrate SB. In addition, in the power supply portion formation region B1 and the capacitive element formation region C1, the upper surface of the polysilicon film P2 formed in a sidewall shape is not exposed because it is covered with the offset spacer OS and the sidewall SW. In order to obtain such a structure, in the etch-back process described with reference to FIG. 27, the polysilicon shown in FIG. 28 is used as much as necessary for the sidewall SW to cover the upper surface of the polysilicon film P2. It is necessary to recede the upper surface height of the film P2 toward the semiconductor substrate SB.

  As the structure for the sidewall SW to completely cover the upper surface of the polysilicon film P2, for example, the following structure is conceivable. That is, the length of the polysilicon film P2 in the direction in which the polysilicon film P2 and the polysilicon film P1 are arranged, that is, in the gate length direction of the memory gate electrode formed by the polysilicon film P2 in a later process is offset. It can be considered that the length is equal to or less than twice the total length of the spacer OS and the insulating film constituting the sidewall SW. Accordingly, the width of the grooves D2 to D4 in the same direction is not more than twice the length obtained by adding the thickness of the offset spacer OS and the thickness of the insulating film constituting the sidewall SW. Thus, the bottom surfaces of the grooves D2 to D4 are completely covered with the offset spacers OS and the sidewalls SW formed on the side walls on both sides of the grooves D2 to D4.

  Next, the process shown in FIGS. 16 and 17 is performed to obtain the structure shown in FIG. Thereby, the silicide layer S1 is formed on the upper surface of the diffusion layer SL. Here, unlike the first embodiment, since the upper surface of the polysilicon film P2 is covered with the sidewall SW, the polysilicon film P2 in the MONOS memory forming region A1, the power feeding portion forming region B1, and the capacitive element forming region C1. No silicide layer is formed on the upper surface of the substrate. That is, the silicide layer S1 is formed only on the upper surface of the exposed semiconductor substrate SB including the diffusion layer SL and the like here.

  Next, the structure shown in FIG. 30 is obtained by performing the same process as that described with reference to FIGS. That is, after the etching stopper film ES and the interlayer insulating film L1 are formed, the interlayer insulating film L1, the etching stopper film ES, the silicon oxide films X1 and X2, the silicon nitride films N1 and N2, and the polysilicon films P1 and P2 are formed by CMP. Then, the offset spacer OS and the sidewall SW are polished. As a result, the upper surfaces of the polysilicon films P1 and P2 are exposed, and a control gate electrode CG made of the polysilicon film P1 and a memory gate electrode made of the polysilicon film P2 are formed in the MONOS memory forming region A1 and the power feeding portion forming region B1. MG is formed.

  That is, in the polishing process by the CMP method, the sidewall SW inside each of the grooves D2 and D3 immediately above the memory gate electrode MG is completely removed by polishing. In the capacitor element formation region C1, the sidewall SW immediately above the polysilicon film P2 between the adjacent polysilicon films P1 is completely removed by polishing. As a result, the upper surfaces of the memory gate electrode MG, the control gate electrode CG, and the polysilicon films P1 and P2 are all exposed. At this time, the memory gate electrode MG and the polysilicon film P2 formed in a sidewall shape are also exposed.

  Unlike the first embodiment, the main feature of the method of manufacturing the semiconductor device of the present embodiment is that the silicide layer is not polished in the polishing step described with reference to FIG. In this way, the fact that the silicide layer is not polished is that the upper surface of the polysilicon film P2 whose upper surface is receded by the process described with reference to FIGS. 27 and 28 is covered with the sidewall SW, as shown in FIG. This can be realized by preventing the silicide layer from being formed on the polysilicon film P2 in the process.

  Here, as described above, the silicide layer is not formed on the upper surface of the polysilicon film P2 (see FIG. 29) because the residue of the silicide layer generated by polishing the silicide layer in the polishing step is later This is to prevent adverse effects on the manufacturing process. That is, the silicide layer is a conductive film containing a metal such as cobalt silicide (CoSi), and the residue generated by polishing the conductive film is generated by polishing an insulating film or a semiconductor layer such as a silicon nitride film or a silicon oxide film. Compared with the residue, the semiconductor layer such as the semiconductor substrate SB and the polysilicon film P1 or P2 is easily damaged, and the influence on the film formed in the subsequent film formation process is large. If the semiconductor layer including the semiconductor substrate SB is damaged due to the generation of the residue of the silicide layer and the film formation failure occurs in the interlayer insulating film formed in the subsequent process, the reliability of the semiconductor device The problem that sex falls.

  Therefore, it is desirable not to polish the silicide layer in the polishing process using the CMP method or the like described with reference to FIG. Therefore, in the present embodiment, the surfaces of the polysilicon films P1 and P2 are covered with an insulating film such as a sidewall SW, and a silicide layer is formed on the upper surfaces of the polysilicon films P1 and P2 in the process described with reference to FIG. By not doing so, the silicide layer is polished in a subsequent polishing step, thereby preventing the silicide layer residue from being formed on the semiconductor substrate SB.

  Accordingly, the semiconductor layer such as the semiconductor substrate SB can be prevented from being damaged, and the film formation failure after the polishing step can be prevented, so that the reliability of the semiconductor device can be improved. it can.

  Subsequent steps are similar to those described with reference to FIGS. 20 to 26, whereby the semiconductor device of the present embodiment shown in FIG. 31 is completed. That is, after forming the gate electrode G1 made of a metal film, the silicide layer S2 is formed on the upper surface of the semiconductor layer such as the power feeding portion, and then the interlayer insulating film L2, the contact plug C2 penetrating the interlayer insulating film L2, etc. Form.

  In the manufacturing method of the semiconductor device of this embodiment, in addition to the same effect as that of the above embodiment, as described above, the effect of improving the reliability of the semiconductor device can be obtained by preventing the polishing of the silicide layer. it can.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first and second embodiments, the case where an n-channel MOSFET is formed on a semiconductor substrate has been described. However, the semiconductor element may be a p-channel MOSFET, or a MIS (Metal Insulator Semiconductor) type. It may be an FET.

A1 MONOS memory formation region B1 Feeding portion formation region C1 Capacitance element formation region C2 Contact plug CG Control gate electrode CGa Control gate electrode D1 Low breakdown voltage element formation region D2 to D4 Groove DP Dummy gate electrode EI Element isolation region ES Etching stopper film EX Extension Region G1 Gate electrode GF Gate insulating film IF Insulating film L1, L2 Interlayer insulating film MG, MGa Memory gate electrode N1, N2 Silicon nitride film OS Offset spacer P1, P2 Polysilicon films PR1-PR4 Photoresist film S1, S2 Silicide layer SB Semiconductor substrate SL Diffusion layer SW Side wall WS Well feeding part X1 to X4 Silicon oxide film

Claims (6)

A semiconductor substrate;
A capacitive element formed on the semiconductor substrate;
Have
The capacitive element is
A first portion formed on the semiconductor substrate and extending in a first direction; and a plurality of second portions extending in a second direction orthogonal to the first direction and connected to the first portion. Including a first conductor film,
A second conductor film formed on the semiconductor substrate and embedded between the adjacent second portions;
An insulating film formed between the first conductor film and the second conductor film formed on the semiconductor substrate and insulated from each other;
A semiconductor device. The semiconductor device according to claim 1,
The first conductor film has three second portions,
The second conductive film includes a third portion extending in the first direction and a plurality of fourth portions extending in the second direction and connected to the third portion. The semiconductor device according to claim 1,
A third conductor film separated from the first conductor film and in the same layer as the first conductor film;
Configuring the second conductor film, a fifth portion surrounding the third conductor film in plan view;
A plug formed over the respective upper surfaces of the second conductor film and the third conductor film and electrically connected to the second conductor film;
A semiconductor device further comprising: The semiconductor device according to claim 1,
The insulating film includes a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The semiconductor device according to claim 1,
An element isolation region formed on the semiconductor substrate;
The capacitor element is a semiconductor device formed on the element isolation region. The semiconductor device according to claim 1,
The semiconductor device, wherein the second conductor film does not have a portion higher than the first conductor film.

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