JP2014041247A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which: in a liquid crystal display device driving in a horizontally divided manner, insufficient writing of pixel voltage occurs in the last rows of vertical scanning in display areas, especially, when the last row is at the center of an image, dark lines are displayed, which results in a reduction of image quality.SOLUTION: For example, a scanning line driving circuit driving a gate line of an upper display area sequentially outputs a scanning pulse Pselecting the k-th row of an image. A video line driving circuit driving a source line of the upper display area outputs a pixel voltage according to data Dduring a period of the scanning pulse P. A timing of completion of application of the pixel voltage to application of the scanning pulse Pis set to a timing later than that of the previous row of the n-th row that is to be the last row of an effective scanning period T.

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique for horizontally dividing a screen into a plurality of display areas and vertically scanning them in parallel.

  Liquid crystal display devices are used in products such as flat-screen TVs, personal computers, tablet terminals, and smartphones. Especially for large panel applications such as flat-screen TVs, the number of pixels such as 4K resolution (4K2K) is increased and high frame rates such as double speed and quadruple speed are required to improve high-definition image display, three-dimensional display, and video quality. There is a demand for driving. These requirements may shorten the data writing time assigned to each horizontal scanning line in the vertical scanning of the screen, and may cause a problem of insufficient data writing to the pixels in the normal driving method. As one solution to this problem, there is known a division drive method in which a screen is divided into a plurality of display areas and data writing is performed in parallel with respect to each display area.

  However, in the division driving in which the screen is divided horizontally into two upper and lower display areas, there is a problem that an unintended luminance change appears at the boundary between the display areas in the display image of the liquid crystal display device, and the joint of the display areas is visible on the image. In the following Patent Documents 1 to 3, countermeasures to the problem are examined.

JP 2000-321552 A JP 2008-70406 A JP-A-11-102172

  The above-mentioned problem that the joint of the display area is displayed also has a cause that has not been studied in the above-mentioned patent document. The cause of the seam display handled by the present application will be described with reference to FIGS.

Figure 6 is a schematic diagram of a screen in division driving that bisects the screen up and down, and the vertical scanning of the display area A _D of the vertical scan and the lower half of the display area A _U of screen half is performed in parallel . The screen is composed of 2n (n is a natural number) horizontal scanning lines from the first to the 2n in order from the top.

7, the area _A U, _{A D} signal _VS U, VS _D and a voltage signal supplied to each source line (video lines) is provided corresponding to each horizontal scanning line of the first to 2n FIG. 5 is a schematic timing chart of signals VG _{1 to} VG _2n that are voltage signals supplied to gate lines (scanning lines). The vertical scanning in the area A _U (first to nth rows) and the area A _D ((n + 1) to second nth rows) is performed from the top to the bottom as indicated by arrows in FIG. Correspondingly, in the effective scanning period _TEFF of the vertical scanning, the scanning pulse P _k (selection signal) is sequentially generated for the signal VG _k and the signal VG _{n + k} (k = 1 to n).

The signals VS _U and VS _D are set to the reference voltage V _BLK corresponding to the pixel value representing black in the blanking period T _BLK of vertical scanning. On the other hand, in the effective scanning period _TEFF , the signals VS _U and VS _D are synchronized with the scanning pulse P _k and the signal voltage V representing the pixel values D _k and D _{n + k} of the pixels in the k-th and (n + k) -th rows. _k and Vn _{+ k} . Here, in order to simplify the description, it is assumed that the pixel values D _{1 to} D _2n of the _2n pixels arranged in the direction along the source line (column direction) are the same, and correspondingly in FIGS. it represents signal _VS U in the effective scanning period _{T EFF,} the VS _D at a constant voltage. Incidentally, the frame inversion driving, the signal _VS U, VS _D are inverted polarity with respect to reference voltage _{V BLK} in an effective scanning period _{T EFF} adjacent.

FIGS. 8 and 9 are schematic signal waveform diagrams showing the signals VS _U and VG _k of the display area A _U and the potential VP of the pixel electrode in the non-tail portion and the tail portion of the effective scanning period _TEFF , respectively. Thin film transistor provided in each pixel (Thin Film Transistor: TFT), when applied to the scanning pulse P _k to the gate electrode, the channel between the source line and the pixel electrode and the ON state, the pixel electrode signal VS _U The battery is charged to a potential corresponding to. By the way, since the waveform of the scan pulse P _k is dull due to the capacitance and wiring resistance associated with the gate line, the scan pulse P _k may continue to fall until a period in which the signal voltage V _k is not applied. In writing to pixels in the α-th row (1 ≦ α ≦ n−1), which is a non-tail row, as shown in FIG. 8, the signal voltage after one row during the falling period of the scan pulse P _{α for} the row. By applying V _{α + 1} , the potential VP of the pixel electrode is set relatively high. On the other hand, in writing to the pixels in the n-th row, which is the last row, as shown in FIG. 9, one row later (that is, the lower display area A) in the falling period of the scan pulse P _{n for} the row. _{Since the} reference voltage V _BLK lower than the signal voltage V _{n + 1 in} the uppermost row of _D is applied, the potential VP of the pixel electrode is set lower than that in the non-tail row shown in FIG. Therefore, even if the pixel values are the same, the nth row has a problem that the signal voltage is insufficiently written as compared with the adjacent (n−1) th row and (n + 1) th row, and is displayed dark on the screen. It was.

This shortage of writing to the pixels in the last row of the vertical scan also occurs in the last row of the normal driving method that does not divide the screen horizontally. However, since the luminance is lowered at the edge of the screen, it is not so noticeable. In comparison, the luminance change is visually easily recognized in other than the end of the screen as the display area A _U described above.

  The present invention has been made to solve the above problem, and in a liquid crystal display device that is driven in a horizontally divided manner, among a plurality of display areas obtained by dividing a screen, a line adjacent to another display area is used for vertical scanning. The object is to make it difficult for an unintended luminance change to appear at the boundary between display areas in the case of including those that end with.

  The liquid crystal display device according to the present invention includes a video line provided corresponding to each column of pixels for each of a plurality of display areas obtained by horizontally dividing a screen composed of a plurality of pixels arranged in a matrix, and each row of the pixels. Corresponding to the scanning line driving circuit that sequentially supplies a selection signal to the plurality of scanning lines provided in each display region and performs vertical scanning in parallel in the plurality of display regions; and A predetermined reference voltage is applied to the video line during a blanking period, and the video is applied to each pixel in a selected row to which the selection signal is supplied via the scanning line during an effective scanning period of the vertical scanning. And a video line driving circuit for applying a signal voltage corresponding to a pixel value via a line, and driving the screen in a divided manner, wherein the scanning line driving circuit is predetermined in the display area. In the specified display area The scanning is finished in a pixel row adjacent to the other display area, and the video line driving circuit applies the first signal voltage applied at the application end timing of the effective scanning period and the application of the blanking period. The second signal voltage applied at the start timing is set to an equal voltage.

  In one embodiment of the present invention, the image display device further includes a mask circuit that controls input of a latch pulse to the video line driver circuit, and the mask circuit includes at least the specific display region of the display region. The signal voltage application end timing based on the timing of the selection signal in each selected row may be set to a timing later than the preceding selected row for the selected row at the end of the effective scanning period. Good.

  In one embodiment of the present invention, the semiconductor device further includes a memory circuit that outputs input data with a delay of at least one horizontal scanning period, and the memory circuit outputs the first signal voltage during the effective scanning period. You may apply until the application start timing of the blanking period.

  Another liquid crystal display device according to the present invention includes a video line provided corresponding to each column of pixels for each of a plurality of display areas obtained by horizontally dividing a screen composed of a plurality of pixels arranged in a matrix, A scanning line driving circuit that sequentially supplies a selection signal to a plurality of scanning lines provided in each display area corresponding to each row and performs vertical scanning in parallel in the plurality of display areas, and the vertical line A predetermined reference voltage is applied to the video line during a scanning blanking period, while the selection signal is supplied to the pixels in the selected row via the scanning line during an effective scanning period of the vertical scanning. A liquid crystal display device that divides and drives the screen, the video line driving circuit applying a signal voltage corresponding to a pixel value via the video line, wherein the scanning line driving circuit is included in the display area. Before a specific display area The vertical scanning is ended in a pixel row adjacent to the other display area, and the video line driving circuit applies the signal voltage in the effective scanning period to at least the specific display area of the display area. After the application is completed, a voltage corresponding to the pixel value of the intermediate gradation set in advance is applied instead of the reference voltage in a transition period of a predetermined length at the beginning of the blanking period.

  According to the present invention, in a liquid crystal display device that performs horizontal division driving, display is performed when a plurality of display areas into which a screen is divided include one that ends vertical scanning in a row adjacent to another display area. Unintentional luminance changes are less likely to appear at the boundaries between regions, and image quality can be improved.

It is a schematic diagram which shows the structure of the liquid crystal display device which concerns on embodiment of this invention. FIG. 5 is a signal waveform diagram illustrating a pixel voltage writing operation with respect to the last row of the specific display area in the liquid crystal display device according to the first embodiment of the present invention. After application end of the signal voltage V _n, a block diagram schematically illustrating an example of a circuit configuration for applying a signal voltage V _n to the application start 1H period blanking period T _BLK. The application end of the signal voltage V _n is a schematic block diagram showing an example of a circuit configuration for slow 1H period. It is a signal waveform diagram explaining the write-in operation | movement of the pixel voltage with respect to the last line of the specific display area in the liquid crystal display device of the 2nd Embodiment of this invention. It is a schematic diagram of the screen in the division | segmentation drive which divided the screen up and down equally. FIG. 5 is a schematic timing chart of voltage signals supplied to source lines and gate lines in upper and lower display areas. FIG. 6 is a schematic signal waveform diagram showing a voltage signal supplied to a source line and a gate line and a potential of a pixel electrode in a non-tail portion of an effective scanning period _TEFF . FIG. 6 is a schematic signal waveform diagram showing a voltage signal supplied to a source line and a gate line and a potential of a pixel electrode in an end portion of an effective scanning period _TEFF .

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic diagram illustrating a configuration of a liquid crystal display device 10 according to the first embodiment. The liquid crystal display device 10 includes a liquid crystal panel 20, scanning line drive circuits 22u and 22d, video line drive circuits 24u and 24d, a control device 26, a backlight unit (not shown), and a backlight drive circuit (not shown).

  The liquid crystal display device 10 is, for example, an IPS (In Plane Switching) method and an active matrix driving method. The liquid crystal panel 20 includes a color filter substrate and a TFT substrate that are arranged to face each other with a gap, and the gap is filled with liquid crystal. A polarizing film is stuck on the outer surface of each glass substrate constituting the color filter substrate and the TFT substrate. The TFT substrate is located on the back side of the liquid crystal panel 20, and a backlight unit is disposed behind the TFT substrate. On the other hand, the color filter substrate is located on the display surface side of the liquid crystal panel 20.

  On the surface of the TFT substrate on the liquid crystal side, a TFT, a pixel electrode, a common electrode, wiring to these, and the like are formed. Specifically, the pixel electrodes and the TFTs are arranged in a matrix corresponding to the pixel arrangement. Similarly to the pixel electrode, a common electrode made of a transparent electrode material is also disposed in each pixel. As the wiring, a plurality of source lines 30, a plurality of gate lines 32, and a common electrode wiring are formed. The plurality of source lines 30 and the plurality of gate lines 32 are arranged substantially orthogonal to each other. The gate line 32 is provided for each row (horizontal arrangement) of TFTs, and is connected in common to the gate electrodes of a plurality of TFTs in the row. The source line 30 is provided for each TFT column (alignment in the vertical direction), and is connected in common to the sources of the plurality of TFTs in the column. A pixel electrode corresponding to the TFT is connected to the drain of each TFT.

  Each TFT has its conduction state controlled in units of rows in accordance with a scanning pulse applied to the gate line 32. The pixel electrode is connected to the source line 30 through the TFT which is turned on, and a signal voltage (pixel voltage) corresponding to the pixel value is applied from the source line 30. A predetermined common potential is applied to the common electrode via the common electrode wiring. The orientation of the liquid crystal is controlled for each pixel by the electric field generated according to the potential difference between the pixel electrode and the common electrode, and the transmittance for light incident from the backlight unit is changed, whereby an image is formed on the display surface. .

The liquid crystal display device 10 is a division driving method in which the screen is horizontally divided into two upper and lower display areas. Here, the total number of pixel rows constituting the screen is 2n (n is a natural number), and the screen is divided into two equal parts, and the upper half of the display area _AU and the lower half of the display area _AD are divided. Vertical scanning is performed in parallel.

For performing division driving, the source line 30 is the area A _U, at the boundary between A _D, is divided into a source line 30d which is disposed on the source line 30u and the area A _D is arranged in the area A _U. A video line driving circuit 24u is connected to the source line 30u, and a video line driving circuit 24d is connected to the source line 30d. The gate lines 32 of the first to n are arranged in the display area A _U from the upper side of the screen, which are connected to the scanning line driving circuit 22u. The (n + 1) th to 2nth gate lines 32 arranged in the display area _AD are connected to the scanning line driving circuit 22d.

  The control device 26 receives a video signal received by a tuner or an antenna (not shown) and a video signal generated by another device such as a video playback device. The control device 26 includes a CPU (Central Processing Unit) and a memory such as a ROM (Read Only Memory) and a RAM (Random Access Memory).

  The control device 26 performs various kinds of image signal processing such as color adjustment on the input video signal, and generates pixel data indicating the gradation value of each pixel. For example, the control device 26 holds the pixel data for one frame obtained from the video signal inputted in line sequential order in the RAM, reads out the pixel data in a desired order for each row, and sends it to the video line driving circuits 24u and 24d. Can be output. Further, the control device 26 generates timing signals for synchronizing the scanning line drive circuits 22u and 22d, the video line drive circuits 24u and 24d, and the backlight drive circuit based on the input video signal, and drives each drive. Output to the circuit.

  The scanning line drive circuits 22u and 22d sequentially select the gate lines 32 according to the timing signal input from the control device 26, and start an operation of outputting a scanning pulse to the selected gate lines 32. In the present embodiment, the scanning line driving circuit 22u selects the gate lines 32 in order from the first row to the nth row, and the scanning line driving circuit 22d in parallel with this selects from the (n + 1) th row to the second nth row. The gate line 32 is selected in order.

The video line driving circuits 24u and 24d receive pixel data of the selected row from the control device 26 in synchronization with the selection of the gate line 32 by the scanning line driving circuits 22u and 22d, respectively. Generate the corresponding voltage. Then, this is output to the source lines 30u and 30d as a pixel voltage. Thereby, a pixel voltage is applied to the pixel electrode corresponding to the selected gate line 32 in each of the display areas A _U and A _D. Incidentally, this corresponds to horizontal scanning of a raster image, and a row is selected in each of the display areas A _U and A _{D for} each horizontal scanning period in the effective scanning period, and pixel voltage is written to the row. For example, the period (1V) or effective scanning period T _EFF and blanking period T _BLK vertical scanning in the liquid crystal display device 10 is set to be the same as the effective display period and the blanking period of the vertical scanning of the video signal, also the horizontal The scanning period (1H) can be set based on the horizontal synchronization signal of the video signal.

Video line drive circuit 24u, 24d basically outputted to the source line 30 by 1H in the effective scanning period _{T EFF} pixel voltage corresponding to the selected row. The potential of the pixel electrode at the time when the TFT is turned off by the writing operation of each row is basically held until writing to the row is started in the next frame. The transmittance is controlled according to the potential. In this embodiment, the polarity of the pixel voltage is inverted for each frame by frame inversion driving. In the blanking period T _BLK , the video line driving circuits 24 u and 24 d basically output a predetermined reference voltage V _BLK to each source line 30. Here, when an unnecessary direct current potential is applied to the pixel electrode due to a leak current of the TFT, the image quality is deteriorated. In order to prevent this, it is preferable that the reference voltage V _BLK is basically set to a potential associated with a pixel value representing black.

Source lines 30u in this embodiment, the signal _VS U applied to 30d, VS _D and, to incorporated 7 as a timing diagram of the first to 2n signal _VG 1 _{VG 2n} applied to the gate line 32 of the Can do. Further, the writing of the pixel voltage to the non-tail row in each effective scanning period _TEFF is performed in the same manner as the operation described above with reference to FIG.

The pixel voltage writing operation for the last row in each effective scanning period _TEFF , which is a feature of the present invention, will be described below. As described above, an object of the present invention is to solve a shortage of writing in the last line when ending in a pixel line adjacent to another display area in vertical scanning in a display area set by horizontal division. It is said. Here, a display area in which vertical scanning ends in a pixel row adjacent to another display area is referred to as a specific display area. In the present embodiment, the upper display area _Au is the specific display area.

In the present embodiment, the video line driving circuit sets the pixel voltage application end timing based on the timing of the scanning pulse in each selected row to at least the specific display region among the plurality of display regions, as the effective scanning period T. The last selected line (end line) of _EFF is set to a timing later than that of the preceding selected line (non-end line).

FIG. 2 is a signal waveform diagram for explaining the pixel voltage writing operation for the last row of the area A _u that is the specific display area, and schematically shows the signal waveforms of the signals VS _u and VG _n and the potential VP of the pixel electrode. ing. The control device 26 generates, for example, a pulse signal (not shown) that generates a pulse in a 1V cycle, a 1H cycle clock signal CPV, and a 1H cycle latch signal LP by measuring time based on a dot clock signal. Further, the control device 26 uses the timing of the 1V cycle pulse of the pulse signal as a reference, the start / end of the effective scanning period _TEFF , or the start / end timing of the blanking period _TBLK , and the scanning line driving circuit 22u (and The output timing of the trigger signal to the scanning line driving circuit 22d) is set.

The scanning line driving circuit 22 u starts the operation of the shift register in response to a trigger signal from the control device 26. The output of each stage of the shift register is connected in turn to the first to n-th gate lines 32 and sequentially outputs scanning pulses to the gate lines 32 in synchronization with the clock signal CPV from the first stage. For example, the shift register raises the scanning pulse for a certain row in synchronization with the rising edge of the clock signal CPV, and lowers the scanning pulse in synchronization with the rising edge of the clock signal CPV after 1H. The video line drive circuit 24u is basically switched sequentially every 1H signal voltage _V 1 ~V _n corresponding to the pixel value _D 1 to D _n to be applied to the source line 30u in the effective scanning period _{T EFF.} For example, the switching of the signal voltages V _{1 to} V _n is performed in synchronization with the rising edge of the latch pulse LP from the control device 26.

As described above, the scanning waveform of the scanning pulse P _k to the scanning line driving circuit 22u is applied to the gate line 32 from the dull by capacitance and the wiring resistance associated with the gate line 32, until the period of the signal voltage V _k is not applied pulse It can happen that the fall of _Pk continues. In the present embodiment, for the α-th row (1 ≦ α ≦ n−1), which is a non-tail row, at the time t _k when the application of the signal voltage V _k ends, the falling of the scanning pulse P _k ends. It is before the time. However, for these non-tail rows, even after the application of the signal voltage V _k is completed, the period τ until the falling of the scanning pulse P _k is completed, and the signal voltage V _{k + 1} after one row is Continue to be applied.

On the other hand, for the last row, the time t _e when the application of the signal voltage V _n ends is after the time t _c when the effective scanning period T _EFF ends and the retrace period T _BLK starts. For example, the time t _e the application of the signal voltage V _n is completed, it is preferable that is later than the time (t c ₊ τ) to the fall of the scanning pulse P _n is ended, in this case, with respect to the end row Te is the effective scanning period even T _EFF is completed, the period to the falling ends of the scan pulse P _n tau, the signal voltage V _n is continuously applied. Thereby, the shortage of writing of the pixel voltage compared with other rows is eliminated or reduced, and deterioration in image quality due to unnecessary dark display of rows other than the edges of the screen can be prevented.

To delay the end of the application of the signal voltage V _{n corresponds} to applying a voltage that is substantially different from the reference voltage V _BLK to the source line 30 at the beginning of the vertical blanking period T _BLK . Here, considering that it is preferable to basically set the potential of the source line 30 in the vertical blanking period T _BLK to the reference voltage V _BLK corresponding to black as described above, the time t _te is excessive. to be rather slow, basically the time t _e can be set in accordance with the timing at which the fall of the scanning pulse P _n is ended (t c ₊ τ). In practice, the time t _c is set later than the timing of the fall of the scanning pulse P _n is ended (t c ₊ τ), for example, can be set to the time t _e after the 1H period from the time t _c.

3 after the application end of the signal voltage V _n, a block diagram schematically illustrating an example of a circuit configuration for applying a signal voltage V _n to the application start 1H period blanking period T _BLK. The one-line memory circuit 40 and the output data switching circuit 42 shown in FIG. 3 are provided in the control device 26, for example. The pixel data in the display area _Au is input in parallel to the one-line memory circuit 40 and the output data switching circuit 42 in the scanning order. The 1-line memory circuit 40 delays the input data by 1H period and outputs it to the output data switching circuit 42. Output data switching circuit 42, for the n-th row from the first row, and outputs the pixel data input directly to the video line drive circuit 24d, the effective scanning period T _EFF is time t _c to end one line The pixel data input from the memory circuit 40 is output to the video line driving circuit 24d. As a result, the signal voltage V _n is also applied to the application start 1H period of the blanking period _TBLK .

Figure 4 is a schematic block diagram showing an example of a circuit configuration to slow the application end of the signal voltage V _n IH period. The mask circuit 44 shown in FIG. 4 is provided in the control device 26, for example. Latch pulse LP for providing pixel data of the display area A _u, and the timing of generating a signal voltage corresponding to the pixel data is input to the video line drive circuit 24u. Mask circuit 44 is provided on a path of the latch pulse LP, to mask latch pulse LP rises at time t _c to an effective scanning period T _EFF is completed, the latch pulse LP is inputted to the video line driving circuit 24u Do not be. According to this, it is maintained without leaving the application of effective scanning period T _EFF the time t _c signal voltage V _n be turned to end, application end of the signal voltage V _n is delayed 1H period.

Here, also for the display area A _d of the lower trailing row of vertical scanning is located at the screen edge, similarly to the display region A _u of the upper described above, as the configuration and operation for compensating for the insufficient writing of the pixel voltage at the end row As a result, it is possible to prevent the line at the edge of the screen from being displayed darkly.

[Second Embodiment]
The schematic configuration of the liquid crystal display device according to the second embodiment is basically the same as the liquid crystal display device 10 of the above-described embodiment shown in FIG. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals to simplify the description. This embodiment is different from the first embodiment in the configuration and operation that compensates for insufficient writing of the pixel voltage of the last row in the vertical scanning of the horizontally divided display region. Here, the upper display area A _u is set as the specific display area, and vertical scanning with respect to the display area A _u is taken as an example to describe the pixel voltage writing operation for the last row in each effective scanning period _TEFF .

In the present embodiment, the video line driving circuit has a predetermined length at the beginning of the blanking period _TBLK after the application of the signal voltage in the effective scanning period _TEFF to at least a specific display area among the plurality of display areas. In the transition period, a voltage corresponding to a preset intermediate gradation pixel value is applied instead of the reference voltage V _BLK .

FIG. 5 is a signal waveform diagram for explaining the pixel voltage writing operation for the last row of the area A _u which is the specific display area, and schematically shows the signal waveforms of the signals VS _u and VG _n and the potential VP of the pixel electrode. ing.

In the present embodiment, the application end time t _c of the signal voltage V _n for the last row _(i.e., the time t _c to an effective scanning period T _{EFF ends)} transition period after are arranged. End time t _e of the transition period is preferable that is later than the time at which the fall of the scanning pulse P _n is ended (t c ₊ τ), for example, set to the time t _e after the 1H period from the time t _c Is done. At time t _c when the effective scanning period T _EFF ends, the control device 26 outputs pixel data of a predetermined intermediate gradation to the video line driving circuit 24d, and the video line driving circuit 24d outputs a voltage V _MID corresponding to the pixel data. Is applied to the source line 30 during a period from time t _c to t _e . The halftone pixel data can be set to, for example, half the number of gradations of the pixel data. Alternatively, an average value for a standard image may be obtained in advance through experiments or the like and set as pixel data of intermediate gradation.

In this configuration, the voltage V _MID expected to be closer to the signal voltage V _n than the reference potential V _BLK is applied to the pixel electrode at the falling edge of the scan pulse P _n . Thus, since the writing of the signal voltage V _n at the end row is assisted, insufficient writing of a signal voltage to the pixel electrode as compared to other rows is eliminated or reduced. Therefore, it is possible to prevent deterioration in image quality due to unnecessary dark display of lines other than the edges of the screen. In addition, the pixel data of the intermediate gradation in the transition period is fixed in each frame, thereby simplifying the circuit configuration.

In each of the above embodiments, the specific display area is the upper display area A _u and the lower display area _Ad is not the specific display area. Conversely, _Ad is the specific display area, and A _u specific configuration that does not display region (i.e., a _U performs vertical scanning toward the first row from the n-th row, a _D configuration for performing vertical scanning direction from the 2n row to the (n + 1) th row) to Ya , A _U and A _D are both specified display areas (that is, A _U performs vertical scanning from the first row to the n-th row, and _AD is directed from the second n-th row to the (n + 1) -th row. Even in a configuration in which vertical scanning is performed, a configuration / operation that compensates for insufficient writing of the pixel voltage in the last row can be achieved.

In each of the above-described embodiments, the screen is composed of an even number of pixel rows, and the display areas A _U and _AD are set by equally dividing the screen up and down, but the screen is composed of an odd number of pixel rows. The number of pixel rows constituting the upper and lower display areas may be different from each other. For example, on a screen composed of an odd number, one pixel row in the display areas A _U and A _D can be set one more than the other.

  Furthermore, the present invention can also be applied to horizontal division driving in which three or more display areas are provided.

In each of the above embodiments, the signals VS _U and VS _D are set to the reference voltage V _BLK corresponding to the pixel value representing black in the blanking period T _BLK of vertical scanning. The reference voltage V _WHT corresponding to the pixel value may be set. Also in this case, a problem that an unintended luminance change appears at the boundary between the display areas may occur, and therefore, the problem can be solved by applying the present invention.

  DESCRIPTION OF SYMBOLS 10 Liquid crystal display device, 20 Liquid crystal panel, 22u, 22d Scan line drive circuit, 24u, 24d Video line drive circuit, 26 Control apparatus, 30, 30u, 30d Source line, 32 Gate line, 40 1 line memory circuit, 42 Output data Switching circuit, 44 mask circuit.

Claims (4)

A video line provided corresponding to each column of pixels for each of a plurality of display areas obtained by horizontally dividing a screen composed of a plurality of pixels arranged in a matrix, and each display area corresponding to each row of pixels. A scanning line driving circuit that sequentially supplies a selection signal to a plurality of scanning lines provided to perform vertical scanning in parallel in the plurality of display areas, and a video line in advance during a retrace period of the vertical scanning. While applying a predetermined reference voltage, according to the pixel value via the video line to each pixel of the selected row supplied with the selection signal via the scan line during the effective scanning period of the vertical scan A video line driving circuit for applying a signal voltage, and a liquid crystal display device for driving the screen in a divided manner,
The scanning line driving circuit ends the vertical scanning in a predetermined specific display area of the display area in a pixel row adjacent to the other display area;
The video line driving circuit sets the first signal voltage applied at the application end timing of the effective scanning period and the second signal voltage applied at the application start timing of the blanking period to an equal voltage;
A liquid crystal display device. The liquid crystal display device according to claim 1.
And a mask circuit for controlling input of a latch pulse to the video line driving circuit,
The mask circuit applies an end timing of application of the signal voltage based on the timing of the selection signal in each selected row to at least the specific display region of the display region at the end of the effective scanning period. Setting the selected row at a timing later than the preceding selected row;
A liquid crystal display device. The liquid crystal display device according to claim 1.
And a memory circuit that outputs the input data with a delay of at least one horizontal scanning period,
The memory circuit applies the first signal voltage in the effective scanning period until application start timing in the blanking period;
A liquid crystal display device. A video line provided corresponding to each column of pixels for each of a plurality of display areas obtained by horizontally dividing a screen composed of a plurality of pixels arranged in a matrix, and each display area corresponding to each row of pixels. A scanning line driving circuit that sequentially supplies a selection signal to a plurality of scanning lines provided to perform vertical scanning in parallel in the plurality of display areas, and a video line in advance during a retrace period of the vertical scanning. While applying a predetermined reference voltage, according to the pixel value via the video line to each pixel of the selected row supplied with the selection signal via the scan line during the effective scanning period of the vertical scan A video line driving circuit for applying a signal voltage, and a liquid crystal display device for driving the screen in a divided manner,
The scanning line driving circuit ends the vertical scanning in a predetermined specific display area of the display area in a pixel row adjacent to the other display area;
The video line driving circuit, for at least the specific display area of the display area, in a transition period of a predetermined length at the beginning of the blanking period after the application of the signal voltage in the effective scanning period, Applying a voltage corresponding to the pixel value of a preset intermediate gradation instead of the reference voltage;
A liquid crystal display device.

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