JP2009116122A - Display drive circuit, display device, and display drive method - Google Patents

Abstract

In driving for changing a CS line after a gate scan, occurrence of a horizontal stripe in a first frame where display of a video signal is started is eliminated.
A gate line driving circuit that outputs a gate signal for turning on a switching element of a row in a horizontal scanning period sequentially assigned to each row, and a polarity is inverted in synchronization with the horizontal scanning period of each row, A source bus line driving circuit that outputs a source signal whose polarity is reversed in adjacent horizontal scanning periods of the same row, and is determined according to the polarity of the source signal in the horizontal scanning period after the horizontal scanning period of each row CS bus line driving circuit that outputs a CS signal whose potential switches in the direction (low → high or high → low), and a source so that the CS bus line driving circuit starts operation in the 0th frame before the first frame. And a control circuit for controlling the bus line driving circuit and the CS bus line driving circuit.
[Selection] Figure 3

Description

  The present invention relates to a scanning signal line, a switching element that is turned on / off by the scanning signal line, a pixel electrode connected to one end of the switching element, and the pixel electrode, such as an active matrix liquid crystal display panel. A display drive circuit for driving a display panel including a plurality of rows including a capacitively coupled capacitively coupled wiring and a data signal line connected to the other end of the switching element of each row; The present invention relates to a display driving method.

  Conventionally, in an active matrix liquid crystal display device, a driving method called “CC (Charge Coupling) driving” has been adopted. This CC drive is disclosed in Patent Documents 1 and 2, for example. Taking the disclosed contents of Patent Document 1 as an example, CC drive will be described as follows.

  The configuration of the device for realizing the CC drive is shown in the equivalent circuit of FIG. 6, and the operation waveforms of various signals in the CC drive are shown in the timing chart of FIG.

  As shown in the equivalent circuit of FIG. 6, a liquid crystal display device that performs CC driving includes a plurality of source lines (signal lines) 101, a plurality of gate lines (scanning lines) 102 orthogonal to the source lines 101, and these Switching element 103 provided in the vicinity of the intersection, pixel electrode 104 connected to switching element 103, and a plurality of CS (Cpacity Storage) bus lines (common electrode lines) that are paired with and parallel to gate line 102 105, a storage capacitor 106 having one end connected to the pixel electrode 104 and the other end connected to the CS bus line 105, and a counter electrode 109 facing each other via a liquid crystal 107 are provided in the image display unit 110.

  The switching element 103 is formed of amorphous silicon (a-Si), polycrystalline polysilicon (p-Si), single crystal silicon (c-Si), etc., and a capacitor 108 is formed between the gate and the drain due to its structure. Is done. The capacitor 108 causes a phenomenon that the gate pulse from the gate line 102 shifts the potential of the pixel electrode 104 to the negative side.

  In addition, the liquid crystal display device includes a source line driving circuit 111 for driving the source line 101, a gate line driving circuit 112 for driving the gate line 102, and a CS bus line driving circuit 113 for driving the CS bus line 105. 110 is provided outside.

  The operation waveforms of various signals in this liquid crystal display device are as shown in FIG. That is, the waveform Wg of a certain gate line 102 becomes Von only in the H period (horizontal scanning period) in which the gate line 102 is selected, and is held at Voff in other periods. Although the amplitude of the waveform Ws of the source line 101 varies depending on the video signal to be displayed, the polarity is inverted every H period and the polarity is inverted in the adjacent H period related to the same gate line 102 (line Reverse drive). In FIG. 7, since it is assumed that a uniform video signal is input, the amplitude of the waveform Ws is constant.

  The waveform Wd of the pixel electrode 104 is the same potential as the waveform Ws of the source line 101 during the period in which Wg is Von, so that the waveform Wd is slightly through the gate-drain capacitance 108 at the moment when Wg becomes Voff. Shift to the negative side.

  The waveform Wc of the CS bus line 105 is Ve + in the H period in which the corresponding gate line 102 is selected and the next H period, and further switches to Ve− in the next H period, and then Ve− until the next field. Hold. By this switching, the waveform Wd of the pixel electrode 104 is shifted to the negative side via the storage capacitor 106.

As a result, the waveform Wd of the pixel electrode 104 obtains an amplitude larger than the amplitude of the waveform Ws of the source line 101, so that the amplitude of the waveform Ws of the source line 101 can be further reduced. Thereby, the circuit configuration in the source line driver circuit 111 can be simplified and the power consumption can be reduced.
JP 2001-83943 A (publication date March 30, 2001) Japanese Patent Laid-Open No. 2-157815 (Publication Date: June 18, 1990)

  In the CC drive described above, in the first frame after the display is started, one line (one horizontal line of the display device) is generated because the relationship between the operation waveforms of various signals is different between the display start time and the normal display time. ) Lightness and darkness occur every time. The reason for this will be described with reference to the timing chart of FIG.

  In FIG. 8, Vsync is a vertical synchronization signal that defines the timing of vertical scanning, and Hsync is a horizontal synchronization signal that defines the timing of horizontal scanning. A period from the fall of Vsync to the next fall is one vertical scanning period (1V period), and a period from the fall of Hsync to the next fall is one horizontal scanning period (1H period).

  In FIG. 8, the source signal S, the gate line driving circuit, and the CS bus line driving circuit supplied from the source line driving circuit to a certain source line (the source line provided in the x-th column) are transferred to the first row. The gate signal G1 and the CS signal CS1, which are respectively supplied to the provided gate line and the CS bus line, and the potential waveform Pix1 of the pixel electrode provided in the first row and the x-th column are illustrated in this order, and the second row The gate signal G2 and the CS signal CS2 respectively supplied to the gate line and the CS bus line, and the potential waveform Pix2 of the pixel electrode provided in the second row and the xth column are illustrated in this order. The two-dot chain line in the potential waveforms Pix1 and Pix2 indicates the potential of the counter electrode.

  In the timing chart of FIG. 8, after the liquid crystal display device starts to operate, for example, when the liquid crystal display device is turned on, a display frame corresponding to a video to be displayed (hereinafter referred to as “video display”) is started. There is a 0th frame in which video display is not performed immediately before the first frame. In the 0th frame, all of the source line driving circuit, the gate line driving circuit, and the CS bus line driving circuit are in a preparation stage or a stop state before entering the normal operation. Therefore, the source signal S is a random signal or HiZ (high impedance), the gate signals G1 and G2 are fixed to a gate-off potential (potential for turning off the gate of the switching element), and the CS signals CS1 and CS2 are set to one potential (for example, Vss). .) Is fixed.

  In the first frame following the 0th frame, the source line driving circuit, the gate line driving circuit, and the CS bus line driving circuit all perform normal operations.

  As a result, the source signal S has an amplitude corresponding to the gradation indicated by the video signal, and becomes a signal whose polarity is inverted every 1H period. In FIG. 8, since it is assumed that a uniform video is displayed, the amplitude of the source signal S is constant. Further, the gate signals G1 and G2 become a gate-on potential (potential for turning on the gate of the switching element) in the first and second 1H periods in the active period (effective scanning period) of each frame, and in other periods. Gate off potential.

  The CS signals CS1 and CS2 are inverted in synchronism with the falling edges of the corresponding gate signals G1 and G2, and have waveforms that are opposite to each other. That is, in the odd frame, the CS signal CS1 falls in synchronization with the fall of the corresponding gate signal G1, the CS signal CS2 rises in synchronization with the fall of the corresponding gate signal G2, and in the even frame, The CS signal CS1 rises in synchronization with the fall of the corresponding gate signal G1, and the CS signal CS2 falls in synchronization with the fall of the corresponding gate signal G2 (in the above description, the odd frame and It may be the opposite of even frames).

  However, the first frame has an irregular waveform because the CS signals CS1 and CS2 are both fixed at one potential in the immediately preceding 0th frame. That is, the CS signal CS2 is the same as the other odd frames in that it rises in synchronization with the fall of the corresponding gate signal G2, but the CS signal CS1 is the same before and after the fall of the corresponding gate signal G1. It differs from the other odd frames in that it holds the potential.

  This irregular waveform is the cause of the horizontal stripes at the start of display. That is, in the pixel electrode in the second row in the first frame, since the potential change of the CS signal CS2 occurs normally, the potential waveform Pix2 is subjected to a potential shift caused by the potential change of the CS signal CS2, whereas Since the potential change of the CS signal CS1 does not occur in one row of pixel electrodes, the potential waveform Pix1 does not undergo a potential shift. As a result, the potential waveforms Pix1 and Pix2 are different from each other even though the source signal S of the same gradation is input, and a luminance difference is generated between the first row and the second row. This brightness difference appears as a brightness difference between the odd and even lines in the entire image display unit. For this reason, horizontal stripes consisting of light and dark for each row are generated in the video of the first frame.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display drive circuit and a display drive method that can improve the display quality by eliminating the occurrence of the horizontal stripes described above. It is in.

  The display driving circuit according to the present invention includes a scanning signal line, a switching element that is turned on / off by the scanning signal line, a pixel electrode that is connected to one end of the switching element, and a capacitor that is capacitively coupled to the pixel electrode. A plurality of rows each including a coupling wiring and a display panel including a data signal line connected to the other end of the switching element of each row to drive a grayscale according to the potential of the pixel electrode A display driving circuit for performing display, and in order to solve the above-mentioned problem, a scanning signal line for outputting a scanning signal for turning on a switching element of the row in a horizontal scanning period sequentially assigned to each row The drive circuit and a data signal for outputting a data signal whose polarity is inverted in synchronization with the horizontal scanning period of each row and whose polarity is reversed in the adjacent horizontal scanning period of the same row. Capacitive coupling that outputs a potential shift signal in which the potential is switched between binary potentials in a direction determined according to the polarity of the data signal in the horizontal scanning period after the horizontal scanning period of each row. The wiring line driving circuit and the signal line so that the capacitive coupling wiring line driving circuit starts its operation in the 0th vertical scanning period before the first vertical scanning period in which the output of the data signal corresponding to the video to be displayed is started. And a control circuit for controlling the drive circuit and the capacitive coupling wiring drive circuit.

  The display panel driven by the display driving circuit has the configuration as described above. A typical arrangement thereof is, for example, a large number of pixel electrodes arranged in a matrix, and scanning signal lines and switching along each row. Elements and capacitive coupling wires are arranged, and data signal lines are arranged along each column. In this typical arrangement, “rows” and “columns” are often arranged in the horizontal and vertical directions of the display panel, respectively, but this is not necessarily the case and the vertical / horizontal relationship is reversed. It may be. Therefore, the “row” in the present invention does not particularly limit the direction.

  The display driving circuit for driving the display panel turns on a switching element of the row in a horizontal scanning period sequentially assigned to each row by a scanning signal, and for a pixel electrode connected to the turned on switching element, A potential corresponding to a data signal is written in such a manner that the polarity is inverted in synchronization with the horizontal scanning period of each row and the polarity is inverted in the adjacent horizontal scanning period of the same row. Thereby, so-called line inversion driving is realized.

  In addition, the display driving circuit shifts the potential of the pixel electrode capacitively coupled to the capacitive coupling wiring by the potential shift signal. This potential shift signal switches the potential between binary potentials after the horizontal scanning period of each row, and the switching direction (from low level to high level or from high level to low level) is the horizontal direction of each row. The direction is determined according to the polarity of the data signal in the scanning period. Thereby, so-called CC drive is realized.

  In the case of CC driving based on such line inversion driving, normally, as described in the column “Problems to be Solved by the Invention” above, the first vertical operation for starting output of a data signal corresponding to a video to be displayed is performed. In the scanning period (first frame), horizontal stripes consisting of light and dark for each row (one line) are generated. As described in detail in the same column, the potential shift signals (CS signals CS1 and CS2) are irregular in the first vertical scanning period, which is different from the normal vertical scanning period after the first vertical scanning period. This is because it has a waveform.

  Therefore, in the display driving circuit, the control circuit controls the capacitive coupling wiring driving circuit to start operation in the 0th vertical scanning period before the first vertical scanning period. As a result, the irregular waveform that causes horizontal stripes in the first vertical scanning period can be eliminated, and the display quality can be improved by preventing the occurrence of horizontal stripes in the first vertical scanning period. Can do.

  The 0th vertical scanning period may be a vertical scanning period before the first vertical scanning period, and is not necessarily a vertical scanning period immediately before the first vertical scanning period, and the 0th vertical scanning period. The scanning period is not necessarily one vertical scanning period.

  In the display driving circuit according to the present invention, in the display driving circuit, the control circuit outputs a scanning signal for turning on the switching elements in each row in the entire horizontal scanning period in the zeroth vertical scanning period. It is desirable to control the scanning signal line driver circuit and the data signal line driver circuit so as to output a data signal for displaying gradation.

  In the above configuration, all the pixels are displayed in the 0th vertical scanning period by turning on the switching elements in each row in the entire horizontal scanning period in the 0th vertical scanning period and outputting a data signal for displaying a predetermined gradation. The predetermined gradation can be obtained. Therefore, the occurrence of horizontal stripes can be eliminated not only in the first vertical scanning period but also in the 0th vertical scanning period, and display quality can be further improved.

  In the display driving circuit according to the present invention, in the display driving circuit, the predetermined gradation is preferably a gradation that is the same as or approximate to a display gradation in an initial state of the pixel electrode.

  In the above configuration, the predetermined gradation is the display gradation in the initial state of the pixel electrode, that is, black display gradation (0 gradation) in the case of normally black, and white display gradation in the case of normally white. (63 gradations (in the case of 6-bit gray scale)), or gradations close to these. Therefore, it is possible to avoid an unnecessary change in display gradation from the start of the operation of the display drive circuit to the 0th vertical scanning period. Note that the approximate gradation means that the gradation difference is within 8 gradations. Therefore, it is desirable that the predetermined gradation is 0 to 8 gradations for normally black, and 55 to 63 gradations (for 6-bit gray scale) for normally white.

  A display device according to the present invention includes any one of the display drive circuits described above and the display panel.

  With the above configuration, a display device with good display quality can be provided by the effect of preventing the occurrence of horizontal stripes by the display drive circuit.

  A display driving method according to the present invention includes a scanning signal line, a switching element turned on / off by the scanning signal line, a pixel electrode connected to one end of the switching element, and a capacitor capacitively coupled to the pixel electrode. A plurality of rows each including a coupling wiring and a display panel including a data signal line connected to the other end of the switching element of each row to drive a grayscale according to the potential of the pixel electrode A display driving method for performing display, and in order to solve the above-described problem, a scanning signal line for outputting a scanning signal for turning on a switching element of a row in a horizontal scanning period sequentially assigned to each row A data signal that outputs a data signal such that the polarity is inverted in synchronization with the driving process and the horizontal scanning period of each row while the polarity is inverted in the adjacent horizontal scanning period of the same row. Capacitive coupling that outputs a potential shift signal in which the potential is switched between binary potentials in a direction determined according to the polarity of the data signal in the horizontal scanning period after the horizontal scanning period of each row in the signal line driving process The capacitive coupling wiring driving process in a zeroth vertical scanning period before a first vertical scanning period in which output of a data signal corresponding to a video to be displayed in the data signal line driving process is started. It is characterized by starting.

  In the above method, similarly to the effect described with respect to the display driving circuit, it is possible to prevent the occurrence of horizontal stripes in the first vertical scanning period and improve the display quality.

  As described above, the display driving circuit and the display driving method according to the present invention provide capacitive coupling wiring in the 0th vertical scanning period before the first vertical scanning period in which the output of the data signal corresponding to the video to be displayed is started. Is started.

  In the configuration and method described above, one row (in the first vertical scanning period (first frame) in which the output of the data signal corresponding to the video to be displayed described in the column “Problems to be solved by the invention” is started ( It is possible to eliminate the occurrence of horizontal streaks composed of light and dark for each line) and to improve the display quality.

  An embodiment of the present invention will be described below with reference to FIGS.

  First, the configuration of the liquid crystal display device 1 corresponding to the display device of the present invention will be described with reference to FIGS. 1 is a block diagram showing the overall configuration of the liquid crystal display device 1, and FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the pixels of the liquid crystal display device 1.

  The liquid crystal display device 1 includes an active matrix type liquid crystal display panel 10 corresponding to a display panel, a data signal line driving circuit, a scanning signal line driving circuit, a capacitive coupling wiring driving circuit, and a control circuit of the present invention, and a source bus line driving. A circuit 20, a gate line driving circuit 30, a CS bus line driving circuit 40, and a control circuit 50 are provided.

  The liquid crystal display panel 10 is configured by sandwiching liquid crystal between an active matrix substrate (not shown) and a counter substrate, and has a large number of pixels P arranged in a matrix.

  The liquid crystal display panel 10 is formed on an active matrix substrate on a source bus line 11, a gate line 12, a thin film transistor (corresponding to a data signal line, a scanning signal line, a switching element, a pixel electrode, and a capacitive coupling wiring of the present invention, respectively. A thin film transistor (hereinafter referred to as “TFT”) 13, a pixel electrode 14, and a CS bus line 15, and a counter electrode 19 on a counter substrate. The TFT 13 is shown only in FIG. 2 and is omitted in FIG.

  One source bus line 11 is formed in each column so as to be parallel to each other in the column direction (vertical direction), and one gate line 12 is provided in each row so as to be parallel to each other in the row direction (lateral direction). Each book is formed. The TFT 13 and the pixel electrode 14 are formed corresponding to the intersections of the source bus line 11 and the gate line 12, respectively. The source electrode s of the TFT 13 is the source bus line 11, the gate electrode g is the gate line 12. Drain electrodes d are connected to the pixel electrodes 14 respectively. In addition, a liquid crystal capacitor 17 is formed between the pixel electrode 14 and the counter electrode 19 via a liquid crystal.

  Thereby, the gate of the TFT 13 is turned on by the gate signal (scanning signal) supplied to the gate line 12, the source signal (data signal) from the source bus line 11 is written to the pixel electrode 14, and the pixel electrode 14 is written to the source signal. By setting a potential according to the above and applying a voltage according to the source signal to the liquid crystal interposed between the counter electrode 19, gradation display according to the source signal can be realized.

  One CS bus line 15 is formed in each row so as to be parallel to each other in the row direction (lateral direction), and is arranged to make a pair with the gate line 12. Each CS bus line 15 is capacitively coupled to the pixel electrode 14 disposed in each row, and forms a storage capacitor (also referred to as “auxiliary capacitor”) 16 with each pixel electrode 14.

  Note that, due to the structure of the TFT 13, a pull-in capacitor 18 is formed between the gate electrode g and the drain electrode d, so that the potential of the pixel electrode 14 is influenced by the potential change (pull-in) of the gate line 12. However, for the sake of simplification of explanation, the above influence is not considered.

  The liquid crystal display panel 10 having the above configuration is driven by a source bus line driving circuit 20, a gate line driving circuit 30, a CS bus line driving circuit 40, and a control circuit 50 for controlling them. Each of the above circuits corresponds to a display driving circuit of the present invention.

  In the present embodiment, in the active period (effective scanning period) in the vertical scanning period that is periodically repeated, the horizontal scanning period of each row is sequentially assigned, and each row is sequentially scanned.

  For this purpose, the gate line driving circuit 30 sequentially outputs a gate signal for turning on the TFT 13 to the gate line 12 of the row in synchronization with the horizontal scanning period of each row.

  Further, the source bus line driving circuit 20 outputs a source signal to each source bus line 11. The source signal is a signal obtained by assigning a video signal supplied from the outside of the liquid crystal display device 1 to the source bus line driving circuit 20 via the control circuit 50 to each column in the source bus line driving circuit 20 and performing boosting or the like. It is. The source bus line driving circuit 20 reverses the polarity of the output source signal in synchronization with the horizontal scanning period of each row and reverses it in the adjacent horizontal scanning period of the same row in order to perform so-called line inversion driving. Like to do. For example, the polarity of the source signal is inverted between the horizontal scanning period of the first row and the horizontal scanning period of the second row, and the horizontal scanning period of the first row in the first frame and in the second frame The polarity of the source signal is reversed between the horizontal scanning period of the first row (see FIG. 3 described later).

  The CS bus line driving circuit 40 outputs a CS signal corresponding to the potential shift signal of the present invention to each CS bus line 15. In this CS signal, the potential is switched between two values (rises or falls), and in synchronization with the end of the horizontal scanning period of each row, that is, the TFT 13 of each row is switched from on to off. At the time, the potential of the CS bus line 15 in the row is switched from one value to the other value. Note that this switching timing may be after the horizontal scanning period of each row, and there may be a time lag with respect to the end of the horizontal scanning period of each row. As a result, the CS bus line driving circuit 40 shifts the potential of the pixel electrode 14 at a time after the horizontal scanning period.

  Here, as in the first frame of FIG. 8 described in the “Problems to be Solved by the Invention” column, the pixel electrode 14 to which the negative polarity source signal is written is not subjected to a potential shift, and the positive polarity source signal. Is subjected to a potential shift, the potential difference between the counter electrode potential and the shifted pixel electrode 14 is positive even though the source signal S of the same gradation is input. It differs from the negative polarity.

  In order to solve this problem, the liquid crystal display device 1 performs the control described below by the control circuit 50.

  The control circuit 50 controls the gate line drive circuit 30, the source bus line drive circuit 20, and the CS bus line drive circuit 40 described above to output the signals shown in FIG. 3 from these circuits.

  In FIG. 3, Vsync is a vertical synchronization signal that defines the timing of vertical scanning, and Hsync is a horizontal synchronization signal that defines the timing of horizontal scanning, as in FIG. 8 described in the column “Problems to be Solved by the Invention”. A period from the fall of Vsync to the next fall is one vertical scanning period (1V period), and a period from the fall of Hsync to the next fall is one horizontal scanning period (1H period).

  In FIG. 3, the source signal S, the gate line driving circuit 30 and the CS bus line driving supplied from the source bus line driving circuit 20 to the source bus line 11 (the source bus line 11 provided in the x-th column). The gate signal G1 and the CS signal CS1, which are supplied from the circuit 40 to the gate line 12 and the CS bus line 15 provided in the first row, respectively, and the potential waveform Pix1 of the pixel electrode 14 provided in the first row and the x-th column, respectively. Further, the gate signal G2 and the CS signal CS2 supplied to the gate line 12 and the CS bus line 15 provided in the second row, respectively, and the pixel electrode 14 provided in the second row and the xth column are illustrated in this order. The potential waveform Pix2 is illustrated in this order. A two-dot chain line in the potential waveforms Pix1 and Pix2 indicates the potential of the counter electrode 19.

  In the timing chart of FIG. 3, after the liquid crystal display device 1 starts to operate, for example, when the liquid crystal display device 1 is turned on, a display corresponding to a video to be displayed (hereinafter referred to as “video display”). Immediately before the first frame which is the start frame, there is a 0th frame in which no video display is performed.

  In the 0th frame, unlike the case of FIG. 8, the CS bus line driving circuit 40 has already started a normal operation. That is, in the case of FIG. 8, the CS signals CS1 and CS2 are both fixed at one potential (for example, Vss), but in the case of FIG. 3, the CS signal CS1 is the end of the horizontal scanning period of the first row. Synchronize with time to switch from low level to high level. In the 0th frame, the CS signal CS2 should be switched from a high level to a low level in synchronization with the end of the horizontal scanning period of the second row in terms of the regularity of the waveform. However, the CS bus line driving circuit Since 40 outputs a low level as the CS signal CS2 when starting a normal operation, the low level is maintained as it is in the 0th frame.

  In the first frame following the 0th frame, the source bus line driving circuit 20 and the gate line driving circuit 30 start normal operations.

  As a result, the source signal S has an amplitude corresponding to the gradation indicated by the video signal, and becomes a signal whose polarity is inverted every 1H period. In FIG. 3, since it is assumed that a uniform video is displayed, the amplitude of the source signal S is constant. In addition, the gate signals G1 and G2 become a gate-on potential in the first and second 1H periods in the active period (effective scanning period) of each frame, and become a gate-off potential in other periods.

  The CS signals CS1 and CS2 are inverted in synchronism with the falling edges of the corresponding gate signals G1 and G2, and have waveforms that are opposite to each other. That is, in the odd frame, the CS signal CS1 falls in synchronization with the fall of the corresponding gate signal G1, the CS signal CS2 rises in synchronization with the fall of the corresponding gate signal G2, and in the even frame, The CS signal CS1 rises in synchronization with the fall of the corresponding gate signal G1, and the CS signal CS2 falls in synchronization with the fall of the corresponding gate signal G2 (in the above description, the odd frame and It may be the opposite of even frames).

  In the timing chart of FIG. 3, since the CS bus line driving circuit 40 starts operating in the 0th frame, the CS signals CS1 and CS2 in the first frame have the same waveform as in a normal odd frame. Therefore, since the potential waveforms Pix1 and Pix2 of the pixel electrode 14 are both appropriately shifted by the CS signals CS1 and CS2, when the source signal S of the same gradation is input, the counter electrode potential and the post-shift potential are changed. The potential difference from the potential of the pixel electrode 14 is the same between positive polarity and negative polarity. As a result, it is possible to eliminate the occurrence of horizontal stripes in the first frame and improve the display quality.

  As described above, by starting the operation of the CS bus line driving circuit 40 in the 0th frame, it is possible to eliminate the occurrence of horizontal stripes in the first frame. However, in this case, the horizontal stripes may occur in the 0th frame. There is.

  In order to eliminate the occurrence of horizontal stripes in the 0th frame, in the timing chart of FIG. 3, in the active period of the 0th frame, the gate signals G1 and G2 of the gate lines 12 in the first and second rows (others) The same applies to the gate signal of the gate line 12.) is fixed at the gate-on potential, and the source signal S of the source bus line 11 in the x-th column (the same applies to the source signals of the other source bus lines 11). It is fixed at a potential corresponding to the tone T and having either positive or negative polarity. Note that the polarity of the source signal S is not necessarily fixed. However, when the polarity of the source signal S is reversed, the smaller the amplitude difference between the positive electrode and the negative electrode is, the smaller the brightness of the horizontal stripe is.

  Thereby, the display gradation of all the pixels P in the 0th frame can be unified to the gradation T, and the occurrence of horizontal stripes in the 0th frame can also be eliminated.

  Furthermore, the gradation T is desirably set to the same gradation as the display gradation in the initial state of the liquid crystal display panel 10. The display gradation in the initial state is the black display gradation (0 gradation) when the liquid crystal display panel 10 is normally black, and the white display gradation (63 gradations (6-bit gray scale) when normally white. Means)). Thereby, it is possible to avoid an unnecessary change in the display gradation immediately after the start of the liquid crystal display device 1 until the end of the 0th frame. Note that the gradation T is not necessarily the same gradation as the display gradation in the initial state, and may be any gradation that approximates the display gradation in the initial state. The approximate gradation means that the gradation difference is within 8 gradations. If the gradation difference is within 8 gradations, it is generally not noticed visually. Therefore, the gradation T may be 0 to 8 gradations for normally black, and 55 to 63 gradations (for 6-bit gray scale) for normally white.

  Note that the 0th frame that is in the above-described operation state may be a frame before the first frame that is the start frame of the video display, and does not necessarily need to be a frame immediately before the first frame. The vertical scanning period is not necessarily one vertical scanning period.

  In order to realize the above-described control, the control circuit 50 includes a circuit 50 'shown in FIG. The input / output signals of this circuit 50 'and the operation states of the source bus line driving circuit 20, the gate line driving circuit 30 and the CS bus line driving circuit 40 are shown in the timing chart of FIG. In FIG. 5, the blanking period is not shown for the sake of simplicity.

  The circuit 50 'includes one NOT circuit 51, two D-type flip-flop circuits 52a and 52b, four AND circuits 53a to 53d, and two XOR (exclusive OR) circuits 55a and 55b. ing.

  Input signals to the circuit 50 ′ are a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a source activation signal SIG_SEL, a CS activation signal CS_SEL, and a line number selection signal LINE_T.

  The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are input to the control circuit 50 from the outside of the liquid crystal display device 1 together with the video signal.

  The CS activation signal CS_SEL is a signal that defines the operation start timing of the CS bus line driving circuit 40 by the rising from the low level to the high level. The source activation signal SIG_SEL is a signal that defines the start of inversion of the source output polarity by the rising from the low level to the high level. As shown in FIG. 5, the source activation signal SIG_SEL rises from a low level to a high level at the start of the active period of the first frame, and the CS activation signal CS_SEL rises from a low level to a high level at the start of the active period of the 0th frame. These source activation signal SIG_SEL and CS activation signal CS_SEL are generated outside the circuit 50 ′ in the control circuit 50.

  The line number selection signal LINE_T is a signal that determines whether the LINE total number in the vertical blanking period is an odd number or an even number, and whether it is a high level or a low level, and has a constant value regardless of the frame and the line.

  The output signals from the circuit 50 'are an all gate on signal G_ALL_ON, source control SIG_CONT, and CS control CS_CONT.

  The all gate-on signal G_ALL_ON is a signal supplied to the gate line driving circuit 30 and is a high level during the active period of the 0th frame and a low level during other periods. In the gate line driving circuit 30, the gate signals of all the gate lines 12 are fixed to the gate-on potential while the all-gate-on signal G_ALL_ON is at the high level. Thereby, the TFTs 13 of all the pixels P can be turned on in the active period of the 0th frame.

  The source control SIG_CONT is a signal supplied to the source bus line driving circuit 20, and the polarity of the source signal is inverted based on the source control SIG_CONT. For example, when the source control SIG_CONT is at a low level, the polarity of the source signal is positive, and when the source control SIG_CONT is at a high level, the polarity of the source signal is negative. Thus, line inversion driving can be realized, and the polarity of the source signal can be fixed in the active period of the 0th frame.

  The CS control CS_CONT is a signal supplied to the CS bus line drive circuit 40. The CS bus line drive circuit 40 sequentially raises / lowers the CS signal in the CS bus line 15 of each row based on the CS control CS_CONT. Do. For example, on the CS bus line 15 in the first row, the CS signal rises / falls in synchronization with the fall / rise of the CS control CS_CONT. As a result, CC driving can be realized, and the source bus line driving circuit 20 can be normally operated in the active period of the 0th frame.

  The connection relationship of each circuit of the circuit 50 ′ is as shown in FIG. 4, and this will be described in detail as follows.

  The source activation signal SIG_SEL is input to the input of the NOT circuit 51, and the output, that is, the inverted source activation signal SIG_SEL is connected to one input of the AND circuit 53a. The CS activation signal CS_SEL is input to the other input of the AND circuit 53a. The output of the AND circuit 53a is the all gate on signal G_ALL_ON.

  The horizontal synchronization signal Hsync is input to the clock input of the D-type flip-flop circuit 52a, and the inverted output / Q of the D-type flip-flop circuit 52a is fed back to the input D of the D-type flip-flop circuit 52a. The output Q of the D-type flip-flop circuit 52a is connected to one input of each of the AND circuits 53b and 53c.

  The vertical synchronization signal Vsync is input to the clock input of the D-type flip-flop circuit 52b, and the inverted output / Q of the D-type flip-flop circuit 52a is fed back to the input D of the D-type flip-flop circuit 52a. The output Q of the D-type flip-flop circuit 52a is connected to one input of the AND circuit 53d.

  A source activation signal SIG_SEL, a CS activation signal CS_SEL, and a line number selection signal LINE_T are input to the other inputs of the AND circuits 53b, 53c, and 53d, respectively.

  The XOR circuit 55a outputs the source control SIG_CONT when the outputs of the AND circuits 53b and 53d are input. Further, the XOR circuit 55b outputs the CS control CS_CONT when the outputs of the AND circuits 53c and 53d are input.

  As described above, in the display drive circuit of the liquid crystal display device 1, the gate line drive circuit 30 outputs the gate signal for turning on the TFT 13 in the row during the horizontal scanning period sequentially assigned to each row, and the source bus line. The drive circuit 20 outputs a source signal whose polarity is inverted in synchronization with the horizontal scanning period of each row and whose polarity is reversed in the adjacent horizontal scanning period of the same row, and the CS bus line driving circuit 40 outputs each source signal. After the horizontal scanning period, a CS signal whose potential is switched between binary potentials in a direction determined according to the polarity of the source signal in the horizontal scanning period is output. Then, the control circuit 50 sets the source bus line driving circuit 20 and the CS bus line driving circuit 40 so that the CS bus line driving circuit 40 starts operation in the 0th frame before the first frame in which the video display is started. Control.

  Thereby, the potential shift of the pixel electrode 14 by the CS signal can be appropriately executed in the first frame in the drive for changing the CS line after the gate scan, and the occurrence of horizontal stripes in the first frame can be eliminated. As a result, the display quality of the liquid crystal display device 1 can be improved.

  The present invention can be particularly preferably applied to driving an active matrix liquid crystal display device.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on one Embodiment of this invention. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of each pixel in the liquid crystal display device of FIG. 1. 2 is a timing chart showing waveforms of various signals in the liquid crystal display device of FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a circuit included in a control circuit of the liquid crystal display device of FIG. 1. 2 is a timing chart showing waveforms of various signals inputted to and outputted from a control circuit of the liquid crystal display device of FIG. It is a block diagram which shows the structure of the conventional liquid crystal display device which performs CC drive. It is a timing chart which shows the waveform of various signals in the conventional CC drive. It is a timing chart which shows the comparative example of the waveform of various signals in a liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Liquid crystal display panel (display panel)
11 Source bus line (data signal line)
12 Gate line (scanning signal line)
13 TFT (switching element)
14 Pixel electrode 15 CS bus line (capacitive coupling wiring)
20 Source bus line drive circuit (data signal line drive circuit)
30 Gate line driving circuit (scanning signal line driving circuit)
40 CS bus line drive circuit (capacitive coupling wiring drive circuit)
50 Control circuit (control circuit)

Claims (5)

A scanning signal line, a switching element that is turned on / off by the scanning signal line, a pixel electrode that is connected to one end of the switching element, and a capacitive coupling wiring that is capacitively coupled to the pixel electrode A display driving circuit for driving a display panel having a plurality of rows and having a data signal line connected to the other end of the switching element of each row, and causing gradation display according to the potential of the pixel electrode In
A scanning signal line driving circuit for outputting a scanning signal for turning on the switching element of the row in a horizontal scanning period sequentially assigned to each row;
A data signal line driving circuit that outputs a data signal whose polarity is inverted in the adjacent horizontal scanning period of the same row while the polarity is inverted in synchronization with the horizontal scanning period of each row;
A capacitively coupled wiring driving circuit that outputs a potential shift signal for switching the potential between binary potentials in a direction determined according to the polarity of the data signal in the horizontal scanning period after the horizontal scanning period of each row;
The signal line driving circuit and the capacitive coupling so that the capacitive coupling wiring driving circuit starts to operate in the 0th vertical scanning period before the first vertical scanning period in which the output of the data signal corresponding to the video to be displayed is started. A display drive circuit comprising a control circuit for controlling the wiring drive circuit.   The control circuit outputs a data signal for displaying a predetermined gradation while outputting a scanning signal for turning on the switching elements in each row in the entire horizontal scanning period in the zeroth vertical scanning period. 2. The display driving circuit according to claim 1, wherein the display driving circuit controls a line driving circuit and a data signal line driving circuit.   The display driving circuit according to claim 2, wherein the predetermined gradation is the same or close to a display gradation in an initial state of the pixel electrode.   A display device comprising: the display drive circuit according to claim 1; and the display panel. A scanning signal line, a switching element that is turned on / off by the scanning signal line, a pixel electrode that is connected to one end of the switching element, and a capacitive coupling wiring that is capacitively coupled to the pixel electrode A display driving method for driving a display panel having a plurality of rows and having a data signal line connected to the other end of the switching element of each row to perform gradation display according to the potential of the pixel electrode In
A scanning signal line driving process for outputting a scanning signal for turning on a switching element of the row in a horizontal scanning period sequentially assigned to each row;
A data signal line driving process for outputting a data signal whose polarity is reversed in the adjacent horizontal scanning period of the same row while the polarity is reversed in synchronization with the horizontal scanning period of each row;
And a capacitively coupled wiring driving process for outputting a potential shift signal for switching the potential between binary potentials in a direction determined according to the polarity of the data signal in the horizontal scanning period after the horizontal scanning period of each row. ,
The capacitive coupling wiring driving process is started in a 0th vertical scanning period before a first vertical scanning period in which output of a data signal corresponding to a video to be displayed in the data signal line driving process is started. Display driving method.

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