JP2012008684A - Memory module and semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory module for preventing malfunction due to the mismatching of the timing of an address signal and a control signal.SOLUTION: A memory module includes: a plurality of semiconductor memory devices divided into a plurality of ranks as units for inputting/outputting data; address signal wiring to which the semiconductor memory devices in all the ranks are serially connected as wiring for supplying an address signal input from the outside to the semiconductor memory devices; control signal wiring to which the semiconductor memory devices are serially connected by rank units as wiring for supplying a control signal input from the outside to the semiconductor memory devices; and a capacity part installed in association with each of the semiconductor memory devices connected to the control signal wiring, and equipped with a capacity which is equal to the product of the input capacity of the semiconductor memory device and (the number of ranks minus 1).

Description

  The present invention relates to a memory module and a semiconductor memory device mounted on the memory module.

  In recent information processing devices such as personal computers and workstation server computers, processing of enormous data is required as the processing speed by the CPU and the number of processing bits increase, and the required storage capacity of the main storage device is also required. It is increasing. Therefore, a memory module such as a single inline memory module (SIMM), a dual inline memory module (DIMM), or a multi chip package (MCP) is used as the main storage device of the information processing apparatus.

  As a technology for improving the data transfer speed and reliability of the memory module, the memory module and the memory controller are connected by a bi-directional serial interface, and an AMB (Advanced Memory) that enables the transfer of memory control commands and data. Buffer) is known. For example, Patent Document 1 discloses a control signal wiring (hereinafter referred to as a control signal wiring) and an address signal wiring (hereinafter referred to as an address) for each of the semiconductor memory devices mounted on the memory module. A configuration is described in which a buffer corresponding to the AMB is provided between the input and output terminals of the memory module and a converter that performs serial / parallel conversion between the input and output terminals of the memory module and the data bus wiring. .

WO99 / 00734 pamphlet

  In the memory module, data is input / output in units called ranks with respect to a plurality of mounted semiconductor memory devices. For example, in a four-rank memory module, all mounted semiconductor memory devices are divided into four ranks, and data writing / reading is controlled by the memory controller in units of the rank. The memory controller uses a chip select signal to designate a rank semiconductor memory device to which data is written / read, and outputs a required command to the designated semiconductor memory device. That is, a control signal is supplied in rank units to each semiconductor memory device mounted on the memory module. Here, since the semiconductor memory devices other than the designated rank do not operate in the memory module, the number of wirings formed on the memory module substrate (module substrate) can be reduced by sharing the address bus and the data bus with all ranks. Reduced.

  By the way, in the memory module adopting the AMB technique, an AMB buffer is provided corresponding to each of the address signal and the control signal. As described above, since address signal wiring is shared by all ranks, semiconductor memory devices of all ranks are cascade-connected to address signal wiring 1 as shown in FIG. In the example shown in FIG. 10A, a DRAM is used as the semiconductor memory device, and the number of DRAMs serving as loads (the number of DRAM loads) is 20. On the other hand, since the control signal is supplied in units of ranks, only the semiconductor memory devices of the rank to be controlled are connected in cascade to the control signal wiring 2 as shown in FIG. In the example shown in FIG. 10B, the number of DRAMs that serve as loads (the number of DRAM loads) is five. In addition, R0 to R3 shown in FIG. 10 (a) means ranks 0 to 3, and R0 shown in FIG. 10 (b) means rank 0. Also, Buffer shown in FIGS. 10A and 10B is an AMB buffer, and Rtt is a termination resistor for reducing signal reflection. 10A and 10B illustrate a memory module in which DRAM 0 to 4 in which four memory chips (DRAM chips) used as ranks R0 to R3 are housed in one package are mounted on a module substrate. ing.

  Therefore, the address signal wiring 1 and the control signal wiring 2 have different load capacities even if the wiring lengths are almost the same, and a difference occurs in the signal propagation delay time depending on the number of connected DRAM loads. In particular, among the cascaded DRAMs, the difference in the propagation delay time between the address signal and the control signal becomes larger as the subsequent DRAM connected at a position farther from the AMB buffer.

  For example, as shown in FIG. 11, the difference between the propagation delay time Ta0 of the address signal for the DRAM 0 closest to the buffer and the propagation delay time Tb0 of the control signal, the propagation delay time Ta4 of the address signal for the DRAM 4 furthest from the buffer, and the control signal When the difference in propagation delay time Tb4 is compared, it can be seen that the difference between Ta4 and Tb4 is much larger than the difference between Ta0 and Tb0. This difference in propagation delay time becomes a serious problem when aiming at further speeding up of the memory module because the operation of the DRAM increases as the speed of each DRAM mounted on the memory module increases. That is, as the speed of the semiconductor memory device increases, the timing margin decreases with the difference in the propagation delay time, so that the possibility of malfunction due to the timing mismatch between the address signal and the control signal increases.

  In order to prevent malfunction, for example, a method of determining the operation timing of each semiconductor memory device for each rank in consideration of the propagation delay time of the signal that arrives the latest can be considered. However, in such a technique, when an SDRAM (Synchronous DRAM) or the like that operates in synchronization with a clock is used as a semiconductor memory device, it is necessary to stop the operation in a period of one clock cycle to several clock cycles. It will be retrograde and difficult to adopt.

A memory module of the present invention includes a plurality of semiconductor memory devices divided into a plurality of ranks, which are units for inputting and outputting data,
Address signal wiring that is a wiring for supplying an externally input address signal to the semiconductor memory device, in which the semiconductor memory devices of all ranks are connected in cascade;
Control signal wiring that is a wiring for supplying a control signal input from the outside to the semiconductor storage device, the semiconductor storage devices being connected in cascade in the rank unit;
A capacity unit provided corresponding to each semiconductor memory device connected to the control signal wiring and having a capacity equal to the product of the input capacity of the semiconductor memory device and (rank number-1);
It is characterized by having.

  In the memory module as described above, a capacity unit having a capacity equal to the product of the input capacity of the semiconductor memory device and (rank number-1) equal to the difference between the load capacity of the address signal wiring and the load capacity of the control signal wiring However, since the control signal wiring is provided corresponding to each semiconductor memory device, the propagation delay time of the control signal increases and the propagation delay time of the address signal and the control signal generated due to the difference in load capacitance Can be reduced.

  According to the present invention, it is possible to obtain a memory module that can prevent a malfunction caused by a mismatch in timing between an address signal and a control signal.

It is a block diagram which shows one structural example of 1st Embodiment of the memory module of this invention. It is a schematic diagram which shows the example of arrangement | positioning of the capacity | capacitance pad shown in FIG. It is a schematic diagram which shows the example of arrangement | positioning of the capacity | capacitance pad shown in FIG. It is a schematic diagram which shows the example of arrangement | positioning of the capacity | capacitance pad shown in FIG. It is a block diagram which shows one structural example of 2nd Embodiment of the memory module of this invention. 1 is a block diagram illustrating a configuration example of a semiconductor memory device. 1 is a block diagram illustrating a configuration example of a capacitor array circuit included in a semiconductor memory device of the present invention. It is a block diagram which shows one structural example of 3rd Embodiment of the memory module of this invention. FIG. 8 is a schematic diagram illustrating a setting example of the capacitor array circuit illustrated in FIG. 7. It is a schematic diagram which shows the example of a connection of DRAM in the memory module of background art. 11 is a graph showing signal propagation delay time in the wiring shown in FIG. 10.

Next, the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing an example of the configuration of the first embodiment of the memory module of the present invention, and FIGS. 2 to 4 are schematic views showing examples of the arrangement of the capacitor pads shown in FIG. FIG. 1A shows a state in which 20 DRAMs (all ranks) having a load capacitance Cdie are connected in series with address signal wiring, and FIG. 1B shows a load capacitance Cdie with respect to control signal wiring. 5 shows a state where five DRAMs (for one rank) are connected in cascade.

  As shown in FIG. 1B, in the memory module of the first embodiment, a plurality of capacitance pads (Pad) 10 are connected to the control signal wiring 2, and the capacitance pad 10 and the capacitance pad Pad are formed. In this example, the propagation delay time of the control signal is increased by the parasitic capacitance C_pad between the adjacent wiring layer and the adjacent plane layer (for example, the Vdd plane (Plane)), and the difference between the propagation delay time of the address signal and the control signal is reduced. . The capacitor pad 10 is connected to the control signal wiring 2 in the vicinity of the DRAM, for example, corresponding to each DRAM mounted on the module substrate.

  The value of the parasitic capacitance C_pad can be adjusted by the area of the capacitance pad 10. For example, in the case of the memory module having a 4-rank configuration shown in FIGS. 1A and 1B, the load capacity per DRAM is set as described above. If Cdie, C_pad = 3 × Cdie may be set. In other words, the capacity pad 10 having the capacity C_pad equal to (rank number−1) × Cdie is controlled corresponding to each DRAM so that the load capacity of the address signal wiring 1 and the load capacity of the control signal wiring 2 match. What is necessary is just to connect to the signal wiring 2, respectively.

  FIG. 1A shows a state in which DRAMs of all ranks are connected to one address signal wiring 1, but there are a plurality of address signal wirings 1 in an actual memory module. DRAMs of all ranks are connected to the address signal wiring 1. FIG. 1B shows a state in which DRAMs are connected to one control signal line 2 in units of ranks. However, an actual memory module has a plurality of control signal lines 2, DRAMs are connected to the control signal wiring 2 in rank units. Further, in FIGS. 1A and 1B, DRAM 0 to 4 in which four DRAM chips used as ranks R0 to R3 are accommodated in one package exemplify a memory module mounted on a module substrate. . The same applies to the following second and third embodiments.

  As shown in FIGS. 2 to 4, the module substrate is a multilayer substrate, and supplies a surface layer (Layer 1) on which DRAM or the like is mounted, a wiring layer (Layer 2) on which control signal wiring is formed, and a power supply Vdd. A Vdd plane layer (Layer 3).

FIG. 2 shows an example in which one capacitor pad (Pad) 10 is arranged on the control signal wiring 2 in the vicinity of the DRAM mounting pad 20 to which the DRAM is connected. Here, when the length of the capacitor pad 10 is a1, the width is b1, and the distance between the wiring layer (Layer 2) and the Vdd plane layer (Layer 3) is h, the parasitic capacitance C_pad is εr × ε0 × ( (A1 × b1) / h). Note that ε0 is the dielectric constant of vacuum, and εr is the relative dielectric constant of the medium between the wiring layer (Layer 2) and the Vdd plane layer (Layer 3). For example, when a1 = 6.78 mm, b1 = 1 mm, h = 0.08 mm, and εr = 4 (glass epoxy), the parasitic capacitance C_pad is C_pad = 4 × 8.854 × 10 ⁻¹² × ((6. 78 × 10 ⁻³ × 1 × 10 ⁻³ ) /0.08×10 ⁻³ ) = 3 pF.

  FIG. 3 shows an example in which a plurality of capacitance pads (pads) 11 are arranged on the control signal wiring 2. FIG. 4 shows an example in which a plurality of capacitance pads (pads) 12 are connected in parallel with the control signal wiring 2. 3 and 4 show a configuration example in which the parasitic capacitance Cpad of the capacitance pad 10 shown in FIG.

  For example, when the parasitic capacitance Cpad is realized by ten capacitance pads 11, the capacitance of each capacitance pad 11 may be set to C_pad / 10. The same applies to the capacitor pad 12 shown in FIG.

For example, the length of each capacitor pad 11 is a2, the width is b2, the distance between the wiring layer (Layer 2) and the Vdd plane layer (Layer 3) is h, a2 = 1.36 mm, b2 = 0.5 mm, h = 0.08 mm and εr = 4 (glass epoxy), the parasitic capacitance C_pad2 of the capacitance pad 11 is C_pad2 = 4 × 8.854 × 10 ⁻¹² × ((1.36 × 10 ⁻³ × 0.5). × 10 ⁻³ ) /0.08×10 ⁻³ ) = 0.3 pF.

  3 and FIG. 4, the area of one capacitor pad 11 (or 12) can be made smaller than that of the capacitor pad 10 shown in FIG. 2, and the capacitance is larger than that shown in FIG. The degree of freedom in design for arranging pads is improved. Note that one capacitor pad 10 shown in FIG. 2 may be connected in parallel with the control signal wiring 2 instead of the plurality of capacitor pads 12 shown in FIG.

According to the memory module of this embodiment, the capacity equal to the product of the input capacity of the semiconductor memory device and (rank number-1) equal to the difference between the load capacity of the address signal wiring 1 and the load capacity of the control signal wiring 2 Since the control signal wiring 2 corresponding to each semiconductor memory device is provided in the control signal wiring 2, the propagation delay time of the control signal is increased, and the address signal generated due to the difference in load capacitance and the control are controlled. The difference in signal propagation delay time can be reduced. Therefore, the timing margin between the address signal and the control signal is improved, and malfunction caused by the mismatch between the timing of the address signal and the control signal is prevented.
(Second Embodiment)
FIG. 5 is a block diagram showing a configuration example of the second embodiment of the memory module of the present invention. FIG. 5A shows a state in which 20 DRAMs (all ranks) having a load capacitance Cdie are connected in cascade to the address signal wiring 1, and FIG. 5B shows a load on the control signal wiring 2. 5 shows a state in which five DRAMs (for one rank) having a capacity Cdie are connected in cascade.

  As shown in FIG. 5B, in the memory module of the second embodiment, a chip capacitor (capacitance unit) 30 is inserted between the control signal wiring 2 and the power supply Vdd, and controlled by the capacitance Ccap of the chip capacitor 30. In this example, the propagation delay time of the signal is increased, and the difference between the propagation delay times of the address signal and the control signal is reduced. The chip capacitor 30 may be inserted between the control signal wiring 2 and the power supply line in the vicinity of each DRAM mounted on the module substrate.

  The value of the capacitance Ccap of the chip capacitor 30 is the same as in the first embodiment, assuming that the load capacity per DRAM is Cdie in the case of the memory module having the 4-rank configuration shown in FIGS. 5 (a) and 5 (b). , Ccap = 3 × Cdie. That is, a chip capacitor 30 having a capacity Ccap equal to (rank number−1) × Cdie is set in correspondence with each DRAM so that the load capacity of the address signal wiring 1 and the load capacity of the control signal wiring 2 coincide with each other. What is necessary is just to connect to the wiring 2, respectively.

According to the memory module of this embodiment, the capacity equal to the product of the input capacity of the semiconductor memory device and (rank number −1), which is equal to the difference between the load capacity of the control signal line 2 and the load capacity of the address signal line 1. By connecting the chip capacitor 30 to the control signal wiring 2 corresponding to each semiconductor memory device, the propagation delay time of the control signal increases as in the memory module of the first embodiment, and the load capacitance It is possible to reduce the difference in propagation delay time between the address signal and the control signal generated due to the difference. Therefore, the timing margin between the address signal and the control signal is improved, and malfunction caused by the mismatch between the timing of the address signal and the control signal is prevented.
(Third embodiment)
In the first embodiment and the second embodiment described above, an address signal is obtained by connecting a capacitor portion such as the capacitor pads 10 (11, 12) and the chip capacitor 30 to the control signal wiring 2 on the module substrate. And a technique to reduce the difference of propagation delay time of control signal is presented.

  The memory module according to the third embodiment is an example in which a capacitor for adjusting the difference in the propagation delay time is provided in each semiconductor memory device mounted on the module substrate.

  First, a semiconductor memory device mounted on a module substrate will be briefly described with reference to the drawings.

  FIG. 6 is a block diagram showing a configuration example of the semiconductor memory device. FIG. 6 shows a configuration example of an SDRAM (Synchronous DRAM).

  As shown in FIG. 6, the semiconductor memory device 100 includes a memory cell array 101 including a plurality of memory cells for storing data, a plurality of sense amplifiers 102 for reading data stored in the memory cells, A row decoder 103 and a column decoder 104 for decoding an address signal for accessing a memory cell for writing / reading data, and a latch circuit for temporarily holding data to be written to the memory cell and data read from the memory cell 105, a row address buffer 106 that temporarily holds a row address supplied to the row decoder 103, a column address buffer 107 that temporarily holds a column address supplied to the column decoder 104, and the semiconductor memory device 100. External to set mode A command decoder 108 that decodes a supplied control command, a mode register 109 that holds mode setting information such as CAS latency, burst length, and burst type, which is set by using an address signal Address, and a memory cell array 101 In accordance with the data control circuit 110 that controls the data write operation and the data read operation from the memory cell array 101, and the output signal of the mode register 109, the row address buffer 106, the column address buffer 107, the row decoder 103, and the column decoder 104 , The control circuit 111 for controlling the operation of the sense amplifier 102, the data control circuit 110, and the like, and the clock signals CK, / CK and CKE (CK Enable) supplied from the outside. A clock generation circuit 112 that generates a clock for operating each circuit in the body storage device 100, and data supplied from the outside are received and supplied to the latch circuit 105, and the data output from the latch circuit 105 is also received. A data input / output buffer 113 to be transmitted to the outside, a timing signal for receiving data supplied from the outside by the data input / output buffer 113, and a timing signal for outputting data from the data input / output buffer 113 to the outside are generated. And a DLL (Digital Locked Loop) circuit 114. FIG. 6 shows a configuration example of the semiconductor memory device 100 including the memory cell array 101 of 8 banks (Banks 0 to 7). The semiconductor memory device 100 shown in FIG. 6 may further include a circuit for realizing a required function such as a well-known circuit for controlling a refresh operation or a circuit for controlling a burst operation. The semiconductor memory device mounted on the memory module is not limited to the configuration shown in FIG. 6 and may be any known semiconductor memory device.

  The semiconductor memory device of this embodiment has a configuration further including a capacitor array circuit shown below.

  FIG. 7 is a block diagram showing a configuration example of a capacitor array circuit included in the semiconductor memory device of the present invention, and FIG. 8 is a block diagram showing a configuration example of the third embodiment of the memory module of the present invention. . FIG. 9 is a schematic diagram showing a setting example of the capacitor array circuit shown in FIG. 8A shows a state in which 20 DRAMs (all ranks) having a load capacitance Cdie are connected in series to the address signal wiring 1, and FIG. 8B shows the control signal wiring 2. 5 shows a state where five DRAMs (for one rank) having a load capacity Cdie are connected in cascade.

As shown in FIG. 7, the capacitor array circuit 40 includes a plurality of first capacitor units 41, second capacitor units 42 and third capacitor units 43 having different capacitance values, and first capacitor units 41 to third capacitor units 43. The semiconductor memory device includes a plurality of AF (Anti-Fuse) circuits 60 serving as a switch unit for connecting or disconnecting the control signal input / output pad 50. FIG. 7 shows three first capacitor portions 41 _{1 to} 41 _{3 having} a capacitance of ₁ pF, three second capacitor portions 42 _{1 to} 42 ₃ having a capacitance of 0.2 pF, and three third capacitor portions having a capacitance of 0.1 pF. It shows an example in which a 43 ₁ to 43 _3. The first capacitor units 41 _{1 to} 41 ₃ are connected in series, the second capacitor units 42 _{1 to} 42 ₃ are connected in series, and the third capacitor units 43 ₁ to 43 ₃ are connected in series. Also, a first capacitor portion 41 _{1-41 3} connected in series, a second capacitor portion 42 _{1-42 3} connected in series, the third capacitor 43 _{1-43 3} connected in series Connected in parallel.

  What is necessary is just to implement | achieve the 1st capacity | capacitance part 41-the 3rd capacity | capacitance part 43 with the parasitic capacitance of diffusion layers, such as a transistor and a diode, for example. Usually, since an ESD (Electro-Static Discharge) protection circuit is connected to the input / output pad of the semiconductor memory device, for example, the same circuit as the ESD protection circuit is used as the first capacitor 41 to the third capacitor 43, for example. The parasitic capacitance of the diffusion layer such as a transistor formed and formed in the circuit may be used. The ESD protection circuit can be realized by, for example, a circuit described in Japanese Patent Application Laid-Open No. 2004-063754.

  The AF circuit 60 may be formed using an antifuse element, for example. The antifuse element is an element that is normally in an open state and short-circuited when a high voltage is applied. The open / short circuit of the antifuse element may be controlled using, for example, a DFT signal that is a control signal for testing the semiconductor memory device. The DFT signal can be input from the input / output pad 50 or the like even when the semiconductor memory device is mounted on the module substrate. By inputting a predetermined code to the mode register 109, the semiconductor memory device is put into the test mode. After the transition, the open / short circuit of the AF circuit 60 may be set using the DFT signal. The AF circuit 60 can be realized by a configuration described in, for example, Japanese Patent Application Laid-Open No. 2003-317496.

Since the capacitor array circuit 40 shown in FIG. 7 has a configuration including three first capacitor units 41 to third capacitor units 43, a 2-bit DFT is provided for each of the first capacitor units 41 to the third capacitor units 43. If the signal is used, the number of connections for each of the first capacitor unit 41 to the third capacitor unit 43 to the input / output pad 50 can be controlled. In FIG. 7, the number of connections of the first capacitor units 41 _{1 to} 41 ₃ is controlled using DFT [1: 0], and the number of connections of the second capacitor units 42 _{1 to} 42 ₃ using DFT [3: 2]. controls, DFT: it shows a third example of controlling the number of connection capacity portion 43 _{1-43 3} using [5 4]. The configuration of the capacitor array circuit 40 is not limited to the configuration shown in FIG. 7, and a plurality of capacitor units having a predetermined capacity and a plurality of switch units (AF circuits) corresponding to the capacitor units. And any configuration may be used as long as each capacitor unit and the control signal input / output pad 50 can be connected or disconnected by an external control signal.

  The semiconductor memory device mounted on the memory module of this embodiment includes the capacitor array circuit 40 for each input / output pad 50 for control signals. In the case of the 4-rank configuration memory module shown in FIGS. 8A and 8B, the capacity Cary of the capacity array circuit 40 is the first and the first when the load capacity per semiconductor memory device (DRAM) is Cdie. Similarly to the second embodiment, Cary = 3 × Cdie is set. That is, the capacity Cary of each capacity array circuit may be set to (rank number−1) × Cdie so that the load capacity of the address signal wiring and the load capacity of the control signal wiring match.

  The capacitance array circuit 40 shown in FIG. 7 sets the capacitance Cary to 0 in the range of 0 pF to 3.9 pF by setting the open / short circuit of each AF circuit 60 included in the capacitance array circuit 40, as shown in FIG. Can be set in units of 1 pF.

  As shown in FIG. 7, normally, the input / output pad 50 of the semiconductor memory device includes a parasitic capacitance C_pad of the pad itself, a capacitance C_gate of a gate electrode of a transistor included in the first stage circuit (for example, the command decoder 108) 70, ESD. It is considered that the parasitic capacitance C_esd of the transistor included in the protection circuit 80 is already connected. Further, the internal wiring 90 that connects the input / output pad 50 to the first stage circuit 70, the ESD protection circuit 80, and the capacitor array circuit 40 also has a parasitic capacitance C_wire. Accordingly, the input capacity (load capacity) of the semiconductor memory device mounted on the memory module is not necessarily the same, and the parasitic capacity of the address signal wiring 1 and the control signal wiring 2 formed on the module substrate is also long. Since the thicknesses are different, they are not necessarily the same.

  According to the present embodiment, each semiconductor memory device mounted on the memory module includes the capacitor array circuit 40, and the capacitance Cary of each capacitor array circuit 40 is equal to the difference in load capacitance between the control signal wiring 2 and the address signal wiring 1. By setting the capacity ((rank number-1) × Cdie), the propagation delay time of the control signal increases as in the first and second embodiments, which is caused by the difference in load capacity. The difference in propagation delay time between the address signal to be controlled and the control signal can be reduced. Furthermore, the capacitance Cary of the capacitance array circuit 40 can be finely adjusted so that the difference between the propagation delay times of the address signal and the control signal is further reduced as compared with the first and second embodiments. Therefore, the timing margin between the address signal and the control signal is further improved, and a malfunction due to the timing mismatch between the address signal and the control signal is prevented.

  In the first to third embodiments, a configuration example is shown in which four memory (DRAM) chips used as ranks R0 to R3 are accommodated in one package as a semiconductor memory device. However, the semiconductor memory device does not need to accommodate a plurality of chips, and may be configured to be accommodated in individual packages for each memory chip.

DESCRIPTION OF SYMBOLS 1 Address signal wiring 2 Control signal wiring 10, 11, 12 Capacitance pad 20 DRAM mounting pad 30 Chip capacitor 40 Capacitance array circuit 41, 411-413 1st capacity | capacitance part 42, 421-423 2nd capacity | capacitance part 43, 431-433 1st 3 capacitor 50 input / output pad 60 AF circuit 70 first stage circuit 80 ESD protection circuit 90 internal wiring 100 semiconductor memory device 101 memory cell array 102 sense amplifier 103 row decoder 104 column decoder 105 latch circuit 106 row address buffer 107 column address buffer 108 command decoder 109 mode register 110 data control circuit 111 control circuit 112 clock generation circuit 113 data input / output buffer 114 DLL circuit

Claims (8)

A plurality of semiconductor memory devices divided into a plurality of ranks, which are units for inputting and outputting data;
Address signal wiring that is a wiring for supplying an externally input address signal to the semiconductor memory device, in which the semiconductor memory devices of all ranks are connected in cascade;
Control signal wiring that is a wiring for supplying a control signal input from the outside to the semiconductor storage device, the semiconductor storage devices being connected in cascade in the rank unit;
A capacity unit provided corresponding to each semiconductor memory device connected to the control signal wiring and having a capacity equal to the product of the input capacity of the semiconductor memory device and (rank number-1);
A memory module comprising: The capacity section is
The memory module according to claim 1, wherein the memory module is a pad arranged on the control signal wiring. The capacity section is
The memory module according to claim 1, wherein the memory module is a plurality of pads arranged on the control signal wiring. The capacity section is
2. The memory module according to claim 1, wherein the memory module is a pad connected in parallel with the control signal wiring. The capacity section is
2. The memory module according to claim 1, wherein the memory module is a plurality of pads connected in parallel with the control signal wiring. The capacity section is
2. The memory module according to claim 1, wherein the memory module is a chip capacitor. A plurality of capacity units having a predetermined capacity;
A plurality of switch units provided corresponding to each capacitor unit, which connects or disconnects the capacitor unit and the control signal input / output pad according to an externally supplied signal;
A semiconductor memory device comprising: The plurality of semiconductor memory devices according to claim 7, which are divided into a plurality of ranks, which are units for inputting and outputting data,
Address signal wiring that is a wiring for supplying an externally input address signal to the semiconductor memory device, in which the semiconductor memory devices of all ranks are connected in cascade;
Control signal wiring that is a wiring for supplying a control signal input from the outside to the semiconductor storage device, the semiconductor storage devices being connected in cascade in the rank unit;
Have
The total capacity of the capacity part is
A memory module having a capacity equal to a product of an input capacity of the semiconductor memory device and (rank number-1).

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