JP2004032759A - Delay adjustment circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust the delayed time of an input signal by controlling the value of an internal register, the internal signal or the external signal of a semiconductor integrated circuit device. <P>SOLUTION: The delay adjustment circuit is provided with a first gate group 10 for effecting the fine adjustment of delayed time of the input signal, load capacities 60-63, 70-73 connected to the output side of specified gates among the first gate group through first switching means 40-43, 50-53, a second gate group 20 for effecting rough adjustment of the delayed time of the input signal, and a control means 30 for adjusting the delayed time of the input signal by adjusting the load capacities connected to the output side of specified gates among the first gate group 10 and the number of gate stages of the second gate group 20. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a waveform-adjustable delay adjustment circuit used to generate a clock signal used for digital processing.
[0002]
[Prior art]
A conventional clock generation circuit often uses a PLL circuit to generate a clock whose operating frequency is multiplied by 0.5 × N (N = 3, 4, 5,...). As shown in FIG. 14, a commonly used PLL circuit 800 includes a phase comparison circuit 802, a low-pass filter (LPF) 804, a voltage-controlled oscillator (VCO) 806, and a 1 / N frequency divider 808. It is configured. A clock distribution circuit 810 supplies the clock generated by the PLL circuit 800 to each unit.
[0003]
In the PLL circuit 800, a clock 807 which is N times the operating frequency of the reference clock 801 input to the PLL circuit 800 is generated. PLL circuit 800
An output clock 809 is supplied from the clock 807 generated by the clock distribution circuit 810 to each block in the semiconductor integrated circuit device (LSI). A comparison signal 810 obtained by dividing the output clock 809 by 1 / N by a 1 / N divider 808 is fed back, and a phase difference from the reference clock 801 is detected by a phase comparison circuit 802.
[0004]
The phase difference detection pulse 803 output from the phase comparison circuit 802 has a pulse width corresponding to the phase difference, is integrated by the low-pass filter 804, and a VCO control voltage 805 having a value corresponding to the pulse width is applied to the voltage control oscillation circuit. (VCO) 806. Then, the oscillation frequency of the voltage controlled oscillation circuit 806 is changed according to the phase difference between the reference clock 801 and the comparison signal 810, and the output 809 of the clock distribution circuit 810 is controlled so as to be finally synchronized with the reference clock 801.
[0005]
[Problems to be solved by the invention]
As described above, the PLL circuit is used for compensating for variations in the semiconductor integrated circuit, such as transistor performance, wiring thickness, and wiring width, which occur during the manufacture of the semiconductor integrated circuit. However, in the PLL circuit, when the power supply voltage rises and falls due to the change in the operation rate of the peripheral circuit, a phenomenon in which the width of the output waveform increases and decreases with time is observed. This is called jitter. As long as the PLL circuit operates so as to synchronize with the reference clock 801, the jitter is never eliminated as long as the PLL circuit is used.
[0006]
If the waveform of the reference clock 801 is different from the expected waveform due to a change in the duty ratio, the phase comparison circuit may not operate as expected. If the jitter is large or the duty ratio is different from the estimate at the time of design, the manufactured LSI may not operate, and there is a problem that remanufacture or redesign must be performed.
[0007]
The present invention has been made in view of such circumstances, and a delay adjustment circuit capable of adjusting a delay time of an input signal by controlling an internal register value or an internal signal of a semiconductor integrated circuit device or an external signal. The primary purpose is to provide. Further, the present invention uses a delay adjustment circuit capable of adjusting a delay time by controlling an internal register value or an internal signal of a semiconductor integrated circuit device or an external signal, and is caused by manufacturing variations of the semiconductor integrated circuit device. It is a second object of the present invention to provide a clock generation circuit which can compensate for clock skew and duty ratio and has small jitter.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 includes a first gate group in which each gate is connected in series for fine adjustment of a delay time of an input signal, and a first gate group among the first gate group. A first load capacitance connected to the output side of the specific gate via a first transfer switch; and a second load capacitance connected to a gate output side of the next stage of the specific gate via a second transfer switch. And a second group of gates connected to the output side of the first group of gates via switch means for coarsely adjusting the delay time of the input signal; and the first and second loads. Control means for controlling the first and second transfer gates and the switch means so as to adjust the delay time of the input signal by adjusting the capacitance and the number of gate stages of the second gate group , The controlling hand Comprises a register provided in the semiconductor integrated circuit device and capable of setting an output value by an internal signal, and based on the register value set in the register, the first and second transfer gates and The switching control of the switch means adjusts a gate output load and the number of gate stages of the second gate group.
[0009]
According to a second aspect of the present invention, there is provided a first gate group in which each gate is connected in series for fine adjustment of a delay time of an input signal, and an output side of a specific gate in the first gate group. A first load capacitance connected via a first transfer switch, a second load capacitance connected via a second transfer switch to a gate output side next to the specific gate, and A second group of gates connected to the output side of the first group of gates via switch means for coarsely adjusting the delay time of the input signal, the first and second load capacitors, and the second group of gates; Control means for controlling the first and second transfer gates and the switch means so as to adjust the delay time of the input signal by adjusting the number of gate stages of the gate group, wherein the control means comprises: Semiconductor integrated circuit And a register which is provided in the device and can set an output value from the outside by initialization. The first and second transfer gates and the switch means are configured based on the register value set in the register. , The gate output load and the number of gate stages of the second gate group are adjusted.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of the delay adjustment circuit according to the embodiment of the present invention. In FIG. 1, a delay adjustment circuit according to the present embodiment includes inverters 11 to 14 each having a gate connected in series and forming a first gate group 10 for performing fine adjustment of a delay time of an input signal; Load capacitances 60 to 63, 70 to 73 connected to the output side of the inverters 12 and 13 of the one gate group via transfer gates 40 to 43 and 50 to 53 as first switch means; An inverter chain 21 which is connected to the output side of the gate group 10 through transfer gates 80 to 83 as second switch means and constitutes a second gate group 20 for coarsely adjusting the delay time of the input signal. To 23, the amount of load capacity 60 to 63, 70 to 73 connected to the output side of the inverters 12 and 13 of the first gate group 10 and the number of gate stages of the second gate group 20 are adjusted. And a register group 30 as control means for controlling the transfer gates 40 to 43, 50 to 53, and 80 to 83 as first and second switch means so as to adjust the delay time of the input signal. are doing.
[0011]
The input side of the inverter 11 constituting the first group of gates 10 is connected to the input terminal 100, the output side of the inverter 11 is connected to the inverters 12, 13, and 14 in that order, and the output side of the inverter 14 is further connected to the inverter chain. 21 to 23 are connected in order. Each of the inverter chains 21 to 23 is a gate delay circuit including an even number of stages of inverters.
[0012]
The output side of the inverter 12 in the first gate group 10 is connected to the input side of the transfer gates 40 to 43, and the output side of the inverter 13 is connected to the input side of the transfer gates 50 to 53. Capacitors 60 to 63 are connected to the output sides of the transfer gates 40 to 43, respectively, and capacitors 70 to 73 are connected to the output sides of the transfer gates 50 to 53, respectively. The output sides of the inverter 14 and the inverter chains 21 to 23 are connected to the input sides of the transfer gates 80 to 83, respectively.
[0013]
The output sides of the transfer gates 80 to 83 are connected in common, and constitute a four-input selector that is controlled so that only one of the transfer gates 80 to 83 is selectively turned on. Output sides of the transfer gates 80 to 83 constituting the 4-input selector are connected to an output terminal 101 of the delay adjustment circuit via a buffer 90.
[0014]
The signals output from the registers 200 to 203 are supplied to the transfer gates 40 to 43 as control input signals, respectively, and the signals output from the registers 210 to 213 are supplied to the transfer gates 50 to 53 as control input signals, respectively. By adjusting the control input signals supplied to the transfer gates 40 to 43 with the register values set in the registers 200 to 203, the capacitance value as the output load of the inverter 12 is set as a combined capacitance by a combination of the capacitances 60 to 63. be able to. Further, by adjusting the control input signal supplied to the transfer gates 50 to 53 by the register value set in the registers 210 to 213, the capacitance value is set as the output load of the inverter 13 as a combined capacitance by a combination of the capacitances 70 to 73. can do.
[0015]
Assuming that the capacitance values of the capacitors 61 to 63 are twice, four times, and eight times as large as the capacitance value of the capacitance 60, the output load of the inverter 12 is synthesized from 0 to 15 times the capacitance value of the capacitance 60 in units of one time. The capacitance value of the capacitance can be adjusted. Similarly, assuming that the capacitance values of the capacitors 71 to 73 are twice, four times, and eight times the capacitance value of the capacitor 70, the output load of the inverter 13 is one time from 0 to 15 times the capacitance value of the capacitor 70. The capacitance value of the combined capacitance can be adjusted in units.
[0016]
The inverters 12 and 13 are designed such that the gate width of the PMOS transistor is increased so as to be smaller than the on-resistance of the NMOS transistor. With such a design, the falling edge requiring the driving force of the NMOS transistor is more susceptible to the output load than the rising edge requiring the driving force of the PMOS transistor. Therefore, the falling of the signal output from the output terminal 101 can be varied by adjusting the output load of the inverter 12, and the rising of the signal output from the output terminal 101 adjusts the output load of the inverter 13. Can be varied. Therefore, the rising waveform and the falling waveform of the signal output from the output terminal 101 can be adjusted by appropriate output load adjustment of the inverters 12 and 13, respectively.
[0017]
The signals output from the registers 220 and 221 are converted by a decoder (not shown) and supplied to the transfer gates 80 to 83 as control input signals. Only one of the transfer gates 80 to 83 is turned on by the control input signal supplied to the transfer gates 80 to 83, and from the input terminal 100 to the output terminal 101 of the delay adjustment circuit according to the setting data of the registers 220 and 221. The number of gate stages up to can be adjusted. Each of the registers 200 to 203, 210 to 213, 220, and 221 is provided in a semiconductor integrated circuit device (LSI), and a register value is externally set by an internal signal or by initialization. .
[0018]
In the delay adjusting circuit having the above configuration, fine adjustment of the delay time of the input signal is performed by adjusting the output load of the inverters 12 and 13, that is, by adjusting the gate output load, and the input is controlled by adjusting the number of input / output gate stages by switching the inverter chains 21 to 23. By roughly adjusting the delay time of the signal, it is possible to adjust the delay time of the rise and fall of the signal until the signal input from the input terminal 100 is output from the output terminal 101.
[0019]
In this embodiment, the register is used as the control means, and the delay time is controlled by the set value. However, the present invention is not limited to this, and the delay time is controlled by the value of the internal memory, the internal logic signal, or the external signal. May be controlled.
[0020]
As shown in FIG. 2, when the reference clock CLK0 is input as an input signal to the input terminal 100 of the delay adjustment circuit 300 shown in FIG. 1, a clock whose operating frequency is equal to the reference clock CLK0 and whose rising and falling waveforms can be adjusted. CLKi can be generated. FIG. 3 shows a waveform diagram of the reference clock CLK0 and the clock CLKi whose waveform can be adjusted.
[0021]
Next, FIG. 4 shows the configuration of the clock generation circuit according to the first embodiment of the present invention. The clock generation circuit according to the present embodiment includes a delay adjustment circuit 300 having the configuration shown in FIG. 1 using reference clock CLK0 as an input signal, and an exclusive OR operation of reference clock CLK0 and an output signal of delay adjustment circuit 300. And an exclusive OR circuit 301 for performing
[0022]
In the above configuration, the clock CLLj delayed by た cycle from the reference clock CLK input from the input terminal 110 is generated by the delay adjustment circuit 300, and the exclusive OR circuit 301 generates the clock CLLj between the reference clock CLK0 and the clock CLLj. By taking exclusive OR, a clock CLKn whose operating frequency is twice as high as that of the reference clock CLK0 can be generated. Since the waveform of the clock CLLj can be adjusted by controlling the register value, the falling edge of CLKn can be adjusted. FIG. 5 shows the reference clock and the output timing of the clock CLLj and the clock CLKn. According to the clock generation circuit according to the first embodiment of the present invention, it is possible to compensate for a clock skew and a duty ratio caused by manufacturing variations of a semiconductor integrated circuit device, and to reduce jitter.
[0023]
Next, a case will be described in which the semiconductor integrated circuit is designed on the assumption that it is used as a clock timing signal whose waveform fall can be adjusted. FIG. 6A shows the waveform of the clock CLKn output by the clock generation circuit shown in FIG. 4, and FIG. 6B shows the configuration of the semiconductor integrated circuit device described above. This semiconductor integrated circuit device is provided between the clock generation circuit shown in FIG. 4, the logic gates 370, 371, and 372, and between the logic gates 370, 371, and 372. (Falling edge), falling edge flip-flops 360 and 361 which operate at the timing of the falling edge.
[0024]
In the above configuration, clock edges 350 and 351 are input to the falling edge flip-flops 360 and 361, respectively. 370, 371 and 372 represent logic gates between flip-flops, respectively. When an LSI design using only the adjustable falling edge of the clock CLKn is performed, the effects of clock skew and jitter can be minimized.
[0025]
Next, the configuration of a clock generation circuit according to a second embodiment of the present invention is shown in FIG. The clock generation circuit according to the present embodiment performs a logic operation on the reference clock and the output signal of the delay adjustment circuit shown in FIG. An exclusive OR circuit 120 as a logic circuit for outputting a clock of a frequency; and a PMOS transistor 110 as setting means for fixing the output of the delay adjustment circuit to a constant value only in the non-operation mode. Based on the logical operation result of the sum circuit 120, a clock having an operation frequency of 1 time of the reference clock as the non-operation mode or N times (2 times in this embodiment) of the reference clock as the operation mode is output.
[0026]
As described above, the delay adjustment circuit is basically the same as the configuration shown in FIG. As shown in FIG. 7, a PMOS transistor 110 for precharging whose source is connected to a power supply is added to a node 91 of the delay adjustment circuit shown in FIG. 1, and a register 222 in the register group 30 'is added. In the clock generation circuit according to the present embodiment, all the control inputs of the transfer gates 80 to 83 are allowed to be in the off state, and in that case, the non-input signal which is input to the gate of the precharge PMOS transistor 110 is output. The operation signal is controlled so that the PMOS transistor 110 is turned on.
[0027]
The signals of the registers 220 to 222 are decoded by a decoder (not shown) and supplied to the transfer gates 80 to 83 and the precharge PMOS transistor 110 as control input signals, and the transfer gates 80 to 83 and the precharge PMOS transistor 110 Is controlled so that only one of them is turned on. When the precharge PMOS transistor 110 is on, the output of the delay adjustment circuit, that is, the output of the buffer 90, becomes a constant value of 1 and enters the non-operation mode. Therefore, by configuring the clock generation circuit using the exclusive OR circuit 120 that performs the exclusive OR operation of the output of the delay adjustment circuit having the non-operation mode and the reference clock input from the input terminal 100, The clock output from the delay adjustment circuit can be set to a fixed value of 1 irrespective of the waveform of the reference clock, so that the operating frequency of the clock output from the output terminal 122 is set to the non-operation mode by setting the register value. It is possible to generate a clock that is one time and twice the reference clock as the operation mode.
[0028]
FIG. 8 shows a clock generation circuit according to a third embodiment of the present invention, and FIG. 9 shows a reference clock and an output timing of an output clock of each unit. In the clock generation circuit of FIG. 4, a clock delayed by 1/4 cycle is generated by the delay adjustment circuit 300, but in the clock generation circuit shown in FIG. The clock CLKy delayed by １ ／ cycle is generated by the delay adjustment circuit 303.
[0029]
When the exclusive OR circuit 304 performs an exclusive OR operation on the reference clock CLK0, the clock CLKx delayed by 1/6 cycle and the clock CLKy delayed by 1/3 cycle, the operating frequency is tripled with respect to the reference clock CLK0. Can be generated. Similarly, according to the present embodiment, by performing a logical operation of outputs of a plurality of delay adjustment circuits having different delay times with a reference clock as an input, waveform control of an N-fold operating frequency with respect to the reference clock CLK0 is performed. A possible clock can be generated.
[0030]
Next, a configuration of a clock generation circuit according to a fourth embodiment of the present invention is shown in FIG. The clock generation circuit 400 according to the present embodiment includes a delay adjustment circuit 410 illustrated in FIG. 1 or 7, a logic circuit 420 that performs a logical operation on an output clock of the delay adjustment circuit 410, and a clock output of the clock generation circuit 400. A detection circuit 430 for detecting the duty ratio and the clock skew of the clock signal, and operating the register value of the register 410 in the delay adjustment circuit 410 based on the detection output of the detection circuit 430 so that the duty ratio and the clock skew are set in advance. And a control circuit 440 for dynamically updating. The delay adjustment circuit 410 includes a register 410 and a variable delay circuit 414. The delay adjustment circuit 410 has the same configuration as the delay adjustment circuit shown in FIG. 1 or FIG. 7, the register 410 corresponds to the register group 30 or 30 ′ shown in FIG. 1 or FIG. Alternatively, this corresponds to a configuration in which the register group 30 or 30 'is removed from the delay adjustment circuit shown in FIG. 500 is a reference clock generation circuit, and 510 is a distribution circuit.
[0031]
In the above configuration, the reference clock 501 output from the reference clock generation circuit 500 is input to the delay adjustment circuit 410, and the logic operation of the output 415 of the delay adjustment circuit and the reference clock 501 is performed by the logic circuit 420. A clock 421 having an operating frequency N times the reference clock 501 is generated. An output clock 512 is output from the clock 421 by the distribution circuit 510 and distributed to each block in the LSI.
[0032]
From a part 511 of the output clock of the distribution circuit 510, the duty ratio and the clock skew of the output clock 511 are detected by the detection time 430, and the deviation between these detected values and the expected clock waveform is detected. If the duty ratio or clock skew of the output clock 511 is different from the expected value, the control circuit 440 adjusts the register based on the output 431 of the detection circuit 430 so that the delay adjustment circuit 410 adjusts the waveform of the output clock 421. Set to an appropriate value. The delay time of the clock in the variable delay circuit 420 is adjusted by the register value 411 set by the output 441 of the control circuit 440, and the output clock 421 is corrected so that the duty ratio and the clock skew match the expected values.
[0033]
According to the clock generation circuit according to the present embodiment, a delay adjustment circuit that adjusts a delay time of an input signal based on a set value of a register without using a PLL circuit, a duty ratio of a clock output of the clock generation circuit, A detection circuit for detecting a clock skew, and a control circuit for dynamically updating a register value in the delay adjustment circuit so as to have a preset duty ratio and clock skew based on the detection output of the detection times. Therefore, it is possible to automatically adjust the clock duty ratio and the clock skew to the expected values.
[0034]
As another embodiment of the present invention,
Although the physical configuration is as described above, the number of delay adjustment circuits used for the clock generation circuit in the above-described embodiment is not limited to one, and may be two or more. The capacitance value set to 2, 4, or 8 times as the load element of the delay adjustment circuit in each of the above embodiments is not limited to this. There are various methods for realizing the load element, such as using a gate input of an inverter or the like. Further, the ratio of the gate widths of the NMOS transistor and the PMOS transistor of the output load capacitance adjusting inverter can be designed so that the on-resistance of the NMOS transistor is smaller.
[0035]
Further, the number of transfer gates and registers for fine adjustment and coarse adjustment of the delay adjustment circuit in the above embodiment is merely an example, and is not limited to this. Further, switch means other than the transfer gate may be used. Further, although an inverter is used as a delay element of the delay adjustment circuit in the above embodiment, a gate other than the inverter can be used, and the number of gate stages is not limited. Also, an example has been described in which an exclusive OR circuit is used as a logical circuit that performs a logical operation on the output of the delay adjustment circuit. However, the present invention is not limited to this, and instead of the exclusive OR circuit, an exclusive NOR circuit and By doing so, it is also possible to invert the clock waveform, in which case the adjustable clock edge is also inverted.
[0036]
In the delay adjustment circuit having the non-operation mode in the above embodiment, the fixed value output is realized by the PMOS transistor for precharging, but the fixed value can be output by using the NMOS transistor. Further, the fixed value is not limited to one.
[0037]
Next, FIG. 11 shows a configuration of a clock generation circuit according to a fifth embodiment of the present invention. In the figure, the clock generation circuit according to the present embodiment can adjust the delay time by the value of the internal register of the semiconductor integrated circuit device, the value of the internal memory, the internal logic signal, or the external signal. The first, second, and third three delay adjustment circuits 601, 602, and 603 and the input terminals of the three delay adjustment circuits 601 to 603 are connected in common, and the first and third delay adjustment circuits 601, 603 A first selector 610 that selects an input of the three delay adjustment circuits 601 to 603 or an output of the second delay adjustment circuit 602 according to one or both of the outputs; A second selector 611 that selects the output of the first or third delay adjustment circuit 601 or 603 based on one or both of the outputs of the second delay adjustment circuit 602; And a logic circuit 612 for obtaining an exclusive logical product of said first output signal of the second selector 610 and 611.
[0038]
In FIG. 11, the first, second, and third delay adjustment circuits 601, 602, and 603 have their input sides commonly connected, and an input signal (a reference clock in this embodiment) 650 is input. ing. The output signal of the first, second, and third three delay adjustment circuits 601, 602, and 603 is determined by a register inside the LSI, an internal signal, or an external signal. The second delay adjustment circuit 602 is adjusted so as to have a delay time of １ ／ of the cycle time c, and adjusted so as to have a delay time of ／ of the cycle time c and inverted. The third delay adjusting circuit 603 has a delay time of ／ of the cycle time c and is adjusted to be inverted.
[0039]
The first selector 610 selects the input signal 650 and the output of the second delay adjustment circuit 602 according to the output of the first delay adjustment circuit 601. The second selector 611 selects the output of the first delay adjustment circuit 601 and the output of the third delay adjustment circuit 603 according to the input signal 650. An exclusive-NOR (EX-NOR) circuit 612 obtains an exclusive logical product of outputs of the first and second selectors 610 and 611, and outputs an output signal 660.
[0040]
Here, the first selector 610 is controlled by the output of the first delay adjustment circuit 601, but the output of the third delay adjustment circuit 603 or the output of the first and third delay adjustment circuits 601 and 603 is controlled. A similar effect can be obtained by controlling both. Similarly, the same effect can be obtained even if the second selector 611 is controlled by one or both of the input signal 650 and the second delay adjustment circuit 602. FIG. 12 shows operation waveforms of each unit shown in FIG.
[0041]
An input signal 650 having an operating frequency f (cycle time c = 1 / f) is input to the first, second, and third three delay adjustment circuits 601, 602, and 603 (FIG. 12A). The input signal 650 is supplied by a delay adjustment circuit (not shown), and is a signal whose rising edge can be adjusted in waveform. As a result of the input signal 650 being input to the first, second and third delay adjustment circuits 601, 602 and 603, the first, second and third internal signals having the frequency f are converted to the first, second and third delay adjustment circuits. Output from 601 602 603
(FIGS. 12 (B), (D), (F)). FIG. 12C is a signal delayed by 2/4 cycle of the input signal 650, and FIG. 12E is a signal delayed by 3/4 cycle of the input signal 650.
[0042]
The input signal 650 and the output signals (internal signals) of the first, second, and third delay adjustment circuits 601, 602, and 603 are integrated by the first and second selectors 610 and 611. That is, the input signal 650 and the output signal of the second delay adjustment circuit 602 are integrated by the first selector 610, and the output signal of the first delay adjustment circuit 601 and the output signal of the third delay adjustment circuit 603 are combined. Integration is performed by the second selector 611.
[0043]
Here, the first selector 610 operates to select the input signal 650 during a period when the output signal of the first delay adjustment circuit 601 is at a low level and to select an output signal from the delay adjustment circuit 602 during a period when the output signal is at a high level. I do. The second selector 611 operates so as to select the output signal of the delay adjustment circuit 603 during a period when the input signal 650 is at a low level and to select the output signal from the delay adjustment circuit 601 during a period when the input signal 650 is at a high level. As a result, an integrated signal of the input signal 650 and the output signal of the second delay adjustment circuit 602 is output from the first selector 610 (FIG. 12G), and the first selector 611 outputs the first signal. A signal in which the output signal of the delay adjustment circuit 601 and the output signal of the third delay adjustment circuit 603 are integrated is output (FIG. 12H).
[0044]
A logical operation is performed on the output signal of the first selector 610 and the output signal of the second selector 611 by the exclusive-OR circuit 612 to generate a signal (clock) having a frequency twice as high as the operating frequency f of the input signal 650. (FIG. 12 (I)).
[0045]
According to the clock generation circuit according to the fifth embodiment of the present invention, the reference clock is input, the value of the internal register of the semiconductor integrated circuit device, the value of the internal memory, the internal logic signal, or the external signal , The outputs of the first, second, and third delay adjustment circuits capable of adjusting the delay time are integrated by the first and second selectors, and the outputs of these selectors are mutually exclusive by the logic circuit Since a logical AND operation is performed, a clock having a free duty ratio can be generated regardless of the duty ratio of the reference clock which is an input signal.
[0046]
Next, FIG. 13 shows a configuration of a clock generation circuit according to a sixth embodiment of the present invention. In the figure, the clock generation circuit according to the present embodiment can adjust the delay time by the value of the internal register of the semiconductor integrated circuit device, the value of the internal memory, the internal logic signal, or the external signal. The first, second, third, and fourth four delay circuits 700, 701, 702, and 703 and the input terminals of the delay adjustment circuits 700, 701, 702, and 703 are commonly connected, and the second and fourth A first selector 710 for selecting the output of the first or third delay adjustment circuit 700, 702 by one or both of the outputs of the delay adjustment circuits 701, 703, and a first selector 710 for selecting the output of the first and third delay adjustment circuits 700, 702; A second selector 711 for selecting an output of the second or fourth delay adjustment circuit 701 or 703 by one or both of the outputs, and an output of the first and second selectors 710 and 711 And a logic circuit 720 for obtaining an exclusive logical product.
[0047]
In FIG. 13, the first, second, third, and fourth four delay adjustment circuits 700, 701, 702, and 703 are commonly connected on the input side, and receive an input signal (a reference clock in this embodiment) 750. It is supposed to be. The output signals of the first, second, third, and fourth delay adjustment circuits 700, 701, 702, and 703 are each set to a target cycle time by one of a register inside the LSI, an internal signal, and an external signal. Is c, and the delay time between the selector and the exclusive-OR circuit is τ, the first delay adjustment circuit 700 determines (（c−τ) by one of the register inside the LSI, an internal signal, and an external signal. ) And the second delay adjustment circuit 701 is adjusted so as to have a delay time of (2 / 4c-τ). The third delay adjustment circuit 702 has a delay time of (3 / 4c−τ) and is adjusted so as to be inverted, and the fourth delay adjustment circuit 703 has a delay time of (c−τ) And adjusted to be inverted.
[0048]
The first selector 710 selects the output of the first delay adjustment circuit 700 and the output of the third delay adjustment circuit 702 according to the output signal of the second delay adjustment circuit 701. The second selector 711 selects the output of the second delay adjustment circuit 701 and the output of the fourth delay adjustment circuit 703 according to the output signal of the first delay adjustment circuit 700. An exclusive-NOR (EX-NOR) circuit 720 obtains an exclusive logical product of outputs of the first and second selectors 710 and 711, and outputs an output signal 760.
[0049]
Here, in the present embodiment, the first selector 710 is controlled by the output of the second delay adjustment circuit 701, but is controlled by one or both of the outputs of the second and fourth delay adjustment circuits 701 and 703. A similar effect can be obtained. Similarly, the same effect can be obtained even if the second selector 711 is controlled by one or both of the outputs of the first and third delay adjustment circuits 700 and 702.
[0050]
As described above, according to the clock generation circuit according to the sixth embodiment of the present invention, the reference clock is input, the value of the internal register of the semiconductor integrated circuit device, the value of the internal memory, the internal logic signal, or the external The outputs of the first, second, third, and fourth delay adjustment circuits capable of adjusting the delay time by the signal of (i) are integrated by the first and second selectors, and the outputs of these selectors are integrated. Is exclusive-ANDed by a logic circuit, so that a clock having a free duty ratio can be generated irrespective of the duty ratio of a reference clock which is an input signal.
[0051]
In another embodiment of the present invention, the basic configuration is as described above. For example, when a delay adjustment circuit adjusted to have a delay time of 1/2 of the cycle time is configured, 1/4 Two delay adjustment circuits adjusted to have the above delay time may be used, or a delay adjustment circuit capable of adjusting the delay that generates a minute delay time may be used.
[0052]
What is important here is the difference between the delay times generated by the respective delay adjustment circuits. The difference is set to 1 / n of the cycle time of the input waveform (clock waveform), and is n times or n / 2 times the input waveform. It is important to generate a waveform having a frequency of Furthermore, whether the delay adjustment circuit operates as an inverter or a buffer depends on whether the logic gate as a logic circuit provided at the output stage of the clock generation circuit is an exclusive OR or an exclusive AND. Is done. Therefore, either the positive logic or the negative logic may be used as the delay circuit. It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.
[0053]
【The invention's effect】
According to the delay adjustment circuit of the present invention, each gate is connected in series, and the first gate group for finely adjusting the delay time of the input signal is provided on the output side of a specific gate in the first gate group. A load capacitance connected through the first switch means and a second capacitance connected to the output side of the first gate group through the second switch means for coarsely adjusting the delay time of the input signal; The first and second gate groups are configured so as to adjust the delay time of the input signal by adjusting the load capacitance connected to the output side of a specific gate in the first gate group and the number of gate stages of the second gate group. Since it has the control means for controlling the second switch means, the delay time of the input signal can be adjusted by controlling the internal register value or the internal signal or the external signal of the semiconductor integrated circuit device.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a specific configuration of a delay adjustment circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an input / output relationship of the delay adjustment circuit shown in FIG. 1;
FIG. 3 is a timing chart showing output timings of a reference clock as an input signal and a clock as an output signal of the delay adjustment circuit in FIG. 2;
FIG. 4 is a circuit diagram showing a configuration of a clock generation circuit according to the first embodiment of the present invention.
FIG. 5 is a timing chart showing signals of respective units of the clock generation circuit shown in FIG. 4;
FIG. 6 is a circuit diagram of a semiconductor integrated circuit device in which a waveform of a clock having an adjustable specific edge generated by a clock generation circuit and a flip-flop operating at the timing of the specific edge of the clock are provided between logic gates. FIG.
FIG. 7 is a circuit diagram showing a configuration of a clock generation circuit according to a second embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a clock generation circuit according to a third embodiment of the present invention.
FIG. 9 is a timing chart illustrating signals of respective units of the clock generation circuit illustrated in FIG. 8;
FIG. 10 is a block diagram showing a configuration of a clock generation circuit according to a fourth embodiment of the present invention.
FIG. 11 is a circuit diagram showing a configuration of a clock forming circuit according to a fifth embodiment of the present invention.
FIG. 12 is a timing chart showing operation waveforms of each unit of the clock generation circuit shown in FIG. 11;
FIG. 13 is a circuit diagram showing a configuration of a clock generation circuit according to a sixth embodiment of the present invention.
FIG. 14 is a block diagram showing a configuration of a PLL circuit used in a conventional clock generation circuit.
[Explanation of symbols]
10 First gate group
11-14 Inverter
20 Second gate group
21-23 Inverter chain
30 register group (control means)
40-43, 50-53 Transfer gate (first switch means)
80-83 transfer gate (second switch means)
300, 302, 303, 400, 410 delay adjustment circuit
301, 304, 420 logic circuit
400 clock generation circuit
412 registers
414 Variable delay circuit
430 detection circuit
440 control circuit
500 Reference clock generation circuit
510 distribution circuit
601, 602, 603 delay adjustment circuit
610, 611 selector
612 Exclusive AND circuit

Claims (2)

A first gate group in which each gate is connected in series to finely adjust a delay time of an input signal;
A first load capacitance connected to an output side of a specific gate in the first gate group via a first transfer switch;
A second load capacitance connected to a gate output side of the next stage of the specific gate via a second transfer switch;
A second group of gates connected to an output side of the first group of gates via switch means for coarsely adjusting the delay time of the input signal;
The first and second transfer gates and the switch means are adjusted so as to adjust the delay time of the input signal by adjusting the first and second load capacitances and the number of gate stages of the second gate group. Control means for controlling,
The control means includes a register provided in the semiconductor integrated circuit device and capable of setting an output value by an internal signal,
The switching control of the first and second transfer gates and the switch means based on a register value set in the register adjusts a gate output load and the number of gate stages of the second gate group. Delay adjustment circuit. A first gate group in which each gate is connected in series to finely adjust a delay time of an input signal;
A first load capacitance connected to an output side of a specific gate in the first gate group via a first transfer switch;
A second load capacitance connected to a gate output side of the next stage of the specific gate via a second transfer switch;
A second group of gates connected to an output side of the first group of gates via switch means for coarsely adjusting the delay time of the input signal;
The first and second transfer gates and the switch means are adjusted so as to adjust the delay time of the input signal by adjusting the first and second load capacitances and the number of gate stages of the second gate group. Control means for controlling,
The control means includes a register provided in the semiconductor integrated circuit device and capable of externally setting an output value by initialization.
The switching control of the first and second transfer gates and the switch means based on a register value set in the register adjusts a gate output load and the number of gate stages of the second gate group. Delay adjustment circuit.

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