JP2011061176A - プリント基板の製造方法 - Google Patents
プリント基板の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 claims abstract description 103
- 229910000679 solder Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 185
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 28
- 239000011889 copper foil Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 239000012790 adhesive layer Substances 0.000 claims description 25
- 238000007747 plating Methods 0.000 claims description 22
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 239000002335 surface treatment layer Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 79
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- 230000009977 dual effect Effects 0.000 description 4
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- 238000004804 winding Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4685—Manufacturing of cross-over conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
【解決手段】(A)一面に第1パターン部140が形成された第1キャリア部を製造する段階、(B)一面に第1ソルダレジスト層230及び第2パターン部240,260が順次形成された第2キャリア部を製造する段階、(C)絶縁層の一面に第1パターン部140が埋め込まれ、絶縁層300の他面に第2パターン部240,260が埋め込まれるように、第1キャリア部と第2キャリア部を絶縁層300に加圧した後、第1キャリア部と第2キャリア部を除去してベース基板を製造する段階、(D)接着層400を使って、第1ソルダレジスト層230が対面するように、二つのベース基板を付着する段階、及び(E)絶縁層300に、第1パターン部と第2パターン部を連結するビアを形成し、第1パターン部140が形成された絶縁層300に第2ソルダレジスト層を形成した後、接着層400を除去する段階を含む。
【選択図】図18
Description
120、220 銅箔層
130 メタルバリア層
140 第1パターン部
230 第1ソルダレジスト層
240 シード層(第2パターン部)
260 メッキ層(第2パターン部)
300 絶縁層
400 接着層
500 ビア
600 第2ソルダレジスト層
Claims (12)
- (A)一面に第1パターン部が形成された第1キャリア部を製造する段階;
(B)一面に第1ソルダレジスト層及び第2パターン部が順次形成された第2キャリア部を製造する段階;
(C)絶縁層の一面に前記第1パターン部が埋め込まれ、前記絶縁層の他面に前記第2パターン部が埋め込まれるように、前記第1キャリア部と前記第2キャリア部を前記絶縁層に加圧した後、前記第1キャリア部と前記第2キャリア部を除去してベース基板を製造する段階;
(D)接着層を使って、前記第1ソルダレジスト層が対面するように、二つの前記ベース基板を付着する段階;及び
(E)前記絶縁層に、前記第1パターン部と前記第2パターン部を連結するビアを形成し、前記第1パターン部が形成された前記絶縁層に第2ソルダレジスト層を形成した後、前記接着層を除去する段階;
を含むことを特徴とするプリント基板の製造方法。 - 前記(A)段階が、
(A1)テープの片面または両面に銅箔層及びメタルバリア層を順次形成する段階;
(A2)前記メタルバリア層に第1パターン部を形成する段階;及び
(A3)前記テープを除去して、前記第1パターン部が一面に形成された、前記メタルバリア層及び前記銅箔層でなった第1キャリア部を製造する段階;
を含むことを特徴とする請求項1に記載のプリント基板の製造方法。 - 前記(B)段階が、
(B1)テープの片面または両面に銅箔層及び第1ソルダレジスト層を順次形成する段階;
(B2)前記第1ソルダレジスト層にシード層を形成する段階;
(B3)前記シード層にメッキ層を形成し、前記シード層及び前記メッキ層をパターニングして第2パターン部を形成する段階;及び
(B4)前記テープを除去して、前記第1ソルダレジスト層と前記第2パターン部が一面に形成された銅箔層でなった第2キャリア部を製造する段階;
を含むことを特徴とする請求項1に記載のプリント基板の製造方法。 - 前記(E)段階で、
前記接着層を除去するに先立ち、前記第2ソルダレジスト層にオープン部を形成し、前記オープン部を通じて露出された前記第1パターン部に表面処理層を形成することを特徴とする請求項1に記載のプリント基板の製造方法。 - 前記(E)段階の後に、
(F1)前記第1ソルダレジスト層にオープン部を形成する段階;及び
(F2)前記オープン部によって露出された前記第2パターン部に表面処理層を形成する段階;
をさらに含むことを特徴とする請求項1に記載のプリント基板の製造方法。 - 前記接着層が、熱処理の際に非接着性を有する熱接着剤でなることを特徴とする請求項1に記載のプリント基板の製造方法。
- (A)一面に第1パターン部が形成されたキャリア部を製造する段階;
(B)接着層の両面に第1ソルダレジスト層及び第2パターン部を順次形成して媒介基板を製造する段階;
(C)前記媒介基板の両側に、絶縁層と前記第1パターン部が対面するように、前記キャリア部を配置した後、熱圧着する段階;
(D)前記キャリア部を除去し、前記絶縁層に、前記第1パターン部と前記第2パターン部を連結するビアを形成した後、前記第2パターン部が形成された前記絶縁層に第2ソルダレジスト層を形成する段階;及び
(E)前記接着層を除去する段階;
を含むことを特徴とするプリント基板の製造方法。 - 前記(A)段階が、
(A1)テープの片面または両面に銅箔層及びメタルバリア層を順次形成する段階;
(A2)前記メタルバリア層に第1パターン部を形成する段階;及び
(A3)前記テープを除去して、前記第1パターン部が一面に形成された、前記メタルバリア層及び前記銅箔層でなったキャリア部を製造する段階;
を含むことを特徴とする請求項7に記載のプリント基板の製造方法。 - 前記(B)段階が、
(B1)接着層に第1ソルダレジスト層を形成する段階;
(B2)前記第1ソルダレジスト層にシード層を形成する段階;及び
(B3)前記シード層にメッキ層を形成し、前記シード層及び前記メッキ層をパターニングして第2パターン部を形成する段階;
を含むことを特徴とする請求項7に記載のプリント基板の製造方法。 - 前記(D)段階の後に、
(D1)前記第2ソルダレジスト層にオープン部を形成する段階;及び
(D2)前記オープン部によって露出された前記第1パターン部に表面処理層を形成する段階;
をさらに含むことを特徴とする請求項7に記載のプリント基板の製造方法。 - 前記(E)段階の後に、
(F1)前記第1ソルダレジスト層にオープン部を形成する段階;及び
(F2)前記オープン部によって露出された前記第2パターン部に表面処理層を形成する段階;
をさらに含むことを特徴とする請求項7に記載のプリント基板の製造方法。 - 前記接着層が、熱処理の際に非接着性を有する熱接着剤でなることを特徴とする請求項7に記載のプリント基板の製造方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2009-0086445 | 2009-09-14 | ||
| KR1020090086445A KR101022873B1 (ko) | 2009-09-14 | 2009-09-14 | 인쇄회로기판의 제조방법 |
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| Publication Number | Publication Date |
|---|---|
| JP2011061176A true JP2011061176A (ja) | 2011-03-24 |
| JP4848451B2 JP4848451B2 (ja) | 2011-12-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2009274579A Expired - Fee Related JP4848451B2 (ja) | 2009-09-14 | 2009-12-02 | プリント基板の製造方法 |
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| Country | Link |
|---|---|
| US (2) | US8881381B2 (ja) |
| JP (1) | JP4848451B2 (ja) |
| KR (1) | KR101022873B1 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190069164A (ko) * | 2017-12-11 | 2019-06-19 | 주식회사 심텍 | 양면 임베디드 회로를 갖는 인쇄회로기판 및 그 제조 방법 |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012021197A2 (en) * | 2010-05-21 | 2012-02-16 | Arizona Board Of Regents, For And On Behalf Of Arizona State University | Method of manufacturing electronic devices on both sides of a carrier substrate and electronic devices thereof |
| US8502391B2 (en) | 2011-12-08 | 2013-08-06 | Stats Chippac, Ltd. | Semiconductor device and method of making single layer substrate with asymmetrical fibers and reduced warpage |
| KR101489159B1 (ko) * | 2011-12-23 | 2015-02-05 | 주식회사 잉크테크 | 금속 인쇄회로기판의 제조방법 |
| JP2013157366A (ja) * | 2012-01-27 | 2013-08-15 | Kyocer Slc Technologies Corp | 配線基板およびそれを用いた実装構造体 |
| KR101466759B1 (ko) * | 2012-11-07 | 2014-11-28 | 주식회사 잉크테크 | 금속 인쇄회로기판의 제조방법 |
| KR20140118161A (ko) * | 2013-03-28 | 2014-10-08 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판 제조 방법 |
| JP2015231003A (ja) * | 2014-06-06 | 2015-12-21 | イビデン株式会社 | 回路基板および回路基板の製造方法 |
| CN105451430A (zh) * | 2014-09-02 | 2016-03-30 | 富葵精密组件(深圳)有限公司 | 部分内埋式线路结构及其制造方法 |
| CN112165773B (zh) * | 2020-10-07 | 2022-10-11 | 广州添利电子科技有限公司 | 一种埋线路的方式制作图形的工艺 |
| JP2022119655A (ja) * | 2021-02-04 | 2022-08-17 | イビデン株式会社 | 配線基板 |
| CN113597118B (zh) * | 2021-09-28 | 2021-12-31 | 深圳和美精艺半导体科技股份有限公司 | 一种无电镀导线镀金工艺方法 |
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| KR100979818B1 (ko) * | 2007-12-13 | 2010-09-06 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
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- 2009-09-14 KR KR1020090086445A patent/KR101022873B1/ko not_active Expired - Fee Related
- 2009-12-02 JP JP2009274579A patent/JP4848451B2/ja not_active Expired - Fee Related
- 2009-12-04 US US12/631,594 patent/US8881381B2/en not_active Expired - Fee Related
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2013
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| JPH1126938A (ja) * | 1997-06-30 | 1999-01-29 | Matsushita Electric Works Ltd | 内層回路入り積層板の製造方法 |
| JP2005243999A (ja) * | 2004-02-27 | 2005-09-08 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
| JP2007173459A (ja) * | 2005-12-21 | 2007-07-05 | Ibiden Co Ltd | プリント配線板の製造方法 |
| JP2008109140A (ja) * | 2006-10-25 | 2008-05-08 | Samsung Electro-Mechanics Co Ltd | 回路基板及びその製造方法 |
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| KR20190069164A (ko) * | 2017-12-11 | 2019-06-19 | 주식회사 심텍 | 양면 임베디드 회로를 갖는 인쇄회로기판 및 그 제조 방법 |
| KR102021772B1 (ko) * | 2017-12-11 | 2019-09-17 | 주식회사 심텍 | 양면 임베디드 회로를 갖는 인쇄회로기판 및 그 제조 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101022873B1 (ko) | 2011-03-16 |
| US8881381B2 (en) | 2014-11-11 |
| US20140090245A1 (en) | 2014-04-03 |
| US20110061231A1 (en) | 2011-03-17 |
| JP4848451B2 (ja) | 2011-12-28 |
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