JP2015064392A - Plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display device in which a slope voltage is generated while suppressing power consumption of a drive circuit in the plasma display device.SOLUTION: A plasma display device includes: a plasma display panel where a plurality of discharge cells each having a scanning electrode, a sustaining electrode, and a data electrode are arranged; and a scanning electrode drive circuit where a drive voltage waveform to be applied to the scanning electrode is generated. The scanning electrode drive circuit includes a downward slope voltage unit 63 composed of a mirror integration circuit and a power recovery unit 65 where an inductor L65, a diode D65, and a switching element Q65 are connected in series. By closing the switching element Q65, and resonating a load capacitor Cp of the scanning electrode and the inductor L65, a voltage of the scanning electrode is lowered down to a first voltage. Thereafter, the voltage of the scanning electrode is lowered from the first voltage to a second voltage using the downward slope voltage unit 63.

Description

  The present invention relates to an AC surface discharge type plasma display device.

  A typical plasma display panel (hereinafter abbreviated as “panel”) as a display device includes a front substrate on which a plurality of display electrode pairs each composed of a pair of scan electrodes and sustain electrodes are formed, and a plurality of data electrodes. A plurality of discharge cells are formed between the rear substrate and the rear substrate. Then, ultraviolet rays are generated by gas discharge in the discharge cell, and the phosphors of red, green and blue colors are excited and emitted by the ultraviolet rays to perform color display.

  As a method for driving the panel, a subfield method in which one field period is divided into a plurality of subfields and gray levels are displayed by a combination of subfields to emit light is generally used. Each subfield has an initialization period, an address period, and a sustain period. During the initialization period, a slowly changing ramp voltage is applied to the scan electrodes to generate a weak initialization discharge, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. To display an image.

  Here, the sustain pulse applied to the display electrode pair in the sustain period is a so-called power recovery circuit that drives the display electrode pair by resonating the interelectrode capacitance of the display electrode pair and the inductor in order to reduce power consumption. (See, for example, Patent Document 1).

  In addition, the ramp voltage applied to the scan electrode in the initialization period is generated using a Miller integration circuit (see, for example, Patent Document 2).

JP 11-242458 A Japanese Patent Laid-Open No. 11-133914

  However, when the ramp voltage is generated using the Miller integration circuit, there is a problem that the power consumption increases when the Miller integration circuit is operated over a wider voltage range than necessary. Furthermore, with the recent increase in screen size of panels, this increase in power consumption cannot be ignored. Since the Miller integrating circuit uses semiconductor elements in the active region, it cannot be used to disperse power consumption by connecting the semiconductor elements in parallel unless semiconductor elements having completely the same characteristics are used. Therefore, when power is increased, usable semiconductor elements are limited, and the heat dissipation design becomes difficult.

  The present invention has been made in view of the above problems, and an object thereof is to provide a plasma display device driving method and a plasma display device having a driving circuit capable of generating a ramp voltage while suppressing power consumption. .

  To achieve the above object, the present invention includes a plasma display panel in which a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode are arranged, and a scan electrode drive circuit that generates a drive voltage waveform applied to the scan electrode. The scan electrode driving circuit includes a descending ramp voltage unit configured by a Miller integrating circuit, and a power recovery unit in which an inductor, a diode, and a switching element are connected in series, and the switching element is closed. The load capacitance of the scan electrode and the inductor are resonated to lower the scan electrode voltage to the first voltage, and then the scan electrode voltage is changed from the first voltage to the second voltage using the descending ramp voltage unit. It is characterized by lowering. With this configuration, it is possible to provide a plasma display device including a drive circuit capable of generating a ramp voltage while suppressing power consumption.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the plasma display apparatus provided with the drive circuit which can generate | occur | produce a ramp voltage, suppressing power consumption.

It is a disassembled perspective view of the panel of the plasma display apparatus in embodiment of this invention. It is an electrode array figure of the panel of the plasma display apparatus. It is a drive voltage waveform figure of the plasma display apparatus. It is a circuit block diagram of the plasma display device. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. FIG. 3 is a circuit diagram of a downward ramp voltage unit and a power recovery unit of the plasma display device. It is a timing chart which shows the detail of the downward ramp voltage of the plasma display apparatus.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view of panel 10 of the plasma display device in accordance with the exemplary embodiment of the present invention. On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. In the present embodiment, a discharge gas with a xenon partial pressure of 10% is used to improve luminance. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

  As described above, the panel in the present embodiment has a configuration in which a plurality of discharge cells each having scan electrode 12 and sustain electrode 13 are arranged. The panel 10 is not limited to the one described above, and may be provided with, for example, striped partition walls.

  FIG. 2 is an electrode array diagram of panel 10 of the plasma display device in accordance with the exemplary embodiment of the present invention. In the panel 10, n scanning electrodes 12 and n sustain electrodes 13 that are long in the row direction are arranged, and m data electrodes 22 that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode 12 and sustain electrode 13 intersects with one data electrode 22, and m × n discharge cells are formed in the discharge space. As shown in FIGS. 1 and 2, since scan electrode 12 and sustain electrode 13 are formed in parallel with each other, a large gap is formed between scan electrode 12 and sustain electrode 13. There is a capacitance, and there is also an interelectrode capacitance between the scan electrode 12 and the data electrode 22 and between the sustain electrode 13 and the data electrode 22. Therefore, each of the scan electrode 12, the sustain electrode 13, and the data electrode 22 becomes a capacitive load. Hereinafter, the load capacitance of the scan electrode 12 is particularly referred to as a capacitance Cp.

  Next, a driving method for driving the panel 10 will be described. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, at least one of a slowly increasing ramp voltage and a slowly decreasing ramp voltage is applied to the scan electrode to generate a weak initialization discharge, and wall charges necessary for the subsequent address discharge are applied to each electrode. Form. The initializing operation at this time includes a forced initializing operation in which initializing discharge is forcibly generated in all the discharge cells, and a selective initial in which initializing discharge is generated in the discharge cell in which the sustain discharge is generated in the immediately preceding subfield. There is an operation. In the address period, a scan pulse is applied to the scan electrode 12 and an address pulse is selectively applied to the data electrode 22 to selectively generate an address discharge in the discharge cells to be lit to form wall charges. In the sustain period, a number of sustain pulses corresponding to the luminance weight are alternately applied to the scan electrode 12 and the sustain electrode 13 to generate a sustain discharge in the discharge cells that have generated the address discharge to emit light.

  In the present embodiment, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is, for example, (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). Further, the subfield SF1 is a subfield for performing a forced initialization operation, and the subsequent subfields SF2 to SF10 are subfields for performing a selective initialization operation. However, in the present invention, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 3 is a drive voltage waveform diagram of the plasma display device in accordance with the exemplary embodiment of the present invention, and shows the drive voltage waveform applied to each electrode of panel 10 in each subfield.

  In the first half of the initialization period Ti of the subfield SF1, the voltage 0 (V) is applied to the data electrode 22, and the voltage 0 (V) is applied to the sustain electrode 13. Then, a ramp voltage that gradually increases from the voltage Vi1 toward the voltage Vi2 is applied to the scan electrode 12. While this ramp voltage rises, a weak initializing discharge occurs between the scan electrode 12, the sustain electrode 13, and the data electrode 22, and a wall voltage is accumulated on each electrode. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the second half of the initialization period Ti, a positive voltage Ve is applied to the sustain electrode 13, and a ramp voltage that gradually decreases from the voltage Vi3 toward the voltage Vi4 is applied to the scan electrode 12. Then, a weak initializing discharge occurs again during this period, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  As described above, in the initialization period Ti of the subfield SF1, the forced initialization operation for forcibly generating the initialization discharge in all the discharge cells is performed.

  In the address period Tw of the subfield SF1, the voltage Vc is applied to the scan electrode 12.

  Next, a scan pulse having a negative voltage Va is applied to the scan electrode 12 in the first row. Then, an address pulse of a positive voltage Vd is applied to the data electrode 22 of the discharge cell that should emit light in the first row of the data electrode 22. Then, in the discharge cells in the first row, address discharge occurs in the discharge cells to which the address pulse is applied, and an address operation for accumulating wall voltage on each electrode is performed. On the other hand, no address discharge occurs in the discharge cells to which no address pulse is applied. In this way, the write operation is selectively performed.

  Next, a scan pulse is applied to the scan electrode 12 in the second row, and an address pulse is applied to the data electrode 22 of the discharge cell that should emit light in the second row of the data electrodes 22. Then, address discharge occurs selectively in the discharge cells in the second row. The above address operation is performed up to the discharge cell in the nth row.

  In sustain period Ts of subfield SF1, voltage 0 (V) is applied to sustain electrode 13, and a sustain pulse of voltage Vs is applied to scan electrode 12. Then, a sustain discharge is generated in the discharge cell that has caused the address discharge in the address period Tw.

  Next, a sustain pulse of voltage Vs is applied to sustain electrode 13, and voltage 0 (V) is applied to scan electrode 12. Then, the sustain discharge occurs again in the discharge cells that have caused the address discharge in the address period Tw.

  Similarly, sustain pulses are alternately applied to scan electrode 12 and sustain electrode 13 in the number corresponding to the luminance weight. As a result, the sustain discharge is continuously generated in the discharge cells that have caused the address discharge in the address period Tw.

  Then, at the end of the sustain period Ts, the sustain electrode 13 is returned to the voltage 0 (V), and then an upward ramp voltage that gradually rises to the voltage Vr is applied to the scan electrode 12. Then, a weak discharge occurs in the discharge cell in which the sustain discharge has occurred, and the wall voltage between the scan electrode 12 and the sustain electrode 13 is weakened. Thereafter, the voltage applied to the scan electrode 12 is returned to the voltage 0 (V).

  In the subsequent initialization period Ti of the subfield SF2, the details will be described later, but the voltage of the scan electrode 12 is first lowered to the first voltage (-2Vx), and then the first voltage (-2Vx) to the second voltage. To the voltage Vi4. Then, a weak initializing discharge is generated in the discharge cells that have undergone the sustain discharge in the sustain period Ts of the subfield SF1, and the wall voltage on each electrode is adjusted to a value suitable for the address operation. As described above, in the initializing period Ti of the subfield SF2, the selective initializing operation for generating the initializing discharge in the discharge cell in which the sustain discharge has been performed is performed.

  The subsequent address period Tw and sustain period Ts are substantially the same except for the address period Tw and sustain period Ts of the subfield SF1 and the number of sustain pulses, and thus description thereof is omitted. Subsequent subfields SF3 to SF10 are similar to the operation of subfield SF2 except for the number of sustain pulses.

  In this embodiment, the voltage values applied to the electrodes are, for example, voltage Vi1 = 150 (V), voltage Vi2 = 370 (V), voltage Vi3 = 0 (V), voltage Vi4 = −170 (V). , Voltage Vc = −50 (V), voltage Va = −200 (V), voltage Vs = 220 (V), voltage Vr = 220 (V), voltage Ve = 150 (V), voltage Vd = 60 (V) It is. However, these voltage values are merely an example, and it is desirable to set them to optimum values as appropriate according to the characteristics of the panel, the specifications of the plasma display device 30, and the like.

  FIG. 4 is a circuit block diagram of plasma display device 30 according to the first exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 31 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 32 converts the image data for each subfield into an address pulse corresponding to each data electrode 22 and drives each data electrode 22. The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the respective circuit blocks. The scan electrode drive circuit 33 drives each scan electrode 12 based on the timing signal. Sustain electrode drive circuit 34 drives sustain electrode 13 based on the timing signal.

  FIG. 5 is a circuit diagram of scan electrode drive circuit 33 of plasma display device 30 in accordance with the exemplary embodiment of the present invention. FIG. 5 also shows the load capacitance Cp of the scan electrode of the panel 10 for later explanation. Scan electrode drive circuit 33 includes sustain pulse generator 50, ramp voltage generator 60, and scan pulse generator 70.

  Sustain pulse generation unit 50 includes a power recovery unit 51 and a clamp unit 56.

  The power recovery unit 51 includes a capacitor C51, an inductor L51, switching elements Q51 and Q52, and diodes D51 to D54. The sustaining pulse rises or falls by resonating the load capacitance Cp and the inductor L51. At the rising edge of the sustain pulse, switching element Q51 is turned on, and charge is transferred from capacitor C51 to load capacitance Cp via inductor L51 and switching element Q51. When the sustain pulse falls, the switching element Q52 is turned on, and the charge of the load capacitance Cp is returned to the capacitor C51 via the diode D51 and the inductor L51. In this way, the power recovery unit 51 drives the scan electrode 12 by resonance without being supplied with power from the power source, so that the power consumption is ideally “0”. The diode D53 and the diode D54 are diodes that absorb spike voltages generated in the inductor L51. The capacitor C51 has a sufficiently large capacity compared to the load capacity Cp, is charged to a voltage (Vs / 2), and functions as a power source for the power recovery unit 51.

  The clamp part 56 has switching elements Q56 and Q57 and diodes D56 and D57. Then, the switching element Q56 is turned on to clamp the scan electrode 12 to the voltage Vs, and the switching element Q57 is turned on to clamp the scan electrode 12 to the voltage 0 (V). Thus, the clamp unit 56 clamps the sustain pulse voltage to the voltage Vs or the voltage 0 (V). Therefore, the impedance at the time of voltage application by the clamp part 56 is small, and a large discharge current due to a strong sustain discharge can be flowed stably. The diode D56 and the diode D57 are provided to bypass the reverse current.

  Then, the power recovery unit 51 and the clamp unit 56 output a sustain pulse to the reference potential of the scan pulse generation unit 70 (the potential of the node P70 shown in FIG. 5). The sustain pulse shown in FIG. 3 is applied to the scan electrode 12 through

  Scan pulse generating unit 70 includes power supply E71, switching elements Q71H1 to Q71Hn, switching elements Q71L1 to Q71Ln, and switching element Q72. Then, a scan pulse is generated based on the power source of voltage Va and the power source E71 of voltage Vp superimposed on the reference potential of the scan pulse generator 70. The voltage (Vp + Va) is applied to the scan electrode 12 by turning on the switching element Q72 and turning on the switching element Q71Hi. Here, the voltage (Vp + Va) is equal to the voltage Vc. In addition, the voltage Va is applied to the scan electrode 12 by turning on the switching element Q72 and turning on the switching element Q71Li. In this way, scanning pulses are sequentially applied at the timing shown in FIG. By turning off switching element Q72, the output voltage of sustain pulse generating unit 50 or the output voltage of ramp voltage generating unit 60 described later is output as it is or with voltage Vp superimposed. That is, the voltage of the node P70 or a voltage obtained by superimposing the voltage Vp on the voltage of the node P70 is applied to the scan electrode 12.

  The ramp voltage generation unit 60 includes an up ramp voltage unit 61, a down ramp voltage unit 63, and a power recovery unit 65, and generates the ramp voltage shown in FIG. The rising ramp voltage unit 61 is configured by a Miller integrating circuit having a transistor Q61, a capacitor C61, and a resistor R61, and generates a rising ramp voltage that rises toward the voltage Vr by applying a constant voltage to the input terminal IN61. To do. For example, when the switching elements Q71H1 to Q71Hn are turned on to operate the rising ramp voltage unit 61, the rising ramp voltage rising toward the voltage (Vr + Vp) is increased as shown in the first half of the initialization period Ti of the subfield SF1. Can be generated. Here, the voltage (Vr + Vp) is equal to the voltage Vi2. Further, when switching element Q71L1 to Q71Ln is turned on to operate rising ramp voltage unit 61, an rising ramp voltage rising toward voltage Vr is generated as shown in sustain period Ts of subfields SF1 to SF3. it can.

  FIG. 6 is a circuit diagram of down-gradient voltage unit 63 and power recovery unit 65 of plasma display device 30 in accordance with the exemplary embodiment of the present invention. The descending ramp voltage unit 63 includes a Miller integrating circuit having a power source E63 having a voltage Vi4, a transistor Q63, a capacitor C63, and a resistor R63, and performs a selective initialization operation by applying a constant voltage to the input terminal IN63. In the initialization period Ti of the subfields SF2 to SF8, a downward ramp voltage that decreases toward the voltage Vi4 is generated.

  The power recovery unit 65 includes a power source E65 having a voltage Vx, an inductor L65, a diode D65, and a switching element Q65, which are connected in series between the node P70 and the ground potential. The voltage Vx is a voltage whose absolute value is lower than the voltage (Vi4 / 2). Then, by turning on the switching element Q65, the load capacitance Cp of the scan electrode 12 and the inductor L65 are resonated, and the voltage at the node P70 is lowered to a predetermined voltage. In the present embodiment, the voltage at node P70 is lowered from voltage 0 (V) to around the voltage (-2Vx) in initialization period Ti of subfields SF2 to SF8 in which the selective initialization operation is performed.

  The switching element Q69 of the ramp voltage generator 60 is a separation switch, and is provided to prevent a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 33.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 35.

  As described above, the scan electrode drive circuit 33 in the present embodiment includes the downward ramp voltage unit 63 configured by the Miller integrating circuit, and the power recovery unit 65 in which the inductor L65, the diode D65, and the switching element Q65 are connected in series. And a downward ramp voltage is applied to the scan electrode 12.

  Next, details of the downward ramp voltage applied to the scan electrode 12 in the initialization period Ti of the subfields SF2 to SF10 in which selective initialization is performed will be described. FIG. 7 is a timing chart showing details of the downward ramp voltage of the plasma display device 30 in the embodiment of the present invention, and also shows the current flowing through the inductor L65 at that time.

  Here, the initialization period Ti of the subfields SF2 to SF10 is divided into four periods of a period T11 to a period T14, and each period will be described in detail.

  Immediately before the initialization period Ti, that is, at the end of the sustain period Ts, the voltage 0 (V) is applied to the scan electrode 12. Therefore, the node P70 has a voltage of 0 (V), and the voltages at the nodes P65 and P66 at both terminals of the inductor L65 are the voltage Vx.

(Period T11)
At time t11, the switching element Q65 of the power recovery unit 65 is turned on. Then, the node P66 becomes a voltage 0 (V), and current starts to flow through the inductor L65. Since this current flows from the scan electrode 12 to the ground potential through the switching elements Q71L1 to Q71Ln, the power source E65, the inductor L65, the diode D65, and the switching element Q65, the voltage of the scan electrode 12 starts to decrease.

  After ¼ of the resonance period of the inductor L65 and the load capacitance Cp, the absolute value of the current flowing through the inductor L65 becomes maximum, and the voltage of the scan electrode 12 drops to almost the voltage (−Vx). After that, the absolute value of the current flowing through the inductor L65 begins to decrease, and the voltage of the scan electrode 12 decreases beyond the voltage (−Vx). Thus, in the first period T11, the load capacitance Cp and the inductor L65 are resonated to reduce the voltage of the scan electrode 12.

(Period T12)
At time t12 after ½ of the resonance period of the inductor L65 and the load capacitance Cp, the absolute value of the current flowing through the inductor L65 becomes “0”, and the voltage of the scan electrode 12 decreases to almost the voltage (−2 Vx). To do. Then, since the diode D65 prevents the reverse current flow, the voltage of the scan electrode 12 does not change.

(Period T13)
At time t13 after a predetermined time has elapsed from time t12, switching element Q65 is turned off. At this time, the voltage of the scan electrode 12, that is, the voltage of the node P70 remains near the voltage (-2Vx) and does not change.

(Period T14)
At time t14, a constant voltage is applied to the input terminal IN63 to operate the descending ramp voltage unit 63. Then, the voltage of the node P70, that is, the voltage of the scan electrode 12, gradually decreases from the voltage (−2Vx) to the voltage Vi4. Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has been performed in the sustain period Ts of the immediately preceding subfield, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  As described above, in the present embodiment, the down ramp voltage is not generated using only the down ramp voltage unit 63, but the switching element Q65 of the power recovery unit 65 is closed, and the load capacitance Cp and the inductor of the scan electrode 12 are closed. L65 is caused to resonate, and the voltage of the scan electrode 12 is lowered to the first voltage (−2 Vx). Thereafter, the Miller integrating circuit of the descending ramp voltage unit 63 is operated, and the voltage of the scan electrode 12 is changed to the first voltage. The voltage is decreased from (−2Vx) to the second voltage Vi4. Therefore, the voltage range for operating the down ramp voltage unit 63 can be narrowed, the selection range of semiconductor elements that can be used for the down ramp voltage unit 63 is widened, and the heat dissipation design is facilitated. A compact down-gradient voltage unit 63 can be realized using a general-purpose semiconductor element.

  In this embodiment, the period T11 is set to 10 μs, the period T12 is set to 2.5 μs, the period T13 is set to 0 μs, the period T14 is set to 30 μs, the first voltage (−2Vx) is set to the voltage −100 (V), The voltage Vi4 of 2 is set to a voltage −170 (V). However, the present invention is not limited to these values.

  Further, the other specific numerical values used in the embodiments are merely examples, and it is desirable to appropriately set the values appropriately according to the panel characteristics, the plasma display device specifications, and the like.

  The driving circuit of the present invention can generate a ramp voltage while suppressing power consumption, and is useful as a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 22 Data electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 50, 80 Sustain pulse generation part 51, 81 Power recovery unit 56, 86 Clamp unit 60 Ramp voltage generation unit 61 Up ramp voltage unit 63 Down ramp voltage unit 65 Power recovery unit 70 Scan pulse generation unit Cp Load capacitance L65 Inductor D65 Diode Q65 Switching element E65 Power supply

Claims (1)

A plasma display device comprising: a plasma display panel in which a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode are arranged; and a scan electrode driving circuit that applies a downward ramp voltage to the scan electrode,
The scan electrode driving circuit includes a falling ramp voltage unit configured by a Miller integrating circuit, and a power recovery unit in which an inductor, a diode, and a switching element are connected in series,
Closing the switching element of the power recovery unit to resonate the load capacitance of the scan electrode and the inductor to reduce the voltage of the scan electrode to a first voltage;
Thereafter, the Miller integrating circuit of the descending ramp voltage unit is operated to reduce the voltage of the scan electrode from the first voltage to the second voltage.

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