JP2010019960A - Plasma display apparatus and method of driving plasma display panel - Google Patents

Abstract

An address discharge is stably generated in a plasma display panel.
A first ramp voltage that gradually rises from an initial voltage is generated during an initialization period, and a second ramp voltage that rises with a steeper slope than the first ramp voltage is generated at the end of a sustain period. A scan electrode driving circuit 43 having a Miller integrating circuit 55 which is a ramp voltage generating circuit and a constant current generating circuit 60 is provided. The Miller integrating circuit 55 responds to a constant current input from the constant current generating circuit 60 to the Miller integrating circuit 55. The scan electrode driving circuit 43 includes a switching element Q21 formed of a MOSFET that switches the output current value of the constant current generation circuit 60, and a Zener diode D10 that is provided in the forward direction and applies an initial voltage to the first ramp voltage. And a switching element Q22 made of a MOSFET for electrically short-circuiting the Zener diode D10.
[Selection] Figure 5

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method for driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. During the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent addressing operation are formed on each electrode, and priming particles (excited particles for generating addressing discharge) for stably generating the address discharge. ).

  In the address period, a scan pulse voltage is applied to the scan electrode and an address pulse voltage is selectively applied to the data electrode to selectively generate an address discharge in a discharge cell to be displayed to form a wall charge (hereinafter referred to as a wall charge). This operation is also referred to as “writing”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which the light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display area that changes depending on the light emission not related to the image display (hereinafter abbreviated as “black luminance”) is only weak light emission in the all-cell initialization operation, High-contrast image display is possible (see, for example, Patent Document 1).

In the above-mentioned Patent Document 1, the pulse width of the last sustain pulse in the sustain period is made shorter than the pulse widths of the other sustain pulses, and so-called narrow erasure is performed to alleviate the potential difference due to wall charges between the display electrode pairs. It also describes the discharge. By this narrow erase discharge, the address operation in the address period of the subsequent subfield can be stabilized, and a plasma display device with a high contrast ratio can be realized.
JP 2000-242224 A

  In recent years, further miniaturization of discharge cells has been progressed with higher definition of panels. In this miniaturized discharge cell, it has been confirmed that a phenomenon called charge loss, in which wall charges are lost, is likely to occur, and when this charge loss occurs, discharge failure occurs and image display quality deteriorates, Or the problem that the applied voltage required for generation | occurrence | production of discharge raises arises.

  One of the main causes of charge loss is discharge variation during the address operation. For example, if the discharge variation during the address operation is large and the address discharge is generated strongly, the discharge cell that emits light and the non-light-emitting discharge cell are adjacent to each other when the discharge cell that emits light and the non-light-emitting discharge cell are adjacent to each other. May be taken away, resulting in loss of charge.

  Therefore, it is important to generate address discharge as stably as possible in order to prevent charge loss.

  On the other hand, in recent years, the panel has been further increased in screen size and resolution, and accordingly, the driving impedance of the panel tends to increase. When the drive impedance increases, waveform distortion such as ringing is likely to occur in the drive waveform generated from the panel drive circuit. The narrow erase discharge described above is intended to stabilize the address operation of the subsequent subfield. For example, if waveform distortion occurs in the drive waveform for generating the narrow erase discharge, the narrow erase discharge is performed. There is a possibility that the erasing discharge itself may be strongly generated. In such a case, there is a problem that it is difficult to stably generate the subsequent address discharge.

  The present invention has been made in view of such problems, and it is possible to stably generate an address discharge even in a panel having a large screen and a high definition, and a plasma display device and a panel having a high image display quality. An object is to provide a driving method.

  A plasma display device of the present invention is a panel having a plurality of scan electrodes driven by a subfield method in which a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field and displayed in gray scale, A second ramp voltage that generates a first ramp voltage that rises from the initial voltage during an initialization period of at least one subfield of one field and rises at a steeper slope than the first ramp voltage at the end of the sustain period And a scan electrode driving circuit having a constant current generating circuit for generating a constant current to be input to the ramp voltage generating circuit. The ramp voltage generating circuit is changed from the constant current generating circuit to the ramp voltage generating circuit. The scan electrode driving circuit includes a Zener diode that is provided in a forward direction with respect to the input constant current and applies an initial voltage to the first ramp voltage. A first switching element made of a MOSFET for switching the output current value of the current generating circuit, and a second switching element made of a MOSFET for electrically short-circuiting a Zener diode, the first switching element and the second switching element A first ramp voltage and a second ramp voltage are generated by switching between conduction and cutoff of the element.

  Thereby, even in a panel with a large screen and high definition, address discharge can be stably generated, and the image display quality of the panel can be improved. Further, it is possible to generate the first ramp voltage and the second ramp voltage having different gradients and ultimate potentials from one ramp voltage generation circuit.

  Further, the panel driving method of the present invention is based on a subfield method in which a panel having a plurality of scan electrodes is provided with a plurality of subfields each having an initialization period, an address period, and a sustain period in one field, and gradation display is performed. In addition to driving, a first ramp voltage rising from the initial voltage is generated during the initialization period of at least one subfield of one field, and rising at a steeper slope than the first ramp voltage at the end of the sustain period A driving method of a panel that is driven using a ramp voltage generation circuit that generates a second ramp voltage that is provided in a forward direction with respect to a constant current input to the ramp voltage generation circuit. A zener diode that applies an initial voltage to the first voltage generation circuit, a first switching element that includes a MOSFET that switches a current value of a constant current input to the ramp voltage generation circuit, A second switching element made of a MOSFET for electrically short-circuiting the diode, and switching the conduction / cutoff of the first switching element and the second switching element from one ramp voltage generating circuit to the first ramp Two different ramp voltages, ie, a voltage and a second ramp voltage, are generated.

  Thereby, even in a panel with a large screen and high definition, address discharge can be stably generated, and the image display quality of the panel can be improved. Further, it is possible to generate the first ramp voltage and the second ramp voltage having different gradients and ultimate potentials from one ramp voltage generation circuit.

  According to the present invention, it is possible to stably generate an address discharge even in a panel with a large screen and a high definition, and to provide a plasma display device with good image display quality and a method for driving the panel. Become.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. On the front plate 21 made of glass, a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. Note that the plasma display device in this embodiment is a subfield method, that is, one field is divided into a plurality of subfields on the time axis, luminance weights are set for each subfield, and each discharge cell is set for each subfield. It is assumed that gradation display is performed by controlling light emission / non-light emission.

  In this subfield method, for example, one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each subfield is 1, 2, 4, 8, 16, 32, A configuration having luminance weights of 64 and 128 can be adopted. In addition, in the initializing period of one subfield among a plurality of subfields, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed (hereinafter, the subfield for performing the all-cell initializing operation is referred to as a subfield for performing all-cell initializing operations). In the initializing period of other subfields, a selective initializing operation for selectively generating initializing discharge is performed for the discharge cells that have undergone sustain discharge (hereinafter referred to as “all-cell initializing subfield”). The subfield that performs the selective initialization operation is referred to as “selective initialization subfield”), and it is possible to reduce light emission not related to gradation display as much as possible and improve the contrast ratio.

  In the present embodiment, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the eighth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance, which is the luminance of the black display area that does not generate the sustain discharge, is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, the ramp voltage is generated at the end of the sustain period, thereby stabilizing the write operation in the subsequent subfield write period. Hereinafter, the outline of the drive voltage waveform will be described first, and then the configuration of the drive circuit will be described.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows scan electrode SC1 that scans first in the address period, scan electrode SCn that scans last in the address period (for example, scan electrode SC1080), sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data. The drive waveform of the electrode Dm is shown.

  FIG. 3 also shows driving voltage waveforms of two subfields, that is, a first subfield (first SF) that is an all-cell initializing subfield and a second subfield (second SF) that is a selective initializing subfield. It shows. The drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses generated in the sustain period is different. In addition, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from each electrode based on subfield data (data indicating light emission / non-light emission for each subfield).

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to each of the data electrode D1 to the data electrode Dm, the sustain electrode SU1 to the sustain electrode SUn, and the scan electrode SC1 to the scan electrode SCn starts from 0 (V). After the voltage Vsc is applied, a voltage Vi1 obtained by superimposing the accumulated voltage on the voltage Vsc is further applied. This accumulated voltage is generated by a Zener diode described later. At this time, the voltage Vi1 is set to a voltage equal to or lower than the discharge start voltage. Further, a first ramp voltage (hereinafter, referred to as a slope of about 1.3 V / μsec) that gradually increases from voltage Vi1 toward voltage Vi2 that exceeds the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. L1) (referred to as “up-ramp voltage”) is applied.

  In the first SF, the initialization period is shortened by generating the up-ramp voltage L1 from the voltage Vi1 obtained by superimposing the accumulated voltage on the voltage Vsc, compared to when generating the up-ramp voltage from the voltage Vsc. For example, if the accumulated voltage is 45 (V) and the slope of the up-ramp voltage L1 is 1.3 V / μsec, the time can be reduced by about 34.6 μsec. By assigning the reduced initializing period to the sustain period in this way, the number of sustain pulses generated can be increased and the image can be displayed brighter.

  While the rising ramp voltage L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. Each weak initializing discharge occurs continuously. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. Down-slope voltage (hereinafter referred to as “down-ramp voltage”) that gradually decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to negative voltage Vi4 that exceeds the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. ) Apply L2.

  During this time, weak initialization discharges occur between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm, respectively. . Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the subsequent address period, a scan pulse voltage is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = 1) corresponding to a discharge cell to emit light is applied to data electrode D1 through data electrode Dm. To m), a positive address pulse voltage Vd is applied to selectively generate an address discharge in each discharge cell.

  In the address period, first, voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, and (voltage Va + voltage Vsc) is applied to scan electrode SC1 through scan electrode SCn.

  The negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd−voltage Va) between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1. The difference is added and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Further, since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is maintained at a difference between externally applied voltages (voltage Ve2−voltage Va). The difference between the wall voltage on the electrode SU1 and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission.

  In this sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, thereby giving a potential difference between the electrodes of display electrode pair 24. As a result, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period.

  At the end of the sustain period, a second ramp voltage (hereinafter referred to as “erase ramp voltage”) that gradually increases from 0 (V), which is the base potential, to the voltage Vers is applied to scan electrode SC1 through scan electrode SCn. (Referred to as L3). As a result, a weak discharge is continuously generated, and some or all of the wall voltages on scan electrode SCi and sustain electrode SUi are erased while the positive wall voltage on data electrode Dk remains.

  Specifically, after the sustain electrode SU1 to the sustain electrode SUn are returned to 0 (V), the second ramp voltage rises from 0 (V) as the base potential toward the voltage Vers exceeding the discharge start voltage. The erasing ramp voltage L3 is generated with a steeper gradient than the up-ramp voltage L1, which is the first ramp voltage, for example, a gradient of about 10 V / μsec, and is applied to the scan electrodes SC1 to SCn. Then, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated while the voltage applied to scan electrode SC1 through scan electrode SCn increases. When the rising voltage reaches the predetermined voltage Vers, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to 0 (V) as the base potential.

  At this time, the charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. To go. As a result, the wall voltage between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn remains as positive voltage applied to scan electrode SCi while leaving positive wall charges on data electrode Dk. It is weakened to the extent of the difference between the discharge start voltages, ie, (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase lamp voltage L3 is referred to as “erase discharge”.

  In the present embodiment, the voltage value of the voltage Vers is set to a voltage substantially equal to the sustain pulse voltage Vs (for example, 200 (V)), but in this embodiment, the voltage value of the voltage Vers is set to It is desirable to set the voltage range between sustain pulse voltage Vs-10 (V) and sustain pulse voltage Vs + 10 (V). If the voltage value of the voltage Vers is larger than the upper limit value, the wall voltage will be excessively adjusted, and if it is smaller than the lower limit value, the wall voltage will be insufficiently adjusted and the subsequent writing operation may not be performed stably. Because.

  In the present embodiment, the configuration in which the gradient of the erase ramp voltage L3 is about 10 V / μsec has been described. However, this gradient is preferably set to 2 V / μsec or more and 20 V / μsec or less. If the slope is steeper than this upper limit value, the discharge for adjusting the wall voltage will not be weak, and if the slope is made gentler than this lower limit value, the discharge itself will be too weak, This is because the voltage may not be adjusted well.

  Thereafter, scan electrode SC1 to scan electrode SCn are returned to 0 (V), and the sustain operation in the sustain period is completed.

  In the initialization period of the second SF, a drive voltage waveform in which the first half of the initialization period of the first SF is omitted is applied to each electrode. That is, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm, respectively, and voltage that is equal to or less than the discharge start voltage (for example, 0) is applied to scan electrode SC1 through scan electrode SCn. (V)) is applied to the ramp-down voltage L4 that gently falls toward the negative voltage Vi4.

  As a result, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the immediately preceding subfield (first SF in FIG. 3), and the wall voltage on the scan electrode SCi and the sustain electrode SUi is weakened. The wall voltage above the data electrode Dk (k = 1 to m) is also adjusted to a value suitable for the write operation. On the other hand, discharge cells in which no sustain discharge has occurred in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the second SF is a selective initializing operation in which the initializing discharge is performed on the discharge cells in which the sustain operation has been performed in the sustain period of the immediately preceding subfield.

  In the address period of the second SF, the same drive waveform as that in the address period of the first SF is applied to scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm.

  In the sustain period of the second SF, similarly to the sustain period of the first SF, a predetermined number of sustain pulses are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. As a result, a sustain discharge is generated in the discharge cells that have generated the address discharge in the address period. At the end of the sustain period, as in the sustain period of the first SF, erase lamp voltage L3 is applied to scan electrode SC1 through scan electrode SCn, and an erase discharge is generated in the discharge cells that have generated the sustain discharge.

  In the subfields after the third SF, scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm are different from each other except that the number of sustain pulses generated in the sustain period is different. A drive waveform similar to 2SF is applied.

  The above is the outline of the driving voltage waveform applied to each electrode of the panel 10.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of plasma display device 1 according to one embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a control signal generation circuit 45, and a power supply that supplies power necessary for each circuit block. A circuit (not shown) is provided.

  The image signal processing circuit 41 converts the input image signal sig into subfield data indicating light emission / non-light emission for each subfield according to the number of pixels of the panel 10.

  The control signal generation circuit 45 generates various control signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and each circuit block (image signal processing circuit 41, data electrode drive circuit 42). To the scan electrode drive circuit 43 and the sustain electrode drive circuit 44).

  The data electrode driving circuit 42 converts the subfield data for each subfield into signals corresponding to the data electrodes D1 to Dm, and based on the control signals supplied from the control signal generating circuit 45, the data electrodes D1 to D1. The data electrode Dm is driven.

  Scan electrode driving circuit 43 is an initialization waveform generating circuit for generating an initialization waveform to be applied to scan electrode SC1 to scan electrode SCn in the initialization period, and a sustain pulse to be applied to scan electrode SC1 to scan electrode SCn in the sustain period. And a plurality of scan electrode driving ICs (hereinafter abbreviated as “scan ICs”), and a scan for generating scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period It has a pulse generation circuit. Then, based on the control signal supplied from control signal generation circuit 45, each of scan electrode SC1 through scan electrode SCn is driven.

  Sustain electrode drive circuit 44 includes a sustain pulse generating circuit and a circuit (not shown) for generating voltage Ve1 and voltage Ve2, and sustain electrodes SU1 to SU1 based on a control signal supplied from control signal generating circuit 45. The electrode SUn is driven.

  Next, details and operation of the scan electrode drive circuit 43 will be described.

  FIG. 5 is a circuit diagram showing a configuration example of scan electrode driving circuit 43 of plasma display apparatus 1 according to the embodiment of the present invention. The scan electrode drive circuit 43 includes a sustain pulse generation circuit 50 that generates a sustain pulse, an initialization waveform generation circuit 53 that generates an initialization waveform, and a scan pulse generation circuit 54 that generates a scan pulse. Each output is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. In the present embodiment, the voltage input to scan pulse generation circuit 54 is referred to as “reference potential A”. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for cutting off the switching element is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”.

  Sustain pulse generation circuit 50 includes a generally used power recovery circuit (not shown) and a clamp circuit (not shown), and each of the sustain pulse generation circuit 50 provided therein based on a control signal output from control signal generation circuit 45. A sustain pulse is generated by switching the switching element.

  Scan pulse generating circuit 54 includes switching elements QH1 to QHn and switching elements QL1 to QLn for applying a scan pulse voltage to each of n scan electrodes SC1 to SCn. Switching element QH1 to switching element QHn and switching element QL1 to switching element QLn are integrated into a plurality of outputs and integrated into an IC. This IC is a scanning IC.

  Further, the scan pulse generation circuit 54 includes a switching element Q5 for connecting the reference potential A to the negative voltage Va in the address period, a power supply Vsc for generating a voltage Vc in which the voltage Vsc is superimposed on the reference potential A, a diode D31 and a capacitor C31. The voltage Vc is connected to the input terminals IN2 of the switching elements QH1 to QHn, and the reference potential A is connected to the input terminals IN1 of the switching elements QL1 to QLn.

  In the scan pulse generation circuit 54 configured as described above, in the address period, the switching element Q5 is turned on to make the reference potential A equal to the negative voltage Va, and the negative voltage Va is applied to the input terminal IN1. A voltage Vc having a voltage Va + voltage Vsc is applied to IN2. Then, based on the subfield data, for the scan electrode SCi to which the scan pulse is applied, the switching element QHi is turned off and the switching element QLi is turned on, so that the negative polarity is applied to the scan electrode SCi via the switching element QLi. For the scan electrode SCh to which the scan pulse voltage Va is applied and no scan pulse is applied (h is 1 to n excluding i), the switching element QLh is turned off and the switching element QHh is turned on. Thus, the voltage Va + voltage Vsc is applied to the scan electrode SCh via the switching element QHh.

  During the period in which the initialization waveform generating circuit 53 or the sustain pulse generating circuit 50 is operated, the switching elements QL1 to QLn are turned off and the switching elements QL1 to QLn are turned on, so that the switching elements QL1 to QL1 are turned on. An initialization waveform voltage or a sustain pulse voltage is applied to each scan electrode SC1 through scan electrode SCn via switching element QLn.

  Initialization waveform generation circuit 53 includes Miller integration circuit 55, Miller integration circuit 56, constant current generation circuit 60, constant current generation circuit 61, and power supply voltage switching circuit 57. Miller integrating circuit 55 and Miller integrating circuit 56 are ramp voltage generating circuits.

  Miller integrating circuit 55 has switching element Q11, capacitor C10, Zener diode D10 connected in series with capacitor C10, and resistor R10, and gradually ramps up to voltage Vi2 (eg, 1.3 V / The rising ramp voltage L1 during the initialization operation rising (in μsec) and the erasing ramp voltage L3 rising to the voltage Vers with a steeper slope (eg, 10 V / μsec) than the rising ramp voltage L1 are generated. The Zener diode D10 is provided in the forward direction with respect to the constant current input from the constant current generation circuit 60 to the Miller integration circuit 55, and during the all-cell initialization operation (here, the initialization period of the first SF). The voltage Vsc is superimposed on a Zener voltage (for example, 45 (V)), which is a built-up voltage, to generate the voltage Vi1, that is, the start voltage of the up-ramp voltage L1 that is the first ramp voltage (the ramp voltage rises). The voltage to be started) is set to the voltage Vi1.

  The constant current generating circuit 60 includes a transistor Q8 having a collector connected to the input terminal INa, a resistor R8 inserted between the input terminal INa and the base of the transistor Q8, a cathode connected to the resistor R8, and an anode connected to the resistor R10. And a resistor R12 connected in series between the emitter of the transistor Q8 and the resistor R10, and applies a predetermined voltage (for example, 5 (V)) to the input terminal INa. Thus, a constant current is generated. This constant current is input to Miller integrating circuit 55, and Miller integrating circuit 55 raises the potential of reference potential A during the period in which this constant current is input.

  Miller integrating circuit 56 has switching element Q14 and capacitor C12, and generates down-ramp voltage L2 and down-ramp voltage L4 that gently fall in a ramp shape to voltage Vi4.

  The constant current generating circuit 61 includes a transistor Q9 having a collector connected to the input terminal INb, a resistor R9 inserted between the input terminal INb and the base of the transistor Q9, and a cathode connected to the resistor R9. By having a Zener diode D9 having an anode connected to the gate and a resistor R11 connected in series to the emitter of the transistor Q9, applying a predetermined voltage (for example, 5 (V)) to the input terminal INb, Generate constant current. This constant current is input to Miller integrating circuit 56, and Miller integrating circuit 56 lowers the potential of reference potential A during the period in which this constant current is input.

  The power supply voltage switching circuit 57 prevents a reverse flow to the power supply that generates the voltage Vers and the switching element Q15 for separating the voltage Vset (for example, 300 (V)) and the voltage Vers (for example, 200 (V)). And a resistor R14, a resistor R15, a Zener diode D11 for adjusting a voltage applied to the gate of the switching element Q15, and a photocoupler PC3. The light emitting side of the photocoupler PC3 serves as an input terminal INc via a current limiting resistor R18. The transistor side of the photocoupler PC3 has a collector connected to the voltage Vset and an emitter connected to the gate of the switching element Q15. Yes. When a predetermined voltage (for example, 5 (V)) is applied to the input terminal INc, the transistor of the photocoupler PC3 is turned on, whereby the gate voltage of the switching element Q15 becomes equal to the voltage Vset, and the switching element Q15 is turned off. Thus, the voltage Vers can be applied to the Miller integrating circuit 55. Further, for example, when 0 (V) is applied to the input terminal INc, the transistor of the photocoupler PC3 is turned off, whereby the voltage Vset and the voltage Vers are divided by the resistance R14 and the resistance R15 at the gate of the switching element Q15. The applied voltage is applied to turn on the switching element Q15, and the voltage Vset can be applied to the Miller integrating circuit 55. As described above, the power supply voltage switching circuit 57 selectively selects one of the voltage Vset used when generating the rising ramp voltage L1 and the voltage Vers used when generating the erasing ramp voltage L3 as a Miller integrating circuit. 55.

  Here, the initialization waveform generation circuit 53 in the present embodiment includes a switching element Q21, which is a first switching element, and a switching element Q22, which is a second switching element, made of a MOSFET (Metal Oxide Field Effect Effect Transistor). It is set as the structure provided with. Note that the gate of the switching element Q21 and the gate of the switching element Q22 are connected to each other to serve as the input terminal INd, and the control signal applied to the input terminal INd is set to “Hi” (for example, 5 (V)). The switching element Q21 and the switching element Q22 can be turned on at the same time, and the control signal applied to the input terminal INd is set to “Lo” (for example, 0 (V)). Can be turned off at the same time. However, the present invention is not limited to this configuration, and may be configured such that switching element Q21 and switching element Q22 can be turned on / off independently of each other.

  Furthermore, the constant current generating circuit 60 is configured to include a resistor R13 that changes the current value of the constant current output from the constant current generating circuit 60 by the switching operation of the switching element Q21. Specifically, one terminal of the resistor R13 is connected to the connection point between the resistor R12 and the transistor Q8, and the other terminal is connected to the drain of the switching element Q21. Then, the source of the switching element Q21 is connected to the connection point between the resistor R12 and the resistor R10. Thus, by turning on the switching element Q21, the resistor R12 and the resistor R13 are electrically connected in parallel, and the current value of the constant current output from the constant current generating circuit 60 is greater than when the switching element Q21 is off. And the gradient of the ramp voltage output from Miller integrating circuit 55 can be increased.

  Further, the switching operation of switching element Q22 is configured to switch whether or not the accumulated voltage is superimposed on the starting voltage of the ramp voltage. Specifically, the cathode of the Zener diode D10 provided in the Miller integrating circuit 55 and the drain of the switching element Q22 are connected, and the anode of the Zener diode D10 and the source of the switching element Q22 are connected. Thereby, when the switching element Q22 is OFF, the Zener voltage (for example, 45 (V)) of the Zener diode D10 can be stacked on the source voltage of the switching element Q11, and the starting voltage of the up-ramp voltage L1 can be set to the voltage Vi1, for example. . Further, when the switching element Q22 is on, the Zener diode D10 is electrically short-circuited so that the starting voltage of the ramp voltage output from the Miller integrating circuit 55 is a voltage that does not cause the Zener voltage of the Zener diode D10 to be accumulated. it can. For example, the start voltage of the erase ramp voltage L3 can be set to 0 (V).

  Thereby, Miller integrating circuit 55 in the present embodiment generates two ramp voltages having different slopes and initial voltages, that is, up-ramp voltage L1 during the initialization operation, and erase ramp voltage L3 generated at the end of the sustain period. Can be generated.

  Even if the Zener diode D10 is provided in the opposite direction to the constant current input to the Miller integrating circuit 55 (even in the opposite direction to the Zener diode D10 shown in FIG. 5), for example, the up-ramp voltage L1 is generated. It was confirmed that the starting voltage at that time could be a voltage Vi1 obtained by superimposing the Zener voltage Vz of the Zener diode D10 on the voltage Vsc. However, when the Zener diode D10 is provided in such a direction, the anode of the Zener diode D10 and the cathode of the parasitic diode of the switching element Q22 are connected, and the cathode of the Zener diode D10 and the anode of the parasitic diode of the switching element Q22 are connected. Thus, an electrical closed loop is formed, and the cathode of the Zener diode D10 and the anode of the parasitic diode of the switching element Q21 are connected, and a current flows from the Zener diode D10 to the parasitic diode of the switching element Q21. Since the path is formed, the initialization waveform generation circuit 53 itself does not operate normally. That is, in the configuration in which the Zener diode D10 is provided in the opposite direction to the constant current input to the Miller integrating circuit 55, MOSFETs cannot be used for the switching element Q21 and the switching element Q22. For example, a parasitic diode such as a photocoupler is used. The switching elements Q21 and Q22 must be configured using switching elements that are not formed.

  However, in the present embodiment, as shown in FIG. 5, the Zener diode D10 is provided in the forward direction with respect to the constant current input to the Miller integrating circuit 55. Therefore, the cathode of the Zener diode D10 and the switching element Q22 are provided. And the anode of the zener diode D10 and the anode of the parasitic diode of the switching element Q21 are not connected to form the above-described path. Therefore, the switching element Q21 that is the first switching element and the switching element Q22 that is the second switching element can be configured using relatively inexpensive MOSFETs.

  Next, an operation for generating the up-ramp voltage L1 that is the first ramp voltage, and an operation for generating the erase ramp voltage L3 that is the second ramp voltage that rises to the voltage Vers with a steeper slope than the up-ramp voltage L1. Will be described with reference to FIG.

  FIG. 6 is a timing chart for explaining an example of the operation of scan electrode driving circuit 43 in the all-cell initializing period in one embodiment of the present invention. In this figure, the drive waveform during the all-cell initialization operation is described as an example, but the operation for generating the down-ramp voltage L4 in the selective initialization operation is the operation for generating the down-ramp voltage L2 described in FIG. It shall be the same.

  In FIG. 6, the last drive waveform of the sustain period is divided into two periods indicated by periods T1 to T2, and the drive waveforms for performing the all-cell initialization operation are indicated by four periods indicated by periods T11 to T14. Each period will be described below. In the following description, it is assumed that the voltage Vi3 is equal to the voltage Vs, the voltage Vi2 is equal to the voltage Vsc + the voltage Vset, and the voltage Vi4 is equal to the negative voltage Va. In the drawing, a signal for turning on the switching element is represented as “Hi” and a signal for turning off the switching element is represented as “Lo”.

  First, the operation for generating the erase ramp voltage L3 at the end of the sustain period will be described.

  First, before entering the period T1, the input terminal INc is set to “Hi”, the photocoupler PC3 is turned on, the voltage Vers is applied to the Miller integrating circuit 55, and the input terminal INd is set to “Hi”. The element Q22 is turned on, the Zener diode D10 is electrically short-circuited, and the voltage Vers is charged in the capacitor C10. Further, the clamp circuit of sustain pulse generating circuit 50 is operated to set reference potential A to 0 (V), switching element QH1 to switching element QHn is turned off, switching element QL1 to switching element QLn is turned on, and reference potential is set. A (0 (V) at this time) is applied to scan electrode SC1 through scan electrode SCn (not shown).

(Period T1)
In the period T1, the input terminal INa is set to “Hi”, and the operation of the constant current generation circuit 60 is started. As a result, a constant current flows toward the capacitor C10, the source voltage of the switching element Q11 increases in a ramp shape, and the output voltage of the scan electrode drive circuit 43 starts to increase in a ramp shape. At this time, the resistor R12 and the resistor R12 are set so that the output current of the constant current generating circuit 60 becomes smaller than the drain current of the switching element Q11 and the gradient of the ramp voltage becomes a desired value (for example, 10 V / μsec). The resistance value of the combined resistance of R13 is set in advance.

  Here, the drain voltage of the switching element Q11 is Vd11, the source voltage of the switching element Q11 is Vs11, the potential difference between both terminals of the capacitor C10 is Vc10 (t), and the voltage drop during forward operation of the Zener diode D10 is Vf10. When the voltage between the gate and the source of the element Q11 is Vgs11, the source voltage Vs11 of the switching element Q11 is expressed by the following formula 1.

Vs11 = Vd11−Vc10 (t) −Vf10−Vgs11 Equation 1
Note that one terminal voltage of the capacitor C10 is the voltage Vers, and the other terminal voltage gradually increases as the output current from the constant current generation circuit 60 is charged in the capacitor C10. Therefore, Vc10 (t) is time It becomes a variable with t as a parameter. Further, since the output current from the constant current generation circuit 60 is a constant current, Vc10 (t) decreases linearly with the passage of time t.

  In the period T1, Vd11 is equal to the voltage Vers. Further, the voltage drop Vf10 during the forward operation of the Zener diode D10 and the voltage Vgs11 between the gate and source of the switching element Q11 are sufficiently small values and can be substantially omitted. Therefore, the source voltage Vs11 of the switching element Q11 shown in Expression 1 can be rewritten as the following Expression 2.

Vs11 = Vers−Vc10 (t) Equation 2
Immediately after the start of the operation of the constant current generating circuit 60 (t = 0), the capacitor C10 is not charged, so the potential difference between both terminals of the capacitor C10 becomes the voltage Vers. That is, Vc10 (0) = Vers. Therefore,
Vs11 = Vers−Vc10 (0) = Vers−Vers = 0 (V)
Thus, the source voltage Vs11 of the switching element Q11 is 0 (V).

  Thereafter, the source voltage of the switching element Q11 rises in a ramp shape with a gradient determined by the constant current output from the constant current generating circuit 60 and the capacitance of the capacitor C10. At this time, since the input terminal INd is “Hi” in the period T1, the resistor R12 and the resistor R13 are electrically connected in parallel. As a result, the current value of the constant current output from the constant current generating circuit 60 is increased, and the output voltage of the scan electrode driving circuit 43 is ramped with a steeper slope (eg, 10 V / μsec) than the up-ramp voltage L1. Begins to rise. In this way, the erase ramp voltage L3 that is the second ramp voltage that rises from 0 (V) toward the voltage Vers (equal to the voltage Vs in the present embodiment) is generated.

  While the erasing ramp voltage L3 rises, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, thereby generating a weak discharge between scan electrode SCi and sustain electrode SUi. be able to. This weak discharge can be continued for a period during which the erase lamp voltage L3 rises.

  In the present embodiment, the scanning electrode is not an intense discharge due to a sudden voltage change such as a sustain pulse, but an erasing ramp voltage L3 that gradually increases the applied voltage (for example, at a gradient of 10 V / μsec). A weak erase discharge is continuously generated between SCi and sustain electrode SUi. Therefore, even for a panel with a larger screen, higher definition, and increased drive impedance, waveform distortion such as ringing generated in the drive waveform generated from the drive circuit can be reduced, and erasure discharge can be generated stably. Can do. Thereby, the wall voltage on scan electrode SCi and sustain electrode SUi can be adjusted to an optimum state for stably generating subsequent writing.

  Although not shown in the drawing, since the data electrode D1 to the data electrode Dm are held at 0 (V) at this time, a positive wall voltage is formed on the data electrode D1 to the data electrode Dm.

(Period T2)
In the period T2, the input terminal INa is set to “Lo”. As a result, the constant current generating circuit 60 stops operating. Further, the input terminal INc is set to “Lo”, the photocoupler PC3 is turned off, and the voltage Vset is applied to the Miller integrating circuit 55. At the same time, the input terminal INd is set to “Lo”, the switching elements Q21 and Q22 are turned off, the resistor R13 is electrically opened, and the Zener diode D10 is electrically operated. Subsequently, the clamp circuit of the sustain pulse generation circuit 50 is operated to set the reference potential A to 0 (V). As a result, the capacitor C10 is charged with a voltage (voltage Vset−voltage Vz) obtained by subtracting the Zener voltage Vz of the Zener diode D10 from the voltage Vset. Thus, it prepares for the subsequent all-cell initialization operation.

  Next, the operation when generating the initialization waveform voltage during the all-cell initialization period will be described.

(Period T11)
In the period T11, the switching element QH1 to the switching element QHn are turned on and the switching element QL1 to the switching element QLn are turned off, so that the voltage Vc in which the voltage Vsc is superimposed on the reference potential A (0 (V) at this time) (ie, , Voltage Vc = voltage Vsc) is applied to scan electrode SC1 through scan electrode SCn.

(Period T12)
Next, the input terminal INa is set to “Hi” while the input terminal INc and the input terminal INd are maintained at “Lo”. When the input terminal INa is set to “Hi”, the constant current generation circuit 60 starts to operate, a constant current flows toward the capacitor C10, the source voltage of the switching element Q11 increases in a ramp shape, and the scan electrode drive circuit The output voltage 43 starts to rise in a ramp shape. At this time, the resistor R12 is set so that the output current of the constant current generating circuit 60 becomes smaller than the drain current of the switching element Q11 and the gradient of the ramp voltage becomes a desired value (eg, 1.3 V / μsec). Set the resistance value.

  In the period T12, the drain voltage Vd11 of the switching element Q11 is equal to the voltage Vset. Further, since the capacitor C10 is charged with a voltage obtained by subtracting the Zener voltage Vz of the Zener diode D10 from the voltage Vset, the potential difference between both terminals of the capacitor C10 immediately after the start of the operation of the constant current generating circuit 60 (t = 0). Is Vset-Vz. Therefore, the source voltage Vs11 of the switching element Q11 at this time is expressed by the following expression 3 based on the above-described expression 1.

Vs11 = Vset−Vc10 (0) = Vset− (Vset−Vz) = Vz Equation 3
Note that the voltage drop Vf10 during forward operation of the Zener diode D10 and the voltage Vgs11 between the gate and source of the switching element Q11 are substantially negligible and are omitted in the same manner as in Equation 2.

  Therefore, as shown in Equation 3, the source voltage Vs11 of the switching element Q11 immediately after the start of the operation of the constant current generation circuit 60 is set to the reference potential A (0 (V)) immediately before the start of the operation of the constant current generation circuit 60. The voltage Vz is obtained by adding the Zener voltage Vz of D10. That is, immediately after the operation of the constant current generating circuit 60 is started, the output voltage of the scan electrode driving circuit 43 sharply increases from the voltage Vsc to the voltage Vi1 obtained by superimposing the Zener voltage Vz of the Zener diode D10 that is the accumulated voltage on the voltage Vsc. . Thereby, the voltage Vi1, that is, the voltage Vsc + the voltage Vz becomes the start voltage of the up-ramp voltage L1. Thereafter, a constant current flows from the resistor R12 toward the capacitor C10, and the source voltage of the switching element Q11 increases from the voltage Vi1 in a ramp shape. At this time, since the input terminal INd is “Lo” in the period T12, the resistor R13 is electrically opened, the current value of the constant current output from the constant current generation circuit 60 becomes small, and the scan electrode driving circuit 43 The output voltage starts to rise in a ramp shape with a gentler gradient (eg, 1.3 V / μsec) than the erase ramp voltage L3.

  Further, since the photocoupler PC3 is turned off, the voltage Vset is applied to the Miller integrating circuit 55, and the output voltage of the scan electrode driving circuit 43 is increased to the voltage Vi2 (here, voltage Vsc + voltage Vset). it can. When the output voltage of the scan electrode driving circuit 43 reaches the voltage Vi2, the input terminal INa is set to “Lo”.

  In the period T12, the ramp-up voltage that is the first ramp voltage that gradually increases from the voltage Vi1 to the voltage Vi2 exceeding the discharge start voltage (equal to the voltage Vsc + the voltage Vset in this embodiment) in this way. L1 is generated and applied to scan electrode SC1 through scan electrode SCn. This voltage increase can be continued while the input terminal INa is set to “Hi” or until the reference potential A reaches the voltage Vset.

(Period T13)
In the period T13, the input terminal INa is set to “Lo”. As a result, the constant current generating circuit 60 stops operating. Further, switching element QH1 to switching element QHn are turned off, switching element QL1 to switching element QLn are turned on, and reference potential A is applied to scan electrode SC1 to scan electrode SCn. At the same time, the clamp circuit of sustain pulse generating circuit 50 is operated to set reference potential A to voltage Vs. Thereby, the voltage of scan electrode SC1 through scan electrode SCn is reduced to voltage Vi3 (equal to voltage Vs in the present embodiment).

(Period T14)
Next, the input terminal INb of Miller integrating circuit 56 for generating down-ramp voltage L2 is set to “Hi”. Then, a constant current flows from the resistor R11 of the constant current generating circuit 61 toward the capacitor C12, and the drain voltage of the switching element Q14 is ramp-shaped toward the negative voltage Vi4 (equal to the voltage Va in the present embodiment). The output voltage of the scan electrode drive circuit 43 also starts to drop in a ramp shape toward the negative voltage Va. Then, immediately before the initialization period ends, the input terminal INb is set to “Lo”. In the period T14, the down-ramp voltage L2 is thus generated and applied to scan electrode SC1 through scan electrode SCn.

  As described above, the scan electrode driving circuit 43 generates the up-ramp voltage L1 that is the first ramp voltage, the erase ramp voltage L3 that is the second ramp voltage, and the down-ramp voltage L2.

  Note that in the period T <b> 14, the input terminal INc is set to “Hi”, the photocoupler PC <b> 3 is turned on, and the voltage Vers is supplied to the Miller integrating circuit 55. In addition, the input terminal INd is set to “Hi”, the switching elements Q21 and Q22 are turned on, the Zener diode D10 is electrically short-circuited, and the starting voltage of the ramp voltage output from the Miller integrating circuit 55 is 0. (V) and the resistor R12 and the resistor R13 of the constant current generating circuit 60 are electrically connected in parallel so that a constant current having a larger current value is output from the constant current generating circuit 60. To. Thus, it is prepared for the subsequent operation.

  The down-ramp voltage L2 may be configured to drop to the voltage Va as shown in FIG. 6, but for example, the down-ramp voltage L2 has reached a voltage obtained by superimposing a predetermined positive voltage Vset2 on the voltage Va. It is good also as composition which stops descent at the time.

  As described above, according to the present embodiment, at the end of the sustain period, that is, after the sustain pulse has been applied to the display electrode pair, the erase ramp voltage L3 having a steeper slope than the up-ramp voltage L1. Is applied to scan electrode SC1 to scan electrode SCn to continuously generate a weak erasure discharge, which is necessary for generating address discharge even in a panel with a large screen and high definition. The address discharge can be stably generated without increasing the voltage, and the image display quality can be improved. Further, the switching element Q21, the switching element Q22, and the photocoupler PC3 are switched on and off, whereby the amount of constant current input to the Miller integrating circuit 55, the presence / absence of the Zener diode D10, and the power supply voltage applied to the Miller integrating circuit 55 are changed. By being configured to be switched, two ramp voltages having different gradients, initial voltages and ultimate potentials, that is, the up-ramp voltage L1 as the first ramp voltage and the second ramp voltage are used by using one Miller integration circuit 55. An erasing ramp voltage L3 that is a ramp voltage can be generated. Further, by providing the Zener diode D10 so as to be in the forward direction with respect to the constant current input to the Miller integrating circuit 55, the switching element Q21 that is the first switching element and the second switching element are used. It is possible to configure a certain switching element Q22 using a relatively inexpensive MOSFET.

  In order to reduce the waveform distortion of the ramp voltage, an emitter follower may be added to the Miller integrating circuit. FIG. 7 is a circuit diagram showing another configuration example of the initialization waveform generating circuit in one embodiment of the present invention. For example, a Miller integrating circuit 58 may be configured by adding an emitter follower having a transistor Q20 and a resistor R20 to the Miller integrating circuit 55 shown in FIG. By adopting such a circuit configuration, the waveform rise when the ramp voltage is generated, in particular, the increase in the gate input capacitance accompanying the decrease in the drain-source voltage of the switching element Q11, the voltage rise is finished and the constant voltage is reached. It is possible to reduce the rounding of the waveform generated at the point where the switching is made.

  In the present embodiment, the configuration in which erase lamp voltage L3 is applied to scan electrode SC1 through scan electrode SCn has been described. However, when the last sustain pulse is applied to scan electrode SC1 through scan electrode SCn, It is also possible to adopt a configuration in which erasing ramp voltage L3 is applied to sustain electrode SU1 through sustain electrode SUn. However, in the present embodiment, it is desirable that the last sustain pulse is applied to sustain electrode SU1 through sustain electrode SUn, and erase lamp voltage L3 is applied to scan electrode SC1 through scan electrode SCn.

  In the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group. Of the panel by so-called two-phase driving, which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group. The present invention can also be applied to a driving method, and the same effect as described above can be obtained.

  In the embodiment of the present invention, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other. , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,...

  It should be noted that specific numerical values shown in the present embodiment, for example, the voltage values of the voltage Vers and the voltage Vset, or the gradients of the rising ramp voltage L1 and the erasing ramp voltage L3, etc. It is set based on the characteristics, and is merely an example of the embodiment. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  Since the present invention can stably generate address discharge even in a panel with a large screen and high definition, it is useful as a plasma display device and a panel driving method.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel The circuit block diagram of the plasma display apparatus in one embodiment of the present invention The circuit diagram which shows the example of 1 structure of the scanning electrode drive circuit of the plasma display apparatus 4 is a timing chart for explaining an example of the operation of the scan electrode drive circuit during the all-cell initialization period in one embodiment of the present invention. The circuit diagram which shows the other structural example of the initialization waveform generation circuit in one embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Control signal generation circuit 50 Sustain pulse generation circuit 53 Initialization waveform generation circuit 54 Scan pulse generation circuit 55, 56, 58 Miller integration circuit 57 Power supply voltage switching circuit 60 , 61 Constant current generating circuit PC3 Photocoupler Q11, Q14, Q15, Q21, Q22 Switching element C10, C12 Capacitor D12 Diode D8, D9, D10, D11 Zener diode R8, R9, R10, R11, R12, R13, R14, R15 R18, R20 resistance Q8, Q9, Q20 transistor

Claims (2)

A plasma display panel having a plurality of scan electrodes driven by a subfield method in which a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field and displayed in gray scale;
A first ramp voltage rising from an initial voltage is generated during the initialization period of at least one subfield of one field, and a second ramp rising at a steeper slope than the first ramp voltage at the end of the sustain period. And a scan electrode driving circuit having a constant voltage generating circuit that generates a constant current to be input to the ramp voltage generating circuit,
The ramp voltage generation circuit is provided in a forward direction with respect to the constant current input from the constant current generation circuit to the ramp voltage generation circuit, and has a Zener diode that applies the initial voltage to the first ramp voltage. And
The scan electrode driving circuit includes:
A first switching element made of a MOSFET for switching an output current value of the constant current generating circuit; and a second switching element made of a MOSFET for electrically short-circuiting the Zener diode, the first switching element and A plasma display device characterized in that the first ramp voltage and the second ramp voltage are generated by switching between conduction and cutoff of the second switching element. A plasma display panel having a plurality of scan electrodes is driven by a subfield method in which a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field to display gradation, and
A first ramp voltage that rises from an initial voltage is generated in the initialization period of at least one subfield of one field, and rises at a steeper slope than the first ramp voltage at the end of the sustain period. A driving method of a plasma display panel that is driven using a ramp voltage generation circuit that generates a second ramp voltage,
A zener diode that is provided in the forward direction with respect to the constant current input to the ramp voltage generation circuit and applies the initial voltage to the first ramp voltage, and a current of the constant current input to the ramp voltage generation circuit A first switching element composed of a MOSFET for switching the value and a second switching element composed of a MOSFET for electrically short-circuiting the Zener diode, and the continuity of the first switching element and the second switching element is provided. 2. A driving method of a plasma display panel, wherein two different ramp voltages of the first ramp voltage and the second ramp voltage are generated from one ramp voltage generation circuit by switching off.

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