JP2011022259A - Method of driving plasma display panel, and plasma display device - Google Patents

Abstract

Even in a high-definition plasma display panel, an abnormal discharge during an address period is suppressed to stabilize an address operation and to improve image display quality.
An initialization period in which a falling down ramp voltage for initialization is applied to a scan electrode, an address period, and a sustain pulse of the number corresponding to the luminance weight set for each subfield are alternately applied to the display electrode pair. A plurality of subfields having a sustain period to be applied are provided in one field, and an adjustment down ramp voltage that is generated later in time than an initialization down ramp voltage is set as an initialization down ramp voltage in the initialization period. Applying the phases of the lowest voltage and the lowest voltage of the adjustment ramp down voltage to the sustain electrodes, and in the subfield with a small luminance weight, the lowest voltage of the initialization ramp voltage is lower than that of the subfield with a large luminance weight. Vi4 and the minimum voltage Vi5 of the downward ramp voltage for adjustment are lowered.
[Selection] Figure 7

Description

  The present invention relates to a driving method of a plasma display panel and a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs. In the back plate, a plurality of parallel data electrodes are formed on a back glass substrate, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. . And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition. Then, the front plate and the back plate are arranged to face each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  A subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell. Thus, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the address discharge) for generating the address discharge stably are generated.

  In the address period, a scan pulse is applied to the scan electrode, and an address pulse is applied to the data electrode based on an image signal to be displayed to generate an address discharge in a discharge cell to be displayed to form a wall charge (hereinafter referred to as a wall charge). This operation is also referred to as “writing”).

  In the sustain period, the number of sustain pulses determined for each subfield is alternately applied to the display electrode pairs including the scan electrodes and the sustain electrodes. Thereby, a sustain discharge is generated in the discharge cell in which the address discharge has occurred, and the phosphor layer of the discharge cell is caused to emit light. As a result, each discharge cell emits light at a luminance corresponding to the luminance weight determined for each subfield. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, thereby performing image display.

  In addition, as one of the subfield methods, gradation discharge is performed by performing initializing discharge using a slowly changing voltage waveform and selectively performing initializing discharge on discharge cells that have undergone sustain discharge. A driving method is disclosed in which light emission not related to the above is reduced as much as possible and the contrast ratio is improved.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display region (hereinafter abbreviated as “black luminance”) that changes due to light emission not related to image display is only weak light emission in the all-cell initialization operation, and has high contrast. Image display is possible (see, for example, Patent Document 1).

  In addition, a technique is disclosed in which an initialization waveform having a portion where the voltage rises with a gentle slope and a portion where the voltage falls with a gentle slope is applied to the discharge cell during the initialization period (for example, Patent Document 2). reference).

JP 2000-242224 A JP 2004-37883 A

  In recent years, further miniaturization of discharge cells has been progressed with higher definition of panels. In this miniaturized discharge cell, it has been confirmed that the wall charges formed in the discharge cell by the initialization discharge are likely to change due to the influence of the address discharge and sustain discharge generated in the adjacent discharge cells. .

  Therefore, an erroneous address discharge occurs in a subfield that should not generate an address discharge (hereinafter also referred to as “erroneous address”), or an address discharge does not occur in a subfield that should generate an address discharge (hereinafter referred to as “incomplete”). An abnormal discharge such as “lamp” may occur, which is a cause of deterioration of image display quality.

  The present invention has been made in view of such a problem, and even in a high-definition panel, it is possible to suppress the occurrence of abnormal discharge in the address period, stabilize the address operation, and improve the image display quality. An object of the present invention is to provide a driving method and a plasma display device.

  The panel driving method of the present invention includes a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, an initialization period in which a downward ramp voltage for initialization is applied to the scan electrode, A panel for displaying gradation by providing a plurality of subfields in one field having a writing period and a sustaining period in which a sustaining pulse is applied alternately to a display electrode pair in accordance with the luminance weight set for each subfield. A driving method, wherein an adjustment down ramp voltage that occurs later in time than an initialization down ramp voltage during an initialization period is defined as a minimum voltage of the initialization down ramp voltage and a minimum voltage of the adjustment down ramp voltage. Are applied to the sustain electrodes in the same manner, and in the subfield with a small luminance weight, the minimum voltage of the initial ramp-down voltage and the adjustment Characterized in that to lower the lowest voltage of the ramp voltage.

  As a result, even in a plasma display device using a high-definition panel, it is possible to suppress the occurrence of abnormal discharge in the address period, stabilize the address operation, and improve the image display quality.

  Further, in this panel driving method, when subfields are arranged so that the luminance weights are in ascending order or descending order, a group is formed by a plurality of adjacent subfields, and the average value of the luminance weights is small. In the subfield belonging to, the minimum voltage of the initializing falling ramp voltage and the lowest voltage of the adjusting descending ramp voltage may be lower than those of the subfield belonging to the group having a large average value of luminance weights. This also makes it possible to suppress the occurrence of abnormal discharge in the address period, stabilize the address operation, and improve the image display quality in the plasma display device using the high-definition panel.

  Also, in this panel driving method, the initialization down ramp voltage is compared with a preset comparison voltage, and after the initialization down ramp voltage reaches the comparison voltage, the adjustment down ramp voltage is generated. The minimum voltage of the downward ramp voltage for adjustment may be controlled by changing the time. This makes it possible to accurately control the minimum voltage of the adjustment downward ramp voltage.

  Further, in this panel driving method, during the period in which the adjustment downward ramp voltage is applied to the sustain electrode, the sustain electrode is electrically disconnected from the sustain electrode drive circuit for driving the sustain electrode, so that the sustain electrode is in a high impedance state. The configuration may be such that the initialization downward ramp voltage applied to the scan electrode is applied to the sustain electrode via a parasitic capacitance between the scan electrode and the sustain electrode. This makes it possible to apply the adjustment down ramp voltage to the sustain electrode without providing a circuit for generating the adjustment down ramp voltage.

  Further, in this panel driving method, the down-gradient voltage for initialization is compared with a preset comparison voltage, and after the down-gradient voltage for initialization reaches the comparison voltage, the sustain electrode is put into a high impedance state. The minimum voltage of the downward ramp voltage for adjustment is controlled by changing the time of the above, and the subfield with a small luminance weight may be configured to have a shorter time than the subfield with a large luminance weight. This makes it possible to apply the adjustment down ramp voltage to the sustain electrode without providing a circuit for generating the adjustment down ramp voltage, and to accurately control the minimum voltage of the adjustment down ramp voltage. It becomes possible.

  The plasma display device of the present invention includes a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field. In the sustain period, a sustain pulse of the number corresponding to the luminance weight set for each subfield is alternately applied to the display electrode pair, and a downward ramp voltage for initialization is generated and maintained in the reset period. A scan electrode driving circuit that generates a sustain pulse during the period and applies the sustain pulse to the scan electrode; and a sustain electrode drive circuit that generates a sustain pulse during the sustain period and applies the sustain pulse to the sustain electrode. The adjustment down ramp voltage, which occurs later in time than the initialization down ramp voltage during the initialization period, is the level of the lowest initialization down ramp voltage and the lowest adjustment down ramp voltage. Are applied to the sustain electrodes in alignment with each other, and in the subfield with a small luminance weight, the minimum voltage of the adjustment downward ramp voltage is made lower than that of the subfield with a large luminance weight. In the field, the minimum voltage of the down ramp voltage for initialization is set lower than that in the subfield having a large luminance weight.

  As a result, even in a plasma display device using a high-definition panel, it is possible to suppress the occurrence of abnormal discharge in the address period, stabilize the address operation, and improve the image display quality.

  Further, in the plasma display device of the present invention, the scan electrode driving circuit has a comparison circuit that compares the downward ramp voltage for initialization with a preset comparison voltage, and the sustain electrode driving circuit displays the comparison result in the comparison circuit. A configuration that generates the downward ramp voltage for adjustment may be used. As a result, it is possible to accurately generate the adjustment downward ramp voltage.

  Further, in the plasma display device of the present invention, the sustain electrode driving circuit is configured to electrically disconnect the sustain electrode from the sustain electrode drive circuit so that the sustain electrode is in a high impedance state during the period in which the adjustment downward ramp voltage is generated. There may be. As a result, the downward ramp voltage for initialization applied to the scan electrode can be applied to the sustain electrode via the parasitic capacitance (interelectrode capacitance) between the scan electrode and the sustain electrode. Even without providing a circuit for generating a voltage, it is possible to apply the adjusting downward ramp voltage to the sustain electrode.

  According to the present invention, there is provided a panel driving method and a plasma display device capable of suppressing the occurrence of abnormal discharge in the address period, stabilizing the address operation, and improving the image display quality even in a high-definition panel. It becomes possible to do.

It is a disassembled perspective view which shows the structure of the panel in one embodiment of this invention. It is an electrode array figure of the panel. It is a drive voltage waveform figure applied to each electrode of the panel. It is a circuit block diagram of the plasma display apparatus in one embodiment of the present invention. It is a circuit diagram which shows the example of 1 structure of the scanning electrode drive circuit of the plasma display apparatus. It is a circuit diagram which shows the example of 1 structure of the sustain electrode drive circuit of the plasma display apparatus. It is a wave form diagram showing roughly a drive voltage waveform applied to a scan electrode and a sustain electrode in an initialization period in an embodiment of the present invention. It is a figure which shows roughly the relationship between the unnecessary wall charge which remains in a discharge cell after erasure discharge, and a subfield. FIG. 6 is a characteristic diagram showing a relationship between an upper limit of a difference voltage between a voltage Vi4 and a scan pulse voltage Va and a subfield. It is a characteristic view showing the relationship between the upper limit of sustain pulse voltage Vs that can generate sustain discharge stably and the subfield. It is a figure which shows roughly the relationship between the unnecessary wall charge accumulate | stored in a discharge cell by a sustain priming movement, and a subfield. FIG. 6 is a characteristic diagram showing a relationship between an upper limit of a difference voltage between a voltage Vi4 and a scan pulse voltage Va and a subfield. FIG. 13 is a diagram in which the characteristic diagram shown in FIG. 9 and the characteristic diagram shown in FIG. 12 are superimposed. It is a characteristic view showing the relationship between the lower limit of the scanning pulse (amplitude) that can generate the address discharge stably and the subfield. It is a figure which shows the example of a setting of the difference voltage of voltage Vi4 and scanning pulse voltage Va, and voltage VeHz in one embodiment of this invention. 6 is a timing chart for explaining an example of operations of the scan electrode drive circuit and the sustain electrode drive circuit during the initialization period of the all-cell initialization subfield according to the embodiment of the present invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is made of a material mainly composed of magnesium oxide (MgO).

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween. And the outer peripheral part is sealed with sealing materials, such as glass frit. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dk (k = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. In the plasma display device according to the present embodiment, one field is divided into a plurality of subfields on the time axis, luminance weights are set for each subfield, and light emission / non-light emission of each discharge cell is performed for each subfield. It is assumed that gradation display is performed by a subfield method for controlling the above.

  In this subfield method, for example, one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each weight is increased so that the luminance weight increases in the later subfield. Each subfield may have a luminance weight of (1, 2, 4, 8, 16, 32, 64, 128). In addition, in the initializing period of one subfield among a plurality of subfields, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed (hereinafter, the subfield for performing the all-cell initializing operation is referred to as a subfield for performing all-cell initializing operations). In the initializing period of other subfields, a selective initializing operation for selectively generating initializing discharge is performed for the discharge cells that have undergone sustain discharge (hereinafter referred to as “all-cell initializing subfield”). The subfield that performs the selective initialization operation is referred to as “selective initialization subfield”), and it is possible to reduce light emission not related to gradation display as much as possible and improve the contrast ratio.

  In the present embodiment, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the eighth SF. Thereby, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initializing operation in the first SF. Therefore, the black luminance, which is the luminance of the black display region where no sustain discharge is generated, is only weak light emission in the all-cell initializing operation, and an image display with high contrast is possible. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows scan electrode SC1 that scans first in the address period, scan electrode SCn that scans last in the address period (for example, scan electrode SC1080), sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data. The drive waveform of the electrode Dm is shown.

  FIG. 3 also shows driving voltage waveforms of two subfields, that is, a first subfield (first SF) that is an all-cell initializing subfield and a second subfield (second SF) that is a selective initializing subfield. It shows. The drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses generated in the sustain period is different. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to data electrode D1 to data electrode Dm, sustain electrode SU1 to sustain electrode SUn, and voltage Vi1 is applied to scan electrode SC1 to scan electrode SCn. To do. At this time, voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. Further, a ramp voltage L1 (hereinafter referred to as “up-ramp voltage L1”) that gradually increases (for example, with a slope of about 1.3 V / μsec) from voltage Vi1 to voltage Vi2 is applied. At this time, voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.

  While the rising ramp voltage L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. Each weak initializing discharge occurs continuously. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. Sustain electrode SU1 to sustain electrode SUn gradually decrease from voltage Vi3 that is less than the discharge start voltage toward negative voltage Vi4 that exceeds the discharge start voltage (for example, with a gradient of about −2.5 V / μsec). An initialization downward ramp voltage L2 (hereinafter referred to as “down ramp voltage L2”) is applied.

  During this time, weak initialization discharges occur between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm, respectively. . Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value.

  In the present embodiment, the downward ramp voltage L5, which is an adjustment downward ramp voltage that decreases from the voltage Ve toward the voltage Vi5 while the downward ramp voltage L2 is being applied to the scan electrodes SC1 to SCn, is applied. The voltage is applied to sustain electrode SU1 through sustain electrode SUn. That is, the down-ramp voltage L5 is generated later in time than the down-ramp voltage L2, and is applied to the sustain electrodes SU1 to SUn. At this time, the ramp-down voltage L5 is generated so that the phases of the lowest voltage (voltage Vi4) of the ramp-down voltage L2 and the lowest voltage (voltage Vi5) of the ramp-down voltage L5 are aligned with each other.

  By applying the down ramp voltage L2 to scan electrode SC1 through scan electrode SCn, the potential difference between scan electrode 22 and sustain electrode 23 gradually increases. As a result, the weak initialization discharge generated between the scan electrode 22 and the sustain electrode 23 is maintained. However, if the duration of the initialization discharge is excessive, the wall charge is excessively adjusted, and a normal address operation cannot be performed in the subsequent address period. At this time, when down-ramp voltage L5 is applied to sustain electrode SU1 through sustain electrode SUn, the expansion of the potential difference between scan electrode 22 and sustain electrode 23 is alleviated, and the initializing discharge generated between scan electrode 22 and sustain electrode 23 is reduced. It is suppressed. In the present embodiment, the initialization discharge is adjusted in this way, and the wall charge adjustment due to the initialization discharge is prevented from becoming excessive.

  Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the subsequent address period, negative scan pulse voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (corresponding to a discharge cell to be lit up is applied to data electrode D1 through data electrode Dm. A positive address pulse voltage Vd is applied to k = 1 to m) to selectively generate an address discharge in each discharge cell.

  Specifically, voltage Ve is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vcc (voltage Vcc = voltage Va + voltage Vsc) is applied to scan electrode SC1 through scan electrode SCn.

  The negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd−voltage Va) between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1. The difference is added and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Further, since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is maintained at the difference between the externally applied voltages (voltage Ve−voltage Va). The difference between the wall voltage on the electrode SU1 and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission.

  In this sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage, so that a sustain discharge occurs again between sustain electrode SUi and scan electrode SCi, and the sustain cell is maintained. Negative wall voltage is accumulated on electrode SUi, and positive wall voltage is accumulated on scan electrode SCi. Similarly, the address discharge was caused in the address period by alternately applying the number of sustain pulses obtained by multiplying the brightness weight to the brightness magnification to scan electrode SC1 to scan electrode SCn and sustain electrode SU1 to sustain electrode SUn. Sustain discharge is continuously generated in the discharge cell.

  Then, after the sustain pulse is generated in the sustain period, 0 (V) is applied to scan electrode SC1 to scan electrode SCn while 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm. A ramp voltage L3 (hereinafter referred to as “erase ramp voltage L3”) that gradually increases (for example, about 10 V / μsec) toward voltage Vers exceeding the discharge start voltage is applied. Thereby, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated while the voltage applied to scan electrode SC1 through scan electrode SCn increases. When the increasing voltage reaches the predetermined voltage Vers, the voltage applied to scan electrode SC1 through scan electrode SCn is decreased to 0 (V) as the base potential.

  At this time, the charged particles generated by this weak discharge are accumulated on sustain electrode SUi and scan electrode SCi so as to alleviate the voltage difference between sustain electrode SUi and scan electrode SCi. Therefore, in the discharge cell in which the sustain discharge has occurred, the wall voltage between scan electrode SC1 on scan electrode SCn and sustain electrode SU1 on sustain electrode SUn is the difference between the voltage applied to scan electrode SCi and the discharge start voltage, That is, it is weakened to the level of (voltage Vers−discharge start voltage). As a result, in the discharge cell in which the sustain discharge has occurred, part or all of the wall voltage on scan electrode SCi and sustain electrode SUi is erased while leaving the positive wall charge on data electrode Dk. That is, the discharge generated by the erasing ramp voltage L3 serves as an “erasing discharge” for erasing unnecessary wall charges accumulated in the discharge cell in which the sustain discharge has occurred (hereinafter, the discharge generated by the erasing ramp voltage L3 is “ This is called “erase discharge”).

  Thereafter, scan electrode SC1 to scan electrode SCn are returned to 0 (V), and the sustain operation in the sustain period is completed.

  In the initialization period of the second SF, a drive voltage waveform in which the first half of the initialization period of the first SF is omitted is applied to each electrode. That is, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm. Scan electrode SC1 through scan electrode SCn has a voltage that is less than the discharge start voltage (for example, 0 (V)) to the negative voltage Vi4 exceeding the discharge start voltage toward the negative voltage Vi4 that gradually decreases (for example, at a gradient of about −2.5 V / μsec) (hereinafter referred to as “down-ramp voltage”). L4 ").

  As a result, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the immediately preceding subfield (first SF in FIG. 3), and the wall voltage on the scan electrode SCi and the sustain electrode SUi is weakened. The wall voltage above the data electrode Dk (k = 1 to m) is also adjusted to a value suitable for the write operation. On the other hand, initializing discharge does not occur in the discharge cells that did not cause sustain discharge in the sustain period of the immediately preceding subfield. As described above, the initializing operation in the second SF is a selective initializing operation in which the initializing discharge is performed on the discharge cells in which the sustain operation has been performed in the sustain period of the immediately preceding subfield.

  In the initialization period of the second SF, as in the initialization period of the first SF, the lowest voltage (voltage) of the down-ramp voltage L4 is being applied while the down-ramp voltage L4 is being applied to the scan electrodes SC1 to SCn. Vi4) and the ramp-down voltage L5 are generated so that the phases of the ramp-down voltage L5 and the lowest voltage (voltage Vi5) are aligned with each other, applied to the sustain electrodes SU1 to SUn, and the initializing discharge is adjusted. Yes.

  In the address period of the second SF, the same drive waveform as that in the address period of the first SF is applied to scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. In the sustain period of the second SF, similarly to the sustain period of the first SF, a predetermined number of sustain pulses are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.

  In the subfields after the third SF, scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm are different from each other except that the number of sustain pulses generated in the sustain period is different. A drive waveform similar to 2SF is applied.

  The above is the outline of the driving voltage waveform applied to each electrode of the panel 10.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of plasma display device 1 according to one embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 assigns gradation values expressed in one field to each discharge cell based on the inputted image signal sig, and the gradation value assigned to each discharge cell is emitted / non-emission for each subfield. Is converted into image data indicating.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H, the vertical synchronization signal V, and a comparison result in the comparison circuit 57 described later, and each circuit block (image signal) Processing circuit 41, data electrode drive circuit 42, scan electrode drive circuit 43 and sustain electrode drive circuit 44).

  The data electrode drive circuit 42 converts the data for each subfield constituting the image data into signals corresponding to the data electrodes D1 to Dm, and each data electrode based on the timing signal supplied from the timing generation circuit 45. D1 to the data electrode Dm are driven.

  Scan electrode driving circuit 43 generates an initialization waveform generating circuit for generating an initialization waveform to be applied to scan electrode SC1 to scan electrode SCn in the initialization period, and generates a sustain pulse to be applied to scan electrode SC1 to scan electrode SCn in the sustain period. And a scan pulse generating circuit that includes a plurality of scan electrode driving ICs (hereinafter abbreviated as “scan ICs”) and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period. Then, each of the scan electrodes SC1 to SCn is driven based on the timing signal supplied from the timing generation circuit 45. The comparator circuit 57 also compares the down-ramp voltage L2 and the down-ramp voltage L4 with a preset comparison voltage Vo and outputs the comparison result to the timing generation circuit 45.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve, and drives sustain electrode SU1 through sustain electrode SUn based on a timing signal output from timing generation circuit 45.

  FIG. 5 is a circuit diagram showing a configuration example of scan electrode driving circuit 43 of plasma display apparatus 1 according to the embodiment of the present invention. Scan electrode driving circuit 43 includes sustain pulse generation circuit 50 that generates a sustain pulse, initialization waveform generation circuit 51 that generates an initialization waveform, and scan pulse generation circuit 52 that generates a scan pulse. Each output terminal is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. In the present embodiment, the voltage input to scan pulse generating circuit 52 is referred to as “reference potential A”. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for switching off is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”. To do.

  In FIG. 5, when a circuit using the negative voltage Va (for example, the Miller integrating circuit 54) is operating, the circuit using the sustain pulse generating circuit 50 and the voltage Vr (for example, the Miller integrating circuit 54) is operated. Miller integration circuit 53) and a separation circuit using switching element Q4 for electrically separating a circuit using voltage Vers (for example, Miller integration circuit 55) are shown. Further, when a circuit using the voltage Vr (for example, the Miller integrating circuit 53) is operating, a circuit using the voltage Vers having a voltage lower than the voltage Vr (for example, the Miller integrating circuit 55) is operated. A separation circuit using a switching element Q6 for electrical separation is shown.

  Sustain pulse generation circuit 50 includes a generally used power recovery circuit (not shown) and a clamp circuit (not shown), and is output from timing generation circuit 45, similarly to sustain pulse generation circuit 80 described later. Based on the timing signal, the internal switching elements are switched to generate sustain pulses. In FIG. 5, details of the signal path of the timing signal are omitted.

  The initialization waveform generation circuit 51 includes a Miller integration circuit 53, a Miller integration circuit 54, and a Miller integration circuit 55. Miller integrating circuit 53 is a ramp voltage generating circuit that generates up-ramp voltage L1, Miller integrating circuit 55 is an erasing ramp voltage L3, and Miller integrating circuit 54 is a ramp voltage generating circuit that generates down-ramp voltage L2 and down-ramp voltage L4. In FIG. 5, the input terminal of Miller integrating circuit 53 is input terminal IN1, the input terminal of Miller integrating circuit 55 is input terminal IN3, and the input terminal of Miller integrating circuit 54 is input terminal IN2.

  Miller integrating circuit 53 has switching element Q1, capacitor C1, and resistor R1, and at the time of initialization operation, reference potential A of scan electrode driving circuit 43 is set to voltage Vi2 based on the timing signal output from timing generating circuit 45. The rising ramp voltage L1 is generated by gradually increasing in a ramp shape (eg, at 1.3 V / μsec).

  Miller integrating circuit 55 has switching element Q3, capacitor C3, and resistor R3, and at the end of the sustain period, reference potential A is steeper than up-ramp voltage L1 based on the timing signal output from timing generating circuit 45. The erase ramp voltage L3 is generated by increasing the voltage Vers at a gradient (eg, 10 V / μsec).

  Miller integrating circuit 54 has switching element Q2, capacitor C2, and resistor R2, and during initialization operation, reference potential A is gradually ramped up to voltage Vi4 based on the timing signal output from timing generating circuit 45 ( For example, the ramp-down voltage L2 and the ramp-down voltage L4 are generated by decreasing the voltage (with a slope of −2.5 V / μsec).

  Although the present embodiment shows an example in which the initialization waveform generation circuit 51 is configured using a Miller integration circuit using a FET (Field Effect Transistor) that is practical and has a relatively simple configuration. The embodiment is not limited to this configuration. Any circuit that can raise or lower the reference potential A in a ramp shape may be used. For example, an RC integration circuit may be used instead of the Miller integration circuit.

  Scan pulse generation circuit 52 includes switching elements QH1 to QHn and switching elements QL1 to QLn for applying a scan pulse to each of n scan electrodes SC1 to SCn. One terminal of the switching element QHj (j = 1 to n) and one terminal of the switching element QLj are connected to each other, and the connecting portion serves as an output terminal of the scan pulse generating circuit 52, and is connected to the scan electrode SCj. It is connected.

  The other terminal of the switching element QHj is an input terminal INb on the high voltage side, and is connected to a voltage Vc obtained by superimposing the voltage Vsc on the reference potential A. The other terminal of the switching element QLj is a low voltage side input terminal INa and is connected to the reference potential A. Switching element QH1 to switching element QHn and switching element QL1 to switching element QLn are integrated into an IC (Integrated Circuits). This IC is a scan IC that outputs a scan pulse to the scan electrode 22, and a plurality of scan ICs are used for the scan pulse generation circuit 52.

  Further, the scan pulse generation circuit 52 includes a switching element Q5 that connects the reference potential A to the negative voltage Va in the address period, a power source VSC that generates the voltage Vsc and superimposes the voltage Vsc on the reference potential A, and a reference potential A. A diode D31 and a capacitor C31 for applying the voltage Vc generated by superimposing the voltage Vsc to the input terminal INb, a comparator CP1 for comparing the magnitudes of the input signals input to the two input terminals, and a voltage Vset2 A power source that generates and superimposes the voltage Va, a power source that generates a voltage Vset3 and superimposes it on the voltage Va, a switching element SW2 for applying voltage Va + voltage Vset2 to one input terminal of the comparator CP1, and a comparator A switching element SW3 for applying voltage Va + voltage Vset3 to one input terminal of CP1 is provided. The other input terminal of the comparator CP1 is connected to the reference potential A, and the output signal of the comparator CP1 is used to control the switching elements QH1 to QHn and the switching elements QL1 to QLn.

  In the scan pulse generation circuit 52 configured as described above, based on the timing signal output from the timing generation circuit 45, image data indicating light emission / non-light emission for each subfield of each discharge cell, and the comparison result in the comparator CP1, One of the signals input to the two input terminals of the input terminal INa and the input terminal INb is output.

  For example, in the writing period, the switching element Q5 is turned on to connect the reference potential A to the negative voltage Va, the negative voltage Va is superimposed on the input terminal INa, and the voltage Vsc is superimposed on the voltage Va on the input terminal INb. A voltage Vc, that is, a voltage Vcc is applied. For the scan electrode SCi to which the scan pulse is applied, the switching element QHi is turned off, the switching element QLi is turned on, and the negative scan pulse voltage Va is applied to the scan electrode SCi via the switching element QLi. For the scan electrode SCh to which no scan pulse is applied (h is a value obtained by excluding i from 1 to n), the switching element QLh is turned off, the switching element QHh is turned on, and scanning is performed via the switching element QHh. A voltage Vcc is applied to the electrode SCh.

  Further, the scan pulse generation circuit 52 includes a comparison circuit 57 that compares the reference potential A with a preset comparison voltage Vo. The comparison circuit 57 compares the down-ramp voltage L2 or the down-ramp voltage L4 with the comparison voltage Vo during the initialization period, and generates a timing signal indicating that the down-ramp voltage L2 or the down-ramp voltage L4 has reached the comparison voltage Vo. Output to the circuit 45.

  Scan pulse generation circuit 52 generates a voltage waveform generated by initialization waveform generation circuit 51 during the initialization period, and outputs a voltage waveform generated by sustain pulse generation circuit 50 during the sustain period. It is assumed that each switching element is controlled by a timing signal output from the circuit 45. In FIG. 5, details of the signal path of the timing signal are omitted. Details of the operation of the scan pulse generation circuit 52 during the initialization period will be described later.

  FIG. 6 is a circuit diagram showing a configuration example of the sustain electrode driving circuit 44 of the plasma display device 1 according to the embodiment of the present invention. In FIG. 6, the interelectrode capacitance of the panel 10 (parasitic capacitance between the scan electrode 22 and the sustain electrode 23) is shown as Cp, and details of the circuit diagram of the scan electrode drive circuit 43 are omitted.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit 80. Sustain pulse generation circuit 80 includes power recovery circuit 81 and clamp circuit 82, and is connected to sustain electrode SU1 through sustain electrode SUn. Note that, in both the writing period and the sustain period, the same drive voltage may be applied to all the sustain electrodes 23 all at once, and it is not necessary to individually drive the sustain electrodes 23 unlike the scan electrodes 22. The output voltage of the drive circuit 44 is applied to all the sustain electrodes 23 in parallel.

  The power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode D21, a backflow prevention diode D22, and a resonance inductor L20. Then, the interelectrode capacitance Cp and the inductor L20 are LC-resonated, and the sustain pulse rises and falls.

  Clamp circuit 82 has switching element Q23 for clamping sustain electrode SU1 through sustain electrode SUn to voltage Vs, and switching element Q24 for clamping sustain electrode SU1 through sustain electrode SUn to the ground potential (0 (V)). is doing.

  Sustain pulse generation circuit 80 generates a sustain pulse by switching on / off of each switching element in accordance with a timing signal output from timing generation circuit 45.

  For example, when the sustain pulse is raised, the switching element Q21 is turned on to cause LC resonance between the interelectrode capacitance Cp and the inductor L20, and the sustain electrode is passed through the switching element Q21, the diode D21, and the inductor L20 from the power recovery capacitor C20. Electric power is supplied to SU1 through sustain electrode SUn. Then, when the voltage of sustain electrode SU1 through sustain electrode SUn approaches voltage Vs, switching element Q23 is turned on to clamp sustain electrode SU1 through sustain electrode SUn at voltage Vs.

  Conversely, when the sustain pulse is lowered, switching element Q22 is turned on to cause LC resonance between interelectrode capacitance Cp and inductor L20, and for power recovery from interelectrode capacitance Cp through inductor L20, diode D22, and switching element Q22. The power is recovered in the capacitor C20. Then, when the voltage of sustain electrode SU1 through sustain electrode SUn approaches 0 (V), switching element Q24 is turned on, and sustain electrode SU1 through sustain electrode SUn are clamped at 0 (V).

  The sustain electrode drive circuit 44 includes a power source VE that generates the voltage Ve, a switching element Q26 and a switching element Q27 for applying the voltage Ve to the sustain electrodes SU1 to SUn, and a backflow prevention diode D30. Have. Then, switching element Q26 and switching element Q27 are turned on based on a timing signal output from timing generation circuit 45, and voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn.

  In FIG. 6, details of the signal path of the timing signal are omitted. Moreover, each switching element can be comprised using generally known elements, such as MOSFET and IGBT.

  In sustain electrode drive circuit 44, all switching elements are turned off to electrically isolate sustain electrode SU1 through sustain electrode SUn from sustain electrode drive circuit 44, and sustain electrode SU1 through sustain electrode SUn are in a high impedance state. Can be. Thus, the voltage applied to scan electrode SC1 through scan electrode SCn can be applied to sustain electrode SU1 through sustain electrode SUn via interelectrode capacitance Cp.

  Next, a method for stabilizing the write operation performed in the initialization period in this embodiment will be described.

  In the present embodiment, as described above, the down-ramp voltage L2 is applied to scan electrode SC1 to scan electrode SCn in the all-cell initializing subfield, while the down-ramp voltage L4 is selected in the selective initializing subfield. Are applied to scan electrode SC1 through scan electrode SCn, down ramp voltage L5, which drops from voltage Ve toward voltage Vi5, is set to down ramp voltage L2 or the lowest voltage of down ramp voltage L4 (voltage Vi4). The down-ramp voltage L5 is generated so that the phases of the down-ramp voltage L5 and the lowest voltage (voltage Vi5) are aligned with each other and applied to the sustain electrodes SU1 to SUn to adjust the initializing discharge.

  At this time, in the present embodiment, in the subfield with a small luminance weight, the lower ramp voltage L2, the lowest voltage of the downramp voltage L4 (voltage Vi4), and the downramp voltage L5 are smaller than those in the subfield with a large luminance weight. The minimum voltage (voltage Vi5) is reduced.

  FIG. 7 is a waveform diagram schematically showing drive voltage waveforms applied to scan electrode 22 and sustain electrode 23 in the initialization period in one embodiment of the present invention. FIG. 7 shows the initialization operation in the selective initialization subfield, that is, the operation when the down-ramp voltage L4 is applied to scan electrode SC1 through scan electrode SCn. The operation in the all-cell initialization subfield is also shown in FIG. It is the same.

  In the present embodiment, in the subfield having a small luminance weight, the voltage Vi4 that is the lowest voltage of the down-ramp voltage L4 is set lower than that in the subfield having a large luminance weight. For example, in the subfield having a small luminance weight, the down-ramp voltage L4 is set to the voltage Vset2 (that is, the voltage Vi4 = the voltage Va + the voltage Vset2) as shown by the broken line in FIG. 7 and the difference voltage between the scanning pulse voltage Va and the voltage Vi4. In the subfield having a large luminance weight, as shown by the solid line in FIG. 7, the difference voltage between the scan pulse voltage Va and the voltage Vi4 is set to a voltage Vset3 (that is, a voltage Vset3 larger than the voltage Vset2). The voltage Vi4 = the voltage Va + the voltage Vset3).

  In the present embodiment, in the subfield with a small luminance weight, the voltage Vi5 that is the lowest voltage of the down-ramp voltage L5 is set lower than that in the subfield with a large luminance weight. For example, in the subfield having a small luminance weight, as shown by the broken line in FIG. 7, the down-ramp voltage L5 is the difference voltage between the voltage Ve and the voltage Vi5 (hereinafter, this difference voltage is referred to as “voltage VeHz”). (Ie, when the voltage Vi5 = voltage Ve−voltage VeHz2) is generated, in the subfield having a large luminance weight, the down-ramp voltage L5 is lower than the voltage VeHz2 as shown by the solid line in FIG. The voltage VeHz3 (that is, voltage Vi5 = voltage Ve−voltage VeHz3) is generated.

  In any case, the down-ramp voltage L5 is generated so that the phases of the lowest voltage of the down-ramp voltage L4 and the lowest voltage of the down-ramp voltage L5 are aligned with each other. This is to prevent an unnecessary potential difference from occurring between the scan electrode 22 and the sustain electrode 23.

  In the present embodiment, this stabilizes the write operation. This is due to the following reason.

  First, the reason why it is desirable to lower the minimum voltage (voltage Vi4) of the down-ramp voltage L4 and lower the minimum voltage (voltage Vi5) of the down-ramp voltage L5 in the subfield having a small luminance weight will be described. In the following description, one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each subfield from the first SF to the eighth SF is (1, 2, 4, 8, 16, 32, 64, 128).

  FIG. 8 is a diagram schematically showing the relationship between unnecessary wall charges remaining in the discharge cells after the erasing discharge and the subfields. In FIG. 8, the vertical axis represents the amount of unnecessary wall charges remaining in the discharge cell after the erase discharge, and the horizontal axis represents the subfield.

  In the sustain period, it has been confirmed that the sustain discharge generated at the beginning of the sustain period has a relatively weak discharge intensity, and the discharge intensity gradually increases by repeating the sustain discharge. This is probably because the number of priming particles in the discharge cell is small at the beginning of the sustain period, and the priming particles are gradually increased by repeating the sustain discharge, so that the discharge is strongly generated.

  Therefore, in a subfield where the luminance weight is small and the number of sustain pulses generated is small, the sustain period ends before the discharge intensity of the sustain discharge sufficiently increases, and the erasing lamp does not generate enough priming particles in the discharge cell. There is a possibility that an erasing discharge is caused by the voltage L3.

  At this time, if an erasing discharge occurs with insufficient priming particles, the erasing discharge is also insufficient and the erasing operation is not performed sufficiently (hereinafter referred to as “erasing failure”), and is unnecessary in the discharge cell. Wall charges remain.

  As a result, as shown in FIG. 8, in the subfield having a small luminance weight, unnecessary wall charges remaining in the discharge cells after the erasing operation with the erasing ramp voltage L3 are larger than those in the subfield having a large luminance weight. Cheap.

  As the unnecessary wall charges remaining in the discharge cells increase due to the erasure failure, the subsequent subfield is more likely to generate “erroneous addressing” in which an erroneous address discharge is generated in the discharge cells that should not generate the address discharge. .

  At this time, if the voltage Vi4 which is the lowest voltage of the down-ramp voltage L4 (or down-ramp voltage L2) is lowered, the duration of the initialization discharge by the down-ramp voltage L4 (or down-ramp voltage L2) can be extended. Accordingly, the amount of wall charges adjusted by the initialization discharge can be increased, and unnecessary wall charges remaining in the discharge cells due to the erasure failure can be adjusted, so that “erroneous writing” can be reduced. Conversely, when the voltage Vi4 is increased, the duration of the initialization discharge by the down-ramp voltage L4 (or the down-ramp voltage L2) is shortened, so that the amount of wall charges adjusted by the initialization discharge decreases. There is a risk of increasing "wrong writing".

  On the other hand, the voltage state in the discharge cell after completion of the initialization operation is formed based on the voltage applied to the scan electrode 22 at the end of the initial operation, that is, the voltage Vi4. For this reason, when the scan pulse voltage Va is applied to the scan electrode 22 in the address period, the difference voltage between the voltage Vi4 and the scan pulse voltage Va is added to the voltage in the discharge cell formed at the end of the initialization operation. become.

  Therefore, as the voltage difference between the voltage Vi4 and the scan pulse voltage Va increases (when the scan pulse voltage Va is constant, the voltage Vi4 increases), the voltage added to the discharge cells during the address operation increases. Address discharge is likely to occur. Conversely, the smaller the difference voltage between the voltage Vi4 and the scan pulse voltage Va (the lower the voltage Vi4 when the scan pulse voltage Va is constant), the lower the voltage added to the discharge cells during the address operation. Thus, the address discharge is less likely to occur.

  That is, if the voltage Vi4 is lowered, “erroneous writing” is reduced, but on the other hand, the address discharge is less likely to occur. Conversely, if the voltage Vi4 is increased, the address discharge is likely to occur, Therefore, it is desirable to set the voltage Vi4 in consideration of these points.

  FIG. 9 is a characteristic diagram showing the relationship between the upper limit of the difference voltage between the voltage Vi4 and the scan pulse voltage Va and the subfield. In FIG. 9, the vertical axis represents the upper limit of the difference voltage between the voltage Vi4 and the scan pulse voltage Va that can stably generate the address discharge with respect to “erroneous writing” due to the erasure failure. The horizontal axis represents a subfield. In the measurement of the characteristics shown in FIG. 9, the scan pulse voltage Va was maintained at a constant voltage, and the experiment was performed by changing the voltage Vi4 while maintaining the gradient of the down-ramp voltage L4.

  As shown in FIG. 9, the upper limit of the difference voltage between the voltage Vi4 and the scan pulse voltage Va that can generate the address discharge stably with respect to the “erroneous writing” due to the erasure failure is the subfield with the smaller luminance weight. Lower. This is because, as described above, in the subfield with a small luminance weight, unnecessary wall charges remaining in the discharge cells due to the erasure failure are likely to increase compared to the subfield with a large luminance weight. By reducing Vi4, that is, by reducing the difference voltage between the voltage Vi4 and the scan pulse voltage Va, it is possible to sufficiently secure the duration of the initialization discharge by the downramp voltage L4 (or the downramp voltage L2). Expresses what is desirable.

  However, if the voltage Vi4 is lowered and the duration of the initialization discharge by the down-ramp voltage L4 (or down-ramp voltage L2) is extended, an erroneous sustain discharge occurs even though no address discharge has occurred. It has been confirmed that “sustained erroneous discharge” tends to occur. This is because the initializing discharge generated between the scan electrode 22 and the sustaining electrode 23 adjusts the wall charge used for the sustaining discharge, and is maintained when the initializing operation is extended by lowering the voltage Vi4. This is probably because the wall charge used for the discharge is excessively adjusted.

  At this time, it is confirmed that the “maintained erroneous discharge” is reduced by increasing the voltage VeHz to extend the generation time of the down-ramp voltage L5 and extending the time to suppress the initialization discharge by the down-ramp voltage L5. It was done.

  FIG. 10 is a characteristic diagram showing the relationship between the upper limit of sustain pulse voltage Vs that can stably generate sustain discharge and the subfield. In FIG. 10, the vertical axis represents the upper limit of sustain pulse voltage Vs at which sustain discharge can be generated stably. When sustain pulse voltage Vs is set to a voltage higher than this upper limit, “sustained erroneous discharge” is likely to occur. ing. That is, the upper limit of the sustain pulse voltage Vs shown in FIG. 10 indicates that “sustain false discharge” is less likely to occur as the numerical value is higher. The horizontal axis represents a subfield.

  In FIG. 10, the characteristic when the voltage VeHz is set to 15 (V) is indicated by a broken line, and the characteristic when the voltage VeHz is set to 20 (V) is indicated by a solid line.

  As shown in FIG. 10, it was confirmed that the upper limit of the sustain pulse voltage Vs that can stably generate the sustain discharge can be increased by increasing the voltage VeHz in all the subfields. That is, it is possible to reduce the “sustained erroneous discharge” by lowering the voltage Vi5 and extending the generation time of the down-ramp voltage L5.

  As described above, when the down-ramp voltage L5 is applied to the sustain electrode 23, the initialization discharge generated between the scan electrode 22 and the sustain electrode 23 is suppressed. Therefore, the voltage VeHz is increased to decrease the down-ramp voltage L5. It is considered that the wall charge used for the sustain discharge can be suppressed from being excessively adjusted by extending the time for applying the voltage to the sustain electrode 23.

  From these facts, it is effective to reduce the minimum voltage (voltage Vi4) of the down-ramp voltage L4 in order to reduce “erroneous writing” due to erasure failure that is likely to occur in a subfield having a small luminance weight. Regarding the reduction of “sustained erroneous discharge” that is likely to occur by lowering Vi4 and extending the duration of the initialization discharge by the downramp voltage L4 (or downramp voltage L2), the minimum voltage (voltage) of the downramp voltage L5 It is considered effective to lower Vi5).

  Next, in the subfield having a large luminance weight, it is desirable to make the lowest voltage (voltage Vi4) of the down-ramp voltage L4 and the lowest voltage (voltage Vi5) of the down-ramp voltage L5 higher than those of the sub-field having a small luminance weight. Will be described.

  When non-lighting discharge cells (hereinafter abbreviated as “non-lighting cells”) and lighting discharge cells (hereinafter abbreviated as “lighting cells”) are adjacent, priming particles generated by the sustain discharge of the lighted cells May move to a non-lighted cell. This phenomenon is hereinafter referred to as “maintenance priming movement”. The amount of priming particles that move into the non-lighted cells by this sustain priming movement increases according to the number of times sustain discharge occurs.

  In addition, the priming particles that move into the non-lighting cells by the maintenance priming movement are accumulated as unnecessary wall charges in the non-lighting cells. Therefore, unnecessary wall charges accumulated in the non-lighted cells due to the maintenance priming movement are likely to increase in the subfield having a large luminance weight than in the subfield having a small luminance weight.

  FIG. 11 is a diagram schematically showing the relationship between unnecessary wall charges accumulated in the discharge cells by the sustain priming movement and the subfields. In FIG. 11, the vertical axis represents the amount of unnecessary wall charges accumulated in the discharge cell, and the horizontal axis represents the subfield.

  In FIG. 11, unnecessary wall charges remaining in the discharge cells after the erasing discharge shown in FIG. 8 are indicated by broken lines, and the results of further accumulation of unnecessary wall charges due to the maintenance priming movement on the wall charges are shown by solid lines. It shows with.

  As indicated by a broken line in FIG. 11, unnecessary wall charges remaining in the discharge cell after the erasing discharge are reduced in the subfield having the larger luminance weight than the subfield having the smaller luminance weight. However, the amount of decrease gradually saturates as the luminance weight increases.

  On the other hand, unnecessary wall charges accumulated in the non-lighted cells due to the sustain priming movement increase according to the number of occurrences of the sustain discharge, and thus increase in the subfield having a larger luminance weight than the subfield having a smaller luminance weight, The increase amount increases as the luminance weight increases.

  Therefore, as indicated by a solid line in FIG. 11, unnecessary wall charges accumulated in the discharge cell due to the addition of unnecessary wall charges due to the sustain priming movement to the wall charges remaining in the discharge cells after the erasing discharge are luminance It increases in a subfield with a larger luminance weight than a subfield with a smaller weight. As the unnecessary wall charges increase, “erroneous writing” is more likely to occur.

  As described above, a subfield with a large luminance weight is likely to cause “wrong writing” due to a different reason from a subfield with a small luminance weight, that is, a maintenance priming movement.

  At this time, by reducing the voltage VeHz, the generation time of the down-ramp voltage L5 is shortened, and the time for suppressing the initialization discharge by the down-ramp voltage L5 is shortened, thereby reducing “wrong writing” due to the maintenance priming movement. It was confirmed that

  FIG. 12 is a characteristic diagram showing the relationship between the upper limit of the differential voltage between the voltage Vi4 and the scan pulse voltage Va and the subfield. In FIG. 12, the vertical axis represents the upper limit of the difference voltage between the voltage Vi4 and the scan pulse voltage Va that can stably generate the address discharge with respect to “erroneous address” due to the maintenance priming movement. The horizontal axis represents a subfield. In the measurement of the characteristics shown in FIG. 12, the scan pulse voltage Va was maintained at a constant voltage, and the experiment was performed by changing the voltage Vi4 while maintaining the gradient of the down-ramp voltage L4. Further, the experiment was performed by maintaining the voltage Ve at a constant voltage and changing the voltage VeHz while maintaining the gradient of the down-ramp voltage L5.

  In FIG. 12, the characteristic when the voltage VeHz is set to 20 (V) is indicated by a broken line, and the characteristic when the voltage VeHz is set to 15 (V) is indicated by a solid line.

  As shown in FIG. 12, the upper limit of the difference voltage between the voltage Vi4 and the scan pulse voltage Va that can generate the address discharge stably with respect to the “erroneous address” due to the sustain priming movement is a subfield having a large luminance weight. It gets lower. As shown in FIG. 11, in the subfield with a large luminance weight, unnecessary wall charges generated in the discharge cells due to the sustain priming movement are larger than those in the subfield with a small luminance weight. For this reason, the voltage Vi4 is lowered, that is, the difference voltage between the voltage Vi4 and the scan pulse voltage Va is reduced, so that the duration of the initialization discharge by the downramp voltage L4 (or the downramp voltage L2) is sufficient. It is desirable to secure.

  Then, as shown in FIG. 12, by reducing the voltage VeHz in all the subfields, the voltage Vi4 and the scanning pulse that can stably generate the address discharge with respect to the “erroneous address” caused by the maintenance priming movement. It was confirmed that the upper limit of the voltage difference from the voltage Va can be increased. That is, by increasing the voltage Vi5 and shortening the generation time of the down-ramp voltage L5, it becomes possible to reduce “wrong writing” due to the maintenance priming movement.

  As described above, when the down-ramp voltage L5 is applied to the sustain electrode 23, the initialization operation by the down-ramp L4 is suppressed. Therefore, the voltage Vi5 is increased and the down-ramp voltage L5 is applied to the sustain electrode 23. It is considered that by shortening the time and extending the duration of the initialization operation by the down ramp L4, it is possible to adjust more unnecessary wall charges generated in the discharge cells due to the maintenance priming movement.

  For these reasons, regarding the reduction of “erroneous writing” due to the maintenance priming movement that is likely to occur in the subfield having a large luminance weight, the minimum voltage (voltage Vi5) of the down-ramp voltage L5 is increased (that is, the voltage VeHz is decreased). ) Is considered effective.

  In the present embodiment, in FIG. 9, with respect to “erroneous writing” caused by an erasure failure that is likely to occur in a subfield with a small luminance weight, the voltage Vi4 is lowered to decrease the downramp voltage L4 (or the downramp voltage). It has been explained that it is effective to ensure a sufficient duration of the initialization discharge according to L2). Further, in FIG. 12, regarding “erroneous writing” caused by the maintenance priming movement that is likely to occur in the subfield having a large luminance weight, the voltage Vi4 is lowered and the initialization is performed by the downramp voltage L4 (or the downramp voltage L2). It was explained that it is effective to ensure a sufficient discharge duration.

  In such a case, it is desirable to set the voltage Vi4 by comparing the characteristics shown in FIG. 9 with the characteristics shown in FIG.

  FIG. 13 is a diagram in which the characteristic diagram shown in FIG. 9 and the characteristic diagram shown in FIG. 12 are superimposed. In FIG. 13, the characteristic shown in FIG. 9 is indicated by a solid line, and the characteristic when the voltage VeHz shown in FIG. 12 is set to 15 (V) is indicated by a broken line.

  As shown in FIG. 13, when the characteristics shown in FIG. 9 are compared with the characteristics shown in FIG. 12, the upper limit of the differential voltage between the voltage Vi4 and the scan pulse voltage Va is shown in FIG. 9 for the first to fifth SFs. The characteristics (characteristics indicated by solid lines) are lower, and the characteristics shown in FIG. 12 (characteristics indicated by broken lines) are lower in the sixth to eighth SFs. In addition, the characteristics indicated by the solid lines in the first to fifth SFs are lower than the characteristics indicated by the broken lines in the sixth to eighth SFs.

  On the other hand, in order to shorten the time required for driving the panel 10, it is desirable to increase the voltage Vi4 to shorten the generation time of the down-ramp voltage L4 (or down-ramp voltage L2).

  Therefore, in the comparison result shown in FIG. 13, the voltage Vi4 is set based on the characteristic shown in FIG. 9 (characteristic indicated by the solid line) in the first SF to the fifth SF, and is shown in FIG. 12 in the sixth SF to the eighth SF. It is desirable to set the voltage Vi4 based on the characteristics (characteristics indicated by broken lines).

  That is, in the present embodiment, the subfield with a small luminance weight (for example, the first SF to the fifth SF) has the lowest down-ramp voltage L4 than the subfield with a large luminance weight (for example, the sixth SF to the eighth SF). It is desirable to set the voltage Vi4, which is a voltage, low.

  On the other hand, it has been confirmed that in the subfield having a large luminance weight, the scanning pulse (amplitude) necessary for generating a stable address discharge increases.

  FIG. 14 is a characteristic diagram showing the relationship between the lower limit of the scan pulse (amplitude) that can generate the address discharge stably and the subfield. In FIG. 14, the vertical axis represents the lower limit of the scan pulse (amplitude) that can stably generate the address discharge. When the scan pulse (amplitude) is set to a value smaller than this lower limit, the address discharge is generated in the discharge cell that should generate the address discharge. This means that “non-light” that does not occur is likely to occur. That is, the lower limit of the scanning pulse (amplitude) shown in FIG. 14 indicates that “non-light” is less likely to occur as the numerical value is lower, and “non-light” is more likely to occur as the numerical value is higher. The horizontal axis represents a subfield.

  In FIG. 14, the characteristic when the difference voltage between the voltage Vi4 and the scan pulse voltage Va (hereinafter also simply referred to as “difference voltage”) is set to 20 (V) is shown by a broken line, and the difference voltage is 20 ( The characteristic when set to V) is indicated by a solid line.

  As shown in FIG. 14, the scan pulse (amplitude) necessary for stably generating the address discharge becomes higher as the subfield has a larger luminance weight. That is, the characteristic diagram shown in FIG. 14 indicates that “non-light” is more likely to occur in a subfield having a larger luminance weight.

  Then, as shown in FIG. 14, by increasing the difference voltage between the voltage Vi4 and the scan pulse voltage Va in all the subfields, the scan pulse (amplitude) required for stably generating the address discharge is lowered. It was confirmed that That is, it is possible to reduce “non-lighting” by increasing the voltage Vi4 and shortening the generation time of the down-ramp voltage L4.

  This seems to be due to the following reasons.

  In the sustain period, priming particles are generated in the discharge cell by the sustain discharge. Some of the priming particles combine with the wall charge, neutralizing the wall charge and reducing the wall charge. Since the amount of priming particles generated in the discharge cell by the sustain discharge changes according to the number of times the sustain discharge is generated, more priming particles are generated in the subfield having a larger luminance weight. Therefore, as the luminance field weight is larger, more wall charges are reduced by the priming particles.

  As the wall charge decreases, the scan pulse (amplitude) necessary for stably generating the address discharge during the address operation in the subsequent subfield increases. This is considered to be the reason why the scan pulse (amplitude) necessary for stably generating the address discharge is higher in the subfield having a larger luminance weight in the present embodiment.

  In addition, since the wall charge is adjusted in the initialization operation using the down-ramp voltage L4, in the discharge cell in which more wall charges are reduced by the priming particles, the initialization operation using the down-ramp voltage L4 is shortened, and the wall charge is reduced. It is desirable to reduce the adjustment amount. This is considered to be the reason why the scan pulse (amplitude) required for stably generating the address discharge can be lowered by increasing the voltage Vi4 and shortening the generation time of the down-ramp voltage L4.

  Further, in FIG. 14, when the difference voltage between the voltage Vi4 and the scan pulse voltage Va is set to 20 (V), and the characteristic when the difference voltage is set to 22 (V), the difference voltage is The lower limit of the scanning pulse (amplitude) of the first SF to the fifth SF when the differential voltage is set to 20 (V) than the lower limit of the scanning pulse (amplitude) of the sixth SF to the eighth SF when set to 22 (V). Is smaller. Therefore, in the characteristics shown in FIG. 14, the difference voltage between the voltage Vi4 and the scan pulse voltage Va may be 20 (V) in the first to fifth SFs, and 22 (V) in the high subfield. It is desirable.

  Also, as shown in FIG. 13, in the subfield with a small luminance weight (for example, the first SF to the fifth SF), the voltage Vi4 is set lower than the subfield with a large luminance weight (for example, the sixth SF to the eighth SF). It is desirable to do.

  For these reasons, in the present embodiment, in the subfield having a small luminance weight, the lowest voltage (voltage Vi4) of the down-ramp voltage L4 is set lower than that in the subfield having a large luminance weight. This reduces “erroneous writing” due to erasure failure that is likely to occur in a subfield with a small luminance weight, and reduces “erroneous writing” due to maintenance priming movement that is likely to occur in a subfield with a large luminance weight. be able to.

  In the subfield having a small luminance weight, the lowest voltage (voltage Vi5) of the down-ramp voltage L5 is set lower than that in the subfield having a large luminance weight. As a result, in the subfield having a small luminance weight, “sustain misdischarge” that is likely to occur by lowering the voltage Vi4 and extending the duration of the initialization discharge by the downramp voltage L4 (or the downramp voltage L2). And “erroneous writing” due to the maintenance priming movement that is likely to occur in a subfield with a large luminance weight.

  FIG. 15 is a diagram illustrating a setting example of the voltage difference between the voltage Vi4 and the scan pulse voltage Va and the voltage VeHz according to the embodiment of the present invention.

  As shown in FIG. 15, in the present embodiment, in a subfield with a large luminance weight (for example, the sixth SF to the eighth SF), the voltage difference between the voltage Vi4 and the scan pulse voltage Va is set to 22 (V), In a subfield with a small luminance weight (for example, the first SF to the fifth SF), the voltage Vi4 is 2 (V) lower than that of the subfield with a large luminance weight, and the difference voltage between the voltage Vi4 and the scan pulse voltage Va is 20 (V ).

  In addition, the voltage VeHz is set to 15 (V) in a subfield with a large luminance weight (for example, the sixth SF to the eighth SF), and the luminance weight is set to a subfield with a small luminance weight (for example, the first SF to the fifth SF). The voltage Vi5 is set 5 (V) lower than the large subfield and the voltage VeHz is set to 20 (V).

  In addition, the numerical value shown here is only what showed one Example of this invention, and this invention is not limited to this numerical value at all. Each numerical value is desirably set optimally according to the characteristics of the panel and the specifications of the plasma display device.

  In the present embodiment, when subfields are arranged so that the luminance weights are in ascending order or descending order, a plurality of adjacent subfields form one group. In the example described above, the first SF to the fifth SF are set as one group, and the sixth SF to the eighth SF are set as one group. Then, in the subfield belonging to the group having the small average value of the luminance weight (for example, the first SF to the fifth SF), the voltage is higher than the subfield belonging to the group having the large average value of the luminance weight (for example, the sixth SF to the eighth SF). Vi4 and voltage Vi5 are set low. However, in the present invention, the grouping is not limited to two groups, and may be grouped into three groups or more, or the voltage Vi4 and the voltage Vi5 are changed for each subfield. It may be.

  Also, as shown in the present embodiment, in the configuration in which the luminance weight of each subfield is set so that the luminance weight becomes larger in the later subfield, one group is a subfield in which the time is continuous. It will consist of However, when the luminance weight is not set so that the luminance weight becomes larger in the later subfield, for example, one field is composed of eight subfields (first SF, second SF,..., Eighth SF). In the configuration in which luminance weights of (1, 4, 16, 64, 2, 8, 32, 128) are set in each subfield, one group is not configured by temporally continuous subfields. For example, the first SF, the second SF, the third SF, the fifth SF, and the sixth SF of the luminance weight (1, 4, 16, 2, 8) constitute one group, and the fourth SF of the luminance weight (64, 32, 128). , 7th SF and 8th SF constitute one group. As described above, in the present embodiment, one group is formed by a plurality of adjacent subfields when the subfields are arranged so that the luminance weights are in ascending order or descending order.

  In the example shown in FIG. 15, the difference voltage between the voltage Vi4 and the scan pulse voltage Va is 20 (V) in the first to fifth SFs and 22 (V) in the sixth to eighth SFs, and the difference is 2 In contrast to (V), the voltage VeHz is 20 (V) in the first to fifth SFs and 15 (V) in the sixth to eighth SFs, and the difference is 5 (V). Therefore, in the first to fifth SFs, the voltage Vi4 must be decreased by 2 (V), while the voltage Vi5 must be decreased by 5 (V) as compared with the sixth to eighth SFs. In this case, if the generation timing of the down-ramp voltage L5 is the same in the first SF to the fifth SF and the sixth SF to the eighth SF, the voltage Vi5 also decreases only by 2 (V).

  Therefore, in the present embodiment, as shown in FIG. 7, the down-ramp voltage L4 (or down-ramp voltage L2) is compared with a preset comparison voltage Vo, and the down-ramp voltage L4 (or down-ramp voltage) is compared. It is assumed that the voltage Vi5 is controlled by changing the time from when L2) reaches the comparison voltage Vo to when the down-ramp voltage L5 is generated. For example, in the example shown in FIG. 7, when the voltage Vi5 is set to the voltage Ve−voltage VeHz2, the downramp voltage L5 after the time T41 after the downramp voltage L4 (or the downramp voltage L2) reaches the comparison voltage Vo. Is generated. Further, when the voltage Vi5 is set to the voltage Ve−voltage VeHz3, after the down-ramp voltage L4 (or the down-ramp voltage L2) reaches the comparison voltage Vo, the down-ramp voltage L5 is set after the time T42 longer than the time T41. appear. In the present embodiment, by performing such control, it is possible to accurately set the minimum voltage of the down-ramp voltage L5 to an arbitrary voltage.

  Next, an operation for generating the up-ramp voltage L1, the down-ramp voltage L2, and the down-ramp voltage L5 in the initialization period of the all-cell initialization subfield will be described with reference to FIG.

  FIG. 16 is a timing chart for explaining an example of the operations of scan electrode drive circuit 43 and sustain electrode drive circuit 44 during the initialization period of the all-cell initialization subfield in one embodiment of the present invention. Although the description of the operation of scan electrode drive circuit 43 when generating downramp voltage L4 in the selective initialization subfield is omitted, the operation of generating downramp voltage L4 is performed as shown in FIG. It is assumed that the operation is the same as that for generating.

  In FIG. 16, the initialization period is divided into four periods indicated by periods T1 to T4, and each period will be described. Hereinafter, it is assumed that the voltage Vi1 is equal to the voltage Vsc, the voltage Vi2 is equal to the voltage Vsc + the voltage Vr, the voltage Vi3 is equal to the voltage Vs used when generating the sustain pulse, and the voltage Vi4 is a negative voltage. In the following description, it is assumed that Va + voltage Vset2 (or voltage Vset3) is equal, and voltage Vi5 is equal to voltage Ve−voltage VeHz2 (or voltage VeHz3). In the drawing, a signal for turning on the switching element is represented as “Hi” and a signal for turning off the switching element is represented as “Lo”.

  FIG. 16 shows an example in which the voltage Vs is set to a voltage value higher than the voltage Vsc. However, the voltage Vs and the voltage Vsc may be equal to each other, or the voltage Vs However, the voltage value may be lower than the voltage Vsc.

  First, before entering the period T1, the clamp circuit of the sustain pulse generating circuit 50 is operated to set the reference potential A to 0 (V), the switching elements QH1 to QHn are turned off, and the switching elements QL1 to QLn are turned on. Turn on and apply the reference potential A, that is, 0 (V) to scan electrode SC1 through scan electrode SCn.

  In sustain pulse generating circuit 80, switching element Q24 of clamp circuit 82 is turned on, and the other switching elements are turned off, and 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn.

(Period T1)
In the period T1, the switching elements QH1 to QHn are turned on, and the switching elements QL1 to QLn are turned off. Thus, voltage Vc (that is, voltage Vc = voltage Vsc) obtained by superimposing voltage Vsc on reference potential A (0 (V) at this time) is applied to scan electrode SC1 through scan electrode SCn.

(Period T2)
In the period T2, the switching elements QH1 to QHn and the switching elements QL1 to QLn maintain the same state as the period T1.

  Then, the input terminal IN1 of the Miller integrating circuit 53 that generates the up-ramp voltage L1 is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN1. As a result, a constant current flows toward the capacitor C1, the source voltage of the switching element Q1 rises in a ramp shape, and the reference potential A starts to rise in a ramp shape from 0 (V). This voltage increase can be continued while the input terminal IN1 is set to “Hi” or until the reference potential A reaches the voltage Vr.

  At this time, a constant current input to the input terminal IN1 is generated so that the gradient of the up-ramp voltage L1 becomes a desired value (eg, 1.3 V / μsec). Scan electrode SC1 to scan electrode SCn have a voltage Vsc superimposed on this ramp-up voltage, that is, voltage Vi1 (equal to voltage Vsc in the present embodiment) to voltage Vi2 (in the present embodiment). , Equal to voltage Vsc + voltage Vr) is applied.

  In the meantime, sustain electrode SU1 through sustain electrode SUn are maintained at 0 (V) as in period T1.

(Period T3)
In the period T3, the input terminal IN1 is set to “Lo”. Specifically, the constant current input to the input terminal IN1 is stopped. Thus, the operation of Miller integrating circuit 53 is stopped. Further, switching element QH1 to switching element QHn are turned off, switching element QL1 to switching element QLn are turned on, and reference potential A is applied to scan electrode SC1 to scan electrode SCn. At the same time, the clamp circuit of sustain pulse generating circuit 50 is operated to set reference potential A to voltage Vs. Thereby, the voltage of scan electrode SC1 through scan electrode SCn is reduced to voltage Vi3 (equal to voltage Vs in the present embodiment).

  Further, switching element Q24 of sustain pulse generating circuit 80 is turned off, switching element Q26 and switching element Q27 are turned on, and voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn.

(Period T4)
In the period T4, the switching elements QH1 to QHn and the switching elements QL1 to QLn maintain the same state as the period T3.

  Then, the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp voltage L2 is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN2. As a result, a constant current flows toward the capacitor C2, the drain voltage of the switching element Q2 starts to decrease in a ramp shape, and the output voltage of the scan electrode driving circuit 43 also decreases in a ramp shape toward the negative voltage Vi4. start. At this time, a constant current input to the input terminal IN2 is generated so that the gradient of the down-ramp voltage L2 becomes a desired value (for example, −2.5 V / μsec).

  In the present embodiment, the voltage Vi4 is set to the voltage Va + voltage Vset2, or the voltage Va + voltage Vset3 having a voltage value higher than the voltage Va + voltage Vset3 to generate the down-ramp voltage L2. When the voltage Vi4 is set to the voltage Va + voltage Vset2 (first SF to fifth SF in the example shown in FIG. 15), the switching element SW2 is turned on, the switching element SW3 is turned off, and the voltage is applied to one terminal of the comparator CP1. Va + voltage Vset2 is applied. When the voltage Vi4 is set to the voltage Va + voltage Vset3 (in the example shown in FIG. 15, the sixth SF to the eighth SF), the switching element SW2 is turned off, the switching element SW3 is turned on, and the voltage is applied to one terminal of the comparator CP1. Va + voltage Vset3 is applied. Thus, in the comparator CP1, the reference potential A, that is, the down-ramp voltage L2 output from the initialization waveform generation circuit 51 (in the second to eighth SFs, the down-ramp voltage L4), and the voltage obtained by superimposing the voltage Vset2 on the voltage Va. Comparison is made between Va + voltage Vset2 or voltage Va + voltage Vset3 obtained by superimposing voltage Vset3 on voltage Va.

  As a result, the comparison result in the comparator CP1 is obtained from “Lo” at time t46 when the down-ramp voltage L2 (or down-ramp voltage L4) reaches the voltage Va + voltage Vset2, or at time t45 when it reaches the voltage Va + voltage Vset3. “Hi” (not shown). Switching element QH1 to switching element QHn and switching element QL1 to switching element QLn are switched in operation based on the comparison result in comparator CP1, and voltage applied to scan electrode SC1 to scan electrode SCn is at time t45, or At time t46, the voltage input to the input terminal INa is switched to the voltage input to the input terminal INb, and the gradual voltage decrease up to that time is switched to a steep voltage increase.

  After the output voltage of the scan electrode driving circuit 43 reaches the negative voltage Vi4 (equal to the voltage Va in this embodiment), the input terminal IN2 is set to “Lo”. Specifically, the constant current input to the input terminal IN2 is stopped. Thus, the operation of Miller integrating circuit 54 is stopped.

  In this manner, the ramp-down voltage L2 that decreases from the voltage Vi3 (equal to the voltage Vs in this embodiment) toward the negative voltage Vi4 is generated and applied to the scan electrodes SC1 to SCn.

  On the other hand, in this embodiment, the down-ramp voltage L5 is generated later in time than the down-ramp voltage L2 (or down-ramp voltage L4), and at the lowest voltage of the down-ramp voltage L2 (or down-ramp voltage L4). The phases of a certain voltage Vi4 and the voltage Vi5 that is the lowest voltage of the down-ramp voltage L5 are aligned with each other and applied to the sustain electrodes SU1 to SUn.

  The comparison circuit 57 compares the reference potential A, that is, the down-ramp voltage L2 (down-ramp voltage L4 in the second to eighth SFs) output from the initialization waveform generation circuit 51 with the preset comparison voltage Vo. The The timing generation circuit 45 receives the comparison result, and after a predetermined time has elapsed from time t40 when the down-ramp voltage L2 (or down-ramp voltage L4) reaches the comparison voltage Vo, for example, the voltage Vi5 is applied to the voltage Ve−. In the subfield (first SF to fifth SF in the example shown in FIG. 15) in which voltage VeHz2 is set, subfield (FIG. 15) in which voltage Vi5 is set to voltage Ve−voltage VeHz3 at time t41 when time T41 has elapsed from time t40. In the example shown in FIG. 6, in the sixth SF to the eighth SF), all the switching elements of the sustain electrode driving circuit 44 are turned off at time t42 when the time T42 has elapsed from time t40.

  As a result, sustain electrode SU1 through sustain electrode SUn are electrically disconnected from sustain electrode drive circuit 44 to enter a high impedance state, and down ramp voltage L2 (or down ramp voltage L4) applied to scan electrode SC1 through scan electrode SCn. ) Is applied to sustain electrode SU1 through sustain electrode SUn via interelectrode capacitance Cp, which is a parasitic capacitance formed between display electrode pair 24. In the present embodiment, in this way, the ramp-down voltage L5 that drops from the voltage Ve to the voltage VeHz2 (or voltage VeHz3) and has the same phase as the ramp-down voltage L2 (or the ramp-down voltage L4) is generated. , Applied to sustain electrode SU1 through sustain electrode SUn.

  Then, at time t47 after the application of the down-ramp voltage L2 (or down-ramp voltage L4) is finished, switching element Q26 and switching element Q27 are turned on again, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and then continued. Prepare for the writing period. To do.

  In this way, in the present embodiment, the down-ramp voltage L2 (or down-ramp voltage L4) that decreases to voltage Vi4 is generated and applied to scan electrode SC1 through scan electrode SCn, and the down-ramp that decreases to voltage Vi5. Voltage L5 is generated and applied to sustain electrode SU1 through sustain electrode SUn.

  Note that the down-ramp voltage L2 (or down-ramp voltage L4) and the down-ramp voltage L5 may increase immediately after reaching the voltages Vi4 and Vi5 as shown in FIG. For example, when the decreasing voltage reaches the voltage Vi4 and the voltage Vi5, the voltage may be maintained for a certain period thereafter.

  As described above, according to the present embodiment, in the initialization period, the adjustment downstream that occurs later in time than the downward ramp voltage L2 (or downward ramp voltage L4) that is the downward ramp voltage for initialization is generated. The ramp-down voltage L5, which is a ramp voltage, is maintained by aligning the phases of the voltage Vi4 that is the lowest voltage of the ramp-down voltage L2 (or the ramp-down voltage L4) and the voltage Vi5 that is the lowest voltage of the ramp-down voltage L5 with each other It is assumed that voltage Vi4 and voltage Vi5 are lower in the subfield with small luminance weight applied to SU1 through sustain electrode SUn than in the subfield with large luminance weight. As a result, the occurrence of abnormal discharge in the writing period such as “erroneous writing” and “non-light” is reduced to stabilize the writing operation, and the occurrence of “maintaining erroneous discharge” in the sustaining period is reduced. 1 can improve the image display quality.

  In the present embodiment, all the switching elements in sustain electrode drive circuit 44 connected to sustain electrode SU1 through sustain electrode SUn are turned off, and sustain electrode SU1 through sustain electrode SUn are electrically connected to sustain electrode drive circuit 44. By separating them into a high impedance state, the down-ramp voltage L2 (or down-ramp voltage L4) applied to scan electrode SC1 through scan electrode SCn is applied to sustain electrode SU1 through sustain electrode via interelectrode capacitance Cp. Although the configuration applied to SUn has been described, the present invention is not limited to this configuration. For example, a circuit that generates the down-ramp voltage L5 may be provided in the sustain electrode drive circuit 44, and the circuit may be operated to apply the down-ramp voltage L5 to the sustain electrodes SU1 to SUn.

  In the present embodiment, the configuration in which the sustain pulse voltage Va is constant and the voltage Vi4 is changed has been described. However, for example, the voltage Vi4 is constant and the voltage Va is changed to change the voltage Vi4 and the voltage Va. It is good also as a structure which changes.

  Note that the drive voltage waveforms shown in FIG. 3 are merely examples of the present invention, and the present invention is not limited to these drive voltage waveforms. Also, the timing chart shown in FIG. 16 is merely an example of the present invention, and the present invention is not limited to this timing chart.

  In the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group. Of a panel by so-called two-phase driving, which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group. The present invention can also be applied to a driving method, and the same effect as described above can be obtained.

  In the embodiment of the present invention, the electrode structure in which the scan electrode and the scan electrode are adjacent to each other and the sustain electrode and the sustain electrode are adjacent to each other, that is, the arrangement of the electrodes provided on the front plate 21 is “. It is also effective in a panel having an electrode structure of “electrode, scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,.

  In the present invention, the subfield configuration (number of subfields, luminance weight of each subfield, etc.) is not limited to the configuration shown in the embodiment. Moreover, the structure which changes a subfield structure based on an image signal etc. may be sufficient. Further, specific numerical values shown in the embodiment of the present invention, such as gradients of ramp voltages of the ramp-up voltage L1, the ramp-down voltage L2, the ramp-down voltage L4, the ramp-down voltage L5, and the erase ramp voltage L3, etc. Is set based on the characteristics of a 50-inch panel having 1080 display electrode pairs and is merely an example of the embodiment. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  INDUSTRIAL APPLICABILITY The present invention is useful as a panel driving method and a plasma display device because even in a high-definition panel, the occurrence of abnormal discharge in the address period can be suppressed to stabilize the address operation and improve the image display quality. It is.

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 53, 54, 55 Miller integration circuit 57 comparison circuit Q1, Q2, Q3, Q4, Q5, Q21, Q22, Q23, Q24, Q26, Q27, SW2, SW3, QH1 to QHn, QL1 to QLn Switching element C1, C2, C3, C20, C31 Capacitor CP1 Comparator D21, D22, D30, D31 Diode R1, R2, R3 Resistance L1 Up-ramp voltage L2, L4 L5 Down-ramp voltage L3 Erase run Voltage L20 inductor

Claims (8)

A plasma display panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, an initializing period for applying a descending initial falling ramp voltage to the scan electrode, an address period, and a subfield A driving method of a plasma display panel, in which a plurality of subfields each having a sustain period in which a sustain pulse of a number corresponding to a luminance weight set every time is alternately applied to the display electrode pair is provided in one field and gradation is displayed. There,
An adjustment down ramp voltage that occurs later in time than the initialization down ramp voltage during the initialization period is a minimum voltage of the initialization down ramp voltage and a minimum voltage of the adjustment down ramp voltage. Applying the phases to the sustain electrodes in alignment with each other,
Driving a plasma display panel characterized in that the minimum voltage of the downfall voltage for initialization and the minimum voltage of the downfall voltage for adjustment are lower in the subfield having a lower luminance weight than in the subfield having a higher luminance weight. Method. When each subfield is arranged so that the luminance weight is in ascending order or descending order, a plurality of adjacent subfields constitute one group,
In a subfield belonging to a group having a small average value of luminance weight, the minimum voltage of the down ramp voltage for initialization and the minimum voltage of the down gradient voltage for adjustment are lower than those in a subfield belonging to the group having a large average value of luminance weight. 2. The method of driving a plasma display panel according to claim 1, wherein the driving method is lowered. The initialization down ramp voltage is compared with a preset comparison voltage, and the time from when the initialization down ramp voltage reaches the comparison voltage until the adjustment down ramp voltage is generated is changed. The method for driving a plasma display panel according to claim 1, wherein a minimum voltage of the downward ramp voltage for adjustment is controlled. During the period in which the adjustment downward ramp voltage is applied to the sustain electrode, the sustain electrode is electrically disconnected from the sustain electrode driving circuit that drives the sustain electrode, and the sustain electrode is in a high impedance state and applied to the scan electrode. 2. The method of driving a plasma display panel according to claim 1, wherein the initialization downward ramp voltage is applied to the sustain electrode via a parasitic capacitance between the scan electrode and the sustain electrode. . The initialization down-gradient voltage is compared with a preset comparison voltage, and the time from when the initialization down-gradient voltage reaches the comparison voltage until the sustain electrode is brought into the high impedance state is changed. Accordingly, the minimum voltage of the adjustment downward ramp voltage is controlled, and the time is shortened in a subfield having a small luminance weight compared to a subfield having a large luminance weight. Driving method of plasma display panel. A plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode are provided, and a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field, and the sustain period is set for each subfield. A plasma display panel that alternately applies a sustain pulse of the number of times according to the luminance weight to the display electrode pair;
A scan electrode driving circuit that generates a down ramp voltage for initialization that falls during the initialization period, generates the sustain pulse during the sustain period, and applies the sustain pulse to the scan electrodes;
A sustain electrode driving circuit that generates the sustain pulse during the sustain period and applies the sustain pulse to the sustain electrode, and
The sustain electrode driving circuit includes:
An adjustment down ramp voltage that occurs later in time than the initialization down ramp voltage in the initialization period is a minimum voltage of the initialization down ramp voltage and a minimum voltage of the adjustment down ramp voltage. While applying the phase to each other to the sustain electrode, in the subfield with a small luminance weight, lower the minimum voltage of the downward ramp voltage for adjustment than the subfield with a large luminance weight,
The scan electrode driving circuit includes:
The plasma display apparatus characterized in that the minimum voltage of the down-gradient voltage for initialization is lower in a subfield with a small luminance weight than in a subfield with a large luminance weight. The scan electrode driving circuit includes a comparison circuit that compares the initialization downward ramp voltage with a preset comparison voltage,
The plasma display apparatus according to claim 6, wherein the sustain electrode driving circuit generates the adjustment downward ramp voltage based on a comparison result in the comparison circuit. The sustain electrode driving circuit includes:
The period for generating the adjustment downward ramp voltage is:
The plasma display apparatus according to claim 6, wherein the sustain electrode is electrically disconnected from the sustain electrode driving circuit to bring the sustain electrode into a high impedance state.

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