JP2009192778A - Plasma display apparatus and driving method of plasma display panel - Google Patents

Abstract

In a plasma display device, stable address discharge is generated without increasing a scan pulse voltage.
A scan electrode is divided into a plurality of scan electrode groups including a first scan electrode group, and a waveform shape is different between a first scan electrode group and a scan electrode group other than the first scan electrode group in an initialization period. Is provided with a shunt regulator 56 for generating a set voltage B used for setting the ultimate potential of the downward ramp waveform voltage. The voltage generated by dividing the set voltage B by resistance is fed back to the reference terminal of the shunt regulator 56, and the set voltage B is generated at a plurality of different voltage values by changing the resistance ratio of the divided resistor. Let
[Selection] Figure 12

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method for driving the panel, a subfield method is generally used (see, for example, Patent Document 1). In the subfield method, one field period is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell. Thereby, wall charges necessary for the subsequent address operation are formed in each discharge cell.

  In the address period, a scan pulse is sequentially applied to the scan electrodes (hereinafter, this operation is also referred to as “scan”), and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes (hereinafter, these operations are performed). Are collectively referred to as “writing”). Thereby, an address discharge is selectively generated between the scan electrode and the data electrode, and a wall charge is selectively formed.

  In the subsequent sustain period, a predetermined number of sustain pulses corresponding to the luminance to be displayed are alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode. Thereby, a discharge is selectively caused in the discharge cell in which the wall charge is formed by the address discharge, and the discharge cell is caused to emit light. Thereby, an image is displayed.

The plurality of scan electrodes are driven by a scan electrode drive circuit, the plurality of sustain electrodes are driven by a sustain electrode drive circuit, and the plurality of data electrodes are driven by a data electrode drive circuit.
JP 2006-18298 A

  In the address period, as described above, scanning is performed by sequentially applying scanning pulses to a plurality of scanning electrodes. Therefore, in a discharge cell in which the scan pulse is applied in a slow order among the plurality of discharge cells, the time from the application of the initialization waveform to the application of the scan pulse becomes long.

  Wall charges formed in the discharge cells by the initializing discharge gradually decrease under the influence of an address pulse applied to the data electrode in order to generate an address discharge in other discharge cells. For this reason, in a discharge cell in which the scan pulse is applied in a late order, wall charges may decrease before the scan pulse and the address pulse are applied to the discharge cell, and a discharge failure of address discharge may occur. In particular, in a high-definition panel, the time spent for scanning becomes longer due to the increase in the number of scanning electrodes, so the wall charge in the discharge cells that are written toward the end of the address period is further reduced. The address discharge tends to become unstable.

  In order to generate the discharge stably, the drive voltage applied to the electrode may be increased, which contributes to an increase in power consumption.

  The present invention has been made in view of these problems, and can generate stable address discharge without increasing the scan pulse voltage (amplitude) even in a panel with a large screen and high definition. An object of the present invention is to provide a plasma display device and a panel driving method.

  A plasma display apparatus according to the present invention includes a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period within one field period. A plurality of scan electrodes are provided, and the scan electrodes are divided into a plurality of scan electrode groups including the first scan electrode group, and the waveform shapes are different between the first scan electrode group and the scan electrode groups other than the first scan electrode group in the initialization period. A scan electrode drive circuit that drives the scan electrode by generating a downward ramp waveform voltage, the scan electrode drive circuit has a shunt regulator that generates a set voltage used to set the ultimate potential of the downward ramp waveform voltage, The voltage generated by dividing the set voltage by resistance is fed back to the shunt regulator, and the resistance ratio of the divided resistance is changed to change the voltage. And wherein the generating the set voltage by a voltage value.

  As a result, the discharge cell group constituted by the scan electrode group other than the first scan electrode group, for example, the second discharge cell group constituted by the second scan electrode group, descends before starting the address operation. Since it is possible to generate an initialization discharge with a ramp waveform voltage, it is possible to generate a stable address discharge without increasing the scan pulse voltage (amplitude) even in a panel with a large screen and high definition. It becomes. Further, it is possible to stably generate a set voltage generated by a plurality of different voltages with a relatively simple circuit configuration regardless of the temperature.

  Also, the panel driving method of the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period in one field. A plurality of scan electrodes are provided in the period, and the scan electrodes are divided into a plurality of scan electrode groups including the first scan electrode group. In the initialization period, the first scan electrode group and a scan electrode group other than the first scan electrode group A panel driving method for driving a scan electrode by generating a downward ramp waveform voltage having a different waveform shape, wherein a set voltage used for setting an ultimate potential of the downward ramp waveform voltage is generated using a shunt regulator, and the set voltage is The voltage generated by resistance division is fed back to the shunt regulator, and the set voltage can be set at multiple different voltage values by changing the resistance ratio of the resistance division. Characterized in that to produce.

  As a result, the discharge cell group constituted by the scan electrode group other than the first scan electrode group, for example, the second discharge cell group constituted by the second scan electrode group, descends before starting the address operation. Since it is possible to generate an initialization discharge with a ramp waveform voltage, it is possible to generate a stable address discharge without increasing the scan pulse voltage (amplitude) even in a panel with a large screen and high definition. It becomes. Further, it is possible to stably generate a set voltage generated by a plurality of different voltages with a relatively simple circuit configuration regardless of the temperature.

  According to the present invention, there is provided a plasma display device and a panel driving method capable of generating a stable address discharge without increasing a scan pulse voltage (amplitude) even in a panel with a large screen and high definition. It becomes possible to provide.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by barrier ribs 34, and discharge cells are formed at portions where display electrode pairs 24 and data electrodes 32 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 3 is a circuit block diagram of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. The plasma display apparatus 1 supplies necessary power to the panel 10, the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the control signal generation circuit 45, and each circuit block. A power supply circuit (not shown) is provided.

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield according to the number of pixels of the panel 10.

  The control signal generation circuit 45 generates various control signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and each circuit block (image signal processing circuit 41, data electrode drive circuit 42). To the scan electrode drive circuit 43 and the sustain electrode drive circuit 44).

  The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and the data electrodes D1 to data based on the control signal supplied from the control signal generation circuit 45. The electrode Dm is driven.

  Scan electrode drive circuit 43 has an initialization waveform generation circuit (not shown) for generating an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn in the initialization period, and scan electrode SC1 through scan electrode SCn in the sustain period. A sustain pulse generating circuit (not shown) for generating a sustain pulse to be applied to the scan pulse, and a scan pulse generating circuit for generating a scan pulse to be applied to scan electrode SC1 through scan electrode SCn in the address period, having a plurality of scan ICs 52. Then, based on the control signal supplied from control signal generation circuit 45, each of scan electrode SC1 through scan electrode SCn is driven.

  Sustain electrode drive circuit 44 includes a sustain pulse generating circuit and a circuit (not shown) for generating voltage Ve1 and voltage Ve2, and sustain electrodes SU1 to SU1 based on a control signal supplied from control signal generating circuit 45. The electrode SUn is driven.

  Scan electrode drive circuit 43 in the present embodiment divides scan electrode SC1 through scan electrode SCn into two scan electrode groups and applies different initialization waveforms to each scan electrode group, as will be described later. Perform the action.

  The control signal generation circuit 45 generates a control signal for a two-phase driving operation and supplies the generated control signal to the scan electrode driving circuit 43. Thereby, scan electrode drive circuit 43 drives scan electrode SC1 through scan electrode SCn by a two-phase drive operation.

  Next, the scan electrode drive circuit 43 will be described. FIG. 4 is a circuit diagram of scan electrode drive circuit 43 in the first embodiment of the present invention. The scan electrode drive circuit 43 includes a sustain pulse generation circuit 50 that generates a sustain pulse, an initialization waveform generation circuit 51 that generates an initialization waveform, and a scan pulse generation circuit 52 that generates a scan pulse. Each output is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. FIG. 4 shows a circuit using the sustain pulse generation circuit 50 and the voltage Vr (for example, the Miller integration circuit 53) when a circuit using the negative voltage Va (for example, the Miller integration circuit 54) is operated. ) Is a separation circuit using a switching element Q4 provided for electrical separation. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for cutting off the switching element is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”.

  Sustain pulse generation circuit 50 includes a generally used power recovery circuit (not shown) and a clamp circuit (not shown), and each of the sustain pulse generation circuit 50 provided therein based on a control signal output from control signal generation circuit 45. A sustain pulse is generated by switching the switching element. Further, a Miller integration circuit (not shown) for generating a rising ramp waveform voltage is provided, and an erase ramp waveform to be described later is generated at the end of the sustain period.

  The initialization waveform generation circuit 51 includes a switching element Q1, a capacitor C1, and a resistor R1, and includes a Miller integration circuit 53 that raises the reference potential A of the scan pulse generation circuit 52 in a ramp shape, a switching element Q2, a capacitor C2, and a resistance R2. And a Miller integrating circuit 54 that drops the reference potential A of the scanning pulse generating circuit 52 in a ramp shape. Miller integration circuit 53 generates a ramp waveform voltage that rises during the initialization operation, and Miller integration circuit 54 generates a ramp waveform voltage that decreases during the initialization operation. In FIG. 4, the input terminal of Miller integrating circuit 53 is shown as input terminal IN1, and the input terminal of Miller integrating circuit 54 is shown as input terminal IN2.

  In the present embodiment, the initialization waveform generating circuit 51 employs a Miller integrating circuit using a practical and relatively simple FET, but the present embodiment is not limited to this configuration. Any circuit that can raise or lower the reference potential A in a ramp shape may be used.

  Scan pulse generation circuit 52 includes a plurality of scan ICs 55 (in this embodiment, scan IC (1) to scan IC (12)) that output a scan pulse to each of scan electrode SC1 to scan electrode SCn, and an address period. A switching element Q5 for connecting the reference potential A to the negative voltage Va, a diode D31 and a capacitor for applying a voltage Vc in which the voltage Vscn is superimposed on the reference potential A to the high voltage side (input terminal INb) of the scan IC 55 C31, comparators CP1 and CP2 for comparing the magnitudes of input signals input to two input terminals, a Vset generation circuit 80 for generating a voltage to be applied to one input terminal of the comparator CP1, and a scan IC 55 (In this embodiment, the control signal SID (in this embodiment, the control signal SID (1) for controlling the scan IC (7)). ) And the output signal CPO of the comparator CP2 are ORed to perform an OR operation, and a first control for controlling the scan IC 55 (in this embodiment, scan IC (1) to scan IC (6)). An AND gate AG that performs a logical product operation of the control signal OC1 that is a signal and the output signal of the OR gate OR is provided. The Vset generation circuit 80 connected to one input terminal of the comparator CP1 includes a switching element SW1 for applying a voltage (Va + Vset2) to one input terminal of the comparator CP1, and one input of the comparator CP1. A switching element SW2 for applying a voltage (Va + Vset3) to the terminal and a switching element SW3 for applying a voltage (Va + Vset4) to one input terminal of the comparator CP1, and the other input terminal of the comparator CP1 Is connected to a reference potential A. One input terminal of the comparator CP2 is connected to the voltage (Va + Vset5), and the other input terminal of the comparator CP2 is connected to the reference potential A.

  The scan IC 55 has two input terminals, an input terminal INa that is a low voltage side input terminal and an input terminal INb that is a high voltage side input terminal, and a plurality of output terminals that are connected to the respective scan electrodes. Based on the control signal, one of the voltages input to the two input terminals is output from each output terminal. In the present embodiment, the scan IC 55 is driven in two groups, and the first scan IC group (in this embodiment, scan IC (1) to scan IC (6)) and the second scan IC group are driven. Different control signals are input to the scan IC groups (in this embodiment, scan IC (7) to scan IC (12)). The scan IC (1) to scan IC (6) belonging to the first scan IC group are output as control signals from the control signal OC1 output from the control signal generation circuit 45 during the writing period and from the comparator CP1. The control signal OC2 is input. In addition, the scan start signal SIU (1) output from the control signal generation circuit 45 in the writing period is input to the scan IC (1) that starts scanning first in the first scan IC group. Further, the scan IC (7) to the scan IC (12) belonging to the second scan IC group have, as control signals, a control signal OC1 ′ which is a third control signal output from the AND gate AG, and a comparator CP1. The control signal OC2 output from is input. Further, in the scan IC (7) that starts scanning first in the second scan IC group, the scan start signal SID (1) that is the second control signal output from the control signal generation circuit 45 in the writing period. Is entered. The control signal OC2 is a control signal input in common to all the scan ICs 55 (in this embodiment, the scan IC (1) to the scan IC (12)). In addition, a clock signal CLK that is a synchronization signal for synchronizing the signal processing operation is commonly input to all the scan ICs 55 (in this embodiment, the scan IC (1) to the scan IC (12)). The

  Scan pulse generation circuit 52 is controlled by control signal generation circuit 45 to output the voltage waveform of initialization waveform generation circuit 51 in the initialization period and to output the voltage waveform of sustain pulse generation circuit 50 in the sustain period. Is done.

  FIG. 5 is a schematic diagram showing a state of connection between scan IC 55 of scan electrode driving circuit 43 and scan electrode SC1 through scan electrode SCn in the first embodiment of the present invention. In FIG. 5, circuits other than the scan IC 55 are omitted.

  Scan pulse generation circuit 52 includes switching elements QH1 to QHn and switching elements QL1 to QLn for applying a scan pulse voltage to each of n scan electrodes SC1 to SCn. Switching element QH1 to switching element QHn and switching element QL1 to switching element QLn are integrated into a plurality of outputs and integrated into an IC. This IC is a scanning IC 55.

  In this embodiment, it is assumed that switching elements for 90 outputs are integrated as one monolithic IC, and the panel 10 includes 1080 scanning electrodes. That is, it is assumed that scan pulse generation circuit 52 is configured by using 12 scan ICs (1) to IC (12), and n = 1080 scan electrodes SC1 to scan electrodes SCn are driven. In this way, by making a large number of switching elements QH1 to QHn and switching elements QL1 to QLn into an IC, the number of parts can be reduced and the mounting area can be reduced. However, the numerical values given in the present embodiment are merely examples, and the present invention is not limited to these numerical values.

  In the address operation, first, scan IC (1) connected to scan electrode SC1 to scan electrode SC90 is operated, and then scan IC (2) connected to scan electrode SC91 to scan electrode SC180 is operated. Thereafter, the scan IC (3) to the scan IC (12) are sequentially operated.

  As described above, in the present embodiment, the scan IC 55 is divided into the first scan IC group and the second scan IC group, and the scan electrodes SC1 to SCn are driven. A first scan electrode group (in this embodiment, scan electrode SC1 to scan electrode SC540) connected to scan IC (1) to scan IC (6) belonging to the scan IC group, and a second scan IC group Initialization waveforms of different waveform shapes are used for the second scan electrode group (in this embodiment, scan electrode SC541 to scan electrode SC1080) connected to scan IC (7) to scan IC (12) belonging to Applied. Details of this will be described later.

  Next, the operation of the scan IC 55 will be described. FIG. 6 is a diagram for explaining a correspondence relationship between the control signals OC1 and OC2 and the operation state of the scan IC 55 in the first embodiment of the present invention. The second scan IC group is assumed to be in the same operation state by replacing the control signal OC1 with the control signal OC1 '.

  As shown in FIG. 6, when both the control signal OC1 and the control signal OC2 are at a high level (hereinafter referred to as “Hi”), the scan IC 55 is in the “All-Hi” state, that is, all of the output terminals of the scan IC 55. Are switched to the high voltage side input terminal INb so that all the switching elements provided in the scan IC 55 are switched.

  When the control signal OC1 is “Hi” and the control signal OC2 is low level (hereinafter referred to as “Lo”), the scan IC 55 is in the “All-Lo” state, that is, all the output terminals of the scan IC 55 are on the low voltage side. All the switching elements provided in the scan IC 55 are switched so as to be electrically connected to the input terminal INa. For example, when the initialization waveform generation circuit 51 or the sustain pulse generation circuit 50 is operated, the switching element QH1 to the switching element QHn are turned off by setting the control signal OC1 to “Hi” and the control signal OC2 to “Lo”. Switching element QL1 to switching element QLn are turned on, and an initialization waveform or a sustain pulse can be applied to each of scan electrode SC1 to scan electrode SCn via switching element QL1 to switching element QLn.

  When the control signal OC1 and the control signal OC2 are both “Lo”, the scan IC 55 is in the “HiZ” state. In this "HiZ" state, the output voltage at the time when the scan IC 55 is in the "HiZ" state is held and output from each output terminal of the scan IC 55 as it is.

  When the control signal OC1 is “Lo” and the control signal OC2 is “Hi”, the scan IC 55 is in a “DATA” state, that is, a state in which a predetermined series of operations are performed based on a scan start signal input to the scan IC 55. Become.

  Specifically, when a scan start signal is input to the scan IC 55 (in this embodiment, when the scan start signal changes from “Hi” to “Lo”), first, the first output terminal of the scan IC 55 Only the low voltage side input terminal INa is electrically connected, and all the remaining output terminals are electrically connected to the high voltage side input terminal INb. After the state continues for a predetermined time (for example, 1 μsec), only the second output terminal of the scan IC 55 is then electrically connected to the low voltage side input terminal INa, and all the remaining output terminals are high. It is electrically connected to the voltage side input terminal INb. Then, after the state is continued for a predetermined time, only the third output terminal of the scan IC 55 is electrically connected to the low voltage side input terminal INa. In this manner, each output terminal of the scan IC 55 is electrically connected to the low voltage side input terminal INa in order for a predetermined time. In the present embodiment, the scan IC 55 is set in this operating state during the address period to sequentially generate the scan pulse voltage Va, and the scan electrodes SC1 to SCn are scanned. In the present embodiment, the scan start signal input to the scan IC 55 belonging to the first scan IC group is used as the scan start signal SIU, and the scan start signal input to the scan IC 55 belonging to the second scan IC group is started to scan. The signal SID is used.

  In the present embodiment, the first scan IC group is scanned first, the scan start signal SIU (1) used for the scan IC (1) that scans first, and the second scan IC group is scanned first. A scan start signal SID (1) used for the scan IC (7) is generated by the control signal generation circuit 45, and scanning is performed from the remaining scan start signal, that is, the scan start signal SIU (2) used for the scan IC (2). Each scan start signal up to scan start signal SIU (6) used for IC (6), and scan start signal SID (6) used for scan IC (12) from scan start signal SID (2) used for scan IC (8) Each scanning start signal until is generated by the scanning IC 55.

  For example, the scan IC (1) is created by delaying the scan start signal SIU (1) for a predetermined time by using a shift register or the like after the scan to all the scan electrodes connected to the scan IC (1) is completed. The scanning start signal SIU (2) is output and supplied to the next scanning IC (2). Similarly, the scan IC (2) supplies the scan start signal SIU (3) created by delaying the scan start signal SIU (2) for a predetermined time to the next-stage scan IC (3). Hereinafter, similarly, each scan IC 55 creates a new scan start signal by delaying the input scan start signal for a predetermined time, and supplies it to the next-stage scan IC 55. With this configuration, the control signal generation circuit 45 does not generate the scan start signal SIU (2) to the scan start signal SIU (6) and the scan start signal SID (2) to the scan start signal SID (6). As a result, the number of wiring lines for the control signal connecting the control signal generating circuit 45 and the scan electrode driving circuit 43 can be reduced.

  In the present embodiment, the first scan IC group and the second scan IC group generate the initialization waveforms having different waveform shapes. For this reason, the control signal OC1 used for the first scan IC group is generated. And the control signal OC1 used for the second scan IC group change the control timing. The control signal OC1 used for the first scan IC group is generated by the control signal generation circuit 45, while the control signal OC1 used for the second scan IC group is generated by the third AND gate AG. Control signal (denoted as “control signal OC1 ′” in the present embodiment in order to be distinguished from the control signal OC1 used for the first scan IC group). Further, a signal generated by the comparator CP1 is used as the control signal OC2. Thus, by generating the control signal OC1 ′ and the control signal OC2 by logical operation, the number of control signals generated by the control signal generation circuit 45 is further reduced, and the control signal generation circuit 45, the scan electrode drive circuit 43, The number of wirings for the control signal that connects can be further reduced.

  As shown in FIG. 4, the comparator CP1 that outputs the control signal OC2 compares the voltage (Va + Vset2) with the reference potential A when the switching element SW1 is on and the switching element SW2 and the switching element SW3 are off. When the switching element SW2 is on and the switching element SW1 and the switching element SW3 are off, the voltage (Va + Vset3) is compared with the reference potential A. When the switching element SW3 is on and the switching element SW1 and the switching element SW2 are off, the voltage (Va + Vset4) ) And the reference potential A. If the reference potential A is higher, “Lo” is output, otherwise “Hi” is output and supplied to the scan ICs (1) to (12). Further, the comparator CP2 that outputs the signal CPO used for generating the control signal OC1 ′ compares the voltage (Va + Vset5) with the reference potential A. When the reference potential A is higher, “Hi” is indicated. Then, “Lo” is output.

  The scan IC 55 adds the control signal OC1 ′ and the scan start signal SID (1) in accordance with the control signal OC2, and further adds the control start signal SID (1) in the second scan IC group. It can be generated by switching at a plurality of different voltages. It is assumed that on / off of switching element SW1 to switching element SW3 is controlled by control signal generation circuit 45.

  Next, the scan electrode group in the present embodiment will be described. FIG. 7 is a schematic diagram showing an example of the division of the scan electrode group in the first embodiment of the present invention. Note that FIG. 7 simply illustrates the connection between the panel 10 and the scan IC 55, and a plurality of regions (in the present embodiment) driven by one scan IC 55 are divided into regions within the panel 10. In the figure, a region where 90 scanning electrodes are arranged is shown. In addition, the display electrode pairs 24 are arranged to extend in the left-right direction in the drawing similarly to FIG. The output of the scan IC 55 is connected to the scan electrode SC1 to the scan electrode SCn by a commonly used flexible wiring board 77.

  When performing the two-phase drive operation, as indicated by a broken line in FIG. 7, the display area of panel 10 is divided into two areas, and a plurality of scan electrodes included in one area are used as one scan electrode group, and scan electrode SC1. The scan electrode SCn is driven by being divided into two scan electrode groups, that is, a first scan electrode group and a second scan electrode group. For example, if the number of scan electrodes n = 1080, scan electrode SC1 to scan electrode SC540 are set as the first scan electrode group, and scan electrode SC541 to scan electrode SC1080 are set as the second scan electrode group. In addition, let the discharge cell which comprises two area | regions enclosed with the broken line be the 1st discharge cell group and the 2nd discharge cell group, respectively.

  If the number of scan electrodes connected to one scan IC 55 is 90, scan electrode SC1 through scan electrode SC90 are connected to first scan IC (1), and scan electrode SC91 through scan electrode SC180 are connected. Connect to the second scan IC (2). In this way, 90 scan electrodes are connected to the scan IC at a time. Scan IC (1) to Scan IC (6) connected to scan electrode SC1 to scan electrode SC540 are set as a first scan IC group, and scan IC (7) to scan IC connected to scan electrode SC541 to scan electrode SC1080 Let IC (12) be the second scan IC group. In this embodiment, different initialization waveforms are generated in the first scan IC group and the second scan IC group.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. Note that the plasma display device in this embodiment is a subfield method, that is, one field period is divided into a plurality of subfields on the time axis, luminance weights are set for each subfield, and each discharge is performed for each subfield. It is assumed that gradation display is performed by controlling light emission / non-light emission of the cell.

  In this subfield method, for example, one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each subfield is 1, 2, 4, 8, 16, 32, A configuration having luminance weights of 64 and 128 can be adopted. Also, among the plurality of subfields, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed in the initializing period of one subfield, and a sustaining discharge is performed in the initializing period of the other subfield. By performing a selective initializing operation for selectively generating an initializing discharge for the discharge cells subjected to the above, it is possible to reduce light emission not related to gradation display as much as possible and improve the contrast ratio.

  In the present embodiment, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the eighth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance that is the luminance of the black display area that does not generate the sustain discharge is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 8 is a drive voltage waveform diagram applied to each electrode of panel 10 in the two-phase drive operation of scan electrode drive circuit 43 in the first embodiment of the present invention.

  FIG. 8 shows a scan electrode that scans at the beginning of the address period and belongs to the first scan electrode group, and a scan electrode that scans at the end of the first scan electrode group. Scan electrode SCn / 2 (for example, scan electrode SC540), scan electrode SCn / 2 + 1 (for example, scan electrode SC541) that is the first scan electrode in the second scan electrode group, and scan at the end of the address period Scan electrode SCn (for example, scan electrode SC1080) belonging to the second scan electrode group. In addition, driving waveforms of sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm are shown.

  FIG. 8 shows the drive voltage waveforms of two subfields, that is, the first subfield (first SF) of the subfield that performs the all-cell initialization operation (hereinafter referred to as “all-cell initialization subfield”). And a second subfield (second SF) of a subfield (referred to as “selective initialization subfield”) for performing a selective initialization operation. The drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses in the sustain period is different. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the respective electrodes based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to data electrode D1 to data electrode Dm, sustain electrode SU1 to sustain electrode SUn, and sustain electrode SU1 to sustain is applied to scan electrode SC1 to scan electrode SCn. A ramp waveform voltage (hereinafter referred to as an “up-ramp waveform”) L1 that gently rises from a voltage Vi1 that is equal to or lower than the discharge start voltage to a voltage Vi2 that exceeds the discharge start voltage is applied to the electrode SUn.

  While the rising ramp waveform L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. Each weak initializing discharge occurs continuously. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm.

  Here, in the present embodiment, different initialization is performed for scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group and scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. A falling ramp waveform voltage having a different arrival potential, which is the lowest voltage of the falling ramp waveform voltage, is applied. First, scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group has a negative voltage exceeding discharge start voltage from voltage Vi3 that is lower than or equal to discharge start voltage with respect to sustain electrode SU1 to sustain electrode SUn / 2. A downward ramp waveform voltage (hereinafter referred to as “down ramp waveform”) L2 that gently falls toward the voltage (Va + Vset2) is applied. During this time, weakness is present between scan electrode SC1 through scan electrode SCn / 2 and sustain electrode SU1 through sustain electrode SUn / 2, and between scan electrode SC1 through scan electrode SCn / 2 and data electrode D1 through data electrode Dm. Initializing discharge occurs. Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn / 2 and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn / 2 are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm. Is adjusted to a value suitable for the write operation. Thus, the all-cell initializing operation for performing the initializing discharge on all the first discharge cell groups constituted by the first scan electrode group is completed.

  On the other hand, a downward ramp waveform L5 that gently falls from voltage Vi3 toward negative voltage (Va + Vset5) is applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. Here, in the present embodiment, the voltage Vset5 is set to a voltage (for example, 70 (V)) higher than the voltage Vset2 (for example, 6 (V)).

  As described above, in this embodiment, the ultimate potential of the downward ramp waveform applied to the second scan electrode group is set higher than the ultimate potential of the downward ramp waveform applied to the first scan electrode group. That is, the down-ramp waveform L2 applied to the first scan electrode group drops to the voltage (Va + Vset2), whereas the down-ramp waveform L5 applied to the second scan electrode group is higher than the voltage (Va + Vset2). Only descend to (Va + Vset5). For this reason, in the second discharge cell group configured by the second scan electrode group, the amount of charge that moves due to the initialization discharge by the down-ramp waveform L5 is smaller than each discharge cell of the first discharge cell group. . Therefore, after the initializing discharge with the down-ramp waveform L5, more wall charges remain in each discharge cell in the second discharge cell group than in each discharge cell in the first discharge cell group.

  In the subsequent address period, a scan pulse voltage is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = 1) corresponding to a discharge cell to emit light is applied to data electrode D1 through data electrode Dm. To m), a positive address pulse voltage Vd is applied to selectively generate an address discharge in each discharge cell.

  In this address period, voltage Ve2 is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc (Vc = Va + Vscn) is applied to scan electrode SC1 through scan electrode SCn.

  Then, scan pulses are sequentially applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group. First, the negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and sustain electrode SU1. The difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this way, an address operation is performed in which an address discharge is caused in the discharge cell to emit light in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The address operation described above is sequentially performed until the discharge cells in the n / 2th row, and the address operation in the first discharge cell group is completed.

  In this embodiment, the down ramp generated in the initialization period after the write operation to the first scan electrode group is completed and before the write operation to the second scan electrode group is started. A down-ramp waveform having a lower potential than the waveform L5 is applied to the second scan electrode group. That is, as shown in FIG. 8, a down-ramp waveform L6 that gently falls from the voltage Vc toward the negative voltage (Va + Vset3) is applied to the second scan electrode group.

  As described above, the down-ramp waveform L5 applied to the second scan electrode group during the initialization period has only dropped to a negative voltage (Va + Vset5), and therefore, the discharge cells of the second discharge cell group More wall charges remain than each discharge cell of the first discharge cell group. Therefore, by setting the voltage Vset3 to a voltage (for example, 8 (V)) that is sufficiently smaller than the voltage Vset5 (for example, 70 (V)), the downward ramp waveform L6 is a potential that is sufficiently lower than the downward ramp waveform L5. Thus, an initializing discharge can be generated in each discharge cell of the second discharge cell group.

  In other words, in each discharge cell of the second discharge cell group, an initializing discharge can be generated immediately before the scan to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group is started.

  The wall charge formed by the initialization discharge decreases with time. For this reason, in the conventional configuration in which the initializing discharge is simultaneously generated only in the initializing period immediately before the address period in all the scan electrodes (hereinafter referred to as “one-phase driving”), the discharge cells whose scanning order is slow in the address period. In this case, the writing operation may become unstable. However, in this embodiment, since the initializing discharge is generated in the second discharge cell group immediately before the scan to the second scan electrode group is started, the address operation is performed in the second discharge cell group. Immediately before starting, wall charges can be brought into an appropriate state. Accordingly, even in the discharge cells belonging to the second discharge cell group whose address operation is late in the address period, it is possible to perform a stable address operation without increasing the applied voltage necessary for the address discharge.

  FIG. 8 shows a waveform diagram in which the down ramp waveform L6 is applied to the first scan electrode group at the same timing as the down ramp waveform L6 is applied to the second scan electrode group. There is no problem in driving even if the down-ramp waveform is not generated in the first scan electrode group in which the writing operation has already been completed. However, when it is difficult to prevent these down-ramp waveforms from being generated due to the configuration of the scan electrode driving circuit 43, the down-ramp waveform L6 is applied to the first scan electrode group as it is as shown in FIG. It doesn't matter. In each discharge cell of the first discharge cell group, a down-ramp waveform L2 that falls to the voltage (Va + Vset2) in the initialization period is applied to each scan electrode of the first scan electrode group to generate an initialization discharge. Yes. For this reason, even if a downward ramp waveform L6 that falls to a voltage (Va + Vset3) that is slightly higher in potential than the voltage (Va + Vset2) is applied to the first scan electrode group, it is initialized again to each discharge cell of the first discharge cell group. There is no risk of electrical discharge. Therefore, there is no problem even if the down-ramp waveform L6 is applied as it is to the first scan electrode group.

  Then, after applying the down-ramp waveform L6 to the second scan electrode group, scan pulses are sequentially applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group in the same procedure as described above. Apply. The address operation described above is performed until the discharge cell in the n-th row, the address operation in the second discharge cell group is completed, and the address period in the first SF is completed.

  It is assumed that the address pulse is not applied to the data electrodes D1 to Dm during the period in which the down ramp waveform L6 is applied to the second scan electrode group.

  In the subsequent sustain period, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission.

  In this sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, thereby giving a potential difference between the electrodes of display electrode pair 24. As a result, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period.

  At the end of the sustain period, after the sustain electrode SU1 to the sustain electrode SUn are returned to 0 (V), the ramp waveform voltage increases from 0 (V), which is the base potential, toward the voltage Vers exceeding the discharge start voltage. L3 (hereinafter referred to as “erasing ramp waveform”) is applied to scan electrode SC1 through scan electrode SCn. Then, a weak erasing discharge occurs between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. The charged particles generated by the erasing discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi. Thus, the wall voltage on the scan electrode SCi and the sustain electrode SUi remains the difference between the voltage applied to the scan electrode SCi and the discharge start voltage, that is, (voltage Vers−discharge) while leaving the positive wall charge on the data electrode Dk. It is weakened to the extent of the starting voltage.

  Thereafter, scan electrode SC1 to scan electrode SCn are returned to 0 (V), and the sustain operation in the sustain period is ended.

  In the initialization period of the second SF, a drive voltage waveform in which the first half of the initialization period of the first SF is omitted is applied to each electrode. That is, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm. Scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group A down-ramp waveform L4 that gently falls from a voltage (for example, 0 (V)) that is equal to or lower than the discharge start voltage toward a negative voltage (Va + Vset4) is applied.

  As a result, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the previous subfield (first SF in FIG. 8), and the wall voltage on the upper part of scan electrode SCi and sustain electrode SUi is weakened. The wall voltage above the data electrode Dk (k = 1 to m) is also adjusted to a value suitable for the write operation. On the other hand, discharge cells in which no sustain discharge has occurred in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the second SF is a selective initializing operation in which the initializing discharge is performed on the discharge cells in which the sustain operation has been performed in the sustain period of the immediately preceding subfield.

  Further, scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group gradually decreases from a voltage (for example, 0 (V)) that is equal to or lower than the discharge start voltage toward a negative voltage (Va + Vset5). The down-ramp waveform L7 to be applied is applied.

  As a result, in the second discharge cell group constituted by the second scan electrode group, the discharge cells in which the sustain discharge has occurred in the sustain period of the previous subfield (first SF in FIG. 8) as described above. Only a weak initializing discharge occurs. However, since the down-ramp waveform L7 applied to the second scan electrode group falls only to a voltage (Va + Vset5) higher than the voltage (Va + Vset2), in the second discharge cell group, the charge that moves due to the initializing discharge. Is less than each discharge cell of the first discharge cell group. Therefore, after the initializing discharge with the down-ramp waveform, more wall charges remain in each discharge cell of the second discharge cell group than in each discharge cell of the first discharge cell group as described above.

  In the second SF address period, the same drive waveform as that in the first SF address period is applied. Therefore, it is possible to generate an initializing discharge in each discharge cell of the second discharge cell group immediately before starting the scan to the second scan electrode group.

  In the sustain period of the second SF, similarly to the sustain period of the first SF, a predetermined number of sustain pulses are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. As a result, a sustain discharge is generated in the discharge cells that have generated the address discharge in the address period.

  In the subfields after the third SF, scan electrode SC1 to scan electrode SCn, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm differ from the second SF except for the number of sustain pulses in the sustain period. A similar drive waveform is applied.

  In the configuration described above, it is desirable to set the voltage Vset2 in the down-ramp waveform L2 to a voltage smaller than the voltage Vset4 (for example, 10 (V)) in the down-ramp waveform L4. This is because the initializing discharge in the first SF, that is, the first initializing discharge in one field period is surely generated by setting the voltage (Va + Vset2) to a voltage smaller than the voltage (Va + Vset4).

  The above is the outline of the driving voltage waveform applied to each electrode of panel 10 during the two-phase driving operation in the present embodiment.

  Next, the operation of the scan electrode drive circuit 43 and the generation of the drive voltage waveform will be described. In FIG. 9, it is assumed that the voltage Vi1 and the voltage Vi3 are equal to the voltage Vs, and the voltage Vi2 is equal to the voltage Vr.

  FIG. 9 is a timing chart for explaining an example of the operation of scan electrode drive circuit 43 in the first embodiment of the present invention. FIG. 9 shows a drive voltage waveform applied to scan electrode SC1 that performs scanning at the beginning of the address period, and scan electrode SCn / 2 + 1 that performs scanning first in the second scan electrode group (for example, scan electrode). The drive voltage waveform applied to SC541) is shown. In addition, the control signal OC1, the control signal OC2, the control signal OC1 ′, the output signal CPO of the comparator CP2, the scanning start signal SIU (1), and the scanning start signal SID (1) are shown, and are input to the input terminal IN1 and the input terminal IN2. The constant current supply state is shown.

  In the present embodiment, it is assumed that the scan IC 55 starts scanning when the scan start signal changes from “Hi” to “Lo” in the “DATA” state. In addition, the switching element Q4 is turned on in the first half of the initialization period and the sustain period, and the switching element Q4 is turned off in the second half of the initialization period and the writing period.

(Initialization period)
In the initialization period, first, the power recovery circuit of the sustain pulse generation circuit 50 is operated to raise the potential of the reference potential A. Thereafter, the clamp circuit of sustain pulse generation circuit 50 is operated to set reference potential A to the voltage Vs (equal to voltage Vi1 in this embodiment).

  Next, at time t1, the input terminal IN1 of the Miller integrating circuit 53 that generates the rising ramp waveform is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN1. Then, a constant current flows from the resistor R1 toward the capacitor C1, the source voltage of the switching element Q1 rises in a ramp shape, and the output voltage of the initialization waveform generation circuit 51 also starts to rise in a ramp shape. This voltage increase continues while the input terminal IN1 is “Hi”.

  When the output voltage rises to the voltage Vr (equal to the voltage Vi2 in this embodiment), the input terminal IN1 is set to “Lo” at the subsequent time t2. Specifically, for example, 0 (V) is applied to the input terminal IN1. When the input terminal IN1 is set to “Lo”, the potential of the reference potential A is decreased to the voltage Vs (equal to the voltage Vi3 in this embodiment).

  During this time, the control signal OC1, the control signal SIU (1), and the control signal SID (1) are kept at “Hi”. Therefore, the control signal OC1 'output from the AND gate AG is also "Hi". Although not shown, the switching element SW1 is turned on, the switching elements SW2 and SW3 are turned off, and the reference voltage A, that is, the drive voltage output from the initialization waveform generating circuit 51 in the comparator CP1. And the voltage (Va + Vset2) are compared. Accordingly, during this period, the reference potential A is higher in potential than the voltage (Va + Vset2), so that the control signal OC2 output from the comparator CP1 is “Lo”.

  That is, since the control signal OC1 and the control signal OC1 ′ are “Hi” and the control signal OC2 is “Lo”, all the scan ICs 55 are in the “All-Lo” state, and the reference potential A, That is, the drive voltage output from the initialization waveform generation circuit 51 is output as it is.

  In this way, the voltage Vs (equal to the voltage Vi1 in the present embodiment) that is equal to or lower than the discharge start voltage gradually decreases toward the voltage Vr (equal to the voltage Vi2 in the present embodiment) that exceeds the discharge start voltage. Is applied to scan electrode SC1 through scan electrode SCn.

  Next, at time t3, a predetermined constant current is input to the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp waveform, and the input terminal IN2 is set to “Hi”. Then, a constant current flows from the resistor R2 toward the capacitor C2, the drain voltage of the switching element Q2 decreases in a ramp shape, the potential of the reference potential A decreases in a ramp shape, and the output voltage of the scan IC 55 also decreases in a ramp shape. Start to descend.

  At this time, the comparator CP1 compares the down-ramp waveform at the reference potential A with the voltage (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va, and the output signal from the comparator CP1, that is, the control signal OC2 Switches from “Lo” to “Hi” at time t5 when the down-ramp waveform at the reference potential A becomes equal to or lower than the voltage (Va + Vset2). As a result, both the control signal OC1 and the control signal OC2 become “Hi”, and the scan ICs (1) to IC (6) belonging to the first scan IC group enter the “All-Hi” state and are input to the input terminal INb. Output voltage. That is, the output voltages of the scan IC (1) to the scan IC (6) are voltages in which the voltage Vscn is superimposed on the reference potential A, and the voltage drop up to that time is switched to the voltage rise at time t5. The down-ramp waveform applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the electrode group is a down-ramp waveform L2 having an ultimate potential of voltage (Va + Vset2).

  Here, in the present embodiment, the scanning start signal SID (1) is set to “Lo” between time t2 and time t3. Since the comparator CP2 compares the reference potential A with the voltage (Va + Vset5), the signal CPO output from the comparator CP2 becomes “Lo” at time t4 when the reference potential A becomes equal to or lower than the voltage (Va + Vset5). Become. At this time, since the scanning start signal SID (1) is “Lo”, “Lo” is output from the OR gate OR, and thereby the control signal OC1 ′ output from the AND gate AG becomes “Lo”.

  As a result, both the control signal OC1 'and the control signal OC2 are "Lo", and the scan ICs (7) to ICs (12) belonging to the second scan IC group are in the "HiZ" state. That is, the output voltages of scan IC (7) to scan IC (12) are the voltages at which the output voltage at time t4 is held as it is, and are applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. The applied down-ramp waveform is a down-ramp waveform L5 whose ultimate potential is voltage (Va + Vset5).

  Since the scan start signal works effectively only when the scan IC 55 is in the “DATA” state, even if the scan start signal SID (1) becomes “Lo” in the initialization period, the scan IC (7) to the scan IC ( It does not affect the operation of 12).

  Then, before time t6 when the initialization period ends, for example, 0 (V) is applied to the input terminal IN2, and the input terminal IN2 is set to “Lo”.

  As described above, scan electrode drive circuit 43 has a ramp waveform that decreases from voltage Vi3 toward voltage (Va + Vset2) for scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group. L2 is generated, and for scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group, a down-ramp waveform L5 falling from voltage Vi3 toward voltage (Va + Vset5) is generated and initialized. The period ends.

(Writing period)
In the address period, although not shown, the switching element Q5 is turned on to maintain the reference potential A at the negative voltage Va. Further, the switching element SW2 is turned on, the switching elements SW1 and SW3 are turned off, and the reference potential A, that is, the negative voltage Va and the voltage (Va + Vset3) are compared in the comparator CP1. Accordingly, during this period, the reference potential A is lower in potential than the voltage (Va + Vset3), so that the control signal OC2 output from the comparator CP1 is “Hi”.

  At time t6, the control signal OC1 is set to “Lo”. Therefore, the control signal OC1 'output from the AND gate AG is also "Lo". As a result, all the scan ICs 55 are in the “DATA” state, and the scan is started by the scan start signal.

  In the first half of the address period, first, scan pulses are sequentially applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group. For this purpose, the scanning start signal SIU (1) is set to “Lo” for a predetermined period (for example, one period of the clock signal CLK) at time t7 immediately after the start of the writing period. Accordingly, the scan IC (1) starts scanning, and scan pulses are sequentially applied from the scan electrode SC1. From the scan IC (1), a scan start signal SIU (2) is output at the timing when scanning of all the scan electrodes connected to the scan IC (1) is completed, and is supplied to the scan IC (2). Thereby, the scanning IC (2) starts scanning. Thereafter, each scan IC 55 starts scanning based on the input scan start signal, generates a new scan start signal, and supplies it to the next-stage scan IC 55. In this way, the scanning electrodes belonging to the first scanning electrode group are sequentially scanned.

  The control signal OC1 is set to “Hi” at time t8 after the application of the scan pulse to the scan electrode SCn / 2 is completed and the scan to all the scan electrodes belonging to the first scan electrode group is completed. Since the scanning start signal SID (1) is maintained at “Hi”, the control signal OC1 ′ output from the AND gate AG also becomes “Hi”. Although not shown, switching element Q5 is turned off at time t8, and the clamp circuit of sustain pulse generating circuit 50 is operated to set reference potential A to 0 (V).

  As a result, the reference potential A is higher in potential than the voltage (Va + Vset2), so that the control signal OC2 output from the comparator CP1 is “Lo”. That is, since the control signal OC1 and the control signal OC1 ′ are “Hi” and the control signal OC2 is “Lo”, all the scan ICs 55 are in the “All-Lo” state, and the reference potential A ( In this embodiment, 0 (V)) is output.

  At a subsequent time t9, a predetermined constant current is input to the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp waveform, and the input terminal IN2 is set to “Hi”. As a result, the drain voltage of the switching element Q2 decreases in a ramp shape, the potential of the reference potential A decreases in a ramp shape, and the output voltage of the scan IC 55 also starts to decrease in a ramp shape.

  The comparator CP1 compares the down-ramp waveform at the reference potential A with the voltage (Va + Vset3), and the control signal OC2 output from the comparator CP1 has a down-ramp waveform at the reference potential A equal to or lower than the voltage (Va + Vset3). At time t10, the “Lo” is switched to “Hi”. As a result, the control signal OC1, the control signal OC1 ′, and the control signal OC2 all become “Hi”, and all the scan ICs 55 are in the “All-Hi” state, that is, the voltage input to the input terminal INb, that is, the reference potential A. A voltage on which the voltage Vscn is superimposed is output. As a result, the down-ramp waveform applied to scan electrode SC1 through scan electrode SCn becomes a down-ramp waveform L6 with an ultimate potential of voltage (Va + Vset3).

  Then, at time t11 after generating the down-ramp waveform L6, the input terminal IN2 is set to “Lo”. As described above, the scan electrode driving circuit 43 generates the down-ramp waveform L6, and generates an initializing discharge in the second discharge cell group immediately before starting the scan to the second scan electrode group.

  At time t11, although not shown, the switching element Q5 is turned on to maintain the reference potential A at the negative voltage Va. Further, the switching element SW1 is turned on, the switching elements SW2 and SW3 are turned off, and the reference potential A, that is, the negative voltage Va and the voltage (Va + Vset2) are compared in the comparator CP1. Accordingly, during this period, the reference potential A is lower in potential than the voltage (Va + Vset2), so that the control signal OC2 output from the comparator CP1 is “Hi”.

  At time t11, the control signal OC1 is set to “Lo”. Therefore, the control signal OC1 'output from the AND gate AG is also "Lo". As a result, all the scan ICs 55 are in the “DATA” state, and the scan is started by the scan start signal.

  In the second half of the address period, scan pulses are sequentially applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. For this purpose, the scanning start signal SID (1) is set to “Lo” for a predetermined period (for example, one cycle of the clock signal CLK) at time t12 immediately after the start of the second half of the writing period. Accordingly, the scan IC (7) starts scanning, and scan pulses are sequentially applied from the scan electrodes SCn / 2 + 1. Thereafter, the scanning electrodes belonging to the second scanning electrode group are sequentially scanned by the same operation as described above.

(Maintenance period)
Then, at time t13 after the application of the scan pulse to the scan electrode SCn is finished and the scan to all the scan electrodes belonging to the second scan electrode group is finished and the address period is finished, the control signal OC1 is set to “Hi”. " Since the scanning start signal SID (1) is maintained at “Hi”, the control signal OC1 ′ output from the AND gate AG also becomes “Hi”.

  Although not shown, the switching element Q5 is turned off at time t13, and the clamp circuit of the sustain pulse generating circuit 50 is also operated to set the reference potential A to 0 (V).

  As a result, the reference potential A is higher in potential than the voltage (Va + Vset2), so that the control signal OC2 output from the comparator CP1 is “Lo”. That is, since the control signal OC1 and the control signal OC1 ′ are “Hi” and the control signal OC2 is “Lo”, all the scan ICs 55 are in the “All-Lo” state, and the reference potential A (this embodiment) is output from the output terminal of the scan IC 55. In this form, 0 (V)) is output.

  Subsequently, although not described in detail, the power recovery circuit and the clamp circuit of the sustain pulse generating circuit 50 are alternately operated to generate a predetermined number of sustain pulses. Then, at the end of the sustain period, the erase ramp waveform L3 is generated. Thus, the maintenance period ends.

(Initialization period)
In the subsequent initialization period, although not shown, the switching element SW3 is turned on while the switching element Q5 is kept off, the switching element SW1 and the switching element SW2 are turned off, and the reference potential A in the comparator CP1. (In this embodiment, 0 (V)) is compared with the voltage (Va + Vset4). Since the reference potential A has a higher potential than the voltage (Va + Vset4), the control signal OC2 output from the comparator CP1 remains “Lo” following the sustain period. Further, the control signal OC1 is also maintained at “Hi” after the sustain period.

  Accordingly, since the control signal OC1 and the control signal OC1 ′ are “Hi” and the control signal OC2 is “Lo”, all the scan ICs 55 are in the “All-Lo” state, and the reference potential A, That is, the drive voltage output from the initialization waveform generation circuit 51 is output as it is.

  At a time t14, a predetermined constant current is input to the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp waveform, and the input terminal IN2 is set to “Hi”. As a result, the drain voltage of the switching element Q2 decreases in a ramp shape, the potential of the reference potential A decreases in a ramp shape, and the output voltage of the scan IC 55 also starts to decrease in a ramp shape.

  The comparator CP1 compares the down-ramp waveform at the reference potential A with the voltage (Va + Vset4), and the control signal OC2 output from the comparator CP1 has a down-ramp waveform at the reference potential A equal to or lower than the voltage (Va + Vset4). At time t16, the switch is made from “Lo” to “Hi”. As a result, both the control signal OC1 and the control signal OC2 become “Hi”, and the first scan IC group enters the “All-Hi” state and is input to the input terminal INb, that is, the voltage Vscn to the reference potential A. Outputs the superimposed voltage. As a result, the down-ramp waveform applied to scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group becomes a down-ramp waveform L4 having an ultimate potential of voltage (Va + Vset4).

  In the present embodiment, the scanning start signal SID (1) is set to “Lo” immediately after the start of the initialization period (in the present embodiment, from time t14 to time t15). Since the comparator CP2 compares the reference potential A with the voltage (Va + Vset5), the signal CPO output from the comparator CP2 becomes “Lo” at time t15 when the reference potential A becomes equal to or lower than the voltage (Va + Vset5). Become. At this time, since the scanning start signal SID (1) is “Lo”, “Lo” is output from the OR gate OR, and thereby the control signal OC1 ′ output from the AND gate AG becomes “Lo”.

  As a result, both the control signal OC1 'and the control signal OC2 are "Lo", and the scan ICs (7) to ICs (12) belonging to the second scan IC group are in the "HiZ" state. That is, the output voltages of scan IC (7) to scan IC (12) are the voltages at which the output voltage at time t15 is held as it is, and are applied to scan electrode SCn / 2 + 1 to scan electrode SCn belonging to the second scan electrode group. The applied down-ramp waveform is a down-ramp waveform L7 whose ultimate potential is voltage (Va + Vset5).

  Then, before time t17 when the initialization period ends, for example, 0 (V) is applied to the input terminal IN2, and the input terminal IN2 is set to “Lo”.

  As described above, scan electrode drive circuit 43 descends from 0 (V) toward voltage (Va + Vset4) for scan electrode SC1 to scan electrode SCn / 2 belonging to the first scan electrode group. A ramp waveform L4 is generated, and for the scan electrodes SCn / 2 + 1 to scan electrodes SCn belonging to the second scan electrode group, a down-ramp waveform L7 that decreases from 0 (V) toward the voltage (Va + Vset5) is generated. This completes the initialization period.

  The subsequent address period, sustain period, and subsequent operations are the same as those described above.

  In the plasma display device 1 according to the present embodiment configured as described above, a stable writing operation can be performed without increasing the scan pulse voltage (amplitude) even in the panel 10 with high definition. Next, this effect will be described.

  FIG. 10 is a schematic characteristic diagram showing the relationship between the scan pulse voltage (amplitude) necessary for generating a stable address discharge and the scan order when performing a one-phase driving operation in the prior art. FIG. 10A is a schematic characteristic diagram showing the relationship between the scanning pulse voltage (amplitude) necessary for generating a stable address discharge when performing a one-phase driving operation and the order of scanning. Scanning order of scan electrode SC1 to scan electrode SCn is represented, and the vertical axis represents scan pulse voltage (amplitude) necessary for generating a stable address discharge in each discharge cell. FIG. 10B is a waveform diagram showing drive waveforms applied to scan electrode SC1 through scan electrode SCn when performing a one-phase drive operation. Scan electrode SC1 that scans first in the write period, write period Drive waveforms of scan electrode SCn / 2 + 1 that scans at approximately the middle point of time, and scan electrode SCn that scans at the end of the address period are shown. FIG. 10 is a graph showing the relationship between the scan pulse voltage (amplitude) necessary for generating a stable address discharge and the passage of time after the initialization operation. Is not changed for each scan electrode.

  As shown in FIG. 10A, in each discharge cell, the scanning pulse voltage (amplitude) necessary for generating a stable address discharge increases as the scanning order becomes slower. Then, in the discharge cell that scans last, compared to the discharge cell that scans first, the scan pulse voltage (amplitude) required to generate a stable address discharge may increase by about 34 (V). Confirmed by experiment.

  This is presumably because the wall charges formed in the discharge cells by the initializing discharge during the initializing period gradually decrease with time. One of the causes is that an address pulse is applied to each data electrode during the address period (according to the display image), so that an address pulse voltage is also applied to discharge cells that are not scanned. It is done. The wall charge is also reduced by the influence of an address pulse applied to the data electrode in order to generate an address discharge in another discharge cell. Accordingly, it is considered that the discharge cells having a slower scanning order reduce more wall charges, and the scanning pulse voltage (amplitude) must be increased accordingly.

  FIG. 11 is a schematic characteristic diagram showing the relationship between the scan pulse voltage (amplitude) necessary for generating a stable address discharge and the scan order when performing the two-phase drive operation in the first embodiment of the present invention. is there. FIG. 11A is a schematic characteristic diagram showing the relationship between the scanning pulse voltage (amplitude) necessary for generating a stable address discharge when performing a two-phase driving operation and the order of scanning. Scanning order of scan electrode SC1 to scan electrode SCn is represented, and the vertical axis represents scan pulse voltage (amplitude) necessary for generating a stable address discharge in each discharge cell. The characteristic indicated by the broken line in FIG. 11A is a scan pulse voltage (amplitude) necessary for generating a stable address discharge during the one-phase driving operation shown in FIG. FIG. 11B is a waveform diagram showing drive waveforms applied to scan electrode SC1 through scan electrode SCn when performing a two-phase drive operation, and is a scan electrode that performs scanning at the beginning of an address period. The scan electrode SC1 belonging to the scan electrode group, the scan electrode scanning at approximately the middle of the address period, the scan electrode SCn / 2 + 1 belonging to the second scan electrode group, and the scan electrode scanning at the end of the address period The drive waveform in scan electrode SCn belonging to the second scan electrode group is shown.

  In the two-phase driving operation in the present embodiment, an initializing discharge with a down-ramp waveform is generated for each discharge cell group immediately before starting scanning in each scan electrode group. That is, in each discharge cell of the first discharge cell group, the initializing discharge with the down-ramp waveform L2 (down-ramp waveform L4 after the second SF) is performed immediately before the scan of each scan electrode of the first scan electrode group is started. In each discharge cell of the second discharge cell group, an initializing discharge is generated with a down-ramp waveform L6 immediately before the scan of each scan electrode in the second scan electrode group is started.

  Since the wall discharge in the discharge cell can be brought into an appropriate state by this initialization discharge, as shown by a solid line in FIG. 11A, a scan pulse voltage (amplitude) necessary for generating a stable address discharge is obtained. ) Can be reduced in the second discharge cell group. In the discharge cell that performs scanning at the end of the address period, the scan pulse voltage (amplitude) necessary for generating a stable address discharge is about 20 (compared with that in the one-phase drive operation in the two-phase drive operation). V) It was confirmed by experiment that it can be reduced.

  As described above, in the present embodiment, by performing the above-described two-phase driving operation of generating the initializing discharge with the down-ramp waveform before starting the scan to the second scan electrode group in the address period, The scan pulse voltage (amplitude) required to generate a stable address discharge can be reduced, and the applied voltage required for driving can be increased even in discharge cells whose scan order is likely to become unstable. This makes it possible to perform a stable write operation without doing so.

  As described above, according to the present embodiment, scan electrode SC1 to scan electrode SCn are divided into the first scan electrode group and the second scan electrode group, in addition to the initialization operation in the initialization period, A scan pulse voltage necessary for generating a stable address discharge by performing a two-phase driving operation for generating an initializing discharge in the second discharge cell group before the start of scanning to the second scan electrode group in the period (Amplitude) can be reduced. This makes it possible to perform a stable address operation without increasing the applied voltage required for driving even in a discharge cell whose scan order is slow, in which the address discharge tends to become unstable.

(Embodiment 2)
In the first embodiment, a Vset generation circuit 80 is configured using a power source that generates the voltage Vset2, a power source that generates the voltage Vset3, a power source that generates the voltage Vset4, and the switching element SW1, the switching element SW2, and the switching element SW3. The example in which the voltage (Vset2 + Va), the voltage (Vset3 + Va), and the voltage (Vset4 + Va) are generated has been described. However, in the second embodiment, an example of a Vset generation circuit capable of generating a voltage (Vset2 + Va), a voltage (Vset3 + Va), and a voltage (Vset4 + Va) with a more rational circuit configuration will be described.

  FIG. 12 is a circuit diagram of the Vset generation circuit 81 according to the second embodiment of the present invention.

  The Vset generation circuit 81 in this embodiment includes a shunt regulator 56. The shunt regulator 56 operates to draw current from the cathode when the comparison voltage applied to the reference terminal (denoted as “Ref” in the drawing) becomes larger than the reference voltage set in the shunt regulator 56. To do. In the present embodiment, this operation is used to control the voltage supplied to the comparator CP1, that is, the set voltage B that sets the ultimate potential of the down-ramp waveform.

  Specifically, the anode of the shunt regulator 56 is connected to the negative voltage Va, and the cathode is connected to the voltage Vo (for example, 16 (V)) via the resistor R10. The cathode of the shunt regulator 56 is also connected to the base of the NPN transistor Q10. The collector of the transistor Q10 is connected to the voltage Vo, and the emitter of the transistor Q10 is connected to the reference terminal of the shunt regulator 56 via the resistor R9. That is, the transistor Q10 has the function of an emitter follower so that the set voltage B based on the voltage of the cathode of the shunt regulator 56 is taken out from the emitter of the transistor Q10 with low impedance, and the set voltage B is supplied to the reference terminal of the shunt regulator 56. It is configured to feed back as a comparison voltage. This set voltage B is supplied to the comparator CP1 and used to determine the ultimate potential of the down-ramp waveform.

  An input terminal SS1 for controlling the Vset generation circuit 81 is connected via a resistor R11 to the emitter of a PNP transistor Q11 whose base is connected to the ground potential. Similarly, the input terminal SS2 is connected to the emitter of a PNP transistor Q21 whose base is connected to the ground potential via a resistor R21, and the input terminal SS3 is the emitter of a PNP transistor Q31 whose base is connected to the ground potential. Is connected via a resistor R31.

  The collector of the transistor Q11 is connected to the base of the switching element Q12 via the resistor R12. Similarly, the collector of transistor Q21 is connected to the base of switching element Q22 via resistor R22, and the collector of transistor Q31 is connected to the base of switching element Q32 via resistor R32.

  The emitters of the switching element Q12, switching element Q22, and switching element Q32 are connected to a negative voltage Va. A resistor R13 is connected between the emitter and base of the switching element Q12, and a resistor R23 is connected between the emitter and base of the switching element Q22. A resistor R33 is inserted between the emitter and base of the switching element Q32.

  Therefore, by setting the input terminal SS1, the input terminal SS2, and the input terminal SS3 to “Hi” (for example, 5 (V) is applied) or “Lo” (for example, 0 (V) is applied), the transistor Q11 The transistor Q21 and the transistor Q31 can be made conductive (ON) or cut off (OFF). When the transistor Q11 is turned on, the switching element Q12 is turned on. When the transistor Q21 is turned on, the switching element Q22 is turned on. When the transistor Q31 is turned on, the switching element Q32 is turned on.

  In addition, a resistor R14, a resistor R24, and a resistor R34 are provided so as to be electrically in parallel with the resistor R8. Specifically, the collector of the switching element Q12 is connected to the reference terminal of the shunt regulator 56 via the resistor R14. Similarly, the collector of switching element Q22 is connected to the reference terminal of shunt regulator 56 via resistor R24, and the collector of switching element Q32 is connected to the reference terminal of shunt regulator 56 via resistor R34. In addition, a resistor R8 is inserted between the reference terminal of the shunt regulator 56 and the negative voltage Va.

  Accordingly, the voltage applied to the input terminal SS1, the input terminal SS2, and the input terminal SS3 is controlled, and the switching element Q12, the switching element Q22, and the switching element Q32 are controlled to be turned on / off, thereby being connected in parallel to the resistor R8. By switching the resistance, the resistance value between the reference terminal of the shunt regulator 56 and the negative voltage Va can be changed.

  The shunt regulator 56 operates to draw current from the cathode when the comparison voltage applied to the reference terminal is larger than the reference voltage set in the shunt regulator 56. Accordingly, the current is drawn from the power supply voltage (in this embodiment, the voltage Vo) to the cathode of the shunt regulator 56 through the voltage drop resistor R10, and the setting is generated by the voltage drop by the resistor R10. If the voltage B is configured to be applied to the reference terminal of the shunt regulator 56, a feedback loop that draws current from the cathode of the shunt regulator 56 so that the comparison voltage applied to the reference terminal is equal to the reference voltage inside the shunt regulator 56. Can be configured.

  That is, as shown in FIG. 12, the set voltage B is divided by resistance and applied to the reference terminal of the shunt regulator 56 as a comparison voltage, and the resistance ratio of the resistance division is changed (in this embodiment, the shunt regulator 56 The resistance value between the reference terminal and the negative voltage Va can be changed). In this configuration, for example, if the resistance value between the reference terminal of the shunt regulator 56 and the voltage Va is reduced, the current drawn to the cathode of the shunt regulator 56 so that the comparison voltage generated by the resistance division becomes equal to the reference voltage. Therefore, the voltage value of the set voltage B can be increased. In this embodiment, the set voltage B can be generated with a plurality of different voltage values in this way.

  Thus, the Vset generation circuit 81 that generates a plurality of different voltages is configured with a relatively simple configuration without using a plurality of power supply voltages and without using a relatively expensive switching element such as a photocoupler. be able to.

  The transistor Q10 has a temperature characteristic (for example, −2 mV / ° C.) in VBE (base-emitter voltage), but a voltage created from the voltage output from the emitter of the transistor Q10 is supplied to the shunt regulator 56 as a comparison voltage. Therefore, even if a change in VBE due to a temperature change occurs, feedback is applied to cancel the change, and the set voltage B can be kept constant regardless of the temperature.

  Note that resistors used for setting a voltage to be applied to the reference terminal of the shunt regulator 56 (in this embodiment, resistors R8, R9, R14, R24, and R34) include resistance elements (for example, variations) with little variation. It is desirable to use a 1% resistance element.

  Next, a change in the voltage value of the set voltage B in the present embodiment will be described. FIG. 13 is a diagram illustrating an example of a correspondence relationship between the control voltage applied to the input terminal SS1, the input terminal SS2, and the input terminal SS3 and the set voltage B in Embodiment 2 of the present invention. Note that the control voltage applied to the input terminal SS1, the input terminal SS2, and the input terminal SS3 is supplied from the control signal generation circuit 45.

  In the present embodiment, when the comparison voltage generated by the resistance division between the resistors R9 and R8 is applied to the reference terminal of the shunt regulator 56, the set voltage B is the voltage (Va + Vset2) (for example, the voltage Vset2 = 6 ( V)), the resistance values of the resistors R8 and R9 are set. Therefore, the setting voltage B can be set to the voltage (Va + Vset2) by setting all of the input terminal SS1, the input terminal SS2, and the input terminal SS3 to “Lo”.

  Further, in the present embodiment, when the resistance value between the reference terminal of the shunt regulator 56 and the negative voltage Va becomes a resistance value obtained by connecting the resistor R8 and the resistor R14 in parallel, the set voltage B is the voltage. The resistance value of the resistor R14 is set so as to be (Va + Vset3) (for example, the voltage Vset3 = 8 (V)). Therefore, the setting voltage B can be set to the voltage (Va + Vset3) by setting the input terminal SS1 to “Hi”, the input terminal SS2, and the input terminal SS3 to “Lo”.

  In the present embodiment, when the resistance value between the reference terminal of the shunt regulator 56 and the negative voltage Va becomes a resistance value obtained by connecting the resistor R8, the resistor R14, and the resistor R24 in parallel, the set voltage The resistance value of the resistor R24 is set so that B becomes the voltage (Va + Vset4) (for example, the voltage Vset4 = 10 (V)). Therefore, the setting voltage B can be set to the voltage (Va + Vset4) by setting the input terminal SS1 and the input terminal SS2 to “Hi” and the input terminal SS3 to “Lo”.

  Although not used in the first embodiment, in the present embodiment, the set voltage B can be generated with a voltage higher than the voltage (Va + Vset4). For example, when the resistance value between the reference terminal of the shunt regulator 56 and the negative voltage Va becomes a resistance value obtained by connecting the resistors R8, R14, R24, and R34 in parallel, the set voltage B is a voltage. The resistance value of the resistor R34 is set so as to be (Va + 12 (V)). In this way, when all of the input terminal SS1, the input terminal SS2, and the input terminal SS3 are set to “Hi”, the set voltage B can be set to a voltage (Va + 12 (V)) higher than the voltage (Va + Vset4).

  As described above, according to the present embodiment, the comparison voltage generated by dividing the set voltage B by resistance is applied to the reference terminal of the shunt regulator 56, and the resistance ratio of the resistance division is changed. By configuring, it is possible to stably generate the set voltage B generated by a plurality of different voltages with a relatively simple circuit configuration regardless of the temperature.

  In the present embodiment, the configuration in which the set voltage B is generated at four different voltage values has been described. However, by changing the number of resistors connected in parallel to the resistor R8, more different voltage values can be easily generated. Can be generated.

  In the present embodiment, the configuration in which the resistance value between the reference terminal of the shunt regulator 56 and the negative voltage Va is changed has been described. For example, the resistance value between the set voltage B and the reference terminal is changed. It can also be set as the structure to do. FIG. 14 is a circuit diagram schematically showing another configuration example of the Vset generation circuit according to the second embodiment of the present invention. For example, as shown in the Vset generation circuit 82 in FIG. 14, a resistor R15, a resistor R25, and a resistor R35 are provided in parallel with the resistor R9, and the shunt regulator 56 is turned on / off by the switching element SW11, the switching element SW21, and the switching element SW31. Even if the resistance value between the reference terminal and the negative voltage Va is changed, the same operation as described above can be performed.

  Although the two-phase driving operation has been described in the embodiment of the present invention, the present invention is not limited to the two-phase driving operation. For example, the display area of the panel 10 may be divided into three so that the number of scan electrode groups is three and a three-phase drive operation is performed. Alternatively, the display area of the panel 10 may be divided into four or more, and the number of scan electrode groups may be four or more, so that the four-phase driving operation or more. In this case, however, only the down ramp waveform applied to the first scan electrode group during the initialization period is set as the down ramp waveform L2, and the down ramp waveform applied to the scan electrode groups other than the first scan electrode group is the down ramp waveform. It is assumed that the waveform is L5. Further, when the down-ramp waveform L6 is applied to the second scan electrode group in the address period, the ultimate potential is set to the voltage (Va + Vset5) or higher voltage in the scan electrode group after the third scan electrode group. A waveform shall be applied. Thereafter, similarly, a down-ramp waveform L5 is applied to the scan electrode group that starts the address operation immediately before the start of the address operation, and a drive voltage waveform that does not generate an address discharge is applied to the other scan electrode groups. It shall be.

  In the embodiment of the present invention, the down-ramp waveform L5 and the down-ramp waveform L7 are shown as waveform shapes that hold the voltage for a certain period after the voltage of the down-ramp waveform reaches the voltage (Va + Vset5). . However, this is merely such a waveform shape in the circuit configuration of the scan electrode drive circuit 43, and the present embodiment is not limited to this waveform shape. For example, it may be a circuit configuration that outputs a waveform that starts voltage increase immediately after the voltage of the ramp-down waveform reaches the voltage (Va + Vset5).

  In the embodiment of the present invention, the configuration in which scan electrode SC1 to scan electrode SCn are divided into two equal parts when the scan electrode group is divided in the two-phase drive operation is described. However, the present invention is not limited to this configuration. Instead, there may be a difference in the number of scan electrodes for each scan electrode group. In the present embodiment, when the scan electrode groups are divided, scan electrode SC1 to scan electrode SCn / 2 arranged in the upper half of the display surface of panel 10 are set as the first scan electrode group, and the lower half is used. The configuration in which the scan electrode SCn / 2 + 1 to the scan electrode SCn to be arranged is the second scan electrode group has been described. For example, the scan electrode belonging to the odd number is the first scan electrode group, and the scan electrode belonging to the even number is The second scanning electrode group may be used.

  In the embodiment of the present invention, the voltage Vset2 is 6 (V), the voltage Vset3 is 8 (V), the voltage Vset4 is 10 (V), and the voltage Vset5 is 70 (V). The numerical value is merely an example, and an optimal voltage value may be set according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  Further, the timing chart shown in FIG. 9 is merely an example in the embodiment and is not limited to these timing charts. The initialization waveform may be generated by a method other than that shown in the present embodiment, or the scan IC may alternately repeat the “DATA” state and the “All-Hi” state during the writing period. A configuration in which the generation interval of the scanning pulse is controlled by generating each control signal may be employed.

  In the embodiment of the present invention, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other. , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,... ”Is also effective in a panel having an electrode structure (referred to as“ ABBA electrode structure ”).

  The specific values such as the voltage Vset2, the voltage Vset3, the voltage Vset4, the voltage Vset5, the number of subfields, the luminance weight, and the scanning pulse voltage (amplitude) shown in the embodiment of the present invention are 50 inches, display electrodes This is set based on the characteristics of the logarithmic 1080 panels, and is merely an example in the embodiment. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. In addition, the polarity of each control signal shown when explaining the operation of the scan IC 55 is merely an example, and may be a polarity opposite to the polarity shown in the description.

  In the embodiment of the present invention, the configuration in which the erase ramp waveform is applied to scan electrode SC1 through scan electrode SCn has been described. However, the erase ramp waveform may be applied to sustain electrode SU1 through sustain electrode SUn. . Alternatively, an erasing discharge may be generated not by an erasing ramp waveform but by a so-called narrow erasing pulse.

  INDUSTRIAL APPLICABILITY The present invention is useful as a plasma display device and a panel driving method because a stable address discharge can be generated without increasing the scan pulse voltage even in a panel with a large screen and high definition. .

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel Circuit block diagram of plasma display device according to Embodiment 1 of the present invention Circuit diagram of scan electrode driving circuit in Embodiment 1 of the present invention Schematic showing a connection state between a scan IC and a scan electrode of the scan electrode driving circuit according to the first embodiment of the present invention. The figure for demonstrating the correspondence of control signal OC1, control signal OC2, and the operation state of scan IC in Embodiment 1 of this invention. Schematic which shows an example of the division of the scanning electrode group in Embodiment 1 of this invention Drive voltage waveform diagram applied to each electrode of the panel in the two-phase drive operation of the scan electrode drive circuit in Embodiment 1 of the present invention Timing chart for explaining an example of the operation of the scan electrode driving circuit in Embodiment 1 of the present invention Schematic characteristic diagram showing the relationship between the scan pulse voltage (amplitude) necessary for generating a stable address discharge and the scan order when performing a one-phase drive operation in the prior art Schematic characteristic diagram showing the relationship between the scan pulse voltage (amplitude) necessary for generating a stable address discharge and the scan order when performing the two-phase drive operation in the first embodiment of the present invention Circuit diagram of Vset generation circuit according to Embodiment 2 of the present invention The figure which shows an example of the correspondence of the control voltage applied to input terminal SS1, input terminal SS2, and input terminal SS3, and setting voltage B in Embodiment 2 of this invention. The circuit diagram which shows the other structural example of the Vset generation circuit in Embodiment 2 of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Control signal generation circuit 50 Sustain pulse generation circuit 51 Initialization waveform generation circuit 52 Scan pulse generation circuit 53, 54 Miller integration circuit 55 Scan IC
56 Shunt regulator 77 Flexible wiring board 80, 81, 82 Vset generation circuit CP1, CP2 Comparator Q1, Q2, Q4, Q5, Q12, Q22, Q32, QH1 to QHn, QL1 to QLn, SW1, SW2, SW3, SW11, SW21, SW31 Switching element Q10, Q11, Q21, Q31 Transistors R1, R2, R8, R9, R10, R11, R12, R13, R14, R15, R21, R22, R23, R24, R25, R31, R32, R33, R34 , R35 Resistor C1, C2, C31 Capacitor D31 Diode OR OR gate AG AND gate

Claims (2)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A plurality of subfields each having an initialization period, an address period, and a sustain period are provided in one field period, and the scan electrodes are divided into a plurality of scan electrode groups including a first scan electrode group, and in the initialization period, A scan electrode driving circuit that drives the scan electrodes by generating a down-slope waveform voltage having a different waveform shape between the first scan electrode group and a scan electrode group other than the first scan electrode group;
The scan electrode driving circuit includes:
A shunt regulator that generates a set voltage used to set the ultimate potential of the descending ramp waveform voltage;
A voltage generated by dividing the set voltage by resistance is fed back to the shunt regulator, and the set voltage is generated at a plurality of different voltage values by changing a resistance ratio of the resistance division. Display device. A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A plurality of subfields each having an initialization period, an address period, and a sustain period are provided in one field period, and the scan electrodes are divided into a plurality of scan electrode groups including a first scan electrode group, and in the initialization period, A driving method of a plasma display panel for driving a scanning electrode by generating a downward ramp waveform voltage having a different waveform shape between a first scanning electrode group and a scanning electrode group other than the first scanning electrode group,
A set voltage used for setting the ultimate potential of the downward ramp waveform voltage is generated using a shunt regulator, and the voltage generated by dividing the set voltage by resistance is fed back to the shunt regulator, and the resistance ratio of the resistance division A method for driving a plasma display panel, wherein the set voltage is generated at a plurality of different voltage values by changing the voltage.

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