JP2010061613A - Method of designing integrated circuit device, clock tree construction tool, integrated circuit device, microcomputer, and electronic equipment - Google Patents

Abstract

An integrated circuit design method capable of constructing a clock tree capable of reducing power consumption when a clock gating cell is present.
For a synchronous circuit in which a clock gating cell is present, a clock skew between a first storage element and a second storage element is smaller than a given value, and a place for further skew adjustment is a clock gate. If the clock skew is changed so that the clock skew is equal to or greater than a given value based on the timing analysis result for the synchronous circuit, if it is determined that the timing error does not occur, By inserting a delay element after the clock gating cell of the clock line connected to the first storage element, processing for changing the clock skew is performed to reconstruct the clock tree.
[Selection] Figure 5

Description

  The present invention relates to an integrated circuit device design method, a clock construction tool, an integrated circuit device, a microcomputer, and an electronic apparatus.

  In designing a synchronous circuit in an integrated circuit device, the design is performed on the assumption that each flip-flop is synchronously controlled by the same clock. However, when the cells included in the synchronous circuit are arranged on the layout, the clock route wiring length varies depending on the relative positional relationship between the clock buffer serving as the clock route and the flip-flops in the layout. The propagation delay of the clock signal from to each flip-flop is different. If this difference in propagation delay is large, a timing error occurs and the circuit malfunctions. For example, in a circuit with a small signal propagation delay between flip-flops such as a shift register, if the clock delay to the subsequent flip-flop is much larger than the clock delay to the previous flip-flop, a hold time error occurs and the circuit Malfunctions. Also, in a circuit in which the signal propagation delay between flip-flops is slightly smaller than the clock cycle, it will not malfunction if there is no clock skew, but the clock delay to the previous flip-flop is higher than the clock delay to the subsequent flip-flop. If it is quite large, a setup time error occurs and the circuit malfunctions.

  For this reason, in designing the synchronous circuit, delays of all clock lines are aligned by inserting a delay element such as a clock buffer from the clock root to the clock input of each flip-flop by using a tool, etc. Generally, a clock tree is constructed so as to be small.

  However, if the clock skew is small, the clock inputs of all flip-flops change almost simultaneously. For this reason, the timings at which the transistors of the clock input buffer in each flip-flop switch are substantially the same, and a through current flows simultaneously from the power supply to the ground when the transistors are switched. Since the peak current increases instantaneously due to such through currents flowing simultaneously, the power supply potential instantaneously drops. If this voltage drop is below the logic threshold of the transistor, the circuit may malfunction.

  In view of the circumstances as described above, the applicant of the present invention is able to reduce the peak current generated during the clock operation of the synchronous circuit and to control the integrated circuit that can be controlled to construct a clock tree that can suppress the voltage drop of the power supply potential. A design method and a clock tree construction tool have been proposed (see, for example, Patent Document 1 below).

JP 2008-152550 A

  By the way, a clock gating cell for gating a clock signal may exist on the transmission path of the clock signal. In such a case, it is desired to reduce power consumption.

  The present invention has been made in view of the above problems, and can reduce power consumption when a clock gating cell for gating a clock signal is present on the transmission path of the clock signal. An object of the present invention is to provide an integrated circuit device design method, a clock tree construction tool, an integrated circuit device, a microcomputer, and an electronic device that can be controlled to construct a clock tree.

(1) A method for designing an integrated circuit device according to the present invention includes:
The first storage element having a plurality of storage elements that operate based on the same clock and not including other storage elements on a signal path from the output of the first storage element to the input of the second storage element And an integrated circuit device including a synchronization circuit in which a clock tree is constructed such that a clock skew between the second storage element and the second storage element is less than or equal to a predetermined value and a clock gating cell is disposed on a clock transmission path A design method,
When the clock skew between the given first storage element and the second storage element is smaller than a given value and the place where the clock skew is adjusted is after the clock gating cell, Based on a timing analysis result for the synchronization circuit, a process for changing the clock skew in a subsequent stage of the clock gating cell so that the clock skew is equal to or greater than a given value is performed. A clock tree restructuring step for reconstructing the tree is included.

  In the method for designing an integrated circuit device according to the present invention, the first storage element and the second storage element that do not include other storage elements on the signal path from the output of the first storage element to the input of the second storage element. A process for changing the clock skew is performed with respect to the clock skew between the storage elements. That is, there is a signal path from the output of the first memory element to the input of the second memory element, and the first memory element and the second memory that do not include other memory elements on the path. Clock skew between elements is an object of adjustment. The first storage element and the second storage element correspond to the storage elements that are the start and end points of the signal path that is the target of the setup time error and hold time error analysis in the timing analysis.

  The clock skew between the first storage element and the second storage element is the propagation delay of the clock signal from the clock root to the clock input of the first storage element and the clock input from the clock root to the clock input of the second storage element. This is the difference in the propagation delay of the clock signal.

  The storage element may be any element that operates in synchronization with the input clock and can store 1-bit information. For example, the storage element may be various flip-flops such as a D flip-flop, Various latches such as a latch may be used.

  In the synchronization circuit in which the clock tree is constructed, the clock skew between the first memory element and the second memory element is less than or equal to a predetermined value based on at least the cell arrangement information on the layout, and the clock It suffices if a clock gating cell is arranged on the transmission path. Further, the clock skew based on more accurate calculation after actual wiring on the layout may be a predetermined value or less. In the synchronization circuit, a clock tree may be constructed such that all clock skews between the first storage element and the second storage element are equal to or less than a predetermined value, or a predetermined signal path, for example, A signal path that does not require consideration of signal propagation delay (dummy path), a signal path that does not require consideration of clock skew between the first memory element and the second memory element (clock skew may be large), etc. The clock tree may be constructed so that the clock skew between the first memory element and the second memory element on the signal path excluding the signal is less than or equal to a predetermined value.

  The timing analysis result for the synchronization circuit in which the clock tree is constructed may be a result of timing analysis based on at least information on cell arrangement on the layout. Further, it may be a more accurate timing analysis result in consideration of actual wiring after performing actual wiring on the layout.

  Examples of the timing error include a setup time error and a hold time error for the storage element.

  In order to make the clock skew between the first memory element and the second memory element equal to or greater than a given value, for example, either the first memory element or the clock line connected to the second memory element Only a delay element may be inserted after the clock gating cell, or delay elements having different delay times may be inserted after the clock gating cells of both clock lines. In addition, when a delay element is inserted in the clock line connected to the first memory element or the second memory element, the delay element is deleted from only one of the clock lines in the subsequent stage of the clock gating cell. Alternatively, delay elements having different delay times may be deleted from both clock lines at the subsequent stage of the clock gating cell.

  According to the present invention, when a clock gating cell for gating a clock signal exists on the transmission path of the clock signal, the clock skew between the first storage element and the second storage element is a given value. As described above, the clock tree is reconstructed at the subsequent stage of the clock gating cell. As a result, since the number of elements that operate when the clock is gated can be reduced, power consumption can be reduced.

  The given value may be a value sufficient to reduce the peak current, and may be obtained by calculation or simulation.

  According to the present invention, at least the clock skew between the first storage element and the second storage element, that is, the clock skew between the two storage elements related to the operation timing is equal to or greater than a given value. The clock tree is reconstructed at the subsequent stage of the clock gating cell. The two storage elements related to the operation timing are likely to be disposed at physically close locations on the layout, and these storage elements are often supplied with power from the same power supply rail. Therefore, if the clock tree is reconstructed in the subsequent stage of the clock gating cell so that the clock skew between the two storage elements related to the operation timing is equal to or greater than a given value, the voltage drop of the power supply potential is effectively reduced. be able to. On the other hand, two storage elements that are irrelevant in the operation timing are unlikely to be physically located in the layout, and these storage elements are often supplied with power from different power supply rails. Therefore, regarding the clock skew between two storage elements that are irrelevant in the operation timing, the voltage drop of the power supply potential can be effectively reduced even if the clock tree is reconstructed while being smaller than a given value. If possible, the clock tree may be constructed in the subsequent stage of the clock gating cell so that the clock skew between the two storage elements that are irrelevant in the operation timing is equal to or greater than a given value.

(2) An integrated circuit device design method according to the present invention includes:
The clock tree reconstruction step includes:
If it is determined that a timing error occurs by changing the clock skew based on the timing analysis result for the synchronous circuit, the process for changing the clock skew is not performed.

  According to the present invention, the process of changing the clock skew is performed only when it is determined that a timing error does not occur based on the timing analysis result. Therefore, the synchronous circuit after the clock tree is reconstructed has no timing error and can reduce the peak current.

(3) An integrated circuit device design method according to the present invention includes:
The clock tree reconstruction step includes:
The clock skew is changed by inserting one or more delay elements in a clock line connected to the first memory element at a subsequent stage of the clock gating cell.

  According to the present invention, since only one or more delay elements are inserted into the clock line connected to the first storage element at the subsequent stage of the clock gating cell, most signal paths have a large margin for setup time errors. In some cases, the clock skew can be easily increased beyond a given value, and the peak current can be reduced.

(4) A method for designing an integrated circuit device according to the present invention includes:
The clock tree reconstruction step includes:
A process of preferentially changing a clock skew between the first storage element and the second storage element on a signal path having a small margin for a setup time error at a subsequent stage of the clock gating cell is performed. And

  According to the present invention, for example, as the margin for the setup time error of the signal path increases, the number of delay elements to be inserted into the clock line connected to the first storage element on the signal path is set to the clock gating cell. If the number is increased in the subsequent stage, the timing at which the transistors of the clock buffer included in each memory element are switched can be efficiently distributed, so that the peak current can be reduced.

(5) A method for designing an integrated circuit device according to the present invention includes:
The clock tree reconstruction step;
For the synchronous circuit after reconstructing the clock tree by the clock tree restructuring step, performing the actual wiring on the layout;
For the synchronous circuit after reconstructing the clock tree, performing a timing analysis in consideration of actual wiring on the layout;
One or more delay elements are deleted from the clock line connected to the first storage element on the signal path where the setup time error occurs based on the timing analysis result considering the actual wiring on the layout. Modifying the clock tree so as to eliminate the setup time error.

  According to the present invention, when reconstructing the clock tree, it is not necessary to perform actual wiring every time a delay element is inserted, and the process of reconstructing the clock tree can be performed in a shorter time. In addition, the setup time error is eliminated without adding a delay element based on the timing analysis result considering the actual wiring on the layout for the synchronous circuit after the clock tree is reconstructed. There is no need to start over, and setup time errors can be resolved more easily and reliably.

  If a hold time error occurs in the timing analysis result considering the actual wiring on the layout for the synchronous circuit after reconstructing the clock tree, the hold time error can be eliminated by various known methods. it can. For example, by inserting a buffer or the like in the signal path where a hold time error occurs to delay the signal, the hold time error can be easily eliminated without changing the clock line wiring.

(6) A clock tree construction tool according to the present invention includes:
The first storage element having a plurality of storage elements that operate based on the same clock and not including other storage elements on a signal path from the output of the first storage element to the input of the second storage element And the second memory element, the clock tree is constructed so that the clock skew is equal to or less than a predetermined value, and the clock tree is provided to the synchronous circuit in which the clock gating cell is arranged on the clock transmission path. A clock tree construction tool to reconstruct,
When the clock skew between the given first storage element and the second storage element is smaller than a given value and the place where the clock skew is adjusted is after the clock gating cell, When it is determined that a timing error does not occur even if the clock skew is changed in the subsequent stage of the clock gating cell so that the clock skew is equal to or greater than a given value based on the timing analysis result for the synchronous circuit , By inserting one or more delay elements in a clock line connected to the first memory element at a subsequent stage of the clock gating cell, the clock skew is set to a given value or more. A process of changing the clock skew is performed at the subsequent stage of the gating cell. And the clock tree restructuring step to reconstruct the clock tree for the circuit,
For the synchronous circuit after reconstructing the clock tree by the clock tree restructuring step, performing the actual wiring on the layout;
For the synchronous circuit after reconstructing the clock tree, performing a timing analysis in consideration of actual wiring on the layout;
One or more delay elements are deleted from the clock line connected to the first storage element on the signal path where the setup time error occurs based on the timing analysis result considering the actual wiring on the layout. Modifying the clock tree so as to eliminate the setup time error.

  The clock tree construction tool according to the present invention, for example, determines the number of delay elements to be inserted into the clock line connected to the first storage element on the signal path as the margin for the setup time error of the signal path increases. If it is increased, the switching timing of the transistors of the clock buffer included in each memory element can be efficiently distributed, and the clock skew between the first memory element and the second memory element is greater than or equal to a given value. The clock tree can be rebuilt so that Accordingly, the peak current can be reduced, and the voltage drop of the power supply potential when the peak current flows can be reduced, so that malfunction of the circuit can be prevented.

  Since the clock tree construction tool according to the present invention does not perform actual wiring every time a delay element is inserted, the process of reconstructing the clock tree can be performed in a shorter time. In addition, the setup time error is eliminated without adding a delay element based on the timing analysis result considering the actual wiring on the layout for the synchronous circuit after the clock tree is reconstructed. There is no need, and setup time errors can be resolved more easily and reliably.

(7) The present invention
An integrated circuit device characterized by being designed and manufactured using the integrated circuit device design method or clock tree construction tool described above.

(8) The present invention
A microcomputer including the integrated circuit device described above.

(9) The present invention
A microcomputer as described above;
Means for inputting data to be processed by the microcomputer;
And an output means for outputting data processed by the microcomputer.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Integrated Circuit Device, Integrated Circuit Device Design Method, Clock Tree Construction Tool FIG. 1 is a diagram for explaining an example of a synchronous circuit that is a target of the clock tree construction tool of the present embodiment.

  The synchronization circuit 10 is a circuit included in an integrated circuit device (IC) and is a target of the clock tree construction tool of the present embodiment. The synchronization circuit 10 includes sub blocks 100 and 200 and a clock tree 300. Here, each flip-flop included in the synchronization circuit 10 is synchronously controlled by the main clock 312. That is, the synchronization circuit 10 is a synchronization circuit that operates based on the main clock 312 (the same clock).

  The sub block 100 includes three flip-flops 110, 120, and 130 and combinational circuits 140 and 150. One input of the combinational circuit 140 is connected to the output of the flip-flop 110, and the other one input 142 is supplied from the outside of the sub-block 100. The output of the combination circuit 140 is connected to the data input of the flip-flop 120. Further, one input of the combinational circuit 150 is connected to the output of the flip-flop 120, and the other one input is connected to the output of the flip-flop 220 included in the sub-block 200. The output of the combinational circuit 150 is connected to the data input of the flip-flop 130.

  The sub-block 200 includes three flip-flops 210, 220, 230 and combinational circuits 240, 250. One input of the combinational circuit 240 is connected to the output of the flip-flop 110 included in the sub-block 100, and the other one input is connected to the output of the flip-flop 210. The output of the combinational circuit 240 is connected to the data input of the flip-flop 220. Further, one input of the combinational circuit 250 is connected to the output of the flip-flop 220, and the other one input 252 is supplied from the outside of the sub-block 200. The output of the combinational circuit 250 is connected to the data input of the flip-flop 230.

  The clock tree 300 includes clock buffers 320, 330, 340, 350, 370 and a clock gating cell 360. The input of the clock buffer 320 is connected to the output of the clock buffer 350, and the output is commonly connected to the clock inputs 112, 122, 132 of the three flip-flops 110, 120, 130 included in the sub-block 100. Has been. The input of the clock buffer 330 is connected to the output of the clock buffer 350, and its output is connected to the input of the clock buffer 340. The output of the clock buffer 340 is connected in common to the clock inputs 212, 222, and 232 of the three flip-flops 210, 220, and 230 included in the sub-block 200. Here, the delay from the output of the clock buffer 350 to the clock inputs 112, 122, 132, 212, 222, and 232 of the six flip-flops 110, 120, 130, 210, 220, and 230 is aligned, Clock buffers 320, 330, and 340 functioning as delay elements are inserted so that the clock skew between the flip-flops is a predetermined value or less (for example, 0).

  One clock buffer 320 is inserted from the output of the clock buffer 350 to each clock input 112, 122, 132 of the flip-flops 110, 120, 130. On the other hand, two clock buffers 330 and 340 are inserted from the output of the clock buffer 350 to the clock inputs 212, 222, and 232 of the flip-flops 210, 220, and 230. The difference in the number of inserted clock buffers is due to the difference in the distance between the clock buffer 350 and each flip-flop due to the difference in the physical arrangement location of each flip-flop on the layout (not shown). . That is, when the distance between the clock buffer 350 and the flip-flop is long, the parasitic resistance and the parasitic capacitance associated with the clock wiring are large, and the clock line wiring delay is large. Therefore, the number of clock buffers to be inserted is reduced. On the other hand, when the distance between the clock buffer 350 and the flip-flop is short, since the wiring delay is small, the number of clock buffers to be inserted is increased. In this way, the clock tree 300 is configured such that the clock skew between any two flip-flops is a predetermined value or less. For example, when the delays from the input to the output of the clock buffers 320, 330, and 340 are all 1 ns, all the wiring delays from the output of the clock buffer 350 to the clock inputs 112, 122, and 132 of the flip-flops 110, 120, and 130 are all. 1 ns, and the wiring delay from the output of the clock buffer 350 to the clock inputs 212, 222, and 232 of the flip-flops 210, 220, and 230 is all zero, the flip-flops 110, 120, 130, and 210 from the output of the clock buffer 350 are assumed. , 220, and 230, the delays to the clock inputs 112, 122, 132, 212, 222, and 232 are all 2 ns, and the clock skew between any two flip-flops is zero.

  The three flip-flops 110, 120, and 130 included in the sub-block 100 are arranged at physically close locations on the layout, and each clock input 112 of the three flip-flops 110, 120, and 130 is provided from the clock buffer 320. , 122, 132 has almost no difference in the wiring delay (the clock skew between these flip-flops is very small), so that the output of the clock buffer 320 and the clock inputs 112, 122 of the flip-flops 110, 120, 130 132, no clock buffer is inserted. Similarly, since the three flip-flops 210, 220, and 230 included in the sub-block 200 are arranged physically close to each other on the layout, the output of the clock buffer 340 and each of the flip-flops 210, 220, and 230 A clock buffer is not inserted between the clock inputs 212, 222, and 232.

  Here, the delay of the path (signal path) p1 from the output of the flip-flop 110 (corresponding to the first memory element) to the data input of the flip-flop 120 (corresponding to the second memory element) in the combinational circuit 140 is The delay of the path p2 from the output of the flip-flop 120 (corresponding to the first memory element) in the combinational circuit 150 to the data input of the flip-flop 130 (corresponding to the second memory element) is 5.5 ns. The delay of the path p3 from the output of the flip-flop 220 (corresponding to the first memory element) to the data input of the flip-flop 130 (corresponding to the second memory element) is 2 ns, and the flip-flop 110 ( Flip-flop 220 (second storage element) from the output of the first storage element The delay of the path p4 until the data input (corresponding) is 2.5 ns, from the output of the flip-flop 210 (corresponding to the first memory element) to the data input of the flip-flop 220 (corresponding to the second memory element) The path p5 has a delay of 6.5 ns, and the path p6 from the output of the flip-flop 220 (corresponding to the first memory element) in the combinational circuit 250 to the data input of the flip-flop 230 (corresponding to the second memory element). Is assumed to be 7.5 ns. Further, it is assumed that the clock frequency of the main clock 312 is 100 MHz (clock period is 10 ns), the delay of all flip-flops (the time from when the clock is input to when the output changes) is 1 ns, and setup for all flip-flops. It is assumed that the time is 1 ns or more and the hold time is 0 ns or more. Further, the clock skew between all flip-flops (in the following description, a value obtained by subtracting the clock delay to the flip-flop corresponding to the first memory element from the clock delay to the flip-flop corresponding to the second memory element) Define) is assumed to be zero.

  In this case, in order to prevent a setup time error, the delay of the combinational circuit path between all flip-flops is 10 ns (clock cycle) +0 ns (clock skew) -1 ns (flip-flop delay) -1 ns (setup time) ) = 8 ns or less. As described above, the delays of the paths p1 to p6 are 5.5 ns, 6.5 ns, 2 ns, 2.5 ns, 6.5 ns, and 7.5 ns, respectively, so no setup time error has occurred for the paths p1 to p6. . On the other hand, in order to prevent a hold time error, the delay of the combinational circuit path between all flip-flops must be 0 ns (hold time) +0 ns (clock skew) -1 ns (flip-flop delay) = − 1 ns or more. I must. Clearly, no hold time error has occurred with respect to the paths p1 to p6.

  The input of the clock buffer 350 is connected to the clock output of the clock gating cell 360, the clock input of the clock gating cell 360 is connected to the output of the clock buffer 370, and the input of the clock buffer 370 is the main clock. It is connected to the output of the buffer 310. A control signal 362 is supplied from the outside of the clock tree 300 to the control input of the clock gating cell 360. When the control signal 362 is activated (enabled), the clock gating cell 360 supplies the clock signal supplied from the output of the clock buffer 370 to the input of the clock buffer 350, and the control signal 362 is inactive. In the enabled (disabled) state, the clock signal is not supplied to the input of the clock buffer 350. That is, when the control signal 362 is activated (enabled), the clock buffers 320, 330, 340, 350 and the sub-blocks 100, 200 operate, and the control signal 362 is deactivated (disabled). In the state, the clock buffers 320, 330, 340, 350 and the sub-blocks 100, 200 do not operate. Therefore, when the control signal 362 is in an inactive (disabled) state, power consumption can be reduced.

  FIG. 2 is a diagram for explaining an example of the synchronization circuit after the clock tree is reconstructed by using the clock tree construction tool of the prior art (described in Non-Patent Document 1) for the synchronization circuit 10 in FIG. is there. The same components as those in FIG.

  2 differs from the synchronization circuit 10 in FIG. 1 only in that the clock tree 302 includes clock buffers 322, 324, 326, 344, and 372. The synchronization circuit 20 in FIG. The input of the clock buffer 322 is connected to the output of the clock buffer 320, and its output is connected to the clock input 122 of the flip-flop 120. The input of the clock buffer 324 is connected to the output of the clock buffer 320, and the output is connected to the input of the clock buffer 326. The output of the clock buffer 326 is connected to the clock input 112 of the flip-flop 110. The input of the clock buffer 344 is connected to the output of the clock buffer 340, and its output is connected to the clock input 212 of the flip-flop 210. The input of the clock buffer 372 is connected to the output of the clock buffer 370, and its output is connected to the clock input of the clock gating cell 360. The clock buffers 322, 324, 326, 344 and 372 are clock buffers inserted by a conventional clock tree construction tool.

  Here, it is assumed that the delays from the input to the output of the clock buffers 322, 324, 326, 344, and 372 are all 1 ns. In this case, the delay from the output of the clock buffer 350 to the clock input 112 of the flip-flop 110 is increased by the delay of the clock buffers 324 and 326 (1 ns + 1 ns = 2 ns) compared to the case of FIG. Similarly, the delay from the output of the clock buffer 350 to the clock input 122 of the flip-flop 120 is increased by the delay (1 ns) of the clock buffer 322, and the delay from the output of the clock buffer 350 to the clock input 212 of the flip-flop 210 is It is increased by the delay (1 ns) of the clock buffer 344. The delay from the output of the clock buffer 350 to the clock inputs 132, 222, 232 of the flip-flops 130, 220, 230 is the same as in the case of FIG. Therefore, the clock skew between the flip-flops 110 and 120 on the path p1 is −1 ns. Similarly, between flip-flops 120 and 130 on path p2, between flip-flops 220 and 130 on path p3, between flip-flops 110 and 220 on path p4, and flip-flop 210 on path p5. And 220, and the clock skew between the flip-flops 220 and 230 on the path p6 are −1 ns, 0 ns, −2 ns, −1 ns, and 0, respectively. That is, the clock buffers 322, 324, 326, and 344 are inserted by the conventional clock tree construction tool so that the clock skew is different.

  On the other hand, the sub-blocks 100 and 200 are exactly the same as in FIG. 1, and the delays of the paths p1 to p6 are not changed. Since the delay of the path p1 is 5.5 ns and 10 ns (clock cycle) + (− 1 ns) (clock skew) −1 ns (flip-flop delay) −1 ns (setup time) = 7 ns or less, the setup time for the flip-flop 120 No error has occurred. Also, the hold time error for the flip-flop 120 is not generated because 0 ns (hold time) + (− 1 ns) (clock skew) −1 ns (delay of the flip-flop 110) = − 2 ns. Similarly, setup time error and hold time error for flip-flop 130 for paths p2 and p3, setup time error and hold time error for flip-flop 220 for paths p4 and p5, setup time error and hold time for flip-flop 230 for path p6. No error has occurred. That is, since the clock tree construction tool of the present embodiment has inserted the clock buffers 322, 324, 326, 344, and 372, no timing error has occurred in the synchronization circuit 20.

  In FIG. 2, a clock buffer 372 is inserted in front of the clock gating cell 360. Therefore, even when the control signal 362 is in an inactive (disabled) state, the clock buffer 372 operates.

  FIG. 3 is a diagram for explaining an example of the synchronization circuit after the clock tree is reconstructed by using the clock tree construction tool of the present embodiment for the synchronization circuit 10 in FIG. The same components as those in FIG.

  3 is different from the synchronization circuit 10 in FIG. 1 only in that the clock tree 304 includes clock buffers 322, 324, 326, 344, and 364. The synchronization circuit 30 in FIG. The input of the clock buffer 322 is connected to the output of the clock buffer 320, and its output is connected to the clock input 122 of the flip-flop 120. The input of the clock buffer 324 is connected to the output of the clock buffer 320, and the output is connected to the input of the clock buffer 326. The output of the clock buffer 326 is connected to the clock input 112 of the flip-flop 110. The input of the clock buffer 344 is connected to the output of the clock buffer 340, and its output is connected to the clock input 212 of the flip-flop 210. The input of the clock buffer 364 is connected to the output of the clock gating cell 360, and the output is connected to the input of the clock buffer 350. Clock buffers 322, 324, 326, 344, and 364 are clock buffers inserted by the clock tree construction tool of the present embodiment.

  Here, it is assumed that the delays from the input to the output of the clock buffers 322, 324, 326, 344, and 364 are all 1 ns. In this case, the delay from the output of the clock buffer 350 to the clock input 112 of the flip-flop 110 is increased by the delay of the clock buffers 324 and 326 (1 ns + 1 ns = 2 ns) compared to the case of FIG. Similarly, the delay from the output of the clock buffer 350 to the clock input 122 of the flip-flop 120 is increased by the delay (1 ns) of the clock buffer 322, and the delay from the output of the clock buffer 350 to the clock input 212 of the flip-flop 210 is It is increased by the delay (1 ns) of the clock buffer 344. The delay from the output of the clock buffer 350 to the clock inputs 132, 222, 232 of the flip-flops 130, 220, 230 is the same as in the case of FIG. Therefore, the clock skew between the flip-flops 110 and 120 on the path p1 is −1 ns. Similarly, between flip-flops 120 and 130 on path p2, between flip-flops 220 and 130 on path p3, between flip-flops 110 and 220 on path p4, and flip-flop 210 on path p5. And 220, and the clock skew between the flip-flops 220 and 230 on the path p6 are −1 ns, 0 ns, −2 ns, −1 ns, and 0, respectively. In other words, the clock buffers 322, 324, 326, and 344 are inserted by the clock tree construction tool of the present embodiment so that there is a difference in clock skew.

  On the other hand, the sub-blocks 100 and 200 are exactly the same as in FIG. 1, and the delays of the paths p1 to p6 are not changed. Since the delay of the path p1 is 5.5 ns and 10 ns (clock cycle) + (− 1 ns) (clock skew) −1 ns (flip-flop delay) −1 ns (setup time) = 7 ns or less, the setup time for the flip-flop 120 No error has occurred. Also, the hold time error for the flip-flop 120 is not generated because 0 ns (hold time) + (− 1 ns) (clock skew) −1 ns (delay of the flip-flop 110) = − 2 ns. Similarly, setup time error and hold time error for flip-flop 130 for paths p2 and p3, setup time error and hold time error for flip-flop 220 for paths p4 and p5, setup time error and hold time for flip-flop 230 for path p6. No error has occurred. That is, since the clock tree construction tool of the present embodiment has inserted the clock buffers 322, 324, 326, 344, 364, no timing error has occurred in the synchronization circuit 30.

  In 32, a clock buffer 364 is inserted in the subsequent stage of the clock gating cell 360. Therefore, when the control signal 362 is inactive (disabled), the clock buffer 364 does not operate. That is, the power consumption of the synchronization circuit 30 when the control signal 362 is in an inactive (disabled) state is the same as that of the synchronization circuit 20 when the control signal 362 is in an inactive (disabled) state (see FIG. 2). Less power consumption.

  FIG. 4 is a diagram for explaining the timing related to the output of the clock buffer and the clock input of each flip-flop.

  FIG. 4A is a diagram for explaining the timing in the synchronization circuit 10 of FIG. At time T0, the output of the clock buffer 350 rises. The delay from the output of the clock buffer 350 to the clock inputs 112, 122, 132 of the flip-flops 110, 120, 130 corresponds to the sum of the delay (1 ns) from the input to the output of the clock buffer 320 and the wiring delay (1 ns). 2 ns. On the other hand, the delay from the output of the clock buffer 350 to the clock inputs 212, 222, and 232 of the flip-flops 210, 220, and 230 is the delay (1 ns) from the input to the output of the clock buffer 330 and the output from the input of the clock buffer 340. This corresponds to the sum of the delay until 1 ns and the wiring delay (0 ns), which is 2 ns. Therefore, at time T1, the clock inputs 112, 122, 132, 212, 222, and 232 of the flip-flops 110, 120, 130, 210, 220, and 230 are simultaneously started up. This is because the clock tree is constructed so that the clock skew is zero for all flip-flops in the circuit of FIG. Therefore, a large shoot-through current from the power supply to the ground because the transistors in the buffers connected to the clock inputs 112, 122, 132, 212, 222, 232 (not shown, but inside each flip-flop) are switched simultaneously. Flows and the peak current increases, so that a large voltage drop occurs in the power supply potential.

  FIG. 4B is a diagram for explaining the timing in the synchronization circuit 30 of FIG.

  At time T0, the output of the clock buffer 350 rises. The delay from the output of the clock buffer 350 to the clock input 112 of the flip-flop 110 includes the delay from the input to the output of the clock buffer 320 (1 ns), the delay from the input to the output of the clock buffer 324 (1 ns), and the delay of the clock buffer 326. This corresponds to the sum of delay from input to output (1 ns) and wiring delay (1 ns), and is 4 ns. The delay from the output of the clock buffer 350 to the clock input 122 of the flip-flop 120 includes the delay from the input to the output of the clock buffer 320 (1 ns), the delay from the input to the output of the clock buffer 322 (1 ns), and the wiring delay (1 ns). ) And 3 ns. The delay from the output of the clock buffer 350 to the clock input 132 of the flip-flop 130 corresponds to the sum of the delay (1 ns) from the input to the output of the clock buffer 320 and the wiring delay (1 ns), and is 2 ns. On the other hand, the delay from the output of the clock buffer 350 to the clock input 212 of the flip-flop 210 is the delay from the input to the output of the clock buffer 330 (1 ns), the delay from the input to the output of the clock buffer 340 (1 ns), and the clock buffer. This corresponds to the sum of the delay (1 ns) from the input to the output 344 and the wiring delay (0 ns), which is 3 ns. The delay from the output of the clock buffer 350 to the clock inputs 222 and 232 of the flip-flops 220 and 230 is the delay from the input to the output of the clock buffer 330 (1 ns) and the delay from the input to the output of the clock buffer 340 (1 ns). Equivalent to the sum of the wiring delay (0 ns) and 2 ns. Therefore, at time T1, the clock inputs 132, 222, and 232 of the flip-flops 130, 220, and 230 rise simultaneously, and at time T2, the clock inputs 122 and 212 of the flip-flops 120 and 210 rise simultaneously, and at time T3, The clock input 112 of the flip-flop 110 rises. As described above, the rising timing of the clock input of each flip-flop is different from the output of the clock buffer 350 to the clock input of each flip-flop as long as the clock tree construction tool of this embodiment does not cause a timing error. This is because the clock tree is constructed so as to make a difference of 1 ns or more as long as possible. This delay difference is such that the timing of through current distribution is distributed based on the circuit scale, the characteristics of the clock buffer used, etc., the peak current is reduced, and the voltage drop of the power supply potential can be effectively suppressed. Must be set to a given value. For example, due to the relationship between the clock buffer drive capability and the clock wire parasitic resistance / parasitic capacitance, when the rise of the clock buffer output is steep, the time for the through current to flow is short, so even if this given value is small Since the peak current can be reduced, the voltage drop can be effectively suppressed. On the contrary, when the rise of the clock buffer output is slow, the through current flows for a long time. Therefore, if this given value is not large, the peak current cannot be reduced and the voltage drop is effectively suppressed. I can't.

  FIG. 5 is a flowchart for explaining a design method (manufacturing method) of the integrated circuit device according to the present embodiment.

  First, the net list described at the gate level is read, and the physical arrangement (cell arrangement) of each cell is performed (step S10).

  Next, each clock is set such that the difference in delay (clock delay) from the clock root (for example, the output of the buffer to which the clock is input) to the clock input of each flip-flop, that is, the clock skew is equal to or less than a predetermined value. A clock tree is constructed by inserting delay elements such as buffers (or an even number of inverters) into the line (step S12). In the construction of the clock tree, the virtual wiring of each clock line is performed based on the information on the cell arrangement obtained in step S10, and the wiring length, parasitic resistance and parasitic capacitance are taken into consideration. When there are severe restrictions on hold time and setup time for each flip-flop, it is ideal to construct a clock tree so that the clock skew is zero, but there are large restrictions on the types of buffers that can be inserted. When it is necessary to suppress an increase in clock delay, the clock skew may be set to a predetermined value (a value that does not cause a hold time error and a setup time error) or less.

  Next, timing analysis is performed on the circuit after the clock tree is constructed (step S14), and cell arrangement (step S10) and clock tree construction (step S12) are performed until the setup time error and the hold time error are eliminated. Repeatedly (step S16). The synchronization circuit 10 in FIG. 1 may be a circuit in which a clock tree is constructed in steps S10 to S16.

  Next, from this timing analysis result, for all paths, the delay from the clock root to the clock input of the flip-flop (corresponding to the second storage element) that is the end point of the path and the start point of the path from the clock root The difference in delay until the clock input of the flip-flop (corresponding to the first memory element) is calculated as the clock skew for the path (step S18). For example, in FIG. 1, the clock skews for the paths p1 to p6 are all zero. If there are paths that do not need to consider signal propagation delay (dummy paths) or paths that do not need to consider clock skew (clock skew may be large), only paths other than these paths are excluded. What is necessary is just to calculate a clock skew.

  Further, the margin for the setup time error of the flip-flop serving as the end point of the path is calculated as a margin of clock skew for the path (step S18). For example, in FIG. 1, as described above, in order not to cause a setup time error, the delay of each path must be 8 ns or less, whereas the delay of path p1 is 5.5 ns. Is 8 ns−5.5 ns = 2.5 ns. By similar calculations, the clock skew margins for paths p2, p3, p4, p5, and p6 are 1.5 ns, 6 ns, 5.5 ns, 1.5 ns, and 0.5 ns, respectively.

  Next, it is determined whether or not the clock skew calculated in step S18 is smaller than a given value (hereinafter referred to as a determination value) for all paths (step S20). Here, the clock skew between the two flip-flops required to prevent a peak current that causes a voltage drop of the power supply potential to cause a malfunction of the circuit is obtained by calculation or simulation and used as a determination value. For example, in FIG. 1, if the clock skew is 1 ns or more, the determination value is 1 ns if there is an effect of suppressing the voltage drop of the power supply potential. Since the clock skews for the paths p1 to p6 are all 0, they are all smaller than the determination value.

  In step S20, when the clock skew for all paths is larger than the determination value, actual wiring is performed (step S26). On the other hand, if there is a path whose clock skew is smaller than the determination value in step S20, it is determined whether or not the clock skew margin for the path is larger than the difference between the determination value in step S20 and the clock skew of the path. (Step S22). For example, in FIG. 1, the clock skew margin (2.5 ns) of the path p1 is larger than the difference (1 ns) between the determination value (1 ns) and the clock skew (0 ns) of the path p1. Similarly, the margin of clock skew of paths p2, p3, p4, and p5 is larger than the difference between the judgment value and the clock skew of each path. The margin of clock skew of path p6 is 0.5 ns, which is smaller than the difference (1 ns) between the judgment value (1 ns) and the clock skew (0 ns) of path p6.

  In step S22, if the clock skew margin for all paths is smaller than the difference between the judgment value and clock skew in step S20, a slight voltage drop may occur in the power supply potential, but a setup time error occurs. In order to prevent this, the clock skew is not reconstructed and actual wiring is performed (step S26). On the other hand, in step S22, when there is a path whose clock skew margin is greater than the difference between the determination value in step S20 and the clock skew, the location where the clock skew is adjusted is further downstream than the clock gating cell. It is determined whether or not (step S23). If the clock skew is adjusted after the clock gating cell, the clock skew is determined in step S20 in order from the path with the smallest clock skew margin (that is, the margin for the setup time error). By inserting one or more delay elements (such as a buffer or an even number of inverters) in the subsequent stage of the clock gating cell in the clock line connected to the flip-flop that is the starting point of the path Then, the clock tree is reconstructed (step S24). In FIG. 1, paths p6, p2, p5, p1, p4, and p3 are in order of paths with the smallest clock skew margin. First, the margin of the clock skew of the path p6 is 0.5 ns, which is smaller than the difference (1 ns) between the determination value (1 ns) and the clock skew (0 ns) of the path p6, and thus the flip-flop 220 serving as the starting point of the path p6. A clock buffer is not inserted into the clock line connected to. Next, the margin of the clock skew of path p2 is 1.5 ns, which is larger than the difference (1 ns) between the determination value (1 ns) and the clock skew (0 ns) of path p2, so that the flip-flop serving as the starting point of path p2 A delay element of 1 ns to 1.5 ns is inserted into the clock line connected to 220. For example, in FIG. 3, a clock buffer 322 that functions as a 1 ns delay element is inserted. By inserting the clock buffer 322, the clock skew of the path p1 decreases by 1 ns to −1 ns, and the margin of the clock skew increases by 1 ns to 3.5 ns. Next, the margin of the clock skew of path p5 is 1.5 ns, which is larger than the difference (1 ns) between the determination value (1 ns) and the clock skew (0 ns) of path p5, so that the flip-flop serving as the starting point of path p5 A delay element of 1 ns to 1.5 ns is inserted in the clock line connected to 210. For example, in FIG. 3, a clock buffer 344 that functions as a 1 ns delay element is inserted. Next, since the margin of the clock skew of the path p1 is 3.5 ns, which is larger than the difference (2 ns) between the determination value (1 ns) and the clock skew (−1 ns) of the path p1, the flip-flop serving as the starting point of the path p1 A delay element of 2 ns to 3.5 ns is inserted into the clock line connected to the group 110. For example, in FIG. 3, clock buffers 324 and 326 functioning as 1 ns delay elements are inserted. Here, the two clock buffers 324 and 326 are inserted in order to make the clock skew of the path p1 equal to or greater than the determination value (1 ns) in consideration of the clock buffer 322 being inserted first. . By inserting the clock buffers 324 and 326, the clock skew of the path p4 increases by 2 ns to 2 ns, and the margin of the clock skew decreases by 2 ns to 3.5 ns. Next, for the path p4, due to the insertion of the clock buffers 324 and 326, the clock skew of the path p4 is 2 ns, which is equal to or greater than the determination value (1 ns), so the clock connected to the flip-flop 110 that is the starting point of the path p4 No further clock buffers are inserted into the line. Next, the margin of clock skew of path p3 is 6 ns, which is larger than the difference (1 ns) between the judgment value (1 ns) and the clock skew (0 ns) of path p3, but the flip-flop 220 that is the starting point of path p3 When a delay element of 0.5 ns or more is inserted into the connected clock line, a setup time error occurs with respect to the path p6, and therefore no clock buffer is inserted in FIG. A clock buffer 364 is inserted between the clock gating cell 360 and the clock buffer 350 in order to adjust a clock skew between the synchronization circuit 30 and another synchronization circuit (not shown).

  Next, actual wiring is performed on the circuit after the clock tree is reconstructed (step S26), and timing analysis is performed on the circuit after the clock tree is reconstructed in consideration of the actual wiring (step S28). If there is a timing error, the correction of the clock tree (step S32) and the actual wiring (step S26) are repeated by deleting the buffer (or even number of inverters) inserted in step S24 until the error disappears (step S26). Step S30). When there is no timing error, the execution flow ends.

  In the integrated circuit device design method of the present embodiment, the clock tree is constructed in steps S10 to S16 in order to generate the synchronous circuit 10 of FIG. 1, but the integrated circuit device design according to the present invention is designed. In the method, the first memory element includes a plurality of memory elements that operate based on the same clock, and does not include another memory element on a signal path from the output of the first memory element to the input of the second memory element. Steps S10 to S16 can be applied to the synchronous circuit in which the clock tree is constructed so that the clock skew between the second storage element and the second storage element is a predetermined value or less. It is not an indispensable component of the integrated circuit device design method. For example, the integrated circuit device design method according to the present invention can be applied to a synchronous circuit in which a clock tree is configured by hand design.

2. Microcomputer FIG. 6 is an example of a hardware block diagram of the microcomputer of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, a RAM 710, a ROM 720, an MMU 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DRAM controller 570, an interrupt controller 580, a communication control device 590, The bus controller 600, A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 660, prescaler 670, clock stop control circuit 740 and these are connected. A general-purpose bus 680, a dedicated bus 750, etc., and various pins 690, etc. are included.

3. Electronic Device FIG. 7 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 8A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 8B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 8C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the microcomputer of this embodiment into the electronic devices in FIGS. 8A to 8C, an electronic device with low cost and high image processing speed can be provided.

  As electronic devices that can use this embodiment, in addition to those shown in FIGS. 8A, 8B, and 8C, a portable information terminal, a pager, an electronic desk calculator, a device including a touch panel, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, in the above embodiment, the case where the clock tree is reconstructed in the order of the paths with the smallest clock skew margin (in the order of the paths with the smallest margin for the setup time error) has been described as an example. Absent. The clock tree may be reconstructed in order of paths with a large margin of clock skew or randomly. Alternatively, every time a delay element is inserted into the clock line, the clock skew margin of the associated path may be recalculated to dynamically change the order of the paths with the small clock skew margin.

  In the above embodiment, the case where the delay of the delay element is not inserted has been described as an example when the clock skew margin is small and the clock skew cannot be made larger than a given value (determination value). Not limited to this. In order to increase the clock skew as much as possible, a delay element may be inserted as much as possible within a range not exceeding the margin of the clock skew.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

The figure for demonstrating the example of the synchronous circuit used as the object of the clock tree structure tool of this Embodiment. The figure for demonstrating the example of the synchronous circuit after reconstructing a clock tree using the clock tree construction tool of a prior art. The figure for demonstrating the example of the synchronous circuit after reconstructing a clock tree using the clock tree construction tool of this Embodiment. FIG. 4A is a diagram for explaining timings related to the output of the main clock buffer and the clock input of each flip-flop in the synchronous circuit that is the target of the clock tree configuration tool of the present embodiment. () Is a figure for demonstrating the timing regarding the output of the main clock buffer in the synchronous circuit after reconstructing a clock tree using the clock tree construction tool of this Embodiment, and the clock input of each flip-flop. FIG. 5 is a flowchart for explaining a design method (manufacturing method) of the integrated circuit according to the present embodiment. It is an example of the hardware block diagram of the microcomputer of this Embodiment. An example of a block diagram of an electronic device including a microcomputer is shown. 8A, 8B, and 8C are examples of external views of various electronic devices.

Explanation of symbols

10 synchronization circuit, 20 synchronization circuit, 30 synchronization circuit, 100 sub-block A, 110 flip-flop, 112 clock input, 120 flip-flop, 122 clock input, 130 flip-flop, 132 clock input, 140 combinational circuit, 142 external input, 150 Combinational circuit, 200 sub-block B, 210 flip-flop, 212 clock input, 220 flip-flop, 222 clock input, 230 flip-flop, 232 clock input, 240 combinational circuit, 250 combinational circuit, 252 external input, 300 clock tree, 302 clock Tree, 304 clock tree, 310 main clock buffer, 312 main clock, 320-344, 350, 362370, 372 clock buffer 360 clock gating cell, 362 control signal input, 510 CPU, 520 cache memory, 530 LCD controller, 540 reset circuit, 550 programmable timer, 560 real-time clock (RTC), 570 DMA controller / bus I / F, 580 interrupt controller 590 Communication control circuit (serial interface), 600 bus controller, 610 A / D converter, 620 D / A converter, 630 input port, 640 output port, 650 I / O port, 660 clock generator (PLL), 670 Prescaler, 680 General purpose bus, 690 Various pins, 700 Microcomputer, 710 ROM, 720 RAM, 730 MMU, 740 Clock stop control circuit, 750 Dedicated bus, 800 Device, 810 microcomputer (ASIC), 820 input unit, 830 memory, 840 power generation unit 850 LCD, 860 sound output unit, 950 mobile phone, 952 dial button, 954 LCD, 956 speaker, 960 portable game device, 962 operation Button, 964 Cross key, 966 LCD, 968 Speaker, 970 Personal computer, 972 Keyboard, 974 LCD, 976 Sound output section

Claims (9)

The first storage element having a plurality of storage elements that operate based on the same clock and not including other storage elements on a signal path from the output of the first storage element to the input of the second storage element And an integrated circuit device including a synchronization circuit in which a clock tree is constructed such that a clock skew between the second storage element and the second storage element is less than or equal to a predetermined value and a clock gating cell is disposed on a clock transmission path A design method,
When the clock skew between the given first storage element and the second storage element is smaller than a given value and the place where the clock skew is adjusted is after the clock gating cell, Based on a timing analysis result for the synchronization circuit, a process for changing the clock skew in a subsequent stage of the clock gating cell so that the clock skew is equal to or greater than a given value is performed. A design method of an integrated circuit device, comprising a clock tree restructuring step of restructuring a tree. In claim 1,
The clock tree reconstruction step includes:
A design method of an integrated circuit device, characterized in that, when it is determined that a timing error occurs by changing the clock skew based on a timing analysis result for the synchronous circuit, a process for changing the clock skew is not performed. In claim 1 or 2,
The clock tree reconstruction step includes:
An integrated circuit device that performs processing for changing the clock skew by inserting one or more delay elements into a clock line connected to the first memory element at a subsequent stage of the clock gating cell. Design method. In any one of Claims 1 thru | or 3,
The clock tree reconstruction step includes:
A process of preferentially changing a clock skew between the first storage element and the second storage element on a signal path having a small margin for a setup time error at a subsequent stage of the clock gating cell is performed. A method for designing an integrated circuit device. In any one of Claims 1 thru | or 4,
The clock tree reconstruction step;
For the synchronous circuit after reconstructing the clock tree by the clock tree restructuring step, performing the actual wiring on the layout;
For the synchronous circuit after reconstructing the clock tree, performing a timing analysis in consideration of actual wiring on the layout;
One or more delay elements are deleted from the clock line connected to the first storage element on the signal path where the setup time error occurs based on the timing analysis result considering the actual wiring on the layout. Modifying the clock tree so as to eliminate the setup time error, thereby designing the integrated circuit device. The first storage element having a plurality of storage elements that operate based on the same clock and not including other storage elements on a signal path from the output of the first storage element to the input of the second storage element And the second memory element, the clock tree is constructed so that the clock skew is equal to or less than a predetermined value, and the clock tree is provided to the synchronous circuit in which the clock gating cell is arranged on the clock transmission path. A clock tree construction tool to reconstruct,
When the clock skew between the given first storage element and the second storage element is smaller than a given value and the place where the clock skew is adjusted is after the clock gating cell, When it is determined that a timing error does not occur even if the clock skew is changed in the subsequent stage of the clock gating cell so that the clock skew is equal to or greater than a given value based on the timing analysis result for the synchronous circuit , By inserting one or more delay elements in a clock line connected to the first memory element at a subsequent stage of the clock gating cell, the clock skew is set to a given value or more. A process of changing the clock skew is performed at the subsequent stage of the gating cell. And the clock tree restructuring step to reconstruct the clock tree for the circuit,
For the synchronous circuit after reconstructing the clock tree by the clock tree restructuring step, performing the actual wiring on the layout;
For the synchronous circuit after reconstructing the clock tree, performing a timing analysis in consideration of actual wiring on the layout;
One or more delay elements are deleted from the clock line connected to the first storage element on the signal path where the setup time error occurs based on the timing analysis result considering the actual wiring on the layout. And modifying the clock tree to eliminate setup time errors.   An integrated circuit device designed and manufactured using the integrated circuit device design method according to claim 1 or the clock tree construction tool according to claim 6.   A microcomputer comprising the integrated circuit device according to claim 7. A microcomputer according to claim 8;
Means for inputting data to be processed by the microcomputer;
An electronic device comprising: output means for outputting data processed by the microcomputer.

Images