JP2013036960A - Delay scan test method, semiconductor device, and semiconductor device design method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem with a conventional scan test method, in which a semiconductor device having a high operation clock frequency cannot be tested with power supply voltage fluctuations suppressed.SOLUTION: The scan test method of the present invention includes the steps of: inputting a clock signal SCLK to scan flip-flops 21-2n to set a first test pattern to the scan flip-flops 21-2n; inputting a clock signal RCLK having a higher frequency than the clock signal SCLK to the scan flip-flops 21-2n and performing control so as to set the scan flip-flops 21-2n to a hold mode in which retained values are held regardless of the clock signal RCLK, and releasing the hold mode and performing control so as to set the scan flop-flops 21-2n to a test result acquisition mode in which the retained values are updated according to the output of a test target circuit; and updating the values, which are retained by the scan flip-flops 21-2n, by using two pulses of the clock signal RCLK in the test result acquisition mode.

Description

  The present invention relates to a delay scan test method, a semiconductor device, and a semiconductor device design method, and more particularly to a delay scan test method for testing a delay time of a circuit in a semiconductor device, a semiconductor device including a test circuit for performing a delay scan test, and a semiconductor device. It relates to the design method.

  In recent years, in semiconductor devices, in order to increase the reliability of circuit operation, a delay failure of a circuit whose operation cannot be observed directly from the outside is tested by a scan test. An example of this scan test is disclosed in Patent Document 1.

  In Patent Document 1, when a delay fault test is performed on a plurality of clock domains operating with an asynchronous operation clock, one shift mode is performed for a scan flip-flop provided corresponding to each of the plurality of clock domains. Set test patterns in a batch using. In Patent Document 1, a set of a launch clock and a capture clock is sequentially input for each clock domain in one launch-capture period. Thus, in Patent Document 1, the test time of the delay fault test for a plurality of clock domains is shortened.

  However, in the scan test, the launch clock and the capture clock are generally clock signals that are faster than the shift clock used in the shift mode. For this reason, when a launch clock and a capture clock are input, the power supply voltage of the semiconductor device to be tested drops due to the high-speed clock signal. When such a power supply voltage drop occurs, the delay time of the circuit under test becomes longer than the original delay time due to the influence of the power supply voltage drop, and there is a problem that erroneous determination of the test result occurs.

  In Patent Document 1, the launch clock and the capture clock are input at different timings for each clock domain. Even in such a case, a power supply voltage drop occurs due to at least the launch clock and the capture clock that are input first. .

  Therefore, Patent Document 2 discloses a technique for preventing a drop in power supply voltage due to an increase in the frequency of a clock signal. In Patent Document 2, when a clock signal is supplied to a semiconductor device, the frequency of the clock signal is gradually increased or decreased to suppress fluctuations in the power supply voltage due to a sudden change in the frequency of the clock signal.

JP 2008-275480 A JP-A-2005-249526

  However, when the technique of Patent Document 2 is applied to the scan test, the frequency of the shift clock signal used in the shift mode is gradually increased using the technique of Patent Document 2, and then the launch clock and the capture clock are input. Need to transition to capture mode. In this case, it is necessary to make the frequency of the shift clock signal in the state immediately before shifting to the capture mode substantially equal to the frequency of the launch clock and the capture clock. When the shift clock signal is controlled as described above, there is a problem that the timing constraint between the scan flip-flops constituting the scan chain becomes severe and the design becomes difficult.

  Here, the launch clock and the capture clock are set to a frequency equal to or higher than the frequency of the operation clock of the semiconductor device. For this reason, the problem of the timing constraint between the scan flip-flops becomes more remarkable as the frequency of the operation clock of the semiconductor device is improved.

  A delay scan test method for a semiconductor device according to the present invention includes a test target circuit, a plurality of cascade-connected scan flip-flops, and a clock buffer group provided in a clock distribution path to the plurality of scan flip-flops. A method for delay scan testing of a semiconductor device for testing the test target circuit with the plurality of scan flip-flops, wherein a first clock signal is input to the plurality of scan flip-flops and input to the test target circuit. A first test pattern is set in the plurality of scan flip-flops, a second clock signal having a higher frequency than the first clock signal is input to the plurality of scan flip-flops, and the plurality of scan flip-flops Is held regardless of the second clock signal Control to a hold mode to be maintained, release the hold mode, and control to a test result acquisition mode for updating a value to hold the plurality of scan flip-flops in accordance with the output of the test target circuit, the test result acquisition mode 2 to update values held in the plurality of scan flip-flops using two pulses of the second clock signal, and after releasing the test result acquisition mode, the first clock signal is changed to the plurality of scan flip-flops. And the values held in the plurality of scan flip-flops are externally output as test results.

  One aspect of a semiconductor device according to the present invention includes: a test target circuit; a plurality of scan flip-flops that test and test-connect the test target circuit; and a clock provided in a clock distribution path to the plurality of scan flips A plurality of scan flip-flops, each of which updates a value held in accordance with an input clock signal and updates a value held in an externally input test mode. A basic scan flip-flop that is switched according to a logic level of a scan mode control signal, and a capture mode that updates a value held in accordance with a value output from the test target circuit, When the capture enable signal is enabled A hold circuit that updates a value held by the basic scan flip-flop and maintains a value held by the basic scan flip-flop when the capture enable signal is in a disenable state, and the basic scan flip-flop Two continuous clock pulses included in the clock signal are input to the group during a period when the capture enable signal is in the enabled state.

  One aspect of a semiconductor device design method according to the present invention is a semiconductor device design method comprising: a test target circuit; and a plurality of scan flip-flops that are cascade-connected to test the test target circuit. Whether the first netlist including the circuit including the test target circuit is read, and the value held in accordance with the value of the scan mode control signal is updated at the position corresponding to the test target circuit by the output of the preceding scan flip-flop Net information of the plurality of basic scan flip-flops that switches whether to update according to the output of the test target circuit is generated, and each of the plurality of basic scan flip-flops corresponds to the plurality of basic scan flip-flops according to a capture enable signal. Switch between updating or maintaining the value held by the basic scan flip-flop Scan mode control for generating net information of a yield circuit and instructing whether the values held by the plurality of basic scan flip-flops are updated by the output of the preceding scan flip-flop or according to the output of the circuit under test Net information of a scan control circuit that switches between enabling and disabling the capture enable signal according to a signal and a clock signal applied to the plurality of scan flip-flops; The second netlist is generated by adding the net information of the plurality of basic scan flip-flops, the net information of the hold circuit, and the net information of the scan control circuit.

  According to the delay scan test method for a semiconductor device according to the present invention, before a high-speed two-pulse second clock signal (for example, a launch clock and a capture clock) used for a delay test is input to the scan flip-flop. The second clock signal is input to the scan flip-flop while maintaining the held value. Thus, the delay scan test can be performed after setting the power supply voltage of the semiconductor device to an appropriate voltage in a state where the second clock signal is input. Further, according to the semiconductor device and the semiconductor device design method according to the present invention, a semiconductor device capable of executing the delayed scan test method can be provided.

  According to the delay scan test method, the semiconductor device, and the semiconductor device design method according to the present invention, it is possible to suppress fluctuations in the power supply voltage during the delay scan test.

1 is a block diagram of a semiconductor device according to a first embodiment; FIG. 2 is a block diagram of a scan flip-flop and a test control circuit according to the first exemplary embodiment. 3 is a timing chart showing a procedure of a test method for the semiconductor device according to the first embodiment; FIG. 6 is a block diagram of a scan flip-flop and a test control circuit according to a second embodiment. 6 is a timing chart illustrating a procedure of a test method for a semiconductor device according to a second embodiment; FIG. 6 is a block diagram of a semiconductor device according to a third embodiment. 10 is a design support apparatus for a semiconductor device according to a fourth embodiment; 10 is a flowchart of a semiconductor device design method according to a fourth embodiment;

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of the semiconductor device 1 according to the first embodiment. As shown in FIG. 1, the semiconductor device 1 includes combinational circuits 11a to 11c, a test control circuit 12, and a test circuit 20. The combinational circuits 11a to 11c are examples of test target circuits.

  The test control circuit 12 switches the frequency of the clock signal CLK applied to the test circuit 20 and the state of the capture enable signal CEN according to the operation mode. The test control circuit 12 includes a clock control circuit 13 and a capture control circuit 16. The clock signal CLK supplied to the test circuit 20 in response to the clock control circuit 13 and the scan mode control signal SMC is the first clock signal (for example, the shift clock SCLK) or the second clock signal (real-time clock RCLK). Switch between. The capture control circuit 16 also generates a capture enable signal CEN that controls the timing at which the scan flip-flop performs a capture operation based on the scan mode control signal SMC and the clock signal CLK. Details of the clock control circuit 13 and the capture control circuit 16 will be described later.

  The test circuit 20 receives the scan mode control signal SMC, the capture enable signal CEN, the clock signal CLK, and the test pattern SIN, and performs a test on the test target circuit. More specifically, when the scan mode control signal SMC indicates the shift mode (for example, high level), the test circuit 20 applies the test pattern SIN input from the outside to a plurality of scan flip-flops in the test circuit. Set. In addition, when the scan mode control signal SMC indicates the capture mode (for example, low level), the test circuit 20 performs a delayed scan test using a test value based on the test pattern SIN held in the test circuit 20. Here, the test circuit 20 according to the first embodiment has a hold mode and a test result acquisition mode as operation modes when the scan mode control signal SMC is in the capture mode. The test circuit 20 enters the hold mode if the capture enable signal CEN output from the capture control circuit 16 is disabled, and enters the test result acquisition mode if it is enabled. In the hold mode, the value held in the scan flip-flop is maintained regardless of the clock signal CLK input to the scan flip-flop. In the test result acquisition mode, the value held in the scan flip-flop is updated with the value output from the combinational circuit in accordance with the clock signal CLK input to the scan flip-flop.

  Here, a detailed configuration of the test circuit 20 will be described. As shown in FIG. 1, the test circuit 20 includes scan flip-flops 21 to 2n (n is an integer, the same applies hereinafter) and clock buffer groups 31 to 3n. The clock buffer groups 31 to 3n are provided for controlling the timing at which the clock signal CLK reaches the scan flip-flops 21 to 2n. The number of clock buffers included in the clock buffer groups 31 to 3n and The arrangement is appropriately set at the time of design.

  The scan flip-flops 21 to 2n receive the scan mode control signal SMC, the capture enable signal CEN, the clock signal CLK, the test pattern SIN, and the data input signal DIN, respectively, and output the output signal Q. In the following description, the input terminal to which the scan mode control signal SMC is input is the scan mode control signal input terminal SMC, the input terminal to which the capture enable signal CEN is input is the capture enable signal input terminal CEN, and the clock signal CLK is input. The input terminal is the clock input terminal CLK, the input terminal to which the test pattern SIN is input is the test pattern input terminal SIN, the input terminal to which the data input signal DIN is input is the data input terminal DIN, and the output terminal to which the output signal Q is output It is called output terminal Q.

  The scan flip-flops 21 to 2n synchronize the test value based on the test pattern SIN with the clock signal CLK when the scan mode control signal SMC is in a state (for example, high level) indicating the first mode (for example, shift mode). And output from the output terminal Q. Further, when the scan mode control signal SMC is in a state (for example, low level) indicating the second mode (for example, capture mode), the scan flip-flops 21 to 2n receive a test value based on the data input signal DIN as a clock signal. It is held in synchronization with CLK and output as an output signal Q. Furthermore, when the capture enable signal CEN is in a disable state (for example, low level), the scan flip-flops 21 to 2n maintain the value held at that time.

  The scan flip-flops 21 to 2n are cascade-connected to form a scan chain circuit. More specifically, the scan flip-flop is input such that the test pattern input terminal SIN is connected to the output terminal Q of the scan flip-flop disposed in the preceding stage. The data input terminals DIN of the scan flip-flops 21 to 2n are connected to one of the combinational circuits 11a and 11b. The output terminals Q of the scan flip-flops 21 to 2n are connected to the test pattern input terminals SIN and the combinational circuits 11b and 11c of the scan flip-flops 21 to 2n arranged in the subsequent stage. Note that the test pattern input terminal SIN of the scan flip-flop 21 arranged in the first stage of the scan chain circuit is supplied with the test pattern SIN from the outside. Further, the output terminal Q of the scan flip-flop 2n arranged at the last stage of the scan chain circuit outputs a test result signal from the output terminal SOUT to the outside.

  The scan flip-flops 21 to 2n according to the first embodiment have a configuration different from that of a general scan flip-flop. Specifically, the scan flip-flops 21 to 2n have a configuration capable of switching whether to update or maintain the value held in accordance with the capture enable signal CEN as one of the features. Therefore, the configuration of the scan flip-flops 21 to 2n will be described in detail. Since the scan flip-flops 21 to 2n have the same configuration, in the following description, the scan flip-flop according to the first embodiment will be described using the scan flip-flop 21 as an example. The detailed configuration of the test control circuit 12 that controls the scan flip-flops 21 to 2n will also be described together with the scan flip-flop 21.

  A detailed block diagram of the scan flip-flop 21 and the test control circuit 12 is shown in FIG. As shown in FIG. 2, the scan flip-flop 21 has a hold circuit 50 in the basic scan flip-flop 40. The hold circuit 50 prevents the value held in the basic scan flip-flop 40 from being updated according to the input clock signal CLK when the capture enable signal CEN is in a disable state (for example, 0). To do. On the other hand, when the capture enable signal CEN is in an enabled state (for example, 1), the hold circuit 50 is updated according to the clock signal CLK to which the value held in the basic scan flip-flop 40 is input. Allow.

  The basic scan flip-flop 40 includes a flip-flop circuit 41 and a first selector 42. The flip-flop circuit 41 has a clock input terminal, a hold value input terminal D, and an output terminal Q. The flip-flop circuit 41 holds a test value based on a signal applied to the hold value input terminal D in accordance with the clock signal CLK. In the first selector 42, the test pattern SIN is given to a first input terminal (a terminal selected when the scan mode control signal SMC indicates a shift mode (eg, 1)), and the second selector 42 of the hold circuit 50 is supplied. The output value of the selector 51 is supplied to the second input terminal (selected when the scan mode control signal SMC indicates the capture mode (eg, 0)). Then, the first selector 42 switches the value given to the hold value input terminal D of the flip-flop circuit 41 according to the value of the scan mode control signal SMC.

  The hold circuit 50 includes a second selector 51. The second selector 51 receives the output value (for example, the data input signal DIN) of the circuit to be tested and the output value of the flip-flop circuit 41, and the first selector 42 according to the state of the capture enable signal CEN. The signal applied to the second input terminal is switched. More specifically, when the capture enable signal CEN is in a disabled state (for example, 0), the second selector 51 sends the output value of the flip-flop circuit 41 to the second input terminal of the first selector 42. give. When the capture enable signal CEN is in an enabled state (for example, 1), the second selector 51 supplies the data input signal DIN to the second input terminal of the first selector 42.

  As shown in FIG. 2, the test control circuit 12 includes a clock control circuit 13 and a capture control circuit 16. The clock control circuit 13 includes a PLL circuit 14 and a selector 15. The PLL circuit 14 multiplies a reference clock REFC input from the outside to generate a second clock signal (for example, a real time clock RCLK). The selector 15 selects one of the shift clock SCLK and the real time clock RCLK according to the scan mode control signal SMC, and outputs the selected signal as the clock signal CLK. More specifically, the selector 15 outputs the shift clock SCLK as the clock signal CLK when the scan mode control signal SMC indicates the shift mode (for example, 1). The selector 15 outputs the real-time clock RCLK as the clock signal CLK when the scan mode control signal SMC indicates the capture mode (for example, 0). The real-time clock RCLK is a launch clock used in the scan test. This is a clock signal having the same frequency as that of the capture clock.

  The capture control circuit 16 generates a capture enable signal CEN that controls the timing at which the scan flip-flop performs a capture operation based on the scan mode control signal SMC and the clock signal CLK. The capture control circuit 16 includes a gating circuit (for example, an AND circuit 17) and a counter 18. One input terminal of the AND circuit 17 is a normal input terminal. The clock signal CLK is input to the normal input terminal. The other input terminal of the AND circuit 17 is an inverting input terminal. A scan mode control signal SMC is input to the inverting input terminal. The AND circuit 17 outputs a logical product operation result of the inverted logic of the scan mode control signal SMC and the clock signal CLK. That is, the AND circuit 17 prevents the clock signal CLK from being transmitted to the subsequent circuit (for example, the counter 18) when the scan mode control signal SMC indicates the shift mode (for example, 1). On the other hand, when the scan mode control signal SMC indicates the capture mode (for example, 0), the AND circuit 17 transmits the clock signal CLK to the subsequent circuit (for example, the counter 18).

  The counter 18 counts the number of clocks of the clock signal CLK input via the AND circuit 17. The counter 18 has a predetermined value (for example, a capture determination value) in a setting register (not shown). Then, the counter 18 switches the capture enable signal CEN from the disabled state to the enabled state in response to the number of clocks of the clock signal CLK reaching the capture determination value. Then, the counter 18 switches the capture enable signal CEN from the enabled state to the disabled state when the count value advances two more. This is because the semiconductor device 1 according to the first embodiment requires two clock pulses of the launch clock pulse and the capture clock pulse during the period when the capture enable signal CEN is enabled. The counter 18 preferably resets the count value in response to the capture enable signal CEN being switched from the enabled state to the disabled state.

  Next, a test method for the semiconductor device 1 according to the first embodiment will be described. First, FIG. 3 shows a timing chart showing the procedure of the test method for the semiconductor device 1 according to the first embodiment. The test method for the semiconductor device 1 is called a delayed scan test. As shown in FIG. 3, in the test of the semiconductor device 1, first, the scan mode control signal SMC is set to the shift mode (for example, 1). In the shift mode, the test pattern SIN is input to the built-in scan flip-flops 21 to 2n in synchronization with the first clock signal (for example, the shift clock SCLK). Here, in the semiconductor device 1 according to the first embodiment, the test pattern SIN input to the scan flip-flops 21 to 2n is once input to the test target circuit in the shift mode, and the test target circuit is output based on the test pattern SIN. The delayed scan test is executed based on the output value. Therefore, the test pattern SIN input to the scan flip-flops 21 to 2n in the shift mode is hereinafter referred to as a first test pattern, and the output value generated by the circuit under test based on the first test pattern is the second test pattern. This is called a pattern. Further, the shift clock SCLK used in the shift mode is a clock signal having a low frequency as well as the real time clock RCLK used in the capture mode.

  Subsequently, in the delayed scan test method according to the first embodiment, the scan mode control signal SMC is set to the capture mode (for example, 0). Then, in response to setting the scan mode control signal SMC to the capture mode, the clock control circuit 13 switches the output clock signal CLK from the shift clock SCLK to the real time clock RCLK. Further, in response to the scan mode control signal SMC being set to the capture mode, the real time clock RCLK is input to the counter 18 via the AND circuit 17. The counter 18 disables the capture enable signal CEN for a period until the number of clocks of the real-time clock RCLK reaches the capture determination value (for example, 0). Here, the operation mode of the semiconductor device 1 during the period in which the capture enable signal CEN is in the disable state is referred to as a hold mode. In the hold mode, the first selector 42 of the scan flip-flops 21 to 2n selects the output value of the second selector 51 according to the value of the scan mode control signal SMC. In the hold mode, the second selectors 51 of the scan flip-flops 21 to 2n output the output value of the flip-flop circuit 41 according to the value of the capture enable signal CEN. Therefore, in the hold mode, the scan flip-flops 21 to 2n maintain the value held at the time of shifting to the capture mode and output the first test pattern to the test target circuit. Then, the test target circuit generates a second test pattern based on the first test pattern. In the hold mode, the real time clock RCLK is input to the clock buffer groups 31 to 3n. Therefore, in the hold mode, the clock buffer groups 31 to 3n are in an operating state, and the current consumption of the semiconductor device 1 increases. A power supply circuit (not shown) that supplies a power supply voltage to the semiconductor device 1 increases the current supply capability so as to suppress fluctuations in the power supply voltage due to the increased power consumption.

  Subsequently, when the count value of the counter 18 reaches the capture determination value, the counter 18 switches the capture enable signal CEN from the disabled state to the enabled state (for example, 1). Thereby, the semiconductor device 1 switches the operation mode to the test result acquisition mode. In this test result acquisition mode, the first selectors 42 of the scan flip-flops 21 to 2n select the output value of the second selector 51 according to the value of the scan mode control signal SMC. In the test result acquisition mode, the second selectors 51 of the scan flip-flops 21 to 2n output the output value of the test target circuit according to the value of the capture enable signal CEN. Thus, in the test result acquisition mode, the scan flip-flops 21 to 2n are in a state of updating the value held in synchronization with the real-time clock RCLK with the output value of the test target circuit. The test result acquisition mode is continued until the real-time clock RCLK is further input to the counter 18 by two clock pulses. At this time, of the two clock pulses, the first clock pulse input after the end of the hold mode is referred to as a launch clock pulse, and the second clock pulse is referred to as a capture clock pulse. In the semiconductor device 1, the launch clock pulse is input to the scan flip-flops 21 to 2n, thereby updating the values held by the scan flip-flops 21 to 2n with the second test pattern output from the test target circuit. Further, the semiconductor device 1 outputs the second test pattern, which is the retained value of the updated scan flip-flops 21 to 2n, to the test target circuit. Next, when the capture clock pulse is input to the scan flip-flops 21 to 2n, the scan flip-flops 21 to 2n acquire the output value output from the test target circuit based on the second test pattern as a test result.

  At this time, the period of the launch clock pulse and the capture clock pulse is set shorter than the maximum allowable delay time allowed for the circuit under test. That is, when the test result acquired by the capture clock pulse is a value different from a predetermined value, it can be determined that the delay time of the test target circuit does not satisfy the regulation.

  Subsequently, when a capture clock pulse is input, the counter 18 switches the capture enable signal CEN from the enabled state to the disabled state. Then, the scan mode control signal SMC is switched to the shift mode. In this shift mode, by inputting the shift clock SCLK, the test result taken in the scan flip-flop can be taken out from the output terminal SOUT.

  From the above description, the semiconductor device 1 according to the first embodiment includes the scan flip-flops 21 to 2n that test the test target circuit. Each of the scan flip-flops 21 to 2n includes a basic scan flip-flop 40 and a hold circuit 50. The basic scan flip-flop 40 updates the value held in accordance with the input clock signal CLK, and updates the value held by the scan pattern input from the outside, and the value output from the test target circuit. In response to this, the capture mode for updating the held value is switched according to the logic level of the scan mode control signal SMC. In the capture mode, the hold circuit 50 updates the value held by the basic scan flip-flop when the capture enable signal is enabled, and the basic scan flip-flop when the capture enable signal is disabled. Maintain the value to hold. In the semiconductor device 1 according to the first embodiment, the test control circuit inputs two consecutive clock pulses included in the clock signal during the period in which the capture enable signal is enabled to the basic scan flip-flop.

  In the semiconductor device 1 according to the first embodiment, a delay scan test is performed using the scan flip-flops 21 to 2n. In this delayed scan test, first, a first clock pattern (for example, shift clock SCLK) is input to the scan flip-flops 21 to 2n and the first test pattern input to the test target circuit is input to the scan flip-flops 21 to 2n. Set. Subsequently, a second clock signal (for example, real-time clock RCLK) having a frequency higher than that of the shift clock SCLK is input to the scan flip-flops 21 to 2n, and the scan flip-flops 21 to 2n are held regardless of the real-time clock RCLK. Control is made to a hold mode that maintains the value, the hold mode is canceled, and the scan flip-flops 21 to 2n are controlled to a test result acquisition mode that updates the value held in accordance with the output of the circuit under test. The values held in the scan flip-flops 21 to 2n are updated using two pulses of the real-time clock RCLK. Subsequently, after canceling the test result acquisition mode, the shift clock SCLK is input to the scan flip-flops 21 to 2n, and the values held in the scan flip-flops 21 to 2n are externally output as test results.

  In the semiconductor device 1 according to the first embodiment, the delayed scan test is executed using the scan flip-flops 21 to 2n. Thereby, in the semiconductor device 1 according to the first embodiment, even if a large current flows due to the real-time clock during the hold mode, the power supply circuit that supplies the power supply voltage to the semiconductor device reduces the power supply voltage. The power supply capacity can be increased to the extent that it can be maintained. In the test result acquisition mode, a delayed scan test is performed by inputting a launch clock pulse and a capture clock pulse given as a real-time clock while the power supply circuit has a sufficient power supply capability. Thereby, in the semiconductor device 1 according to the first embodiment, it is possible to prevent the power supply voltage from being lowered due to the launch clock pulse and the capture clock pulse, and to improve the accuracy of the delay scan test.

  As another test method of the delayed scan test, there is a method of controlling the semiconductor device 1 to the capture mode only during a period in which the capture clock pulse input during the test result acquisition mode in the present embodiment is input. However, when this other test method is used, the frequency of the scan mode control signal SMC must be increased when the frequency of the real-time clock RCLK increases (or when the maximum delay allowable time of the test target circuit decreases). . However, the scan mode control signal SMC is generally transmitted from the semiconductor tester to the test target semiconductor device 1 via a cable. Therefore, the upper limit of the frequency of the scan mode control signal SMC may be lower than the frequency of the real time clock RCLK. For this reason, when another test method is used, there arises a problem that the frequency of the real-time clock RCLK is limited by the upper limit of the frequency of the scan mode control signal SMC.

  However, in the delayed scan test method according to the first embodiment, during the period in which the semiconductor device 1 is in the capture mode, the hold mode for maintaining the values held by the scan flip-flops 21 to 2n and the test for the test target circuit are performed. There are two operation modes: a test result acquisition mode. In the semiconductor device 1 according to the first embodiment, a plurality of clock pulses of the real time clock RCLK are input during the hold mode, and a launch clock pulse and a capture clock pulse using the real time clock RCLK are input during the test result acquisition mode. To do. That is, in the delayed scan test method according to the first embodiment, a plurality of clock pulses of the real-time clock RCLK are included in the period when the scan mode control signal SMC is in the capture mode. Thereby, in the delayed scan test method according to the first embodiment, the frequency of the real-time clock RCLK can be increased without being limited by the frequency of the scan mode control signal SMC. In addition, since the frequency of the real-time clock RCLK can be increased, the delay scan test of the semiconductor device 1 having a higher operating speed can be executed in the delay scan test method according to the first embodiment.

  In the semiconductor device 1 according to the first embodiment, the state of the capture enable signal CEN that switches between the hold mode and the test result acquisition mode is switched by the counter 18 in the semiconductor device 1 that counts the number of clocks of the real-time clock RCLK. That is, in the semiconductor device 1 according to the first embodiment, the switching timing of the state of the capture enable signal CEN can be adjusted at the design stage of the semiconductor device 1. As a result, the semiconductor device 1 can easily adjust the switching timing of the capture enable signal CEN in response to the increase in the frequency of the real-time clock RCLK without being affected by the test environment such as the performance of the tester of the semiconductor device 1. can do.

Embodiment 2
In the second embodiment, another form of the scan flip-flops 21 to 2n will be described. Therefore, the scan flip-flops 21a to 2na showing other forms of the scan flip-flops 21 to 2n will be described. In the following, since the scan flip-flops 21a to 2na are the same circuit, the configuration of the scan flip-flops 21a to 2na will be described by taking the scan flip-flop 21a as an example.

  In the second embodiment, the configuration of the capture control circuit 16 is changed in accordance with the change in the configuration of the scan flip-flop. Therefore, in the second embodiment, a capture control circuit 16a showing another form of the capture control circuit 16 will be described. In addition, about the same component as Embodiment 1, the same code | symbol as Embodiment 1 is attached | subjected and description is abbreviate | omitted.

  FIG. 4 is a block diagram of the scan flip-flop 21a and the test control circuit 12a according to the second embodiment. Note that the test control circuit 12 a includes a capture control circuit 16 a instead of the capture control circuit 16.

  As shown in FIG. 4, the scan flip-flop 21 a includes a basic scan flip-flop 60 and a hold circuit 70. The hold circuit 70 prevents the value held in the basic scan flip-flop 60 from being updated according to the input clock signal CLK when the capture enable signal CEN is in a disable state (for example, 0). To do. On the other hand, when the capture enable signal CEN is in an enable state (for example, 1), the hold circuit 70 is updated according to the clock signal CLK to which the value held in the basic scan flip-flop 60 is input. Allow.

  The basic scan flip-flop 60 includes a flip-flop circuit 61 and a first selector 62. The flip-flop circuit 61 has a clock input terminal, a hold value input terminal D, and an output terminal Q. The flip-flop circuit 61 receives the clock signal CLK via the hold circuit 70. The flip-flop circuit 61 holds a test value based on a signal applied to the hold value input terminal D in accordance with the edge of the clock signal CLK. In the first selector 62, the test pattern SIN is given to the first input terminal (the terminal selected when the scan mode control signal SMC indicates the shift mode (for example, 1)), and the output value of the test target circuit (For example, the data input signal DIN) is applied to the second input terminal (selected when the scan mode control signal SMC indicates the capture mode (eg, 0)). Then, the first selector 62 switches the value applied to the hold value input terminal D of the flip-flop circuit 61 according to the value of the scan mode control signal SMC.

  The hold circuit 70 has a second selector 71. The second selector 71 receives the clock signal CLK and a fixed value (for example, 0). The second selector 71 switches between supplying and stopping the clock signal CLK to the clock input terminal of the flip-flop circuit 61 according to the state of the capture enable signal CEN. More specifically, when the capture enable signal CEN is in an enabled state (for example, 1), the second selector 71 provides the clock signal CLK to the clock input terminal of the flip-flop circuit 61. When the capture enable signal CEN is in a disable state (for example, 0), the second selector 71 stops supplying the clock signal CLK to the clock input terminal of the flip-flop circuit 61.

  As shown in FIG. 4, the test control circuit 12a includes a clock control circuit 13 and a capture control circuit 16a. Here, since the clock control circuit 13 has the same configuration as that of the first embodiment, description thereof is omitted. The capture control circuit 16a is obtained by adding an OR circuit 19 to the capture control circuit 16 according to the first embodiment. The scan mode control signal SMC is input to one input terminal of the OR circuit 19. The output signal of the counter 18 is input to the other input terminal of the OR circuit 19. Then, the OR circuit 19 outputs the logical sum operation result of the two input signals as the capture enable signal CEN. That is, in the capture control circuit 16a according to the second embodiment, when the scan mode control signal SMC indicates the shift mode (for example, 1), the signal output from the counter 18 (capture enable signal CEN in the first embodiment) The capture enable signal CEN is enabled in either the enabled state or the enabled state.

  Subsequently, a procedure of a delay scan test of the semiconductor device according to the second embodiment using the scan flip-flops 21a to 2na will be described. FIG. 5 is a timing chart showing the procedure of the delay scan test of the semiconductor device according to the second embodiment.

  As shown in FIG. 5, also in the semiconductor device according to the second embodiment, the semiconductor device is controlled to the hold mode and the test result acquisition mode in the capture mode. The control method of the capture enable signal CEN in the hold mode and the test result acquisition mode is the same as that in the first embodiment. On the other hand, the scan flip-flops 21a to 2na must enable the capture enable signal CEN to supply the clock signal CLK while the flip-flop circuit is in the shift mode. Therefore, in the capture control circuit 16a according to the second embodiment, the capture enable signal CEN is enabled (for example, 1) even when the scan mode control signal SMC is in the shift mode. Thereby, in the semiconductor device according to the second embodiment, the clock signal CLK (or the shift clock SCLK) is supplied to the flip-flop circuit 61 even in the shift mode.

  From the above description, the semiconductor device according to the second embodiment has the scan flip-flops 21a to 21na shown in FIG. 4 as the scan flip-flop. However, even when the scan flip-flops 21a to 21na are used, the control in the capture mode can be performed in the same procedure as in the first embodiment. In the shift mode, the same operation as in the first embodiment can be performed by enabling the capture enable signal CEN. In this way, even if the form of the scan flip-flop is changed, if the scan flip-flop can be controlled in the hold mode and the test result acquisition mode in the capture mode, the launch clock pulse and the capture clock pulse are used as in the first embodiment. A highly accurate delayed scan test can be executed by suppressing fluctuations in the power supply voltage. In the delay capture test according to the second embodiment, since the operation in the capture mode is the same as that in the first embodiment, the frequency of the real-time clock RCLK is increased without depending on the test environment as in the first embodiment. be able to.

Embodiment 3
FIG. 6 shows a block diagram of the semiconductor device 3 according to the third embodiment. As shown in FIG. 6, the semiconductor device 3 according to the third embodiment has only the clock control circuit 13 as a test control circuit. In the semiconductor device 3 according to the third embodiment, the capture enable signal CEN is supplied from the outside (for example, a tester).

  As shown in FIG. 3 or FIG. 5, in the delayed scan test method according to the present invention, the capture enable signal CEN only needs to be enabled only during the period when the launch clock pulse and the capture clock pulse are input. That is, in the delayed scan test method according to the present invention, the frequency of the capture enable signal CEN is lower than the frequency of the real-time clock RCLK. For this reason, if the frequency of the capture enable signal CEN can be set to a sufficient speed in a test environment including a tester, the capture control circuit 16 can be omitted. Further, by removing the capture control circuit 16, the chip area of the semiconductor device 3 can be made smaller than the chip area of the semiconductor device 1 of the first embodiment.

Embodiment 4
In the fourth embodiment, a design support apparatus and a design method for designing the semiconductor device described in the first to third embodiments will be described. FIG. 7 is a block diagram of the design support apparatus 4 according to the fourth embodiment.

  As illustrated in FIG. 7, the design support apparatus 4 according to the fourth embodiment includes a calculation unit 80, a storage device 81, a display unit 82, and an operation instruction input unit 83. The arithmetic unit 80 executes a design support program that supports the design of the semiconductor device. The storage device 81 stores various information used for the design support program and circuit design. In the following description, an example will be described in which various information includes circuit design information, first and second netlist circuit libraries, and test pattern information. The display unit 82 displays a user interface screen for operating the design support program. The operation instruction input unit 83 is an apparatus that inputs an operation instruction to the design support program using devices such as a keyboard and a mouse.

  Here, the calculation unit 80 will be described in more detail. The computing unit 80 reads and executes the design support program stored in the storage device 81. Then, the arithmetic unit 80 implements the functions of the logic synthesis unit 84, the test circuit information addition unit 85, and the test circuit information verification unit 86 by executing the design support program. The logic synthesis unit 84 includes a logic synthesis processing unit 90 and a net list generation unit 91. The logic synthesis processing unit 90 reads circuit design information from the storage device 81 and generates a gate level circuit that realizes the operation of the circuit described in the circuit design information. The circuit design information describes the operation of the circuit and is information such as HDL (Hardware Description Language). The net list generation unit 91 generates a first net list describing connection information between gates included in the gate level circuit information generated by the logic synthesis processing unit 90. This first netlist is stored in the storage device 81. Further, since the circuit design information does not include information on the test circuit 20 (for example, DFT (Design For Test) circuit), the first netlist does not include information on the test circuit 20.

  The test circuit information adding unit 85 includes a DFT circuit insertion processing unit 92 and a DFT circuit correction processing unit 93. The DFT circuit insertion processing unit 92 reads the first netlist from the storage device 81. In addition, the DFT circuit insertion processing unit 92 reads out the basic flip-flop circuit library included in the circuit library group from the storage device 81. Then, the DFT circuit insertion processing unit 92 adds the net list information of the basic flip-flop to the test target circuit included in the first net list.

  The DFT circuit correction processing unit 93 reads the circuit library of the selector and the test control circuit included in the circuit library group from the storage device 81. Here, the selector read from the circuit library group is a selector constituting the hold circuit 50 shown in FIG. 2 or the hold circuit 70 shown in FIG. The DFT circuit correction processing unit 93 adds a selector to the basic flip-flop added by the DFT circuit insertion processing unit 92. The DFT circuit correction processing unit 93 adds the circuit library of the test control circuit to the first netlist.

  The test circuit information verification unit 86 includes a test pattern generation unit 94 and a failure detection rate calculation unit 95. The test pattern generation unit 94 generates a test pattern for the semiconductor device generated by the net list generated by the DFT circuit correction processing unit 93. This test pattern is stored in the storage device 81 as test pattern information. The failure detection rate calculation unit 95 reads the test pattern information from the storage device 81 and calculates the failure detection rate based on the test pattern. If the calculated failure detection rate satisfies the standard, the second netlist generated by the DFT circuit correction processing unit 93 is output. This second netlist includes the scan flip-flop shown in FIG. 2 or FIG. 4 and the test control circuit shown in FIG. 2, FIG. 4 or FIG. On the other hand, when the calculated failure detection rate does not satisfy the standard, the DFT circuit insertion processing unit 92 performs test circuit generation processing again.

  Next, a semiconductor device design method using the design support apparatus 4 according to the fourth embodiment will be described. FIG. 8 is a flowchart of a semiconductor device design method according to the fourth embodiment.

  As shown in FIG. 8, in the design method according to the fourth embodiment, first, circuit design information F1 is generated by RTL (Register Transfer Level) design (step S1). Subsequently, the logic synthesis unit 84 performs a logic synthesis process on the circuit design information F1 to generate a first netlist F2 (step S2). Next, the basic scan flip-flop circuit library group F3 is read, and the basic scan flip-flop net information is added to the first netlist F2. (Step S3). Next, the circuit library information of the selector is added to the basic scan flip-flop added to the first netlist F2 in step S3, and the basic scan flip-flop is changed to the scan flip-flop according to the present invention (for example, the scan flip-flop 21, To 21a). Further, a circuit library related to the test control circuit is added to the first netlist in order to control the scan flip-flop according to the present invention (step S4). The circuit library read in steps S3 and S4 is included in the circuit library group F3.

  Next, the failure detection rate of the semiconductor device formed using the net list corrected in step S4 is confirmed (step S5). In step S5, if the failure detection rate does not satisfy the standard, the process returns to step S3 again to review the configuration of the test circuit. On the other hand, if the failure detection rate satisfies the standard in step S5, the net list generated in step S4 is output as the second net list F5. Thereafter, a layout process is performed using the second netlist F5. The semiconductor device according to the above embodiment is formed using the layout information generated in the layout process.

  From the above description, in the design support apparatus and design method for a semiconductor device according to the fourth embodiment, the first netlist F2 including the circuit including the test target circuit is read, and the scan mode control is performed at the position corresponding to the test target circuit. A plurality of basic scan flip-flops (for example, the basic scan flip-flop 40) that switches whether the value held according to the signal value is updated according to the output of the preceding scan flip-flop or according to the output of the circuit under test. Generate net information. Then, for each of the plurality of basic scan flip-flops, the net information of the hold circuit (for example, the selector 51) that switches whether the values held by the plurality of scan flip-flops are updated or maintained according to the capture enable signal CEN. Is generated. A scan mode control signal SMC for instructing whether the values held by the plurality of basic scan flip-flops are updated by the output of the preceding scan flip-flop or according to the output of the circuit under test; and the plurality of scan flip-flops The scan control circuit for switching the enable state or the disable state of the capture enable signal CEN in accordance with the clock signal CLK applied to the scan signal is generated. This information of the scan control circuit is included in the circuit library of the test control circuit. Then, the second netlist is generated by adding the net information of the plurality of basic scan flip-flops, the net information of the hold circuit, and the net information of the scan control circuit to the first netlist F2.

  By performing such a process, the semiconductor device design support apparatus and design method according to the fourth embodiment can form the semiconductor device described in the first to third embodiments. In addition, for the formed semiconductor device, a delayed scan test can be performed on the semiconductor device described in the first to third embodiments.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1, 3 Semiconductor device 4 Design support apparatus 11a-11c Combination circuit 12, 12a Test control circuit 13 Clock control circuit 14 PLL circuit 15 Selector 16, 16a Capture control circuit 17 AND circuit 18 Counter 19 OR circuit 21-2n, 21a Scan flip-flop 20 Test circuits 31 to 3n Clock buffer group 40, 60 Basic scan flip-flop 41, 61 Flip-flop circuit 42, 51, 62, 71 Selector 50, 70 Hold circuit 80 Operation unit 81 Storage device 82 Display unit 83 Operation instruction input unit 84 logic synthesis unit 85 test circuit information addition unit 86 test circuit information verification unit 90 logic synthesis processing unit 91 net list generation unit 92 DFT circuit insertion processing unit 93 DFT circuit correction processing unit 94 test pattern generation unit 95 failure detection rate calculation unit CE N capture enable signal CLK clock signal RCLK real time clock REFC reference clock SCLK shift clock SIN test pattern SMC scan mode control signal

Claims (13)

The circuit under test,
A plurality of scan flip-flops connected in cascade;
A clock buffer group provided in a clock distribution path to the plurality of scan flips,
A delay scan test method for a semiconductor device for testing the test target circuit by the plurality of scan flip-flops,
A first test pattern to be input to the test target circuit by inputting a first clock signal to the plurality of scan flip-flops is set in the plurality of scan flip-flops;
A second clock signal having a frequency higher than that of the first clock signal is input to the plurality of scan flip-flops, and a value that holds the plurality of scan flip-flops regardless of the second clock signal is maintained. Control to hold mode,
Controlling the test result acquisition mode to release the hold mode and update the values held in the plurality of scan flip-flops according to the output of the test target circuit;
Updating the values held in the plurality of scan flip-flops using two pulses of the second clock signal in the test result acquisition mode;
A delayed scan test method in which the first clock signal is input to the plurality of scan flip-flops after the test result acquisition mode is released, and values held in the plurality of scan flip-flops are externally output as test results . A scan mode control signal and a capture enable signal are input to the plurality of scan flip-flops,
By setting the scan mode control signal to the first logic level, the value held in the plurality of scan flip-flops is controlled to a shift mode for transitioning to a scan flip-flop arranged in the next stage,
By setting the scan mode control signal to the second logic level, the value held in the plurality of scan flip-flops is controlled to a capture mode that is updated by an output signal from the test target circuit,
During the capture mode, by disabling the capture enable signal, to control the plurality of scan flip-flops to the hold mode,
The delayed scan test method according to claim 1, wherein the plurality of scan flip-flops are controlled to the test result acquisition mode by setting the capture enable signal in an enable state during the capture mode.   3. The delayed scan test method according to claim 1, wherein the second clock signal is continuously supplied to the plurality of scan flip-flops in the hold mode and the test result acquisition mode. The capture enable signal is
Transition from the disabled state to the enabled state in response to the number of clocks of the second clock signal input after the scan mode control signal reaches the second logic level reaching a predetermined value;
The delayed scan test method according to claim 2, wherein the launch clock and the capture clock are input to the plurality of scan flip-flops after the enable state is entered, and then transition to the disable state.   3. The delayed scan test method according to claim 2, wherein a first test pattern is set in the plurality of scan flip-flops regardless of whether the capture enable signal is enabled or disabled during the shift mode. .   3. The delayed scan test method according to claim 2, wherein the capture enable signal is enabled during the shift mode and a first test pattern is set in the plurality of scan flip-flops. The circuit under test,
A plurality of scan flip-flops that test the test target circuit and are connected in cascade;
A clock buffer group provided in a clock distribution path to the plurality of scan flips,
Each of the plurality of scan flip-flops updates a value to be held in accordance with an input clock signal, and also outputs a shift mode for updating a value to be held by an externally input scan pattern, and the test target circuit outputs A capture mode for updating a value to be held according to a value; a basic scan flip-flop that is switched according to a logic level of a scan mode control signal;
In the capture mode, when the capture enable signal is enabled, the value held by the basic scan flip-flop is updated, and when the capture enable signal is disabled, the basic scan flip-flop holds. A hold circuit for maintaining the value;
A semiconductor device in which two continuous clock pulses included in the clock signal are input to the basic scan flip-flop while the capture enable signal is in an enabled state.   The hold circuit supplies an output value of the basic scan flip-flop to the input of the basic scan flip-flop when the capture enable signal is in a disenable state, and the test target when the capture enable signal is in an enable state. The semiconductor device according to claim 7, further comprising a selector that provides an output value of the circuit to an input of the basic scan flip-flop.   The hold circuit stops the supply of the clock signal to the basic scan flip-flop when the capture enable signal is in the disenable state, and holds the basic scan flip-flop when the capture enable signal is in the enabled state. The semiconductor device according to claim 7, further comprising a selector that supplies the clock signal.   A capture control circuit for switching the capture enable signal from a disabled state to an enabled state in response to the number of clocks of the clock signal input during a period in which the scan mode control signal indicates the capture mode reaching a predetermined value; The semiconductor device according to claim 7, comprising:   The semiconductor device according to claim 10, wherein the capture control circuit enables the capture enable signal during the shift mode. Either a first clock signal input from the outside or a second clock signal having a frequency higher than that of the first clock signal is selected according to the scan mode control signal and output as the clock signal. A clock selector to
The clock selector outputs the first clock signal as the clock signal when the scan mode control signal indicates the shift mode, and the second clock when the scan mode control signal indicates the capture mode. The semiconductor device according to claim 7, wherein a signal is output as the clock signal. The circuit under test,
A test method of a semiconductor device having a plurality of scan flip-flops that test the test target circuit and are connected in cascade,
The first netlist including the circuit including the test target circuit is read, and the value held in accordance with the value of the scan mode control signal is updated at the position corresponding to the test target circuit by the output of the previous scan flip-flop. Or generating net information of the plurality of basic scan flip-flops for switching whether to update according to the output of the circuit under test,
For each of the plurality of basic scan flip-flops, generate net information of a hold circuit that switches whether to update or maintain a value held by the plurality of basic scan flip-flops according to a capture enable signal,
A scan mode control signal for instructing whether values held by the plurality of basic scan flip-flops are updated according to an output of a preceding scan flip-flop or according to an output of the test target circuit; and the plurality of scan flip-flops Generating the net information of the scan control circuit that switches between enabling the clock enable signal and disabling the capture enable signal according to the clock signal applied to
Designing a semiconductor device for generating a second netlist by adding net information of the plurality of basic scan flip-flops, net information of the hold circuit, and net information of the scan control circuit to the first netlist Method.

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