JP2010040549A - Semiconductor wafer and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer capable of highly maintaining flatness of a main surface by a simple process, and to provide a manufacturing method of the semiconductor wafer. <P>SOLUTION: The semiconductor wafer 1 has: a main surface 10, namely a flat surface, and a first chamfering surface 21 formed at a peripheral section 20; and further a second chamfering surface 22 inclined toward the outside in the radial direction of the semiconductor wafer 1 between the main surface 10 and the first chamfering surface 21 when viewing the semiconductor wafer 1 in terms of a section in the thickness direction of the semiconductor wafer 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer and a manufacturing method thereof.

  In a semiconductor wafer (hereinafter, also simply referred to as “wafer”), chamfered surfaces are formed on the peripheral edge portions in order to prevent cracking and chipping. Here, the outer surface (front surface) of the wafer includes a main surface (main surface and back surface) that is a flat surface and a chamfered surface, and the chamfered surface has a predetermined inclination angle with respect to the main surface.

  The chamfered surface is mirror-finished, for example, in a peripheral polishing process. In the outer periphery polishing step, for example, while supplying the polishing liquid to the rotating wafer, the chamfered surface is pressed against the polishing cloth and polished to a mirror surface. At this time, since the chamfered surface has an inclination angle with respect to the main surface, overpolishing may occur where the polishing cloth contacts not only the chamfered surface but also the main surface. As a result, there is a problem that the flatness of the main surface deteriorates.

As a technique for suppressing such overpolishing, for example, after a double-side polishing step, after forming a resin protective film that suppresses polishing on the main surface or main surface and back surface of the wafer, a mirror chamfering step is performed, Thereafter, a technique for removing the protective film made of resin is disclosed (see Patent Document 1).
JP 2006-237055 A

  However, the technique described in Patent Document 1 requires a process of forming a protective film made of resin and a process of removing the protective film made of resin, which increases man-hours and deteriorates throughput. was there.

  Therefore, an object of the present invention is to provide a semiconductor wafer capable of maintaining high flatness of the main surface by a simple process and a method for manufacturing the same.

  (1) The semiconductor wafer of the present invention is a semiconductor wafer having a main surface that is a flat surface and a first chamfered surface formed on a peripheral edge, and when viewed in a cross section in the thickness direction of the semiconductor wafer. A second chamfered surface that is inclined radially outward of the semiconductor wafer is further provided between the main surface and the first chamfered surface.

  (2) The inclination angle of the second chamfered surface with respect to the main surface is 5 to 15 °, and the width of the second chamfered surface along the radial direction of the semiconductor wafer is 50 to 200 μm. preferable.

  (3) The inclination angle of the first chamfered surface with respect to the second chamfered surface is 5 to 25 °, and the width of the first chamfered surface along the radial direction of the semiconductor wafer is 50 to 300 μm. Preferably there is.

  (4) The method for manufacturing a semiconductor wafer according to the present invention is a method for manufacturing the semiconductor wafer, comprising: a first chamfering process for forming the first chamfered surface on the semiconductor wafer; and the first chamfering process. And a second chamfering step of forming a second chamfered surface by removing a part of the peripheral portion including the first chamfered surface.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor wafer which can maintain the flatness of a main surface highly by a simple process and its manufacturing method can be provided.

  Hereinafter, an embodiment of a semiconductor wafer (hereinafter also simply referred to as “wafer”) of the present invention will be described with reference to the drawings. FIG. 1 is a view showing an embodiment of a wafer 1 according to the present invention, where (a) is a perspective view, (b) is a view seen from the thickness direction of the wafer 1, and (c) is a diameter of the wafer 1. It is the figure seen from the direction.

  The wafer 1 of this embodiment is made of, for example, a silicon wafer or a gallium arsenide wafer.

As shown in FIG. 1B, the shape of the wafer 1 viewed in the thickness direction is generally a perfect circle shape, and its diameter is, for example, 200 mm, 300 mm, or 450 mm. Here, the diameter of the wafer 1 is a target value in manufacturing, and includes a predetermined tolerance (allowable error) and the like. The shape of the wafer 1 viewed in the thickness direction may be an elliptical shape.
The thickness t of the wafer 1 is, for example, 725 to 2000 μm, and preferably 925 to 1800 μm.

FIG. 2 is an enlarged view of the portion indicated by the arrow A shown in FIG.
The outer surface (front surface) of the wafer 1 of this embodiment includes a main surface 10 that is a flat surface, a first chamfered surface 21, and a second chamfered surface 22.
The main surface 10 includes a main surface 11 on which various processes are performed and a semiconductor device is formed, and a back surface 12 that is the opposite surface. Since the main surface 11 is a region where a semiconductor device is formed, flatness and reduction of particles are required at a higher level than the back surface 12.
The first chamfered surface 21 and the second chamfered surface 22 are located at the peripheral edge 20. The first chamfered surface 21 is located on the outermost periphery of the peripheral edge portion 20. The second chamfered surface 22 is located between the main surface 10 and the first chamfered surface 21 along the radial direction of the wafer 1.

  The first chamfered surface 21 extends in the radial direction of the wafer 1. The first chamfered surface 21 </ b> A is located on the main surface 11 side with respect to the center line C in the thickness direction of the wafer 1, and And a first chamfered surface 21B located on the 12th side.

  The first chamfered surface 21 is inclined outward in the radial direction of the wafer 1 and toward the center line C. The inclination angle θ1 formed between the tangent line in contact with the first chamfered surface 21A and the second chamfered surface 22A is preferably 5 to 25 °. The same applies to the inclination angle θ1 formed by the tangent line in contact with the first chamfered surface 21B and the second chamfered surface 22B. When the inclination angle θ1 is smaller than 5 °, for example, in the etching process in the device forming process, the cleaning liquid or the rinse liquid containing particles easily adheres to the main surface 10. Further, when the inclination angle θ1 is larger than 25 °, particles are likely to be generated from the interface between the first chamfered surface 21 and the second chamfered surface 22.

  Further, the width W1 of the first chamfered surface 21 along the radial direction of the wafer 1 is preferably 50 to 300 μm. Here, when the width W1 of the first chamfered surface 21 is smaller than 50 μm, the cleaning liquid and the rinse liquid containing particles are likely to adhere to the main surface 10. On the other hand, when the width W1 of the first chamfered surface 21 is larger than 300 μm, there arises a problem that the strength of the peripheral portion 20 is lowered and the peripheral portion 20 is missing.

  The second chamfered surface 22 includes a second chamfered surface 22A located on the main surface 11 side with respect to the center line C, and a second chamfered surface 22B located on the back surface 12 side with respect to the center line C. .

  The second chamfered surface 22 is formed between the main surface 10 and the first chamfered surface 21. The second chamfered surface 22 is inclined outward in the radial direction of the wafer 1 and toward the center line C. The inclination angle θ2 formed between the tangent line in contact with the second chamfered surface 22A and the main surface 11 is preferably 5 to 15 °. The same applies to the inclination angle θ2 formed between the tangent line in contact with the second chamfered surface 22B and the back surface 12. When the inclination angle θ2 is smaller than 5 °, when the second chamfered surface 22 is formed, the polishing cloth comes into contact with the main surface 10 to cause overpolishing and the flatness of the main surface 10 is deteriorated, and particles are included. The cleaning liquid and the rinsing liquid easily adhere to the main surface 10. On the other hand, when the inclination angle θ2 is greater than 15 °, particles are likely to be generated from the interface between the main surface 10 and the second chamfered surface 22.

  Further, the width W2 of the second chamfered surface 22 along the radial direction of the wafer 1 is preferably 50 to 200 μm. Here, when the width W2 of the second chamfered surface 22 is smaller than 50 μm, when the second chamfered surface 22 is formed, the polishing cloth comes into contact with the main surface 10 to cause overpolishing, and the flatness of the main surface 10 is increased. In addition, the cleaning liquid and the rinse liquid containing particles are likely to adhere to the main surface 10. On the other hand, when the width W2 of the second chamfered surface 22 is larger than 100 μm, there arises a problem that the strength of the peripheral portion 20 is lowered and the peripheral portion 20 is missing.

Here, the sum of the width W1 of the first chamfered surface 21 and the width W2 of the second chamfered surface 22 needs to be within the range of the edge exclusion region E. The significance lies in the following points.
The edge exclusion area is an exclusion area that does not use a chip formed within the edge exclusion area, and an area of a predetermined distance from the outermost periphery of the wafer 1 is set. For example, in this embodiment, an area of 1 mm from the outermost periphery of the wafer 1 toward the center of the wafer 1 is set as the edge exclusion area E.

  The first chamfered surface 21 and the second chamfered surface 22 are regions where devices are not formed. For this reason, the sum of the width W1 of the first chamfered surface 21 and the width W2 of the second chamfered surface 22 needs to be within the range of the edge exclusion region E.

  The inclination angle θ3 formed by the tangent line in contact with the first chamfered surface 21A and the tangent line in contact with the main surface 11 is preferably 10 to 30 °. The same applies to the inclination angle θ3 formed by the tangent line in contact with the first chamfered surface 21B and the tangent line in contact with the back surface 12.

According to the wafer 1 of the present embodiment, the following effects are exhibited.
The wafer 1 according to the present embodiment includes a second chamfered surface 22 that is inclined toward the radially outer side of the wafer 1 between the main surface 10 and the first chamfered surface 21. Therefore, when the second chamfered surface 22 is formed, the pressure from the polishing cloth is dispersed, the polishing cloth does not contact the main surface 10, and overpolishing does not occur. Therefore, the flatness of the main surface 10 can be maintained high without deteriorating.

Further, for example, in the etching process in the device forming process, the cleaning liquid or the rinsing liquid may contain particles that cause a device failure. When the cleaning liquid or the rinsing liquid containing such particles adheres to the back surface 12 or the first chamfered surface 21, the cleaning liquid or the rinsing liquid including the particles wraps around from the back surface 12 or the first chamfered surface 21, and the main surface 11 may adhere.
In the wafer 1 according to the present embodiment, the cleaning liquid and the rinse liquid containing particles are blocked by the second chamfered surface 22, and therefore the adhesion of the cleaning liquid and the rinse liquid containing particles to the main surface 11 can be prevented.

  Next, one manufacturing method of the wafer 1 of this embodiment will be described with reference to the drawings. FIG. 3 is a flowchart showing a method for manufacturing the wafer 1 of the present invention. As shown in FIG. 3, the manufacturing method of the semiconductor wafer 1 of this embodiment includes the following steps S1 to S12. FIGS. 4A to 4C are views sequentially illustrating the process in which the first chamfered surface 21 and the second chamfered surface 22 are formed on the wafer 1 (corresponding to FIG. 2).

(S1) Single Crystal Ingot Growth Step First, a single crystal semiconductor ingot is grown by the Czochralski method (CZ method), the floating zone method (FZ method), or the like.

(S2) Outline Grinding Step The semiconductor ingot grown through the single crystal ingot growth step S1 is cut at the front end portion and the terminal end portion. Then, in the external grinding process, in order to make the diameter uniform, the outer periphery of the semiconductor ingot is ground with a cylindrical grinder or the like to form a block body, and the outer peripheral shape is adjusted.

(S3) Slicing Step The block body that has undergone the external grinding step S2 is provided with an orientation flat or an orientation notch in order to show a specific crystal orientation. After this process, the block body is sliced with a wire saw or the like at a predetermined angle with respect to the rod axis direction to form a wafer. Thereby, as shown in FIG. 4A, when the wafer 1A is viewed from the thickness direction, the shape of the wafer 1A is substantially rectangular.

(S4) Rough chamfering process The wafer sliced through the slicing process S3 is subjected to a rough chamfering process on the peripheral edge 20 in order to prevent the peripheral edge 20 from being chipped or chipped. That is, the peripheral edge portion 20 is chamfered into a predetermined shape with a chamfering grindstone or a polishing cloth.

(S5) Lapping Step In the wafer that has undergone the rough chamfering step S4, the concavo-convex layers on the front and back surfaces of the thin disk-like wafer generated in the slicing step are flattened by lapping. In the lapping step, the wafer is placed between lapping platens parallel to each other, and a lapping solution that is a mixture of alumina abrasive grains, a dispersant, and water is poured between the lapping platen and the wafer. Then, rotation and rubbing are performed under pressure, and both front and back surfaces of the wafer are lapped. This increases the flatness of the wafer front and back surfaces and the parallelism of the wafer.

(S6) Etching Step The wafer that has undergone the lapping step S5 is dipped in an etchant and etched. In the etching process, an etching solution is supplied to the surface of the wafer while spinning the wafer, the supplied etching solution is spread over the entire wafer surface by centrifugal force due to the spin, and the entire wafer surface is etched to obtain a surface roughness Ra of the wafer surface. Is controlled to a predetermined surface roughness. In this etching process, the work-affected layer introduced by the machining process such as the rough chamfering process S4 and the lapping process S5 is completely removed by etching.

(S7) First chamfering step The peripheral portion 20 of the wafer that has undergone the etching step S6 is polished. In the first chamfering step, the peripheral edge 20 is pressed against the polishing cloth and polished to a mirror surface while supplying the polishing liquid to the rotating wafer. By the first chamfering step, as shown in FIG. 4B, a first chamfered surface 21 is formed on the wafer 1B. In the first chamfering process, the wafer is polished using a polishing cloth. However, the present invention is not limited to this, and polishing may be performed using a polishing grindstone.

(S8) Second Chamfering Step In the wafer that has undergone the first chamfering step S7, the second chamfered surface 22 is formed by removing a part of the peripheral edge portion 20 including the first chamfered surface 21. The second chamfered surface 22 is formed by polishing the mirror surface by pressing the boundary portion where the first chamfered surface 21 and the main surface 10 are in contact with the polishing cloth while supplying the polishing liquid to the rotating wafer. The By the second chamfering step, a first chamfered surface 21 and a second chamfered surface 22 are formed on the wafer 1 as shown in FIG. In the second chamfering process, the wafer is polished using a polishing cloth, but the wafer may be polished using a polishing grindstone.

(S9) Primary polishing (mirror polishing) step The wafer subjected to the second chamfering step S8 is subjected to primary polishing as a mirror polishing of the front surface using a double-side simultaneous polishing apparatus that simultaneously polishes the front and back surfaces.

(S10) Secondary polishing (mirror polishing) step The wafer subjected to the primary polishing (mirror polishing) step S9 is subjected to secondary polishing as mirror polishing using a double-sided simultaneous polishing apparatus that simultaneously polishes the front and back surfaces. In the primary polishing step S9 and the secondary polishing step S10 of the present embodiment, the front and back surfaces of the wafer are simultaneously polished by double-sided simultaneous polishing. Instead of this double-sided simultaneous polishing, the front and back surfaces of the wafer are polished one by one. The wafer may be polished by polishing.

(S11) Final cleaning step The wafer that has undergone the secondary polishing (mirror polishing) step S10 is subjected to final cleaning. Specifically, it is cleaned with an RCA cleaning solution.

(S12) Flatness measurement The wafer that has undergone the final cleaning step S11 is measured with the degree of polishing as flatness.

Thus, the semiconductor wafer 1 provided with the 2nd chamfering surface 22 between the main surface 10 and the 1st chamfering surface 21 can be obtained by passing through each said process.
According to the manufacturing method of the wafer 1 of the present embodiment, the second chamfered surface 22 can be formed by a simple process, and the flatness of the wafer 1 can be maintained high.

As mentioned above, although one Embodiment of this invention was described, this invention is not restrict | limited to embodiment mentioned above.
For example, in the above-described embodiment, the second chamfered surface 22 is formed on the main surface 11 side and the back surface 12 side of the peripheral edge portion 20, but the present invention is not limited thereto, and the second chamfered surface 22 is formed only on the main surface 11 side or the back surface 12 side. A chamfered surface 22 may be formed. In addition, the second chamfered surface 22 is provided only at one location between the main surface 11 or the back surface 12 and the first chamfered surface 21, but the present invention is not limited to this, and the range of the edge exclusion region E If it is inside, the some 2nd chamfering surface 22 may be provided in radial direction.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows one Embodiment of the wafer 1 of this invention, (a) is a perspective view, (b) is the figure seen from the thickness direction of the wafer 1, (c) is the figure seen from the radial direction of the wafer 1 It is. It is an enlarged view of the A arrow part shown in FIG.1 (c). It is a flowchart which shows one manufacturing method of the wafer 1 of this invention. FIG. 3 is a diagram sequentially illustrating a process in which a first chamfered surface 21 and a second chamfered surface 22 are formed on a wafer 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1A, 1B Semiconductor wafer 10 Main surface 11 Main surface 12 Back surface 20 Peripheral part 21, 21A, 21B 1st chamfer surface 22, 22A, 22B 2nd chamfer surface

Claims (4)

A semiconductor wafer comprising a main surface that is a flat surface and a first chamfered surface formed on a peripheral portion,
When the semiconductor wafer is viewed in a cross section in the thickness direction, the semiconductor wafer further includes a second chamfered surface inclined toward the radially outer side of the semiconductor wafer between the main surface and the first chamfered surface. A semiconductor wafer characterized by   The inclination angle of the second chamfered surface with respect to the main surface is 5 to 15 °, and the width of the second chamfered surface along the radial direction of the semiconductor wafer is 50 to 200 µm. 2. The semiconductor wafer according to 1.   The inclination angle of the first chamfered surface with respect to the second chamfered surface is 5 to 25 °, and the width of the first chamfered surface along the radial direction of the semiconductor wafer is 50 to 300 μm. The semiconductor wafer according to claim 1 or 2. It is a manufacturing method of the semiconductor wafer according to claim 1,
A first chamfering step for forming the first chamfered surface on the semiconductor wafer;
And a second chamfering step of forming the second chamfered surface by removing a part of the peripheral portion including the first chamfered surface after the first chamfered step. A method for manufacturing a semiconductor wafer.

Images