JP2009283720A - Semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer capable of reducing material resources at the time of manufacturing. <P>SOLUTION: The semiconductor wafer 1 has features that it has a diameter ϕ of 450 mm, and a thickness t of no less than 300 μm and no more than 775 μm. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer.

  In recent years, due to the increase in chip size accompanying higher integration and higher functionality of semiconductor devices, semiconductor wafers used for manufacturing semiconductor devices (hereinafter also simply referred to as “wafers”) are required to have larger diameters. ing.

However, a large diameter wafer may cause various problems during manufacturing. For example, Patent Document 1 proposes a technique for calculating the amount of deflection from the diameter and thickness of a wafer to be loaded, thereby determining the groove width of a wafer cassette in batch conveyance.
Japanese Patent Laid-Open No. 2004-95942

  The above-mentioned Patent Document 1 discloses a wafer whose thickness is reduced after grinding the back surface of the wafer. However, even in a large-diameter semiconductor wafer, due to an increase in the amount of deflection due to the weight of the wafer, the wafer into the storage container is disclosed. Whether the wafer is loaded and taken out from the storage container or the wafer is transferred in the manufacturing apparatus or the like becomes a problem. In addition, as the wafer diameter increases, the amount of material resources used during manufacturing increases, which may lead to an increase in wafer cost.

  Accordingly, an object of the present invention is to provide a semiconductor wafer capable of reducing material resources during manufacturing.

  (1) The semiconductor wafer of the present invention has a diameter of 450 mm and a thickness of 300 μm to 775 μm.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor wafer which can reduce the material resource at the time of manufacture can be provided.

  Hereinafter, an embodiment of a semiconductor wafer of the present invention will be described with reference to the drawings. FIG. 1 is a view showing one embodiment of a semiconductor wafer 1 of the present invention, (a) is a perspective view, (b) is a view as seen from the thickness direction of the semiconductor wafer 1, and (c). These are the figures seen from the diameter direction of semiconductor wafer 1. FIG.

  The semiconductor wafer 1 of the present embodiment (hereinafter also simply referred to as “wafer”) has a diameter of 450 mm and a thickness of 300 μm or more and 775 μm or less.

Moreover, the wafer 1 of this embodiment consists of a silicon wafer and a gallium arsenide wafer, for example.
As shown in FIGS. 1A and 1B, the wafer 1 of this embodiment has a diameter φ of 450 mm. Here, the diameter φ of the wafer 1 is a numerical value as a target value at the time of manufacture, and includes an allowable error at the time of manufacture. For example, the diameter φ of the wafer 1 includes a tolerance of ± 0.2 mm.

  The wafer 1 of the present embodiment has a thickness t shown in FIG. The significance of this is that the amount of material used for the wafer 1, that is, the volume of the wafer 1, is 300 mm in diameter. Currently, the wafer volume (material usage) is 775 μm. Π × 150 mm × 150 mm × 775 μm. In order to realize the same material usage amount with a wafer having a diameter of 450 mm, assuming that the thickness of the wafer is X μm, π × 150 mm × 150 mm × 775 μm = π × 225 mm × 225 mm × X, that is, X≈344 μm. Therefore, the thickness t of the wafer 1 is set to 300 μm or more.

  Since the wafer 1 of this embodiment has a thickness t of 300 μm or more, it can be manufactured with the same material usage as a semiconductor wafer with a diameter of 300 mm from the viewpoint of the material usage of the wafer. Therefore, the material resources at the time of manufacturing a semiconductor wafer having a diameter of 450 mm can be reduced, and the cost can be reduced. If the thickness t of the wafer 1 is less than 300 μm, the shape of the edge portion of the semiconductor wafer becomes an acute angle, which may cause generation of particles when the edge portion comes into contact with a storage container or a manufacturing apparatus.

  Further, the wafer 1 of the present embodiment has a thickness t of 775 μm or less. The significance lies in the following points. Since the diameter ratio of a semiconductor wafer having a diameter of 450 mm is 1.5 times that of a wafer having a diameter of 300 mm, the volume ratio is 2.25 times. Considering the volume ratio with respect to a wafer having a diameter of 300 mm and a thickness of 775 μm, in order to realize the same material usage with a wafer having a diameter of 450 mm, assuming that the thickness of the wafer is Y μm, π × 150 mm × 150 mm × 775 μm × 2.25 = π × 225 mm × 225 mm × Y That is, Y = 775 μm. Therefore, the thickness t of the wafer 1 is set to 775 μm or less.

Next, the manufacturing method of the semiconductor wafer 1 of this embodiment is demonstrated. FIG. 2 is a flowchart showing a method for manufacturing the semiconductor wafer 1 of the present invention. As shown in FIG. 2, the manufacturing method of the semiconductor wafer 1 of this embodiment includes the following steps S1 to S11.
(S1) Single Crystal Ingot Growth Step First, a single crystal semiconductor ingot is grown by the Czochralski method (CZ method), the floating zone method (FZ method), or the like.

(S2) Outline Grinding Step The semiconductor ingot grown through the single crystal ingot growth step S1 is cut at the front end and the terminal end. Then, in the external grinding process, in order to make the diameter uniform, the outer periphery of the semiconductor ingot is ground with a cylindrical grinder or the like to form a block body, and the outer peripheral shape is adjusted.

(S3) Slicing Step The block body that has undergone the external grinding step S2 is subjected to an orientation flat or an orientation notch to indicate a specific crystal orientation. After this process, the block body is sliced with a wire saw or the like at a predetermined angle with respect to the rod axis direction to form a wafer.

(S4) Chamfering process The wafer sliced through the slicing process S3 is chamfered around the wafer in order to prevent chipping and chipping of the peripheral part of the wafer. That is, the outer peripheral portion of the wafer is chamfered into a predetermined shape by the chamfering grindstone. Thereby, the outer peripheral portion of the wafer is formed into a predetermined rounded shape.

(S5) Lapping process In the wafer that has undergone the chamfering process S4, the concavo-convex layers on the front and back surfaces of the thin disk-shaped wafer generated in the process such as slicing are flattened by lapping. In the lapping step, the wafer is placed between lapping platens parallel to each other, and a lapping solution that is a mixture of alumina abrasive grains, a dispersant, and water is poured between the lapping platen and the wafer. Then, rotation and rubbing are performed under pressure, and both front and back surfaces of the wafer are lapped. This increases the flatness of the wafer front and back surfaces and the parallelism of the wafer.

(S6) Etching Step The wafer that has undergone the lapping step S5 is dipped in an etchant and etched. In the etching process, an etching solution is supplied to the surface of the wafer while spinning the wafer, the supplied etching solution is spread over the entire wafer surface by centrifugal force due to the spin, and the entire wafer surface is etched to obtain a surface roughness Ra of the wafer surface. Is controlled to a predetermined surface roughness. In this etching process, the work-affected layer introduced by the machining process such as the chamfering process S4 and the lapping process S5 is completely removed by etching.

(S7) Outer peripheral polishing step The outer peripheral portion of the wafer that has undergone the etching step S6 is subjected to outer peripheral polishing. Thereby, the chamfered surface of the wafer is mirror-finished. In the outer peripheral polishing step, the chamfered surface of the wafer is pressed against the outer peripheral surface of the polishing cloth rotating around the axis while supplying the polishing liquid, and polished to a mirror surface.

(S8) Primary polishing step The wafer that has undergone the outer periphery polishing step S7 is subjected to primary polishing as rough surface polishing using a double-sided simultaneous polishing apparatus that simultaneously polishes the front and back surfaces.

(S9) Secondary polishing (mirror polishing) step The wafer that has undergone the primary polishing step S8 is subjected to secondary polishing as mirror polishing using a double-sided simultaneous polishing apparatus that simultaneously polishes the front and back surfaces. In the primary polishing step S8 and the secondary polishing step S9 of the present embodiment, the front and back surfaces of the wafer are simultaneously polished by double-sided simultaneous polishing. The wafer may be polished by polishing.

(S10) Final cleaning step The wafer that has undergone the secondary polishing (mirror polishing) step S9 is subjected to final cleaning. Specifically, it is cleaned with an RCA cleaning solution.

(S11) Flatness measurement Wafers that have undergone the final cleaning step S10 are measured using the degree of polishing as flatness.

  The semiconductor wafer 1 having a diameter φ of 450 mm and a thickness t of 300 μm or more and 775 μm or less can be obtained by the manufacturing steps described in S1 to S11.

  Thus, in the semiconductor wafer 1 of this embodiment, since the thickness t is 300 μm or more, from the viewpoint of the amount of material used for the wafer, it can be manufactured with the same amount of material used as a semiconductor wafer having a diameter of 300 mm. it can. Therefore, it is possible to reduce the material resources at the time of manufacturing and reduce the cost. Further, in the semiconductor wafer 1 of the present embodiment, since the thickness t is 300 μm or more, the shape of the edge portion of the semiconductor wafer 1 becomes an acute angle, and when this edge portion comes into contact with a storage container or a manufacturing apparatus, particles are formed. There is also no risk of occurrence.

  Moreover, in the semiconductor wafer 1 of this embodiment, since the thickness t is 775 μm or less, from the viewpoint of the amount of material used for the wafer, even when considering the volume ratio based on the diameter ratio, It can be manufactured with the same amount of material used. Therefore, it is possible to reduce the material resources at the time of manufacturing and reduce the cost.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows one Embodiment of the semiconductor wafer 1 of this invention, (a) is a perspective view, (b) is the figure seen from the thickness direction of the semiconductor wafer 1, (c) is a semiconductor wafer. It is the figure seen from the diameter direction of 1. It is a flowchart shown about the manufacturing process of the semiconductor wafer 1 of this embodiment.

Explanation of symbols

1 Semiconductor wafer φ Diameter t Thickness

Claims (1)

  A semiconductor wafer having a diameter of 450 mm and a thickness of 300 μm to 775 μm.

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