JP2004319910A - Method for manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor wafer which can suppress generation of a damage of the outermost periphery of the wafer caused by the contact between the outermost periphery of the wafer and the peripheral wall of a wafer holding hole of a carrier plate. <P>SOLUTION: In first chamfering, the outermost peripheral side of a silicon wafer W after sliced is made to be a flat surface including a wafer thickness direction. Thus, in lapping, the contact between the outermost periphery of the wafer W after subjected to the first chamfering and the peripheral wall of a wafer holding hole 13a of each carrier plate 13 can be made to be a surface contact. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor wafer, and more specifically, to remove, by secondary chamfering, damage caused on the outer peripheral portion of a wafer due to contact with an inner wall of a wafer holding hole of a wafer holding plate during lapping of a semiconductor wafer after primary chamfering. The present invention relates to a semiconductor wafer manufacturing technique.
[0002]
[Prior art]
An example of a conventional method for manufacturing a silicon wafer will be described with reference to FIG.
As shown in the flow sheet of FIG. 4, in the slicing step (S401), a silicon wafer W is sliced from a silicon single crystal ingot pulled up by the CZ method. In the subsequent primary chamfering step (S402), the outer peripheral portion of the wafer is roughly chamfered by, for example, a # 600 metal bond chamfering grindstone to make it round. The chamfered shape is the final shape at the time of shipment (FIG. 4A). In the next lapping step (S403), the silicon wafer W sliced is held in the wafer holding holes 103a of the SK material carrier plate 103 by the pair of upper and lower lapping plates 101 and 102, and the lapping liquid (slurry) is supplied. While supplying, the front and back surfaces of the wafer are wrapped to increase the wafer parallelism (FIG. 4B).
[0003]
After that, the silicon wafer W is second chamfered (S404). Here, for example, a # 2000 metal bond chamfering grindstone is used. The chamfered shape is the same final shape as at the time of primary chamfering aiming at the final shape (FIG. 4C). In the next etching step (S405), the silicon wafer W is immersed in a predetermined etching solution to remove distortion and the like during lapping. Thereafter, mirror polishing (PCR: Polish Corner Rounding) is performed on the outer peripheral portion of the wafer (S406), and the outer peripheral surface of the wafer is mirror-finished. In the subsequent polishing step (S407), the surface of the wafer is primarily polished by the polishing apparatus, and then the silicon wafer W is finish-polished with a polishing amount of 1 μm or less using the single-side polishing apparatus (S408). Then, final finishing cleaning (S409) and inspection are performed before shipment.
In the above case, the silicon wafer W rotates in the wafer holding hole 103a of the carrier plate 103 at the time of the lap. Thereby, the outermost peripheral portion of the wafer comes into contact with the vertical peripheral wall of the wafer holding hole 103a, causing rubbing, and the outermost peripheral portion is easily damaged. Further, particles were generated due to the rubbing, and there was a possibility that the particles would adhere to both the front and back surfaces of the silicon wafer W (FIG. 4B). In the secondary chamfering, the scratch on the outermost peripheral portion of the wafer is removed.
[0004]
[Problems to be solved by the invention]
However, in the above-described conventional method, the chamfered shape at the time of primary chamfering has a shape similar to that at the time of shipping. That is, the cross-sectional shape of the chamfered surface of the silicon wafer W is a semicircular wafer, and in any case of a wafer having a substantially shell shape slightly tapered, when lapping, the outermost peripheral portion of the wafer The contact with the peripheral wall of the wafer holding hole 103a is a line contact. Therefore, during the lap, the force per unit area acting on the outermost peripheral portion is increased, and the outermost peripheral portion is easily damaged. As a result, the machining allowance of the chamfered portion in the mirror chamfering step is increased, and the productivity of the silicon wafer W may be reduced.
[0005]
Then, as a result of earnest research, the inventors first perform predetermined primary chamfering on the sliced semiconductor wafer. After the primary chamfering, the cross section of the outer peripheral portion of the wafer has a first straight line and a second straight line inclined at a predetermined angle with respect to the straight lines indicating the front and back surfaces of the wafer, and the straight lines indicating the front and back surfaces. , And a tapered shape surrounded by a third straight line that intersects the first straight line and the second straight line. Subsequently, wrapping is performed, and then, if secondary chamfering for forming the final shape is performed, contact between the outermost peripheral portion in the wrap and the peripheral wall of the wafer holding hole becomes surface contact, and the conventional line contact is performed. The inventors have found that the occurrence of scratches on the outermost peripheral portion can be suppressed as compared with the case, and that even if a scratch occurs, the scratch can be made shallower, and the present invention has been completed.
[0006]
[Object of the invention]
An object of the present invention is to suppress the occurrence of scratches on the outermost peripheral portion of the wafer due to contact between the outermost peripheral portion of the semiconductor wafer and the peripheral wall of the wafer holding hole of the carrier plate during lapping, and furthermore, the occurrence of chipping due to the scratches. It is an object of the present invention to provide a method of manufacturing a semiconductor wafer that can reduce the amount of generation and can reduce the size of the damage even if the damage occurs.
[0007]
[Means for Solving the Problems]
The first aspect of the present invention provides a primary chamfering step of performing primary chamfering on an outer peripheral portion of a sliced semiconductor wafer, a lapping step of wrapping the semiconductor wafer after the primary chamfering, A secondary chamfering step of performing a secondary chamfering to form a final shape on an outer peripheral portion, wherein the primary chamfer has a cross section of an outer peripheral portion of the sliced semiconductor wafer, A first straight line and a second straight line which are inclined at a predetermined angle with respect to each straight line indicating the front and back surfaces of the semiconductor wafer, and the first straight line and the second straight line perpendicular to the straight lines indicating the front and back surfaces, respectively. This is a method for manufacturing a semiconductor wafer having a tapered shape surrounded by a third straight line that crosses a second straight line.
[0008]
Semiconductor wafers include silicon wafers and gallium arsenide wafers.
As the chamfering grindstone for the primary chamfering, for example, a # 800 metal bond chamfering grindstone can be adopted. The chamfer amount in the primary chamfer is 100 to 200 μm. The chamfering time is 0.5 to 1 minute.
The inclination angle of the first straight line in the primary chamfering step is 10 to 45 degrees, preferably 20 to 24 degrees. If the angle is less than 10 degrees, there is a disadvantage that a margin for forming the final shape is insufficient. Further, when the angle exceeds 45 degrees, a problem of chipping occurs.
[0009]
The angle of inclination of the second straight line in the primary chamfering step is 10 to 45 degrees, preferably 20 to 24 degrees. If the angle is less than 10 degrees, there is a disadvantage that a margin for forming the final shape is insufficient. In addition, when the angle exceeds 45 degrees, a problem of chipping occurs. The inclination angles of the first straight line and the second straight line may be the same. Also, they may be different.
The length of the third straight line in the primary chamfering step is, for example, 100 to 600 μm, and preferably 300 to 500 μm. If it is less than 100 μm, the inside of the wrap carrier is shaved at the chamfered end face, and when the life is near, the cross section of the carrier becomes hemispherical, causing a problem of chipping at the edge. On the other hand, when the thickness exceeds 600 μm, there arises a problem of chipping during preparation and collection.
The cross section of the outer peripheral portion of the sliced semiconductor wafer has a first straight line and a second straight line inclined with respect to each straight line indicating the front and back surfaces of the wafer, and a first straight line perpendicular to each straight line indicating the front and back surfaces. In the case of a tapered shape surrounded by a straight line and a third straight line that intersects the second straight line, both the front and back surfaces of the outer peripheral portion of the wafer are tapered surfaces, and the outermost peripheral side of the wafer is a flat surface including the wafer thickness direction. Become.
[0010]
The lapping device used in the lapping process includes a pair of lapping plates arranged vertically and a carrier plate disposed between the lapping plates and having a plurality of wafer holding holes. The sliced semiconductor wafer is held in each wafer holding hole of the carrier plate, and each semiconductor wafer is wrapped while supplying a lapping liquid from above. Specifically, the carrier plate is rotated and revolved between a sun gear and an internal gear rotated by a rotary motor, and thereby the front and back surfaces (upper surface and lower surface) of the semiconductor wafer in the wafer holding hole are moved to the upper surface plate. And, it slides while pressing each opposing surface (lap action surface) of the lower surface plate.
The wrap amount is 60 to 100 μm on both the front and back surfaces of the semiconductor wafer. The lap time is 10-20 minutes. As the lapping liquid, for example, a mixture of alumina abrasive grains, a dispersant, and water can be used.
As the chamfering grindstone for secondary chamfering, for example, a metal bond chamfering grindstone of # 1200 to # 1500 can be adopted. Here, the chamfer amount is 200 to 300 μm. Chamfer time is 3-6 minutes.
[0011]
The invention according to claim 2 is the method for manufacturing a semiconductor wafer according to claim 1, wherein after the secondary chamfering, a mirror chamfering step of mirror-finishing a chamfered surface of an outer peripheral portion of the semiconductor wafer is performed.
As a mirror chamfering apparatus used in the mirror chamfering step, for example, a cylindrical urethane buff is rotated, and the outer peripheral surface of the rotating buff is brought into contact with the outer peripheral surface of the semiconductor wafer sucked and held by the holding plate, The outer peripheral surface may be mirror-finished. During the mirror polishing, the semiconductor wafer is vacuum-sucked to the holding plate.
The machining allowance in the mirror chamfering step is, for example, 2 to 5 μm.
[0012]
A third aspect of the present invention is the method for manufacturing a semiconductor wafer according to the first or second aspect, wherein, in the first chamfering step, a joining portion between the tapered surface and the flat surface is rounded. .
[0013]
[Action]
According to the present invention, at the time of lapping, the semiconductor wafer rotates in the wafer holding hole of the carrier plate, and its outermost peripheral portion comes into contact with a vertical peripheral wall of the wafer holding hole. However, in the primary chamfering of the previous step, the cross section of the outer peripheral portion of the sliced semiconductor wafer is formed by first and second straight lines inclined with respect to the straight lines indicating the front and back surfaces of the wafer, and Since the tapered shape is perpendicular to the straight line and surrounded by a third straight line that intersects the first straight line and the second straight line, the contact between the outermost peripheral portion of the wafer and the peripheral wall of the wafer holding hole is equal to the surface contact. Become. As a result, the unit area acting on the outermost peripheral portion during the lap is smaller than when the chamfer shape of the primary chamfer is the final shape at the time of shipping and the contact with the peripheral wall of the wafer holding hole is a line contact as in the conventional case. Hit force is reduced. As a result, it is possible to suppress the occurrence of the scratch on the outermost peripheral portion, and even if the scratch occurs, the scratch can be made shallow. Further, the amount of particles generated due to the scratch can be reduced.
[0014]
In addition, when the semiconductor wafer is subsequently mirror-polished, the machining allowance is reduced, and the productivity of the wafer can be increased. Further, tapered surfaces are respectively formed on the front and back surfaces of the semiconductor wafer by primary chamfering. As a result, at the time of lapping, although the contact between the outermost peripheral portion of the wafer and the peripheral wall of the wafer holding hole is in surface contact, the semiconductor wafer immediately after slicing is directly chipped or chipped at the outer peripheral portion of the wafer as if it were wrapped. Is less likely to occur.
Next, the semiconductor wafer after lapping is subjected to secondary chamfering and shaped into a final shape. Even if scratches occur on the outermost peripheral portion of the wrapped semiconductor wafer, the scratches can be removed in a short time during secondary chamfering.
[0015]
In particular, according to the third aspect of the present invention, since the junction between the tapered surface and the flat surface is rounded, the occurrence of chipping and chipping on the outer peripheral portion of the semiconductor wafer during lapping can be further suppressed. .
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
As shown in FIG. 1, in this embodiment, the surface is mirror-polished through the steps of slicing, primary chamfering, wrapping, secondary chamfering, etching, mirror polishing, primary polishing, finish polishing, and finish cleaning. A finished silicon wafer is produced. Hereinafter, each step will be described in detail.
The silicon ingot pulled up by the CZ method is sliced into a silicon wafer W having a diameter of 201 mm and a thickness of about 860 μm in a slicing step (S101).
Next, the outer peripheral portion of the silicon wafer W is first chamfered (S102). Specifically, using a # 800 metal bond chamfering grindstone, the cross-sectional shape of the chamfered surface becomes a tapered surface of 20 to 24 degrees on the front side of the wafer and a tapered surface of 20 to 24 degrees on the back side of the wafer. . Then, the outermost peripheral side is chamfered so as to be a flat surface perpendicular to the front and back surfaces of the wafer and intersecting both tapered surfaces. Thereby, the wafer is rounded. The chamfer amount in the primary chamfer is 300 μm. The chamfering time is 0.5 to 1 minute. Also, at the time of the primary chamfering, the joining portion between the tapered surface and the flat surface is rounded (FIG. 1A).
[0017]
Next, a lapping step (S103) is performed. As shown in FIGS. 2 and 3, the lapping device 10 used here includes a pair of lap plates 11, 12 arranged vertically, and is disposed between the lap plates 11, 12, and has four wafer holding holes. 13a on which five carrier plates 13 are formed. FIG. 2 shows only one of the five sheets. The carrier plates 13 are made of SK material, hold the silicon wafer W after the primary chamfering in each of the wafer holding holes 13a, and supply a lapping liquid, which is a mixture of alumina abrasive grains, a dispersant, and water, from above. Each silicon wafer W is wrapped. Specifically, the carrier plates 13 are rotated and revolved between a sun gear 14 and an internal gear 15 rotated by a rotation motor (not shown), and thereby the front and back surfaces of the silicon wafer W in the wafer holding holes 13a are rotated. The upper and lower lapping surfaces 11 and 12 are in sliding contact with each other while being pressed (FIG. 1B). Thereby, the front and back surfaces of the silicon wafer W are mechanically ground. The lap amount is 70 to 100 μm on both sides of the wafer, and the lap time is 10 to 20 minutes.
[0018]
During this lap, the silicon wafer W rotates within the wafer holding holes 13a of the carrier plate 13, and the outermost peripheral portion of the wafer comes into contact with the peripheral wall of the wafer holding holes 13a. The outermost peripheral side of the silicon wafer W is a flat surface including the wafer thickness direction by primary chamfering. Therefore, the contact between the outermost peripheral portion of the wafer and the peripheral wall of the wafer holding holes 13a becomes surface contact. As a result, the outermost peripheral portion during the wrapping is different from the conventional case where the chamfered shape of the primary chamfer is the final shape at the time of shipment and the contact with the peripheral wall of the wafer holding holes 13a. The force per unit area acting on the surface is reduced. As a result, generation of scratches on the outermost peripheral portion of the wafer can be suppressed. In addition, the machining allowance in the subsequent mirror polishing step is reduced, and the productivity of the silicon wafer W can be increased.
Further, at the time of lapping, a tapered surface is formed on each of the front and back surfaces of the silicon wafer W in advance. As a result, although the outermost peripheral portion of the wafer is in surface contact with the peripheral wall of the wafer holding hole 13a, as described above, the silicon wafer W immediately after slicing is directly wrapped. The occurrence of chipping and chipping on the outer periphery is unlikely to occur.
[0019]
Next, the rounded silicon wafer W is subjected to secondary chamfering on the outer peripheral surface of the wafer (S104).
Here, a # 1500 metal bond chamfering grindstone is used. The chamfer amount is 600 μm, and the chamfer time is 3 to 6 minutes.
By the second chamfering, the outer peripheral portion of the silicon wafer W is shaped into a chamfered shape that is the final shape (FIG. 1C). In addition, even if the outermost peripheral portion of the wrapped wafer W has a flaw, the flaw can be removed in a short time.
Subsequently, the second chamfered silicon wafer W is etched (S105). Specifically, the silicon wafer W is immersed for a predetermined time in a mixed acid solution (normal temperature to 50 ° C.) in which hydrofluoric acid and nitric acid are mixed.
[0020]
After that, mirror chamfering (PCR) is performed on the outer peripheral portion of the etched silicon wafer W (S106). At the time of this processing, a mirror chamfering device (not shown) is used. That is, here, a device for rotating a cylindrical urethane buff with a motor is employed. The urethane buff is rotated by the motor, and the outer peripheral surface of the silicon wafer W is brought into contact with the outer peripheral surface of the rotating buff. Thereby, the outer peripheral surface of the wafer is mirror-finished.
Then, the surface of the mirror-polished silicon wafer W is primarily polished using a single-side polishing apparatus (S107).
Specifically, a silicon wafer W is inserted into each of the wafer holding holes 13a of the carrier plate 13, and while the slurry containing loose abrasive grains is supplied, the nonwoven fabric is impregnated with a urethane resin and hardened to form a two-piece polishing. First polishing with a cloth.
Next, the surface of the silicon wafer W after the primary polishing is finish-polished (S108). As a polishing device for finish polishing, a known polishing device for polishing one side is used. That is, a non-woven fabric for finish polishing is used, and the polishing amount is about 0.1 to 2 μm.
After that, the silicon wafer W is subjected to finish cleaning (S109). The cleaning here is RCA cleaning based on two types of cleaning liquids, SC-1 and SC-2.
[0021]
【The invention's effect】
According to the present invention, at the time of the primary chamfering, the cross section of the outer peripheral portion of the sliced semiconductor wafer has the first straight line and the second straight line inclined at a predetermined angle with respect to each straight line indicating the front and back of the semiconductor wafer. 2 and a chamfer having a tapered shape surrounded by a third straight line perpendicular to each of the front and back surfaces and intersecting the first straight line and the second straight line. Since the shaping secondary chamfering is performed, the contact between the outermost peripheral portion of the semiconductor wafer and the peripheral wall of the wafer holding hole becomes a surface contact during the lap. As a result, the occurrence of scratches on the outermost periphery during the lap can be suppressed, the amount of particles generated due to the scratches can be reduced, and even if a scratch occurs, the scratch can be made shallow. it can. In addition, when mirror polishing is performed in a subsequent process, the machining allowance at the time of mirror polishing is reduced, and wafer productivity can be increased.
[0022]
In particular, according to the third aspect of the present invention, since the joining portion between the tapered surface and the flat surface is rounded, the occurrence of chipping and chipping on the outer peripheral portion of the semiconductor wafer during lapping can be further suppressed. .
[Brief description of the drawings]
FIG. 1 is a flow sheet showing a method for manufacturing a semiconductor wafer according to one embodiment of the present invention.
FIG. 2 is a schematic view of a lapping apparatus in a method for manufacturing a semiconductor wafer according to one embodiment of the present invention.
FIG. 3 is an enlarged vertical sectional view of a main part of a lapping apparatus in a method for manufacturing a semiconductor wafer according to one embodiment of the present invention.
FIG. 4 is a flow sheet showing a method for manufacturing a semiconductor wafer according to a conventional means.
[Explanation of symbols]
W Silicon wafer (semiconductor wafer).

Claims (3)

A primary chamfering step of performing primary chamfering on an outer peripheral portion of the sliced semiconductor wafer;
After the primary chamfering, a lapping step of wrapping the semiconductor wafer;
A secondary chamfering step of performing a secondary chamfering to form a final shape on an outer peripheral portion of the wrapped semiconductor wafer, the method comprising:
The first chamfer is
The cross section of the outer peripheral portion of the sliced semiconductor wafer shows a first straight line and a second straight line inclined at a predetermined angle with respect to each straight line indicating the front and back surfaces of the semiconductor wafer, and the front and back surfaces. A method of manufacturing a semiconductor wafer having a tapered shape which is perpendicular to each straight line and surrounded by a third straight line intersecting the first straight line and the second straight line. 2. The method of manufacturing a semiconductor wafer according to claim 1, wherein after the second chamfering, a mirror chamfering step of mirror-finishing a chamfered surface of an outer peripheral portion of the semiconductor wafer is performed. 3. The method of manufacturing a semiconductor wafer according to claim 1, wherein in the primary chamfering step, a joining portion between the tapered surface and the flat surface is rounded.

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