JP2009038186A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that latchup which occurs in a semiconductor device can not be accurately detected in a conventional semiconductor device. <P>SOLUTION: The semiconductor device comprises: a power supply element 10 for supplying a first power supply to an internal circuit 13; a current detection part 12 connected between a well NW where the internal circuit 13 is formed and a well potential supply terminal VDDw for supplying a well potential to the well NW; and a power supply element control circuit 11 for controlling the conductive state of the power supply element 10 on the basis of a current detected by the current detection part 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that detects latch-up occurring in a semiconductor device and controls a latch-up current.

  A semiconductor device is generally composed of a semiconductor substrate or a semiconductor element formed in an upper layer of a well on the semiconductor substrate. Further, the semiconductor device has a parasitic transistor configured by disposing a diffusion layer of the semiconductor element separately from the semiconductor element. This parasitic transistor may become conductive due to the influence of an externally input voltage or current. In a semiconductor device, when a parasitic transistor conducts and a large current flows through a path different from the original current path, the semiconductor element may generate heat and be destroyed. Such a phenomenon that a large current flows through the parasitic transistor is referred to as latch-up.

  Conventionally, various methods for preventing the destruction of the semiconductor device due to the latch-up have been proposed. Examples thereof are disclosed in Patent Documents 1 to 5. In the semiconductor device, in a state where latch-up has not occurred, almost no current flows through the semiconductor substrate or well, and the potential of the semiconductor substrate (hereinafter referred to as substrate potential) or the potential of the well (hereinafter referred to as well potential) Almost no change. In contrast, when latch-up occurs, a large current flows through the semiconductor substrate or well. The substrate potential or well potential immediately below the source of the transistor is greatly increased by this large current. On the other hand, the potential rise in the portion other than directly under the source is small.

  In Patent Documents 1 and 2, the occurrence of latch-up is detected by monitoring the substrate potential or well potential. Therefore, when latch-up is detected with high accuracy in Patent Documents 1 and 2, it is necessary to provide an observation terminal for monitoring the potential directly under the source of the transistor. However, it is difficult to provide an observation terminal directly under the source because of the configuration of the semiconductor device, and it is difficult to detect latch-up with high accuracy only by observing the potential in a portion other than directly under the source.

Further, in Patent Documents 3 to 5, focusing on the fact that the current flowing from the power supply increases when the latchup occurs, the latchup is detected by monitoring the current flowing from the electricity to the circuit. However, since a large-scale semiconductor device in recent years has a large current consumption, a large current flows from the power source regardless of whether latch-up occurs or not. Latchup cannot be detected accurately. In addition, since the current flowing through the semiconductor device itself is large in a power supply semiconductor device that handles a large current, the techniques disclosed in Patent Documents 3 to 5 can detect latch-up with high accuracy even for the power supply semiconductor device. Absent.
Japanese Patent Laid-Open No. 5-90504 JP-A-9-116022 JP-A-63-76362 Japanese Patent Laid-Open No. 2-105624 JP-A-4-167557

  In the techniques disclosed in Patent Documents 1 to 5, there is a problem that detection with high accuracy of latch-up cannot be performed.

  One embodiment of the present invention is connected between a power supply element that supplies a first power supply to an internal circuit, a well in which the internal circuit is formed, and a well potential supply terminal that supplies a well potential to the well. The semiconductor device includes a current detection unit and a power supply element control circuit that controls a conduction state of the power supply element based on a current detected by the current detection unit.

  According to the semiconductor device of the present invention, since latch-up is detected based on the current flowing from the well potential supply terminal to the well, it is possible to detect latch-up with high accuracy even in a semiconductor device with a large current consumption.

  According to the semiconductor device of the present invention, it is possible to improve the detection accuracy of latch-up.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of the semiconductor device 1 of the present embodiment. As illustrated in FIG. 1, the semiconductor device 1 includes a power supply element 10, a power supply element control circuit 11, a current detection unit 12, and an internal circuit 13. In the present embodiment, description will be made assuming that these components are formed on the same semiconductor substrate.

  The power supply element 10 is, for example, a power switch transistor (for example, a PMOS transistor M1), a source connected to a first power supply (for example, an operation power supply node VDD), and a drain connected to the internal circuit 13. And a gate connected to the power supply element control circuit 11. The PMOS transistor M1 has a back gate terminal for supplying the potential of the well of the transistor, and the back gate terminal is connected to the operation power supply node VDD.

  The power supply element control circuit 11 includes a control transistor (for example, a PMOS transistor M2) and a resistor R1. The PMOS transistor M2 has a source connected to a well potential supply terminal (eg, well potential supply node VDDw), a drain connected to a second power supply (eg, ground node GND) via a resistor R1, and current detection. And a gate connected to the portion 12. Further, the power supply element control circuit 11 outputs a potential generated at a node between the PMOS transistor M2 and the resistor R1 as a latch-up detection signal S2.

  The current detection unit 12 includes a well current detection transistor (for example, a PMOS transistor M3). PMOS transistor M3 has a source connected to well potential supply node VDDw, a drain connected to the well of internal circuit 13, and a gate connected to ground node GND. Further, the current detection unit 12 outputs a potential generated at the drain of the PMOS transistor M3 to the PMOS transistor M2 as a current detection signal S1.

  The internal circuit 13 is formed with a circuit that realizes the function of the semiconductor device. In FIG. 1, only three inverters are shown as an example. Each of the three inverters includes a PMOS transistor (MP1 to MP3 in the figure) and an NMOS transistor (MN1 to MN3 in the figure) connected in series between the operation power supply node VDD and the ground node GND. In the present embodiment, the sources of the PMOS transistors MP1 to MP3 are connected to the operating power supply node VDD via the power supply element 10, respectively. The PMOS transistors MP1 to MP3 each have a back gate terminal that supplies a potential to a well in which the transistor is formed. The sources of the PMOS transistors MP1 to MP3 are connected to the well potential supply node VDDw via the current detection unit 12, respectively. On the other hand, the sources of the NMOS transistors MN1 to MN3 are connected to the ground node GND, respectively. The back gate terminals of the NMOS transistors MN1 to MN3 are connected to the ground node GND, respectively.

  Here, in order to describe the connection relationship between the internal circuit 13 and the current detection unit 12 in more detail, FIG. 2 is a diagram showing the portion of the internal circuit 13 in FIG. 1 as a planar layout, and FIG. A cross-sectional view of the internal circuit along X is shown in FIG. Note that in FIGS. 2 and 3, wirings connecting the transistors are omitted. As shown in FIG. 2, the PMOS transistors MP1 to MP3 of the internal circuit 13 have an N well NW formed of an N type semiconductor, and a source S and a drain D formed of a P type semiconductor are formed in the N well NW. It is formed. The PMOS transistors MP1 to MP3 have a gate G so as to be sandwiched between the source S and the drain D. The sources S of the PMOS transistors MP1 to MP3 are connected to the power supply element 10, respectively. The N well NW further includes an N-type semiconductor region having a higher impurity concentration than the N well NW as a back gate terminal ND used in common with the PMOS transistors MP1 to MP3. The back gate terminal ND is connected to the current detection unit 12.

  On the other hand, the NMOS transistors MN1 to MN3 of the internal circuit 13 have a P well PW formed of a P type semiconductor, and a source S and a drain D formed of an N type semiconductor are formed in the P well PW. The NMOS transistors MN1 to MN3 have a gate G so as to be sandwiched between the source S and the drain D. The sources S of the NMOS transistors MN1 to MN3 are connected to the ground node GND, respectively. The P well PW further has a P-type semiconductor region having a higher impurity concentration than the P well PW as a back gate terminal PD used in common with the NMOS transistors MN1 to MN3. The back gate terminal PD is connected to the ground node GND.

  Next, the sectional view shown in FIG. 3 will be described. As shown in FIG. 3, the N well NW is formed in common under the PMOS transistors MP1 to MP3. That is, the well potential supplied to the back gate terminal ND is supplied to the PMOS transistors MP1 to MP3. The N well NW has a parasitic resistance corresponding to the well concentration. This parasitic resistance has a particularly large resistance value under the trench insulating film STI because the current path is blocked by the trench insulating film STI functioning as an element isolation film supplied to the PMOS transistors MP1 to MP3.

  Next, before describing the operation of the semiconductor device 1 according to the present embodiment, the characteristics of the PMOS transistor M3 constituting the current detection unit 12 will be described. FIG. 4 shows the current-voltage characteristics of the PMOS transistor M3. As shown in FIG. 4, the PMOS transistor M3 has a characteristic that the source-drain voltage Vds increases as the source-drain current Ids increases. In addition, when the source-drain current Ids is below a certain level (in the linear region operation range), the change in the source-drain voltage Vds is small with respect to the change in the source-drain current Ids. The source-drain voltage Vds changes greatly with respect to the change in the drain-to-drain current Ids.

  When this source-drain voltage Vds is viewed in relation to latch-up, in an operation in which latch-up has not occurred (hereinafter, this operation is referred to as normal operation), a very large current flows in the well of the internal circuit 13. Does not flow, the source-drain voltage Vds of the PMOS transistor M3 is small, and is in the normal operation range shown in FIG. On the other hand, since a large current flows through the well when latch-up occurs, the source-drain voltage Vds of the PMOS transistor M3 increases (range during latch-up shown in FIG. 4). Further, the gate length and the gate width of the PMOS transistor MP3 are set so that the voltage range of the source-drain voltage Vds at the latch-up includes the threshold voltage Vth of the PMOS transistor M2.

  Subsequently, the operation of the semiconductor device 1 will be described. First, the operation during normal operation will be described. In normal operation, since the current flowing through the N well NW is small, the voltage drop at the drain of the PMOS transistor M3 is small, and the PMOS transistor M2 is not turned on by the potential transmitted by the current detection signal S1. Therefore, the drain potential of the PMOS transistor M2 is almost the ground potential. That is, the potential of the latch-up detection signal S2 is almost the ground potential. Accordingly, the power supply element 10 maintains a conductive state, and the power supply potential is supplied from the operation power supply node VDD to the internal circuit 13.

  Next, the operation when latch-up occurs will be described. When latch-up occurs, a larger current flows from the well potential supply node VDDw toward the N well NW than during normal operation. For this reason, the voltage drop at the drain of the PMOS transistor M3 becomes large, and the PMOS transistor M2 becomes conductive by the potential transmitted by the current detection signal S1. Then, the drain potential of the PMOS transistor M2 is substantially the well potential. That is, the potential of the latch-up detection signal S2 is substantially the well potential. Accordingly, the power supply element 10 is cut off, and the power supply to the internal circuit 13 is stopped.

  Thus, in the semiconductor device 1 according to the present embodiment, the current flowing into the N well NW that increases at the time of latch-up is detected, and the latch-up detection signal S2 is output according to the detected current (the signal potential is set). To raise). Then, by controlling the conduction state of the power supply element according to the potential of the latch-up detection signal S2, the current flowing from the operating power supply node VDD to the internal circuit 13 at the time of latch-up is cut off, and the temperature of the semiconductor device at the time of latch-up Prevent rise and converge latch-up condition.

  From the above description, according to the semiconductor device 1 according to the present embodiment, the current detection unit 12 detects the current flowing through the well and controls the power supply element when the current flowing through the well exceeds a predetermined level. The circuit 11 outputs a latch-up detection signal S2, and controls the conduction state of the power supply element based on the latch-up detection signal S2. Thereby, the semiconductor device 1 cuts off the current flowing from the operation power supply node VDD into the internal circuit 13 at the time of latch-up, prevents the temperature rise of the semiconductor device at the time of latch-up, and converges the latch-up state.

  Thus, the semiconductor device 1 is effective for protecting the semiconductor device 1 from latch-up. Further, in the semiconductor device 1, since it is not necessary to monitor the potential of the well, it is not necessary to provide an observation terminal or the like separately in the well. Although the circuit area may increase by receiving the observation terminal separately, the semiconductor device 1 does not increase the circuit area. Further, since the semiconductor device 1 detects the current flowing into the well that increases at the time of latch-up, it is possible to detect the latch-up with high accuracy regardless of the current consumption of the semiconductor device. Since the current flowing into the well during normal operation is much smaller than that during latch-up, there is a risk of malfunction that causes the current detection unit 12 and the power supply element control circuit 11 to malfunction during normal operation, causing the power supply element 10 to be cut off. You can think that there is almost no.

  Further, by forming the power supply element 10, the power supply element control circuit 11, and the current detection unit 12 on a well different from the internal circuit 13, the power supply element 10 due to the influence of latch-up generated in the internal circuit 13, A malfunction of the power supply element control circuit 11 and the current detection unit 12 can be prevented. The power supply element 10, the power supply element control circuit 11, and the current detection unit 12 can be realized as a device different from the semiconductor device 1. By doing so, it is possible to further improve the certainty of preventing malfunction of the power supply element 10, the power supply element control circuit 11, and the current detection unit 12 due to the latch-up generated in the internal circuit 13.

Embodiment 2
FIG. 5 shows a circuit diagram of the semiconductor device 2 according to the second embodiment. As shown in FIG. 5, the semiconductor device 2 is obtained by adding a power control circuit 14 and a signal synthesis circuit 15 to the semiconductor device 1 according to the first embodiment.

  The power supply control circuit 14 controls the power supply for each circuit block in the semiconductor device 2, for example. The power supply control circuit 14 cuts off power supply to unused circuit blocks and supplies power only to used circuit blocks. Take control. The power supply control circuit 14 outputs a power supply control signal S3 and changes the signal level depending on whether power is supplied to or shut off from the control target circuit block.

  The signal synthesis circuit 15 receives the latch-up detection signal S2 and the power supply control signal S3. When the potential of the latch-up detection signal S2 does not indicate a latch-up state (for example, when it is a ground potential), the signal level of the power supply control signal S3 is output as the block control signal S4. On the other hand, when the potential of the latch-up detection signal S2 indicates a latch-up state (for example, when it is a well potential), the block control signal S4 is set to the power supply potential or the well potential regardless of the signal level of the power control signal S3. To do. In the present embodiment, the conduction state of power supply element 10 is controlled based on this block control signal S4.

  From the above description, according to the semiconductor device 2 according to the present embodiment, when the latch-up occurs, the semiconductor device 1 according to the first embodiment prevents the heat generation of the semiconductor device due to the latch-up and converges the latch-up state, similarly to the semiconductor device 1 according to the first embodiment. Is possible. In the semiconductor device 2, in addition to the operation of the semiconductor device 1, it is possible to control the power supplied to each circuit block in the semiconductor device. This control is performed during normal operation, but has the effect of reducing power consumption according to the operating state of the semiconductor device 2.

Embodiment 3
FIG. 6 shows a circuit diagram of the semiconductor device 3 according to the third embodiment. As illustrated in FIG. 6, the semiconductor device 3 includes a current detection unit 12 a in which the current detection unit 12 of the semiconductor device 1 according to the first embodiment is configured with a resistor. The current detection unit 12a has a resistor Rm connected between the well potential supply node VDDw and the N well NW. Then, the potential of the node on the N well NW side of the resistor Rm is changed according to the current flowing through the N well NW and the resistance value of the resistor Rm. Based on this potential fluctuation, the potential of the node on the N well NW side of the resistor Rm is output as the current detection signal S1.

  In other words, the current detection unit only needs to be able to detect the current flowing into the N well NW, and can be realized by detecting the current using a resistor instead of detecting the current using a transistor.

Embodiment 4
FIG. 7 shows a circuit diagram of the semiconductor device 4 according to the fourth embodiment. As shown in FIG. 7, the semiconductor device 4 is a modification of the power supply element control circuit 11 of the semiconductor device 1 according to the first embodiment. The semiconductor device 4 includes a power supply element control circuit 11 a as a modification of the power supply element control circuit 11.

  The power supply element control circuit 11a includes a determination potential generation circuit 101 and a comparator COMP. The determination potential generation circuit 101 includes resistors R1 and R2 connected in series between, for example, a well potential supply node VDDw and a ground node GND. Then, based on the resistance ratio between the resistors R1 and R2, a potential obtained by dividing the well potential by resistance is output as the determination potential Vref. The comparator COMP receives the determination potential Vref and the current detection signal S1, and switches the signal level of the latch-up detection signal S2 output based on the magnitude relationship between the determination potential Vref and the potential of the current detection signal S1. In the present embodiment, if the potential of the current detection signal S1 is larger than the value of the determination potential Vref, the latch-up detection signal S2 is set to the power supply potential (indicating the latched-up state), and is higher than the value of the determination potential Vref. If the potential of the current detection signal S1 is small, the latch-up detection signal S2 is set to the ground potential (indicating a state in which no latch-up has occurred).

  In the semiconductor device 4, the value of the determination potential Vref can be changed based on the resistance ratio between the resistor R1 and the resistor R2. Thus, the potential of the current detection signal S1 for switching the signal level of the latch-up detection signal S2 can be changed based on the value of the determination potential Vref. That is, the semiconductor device 4 can arbitrarily set a criterion for determining the occurrence of latch-up. Thus, it is possible to arbitrarily set a reference for determining latch-up according to the function and circuit scale of the semiconductor device 4.

  Also in the fourth embodiment, the current detection unit can be configured by the resistor Rm as in the third embodiment. A circuit diagram in this case is shown in FIG.

Embodiment 5
FIG. 9 shows a schematic diagram of a planar layout of the semiconductor device 5 according to the fifth embodiment. As shown in FIG. 9, in the semiconductor device 5, a plurality of N wells NW are connected to one current detection unit 12. In semiconductor devices, wells are generally separated according to circuit blocks. The wells that supply the same well potential among the wells thus separated can be supplied with the well potential from the same well potential supply node VDDw. Therefore, it is possible to connect wells that supply the same well potential to one current detection unit 12. In this case, it is possible for one current detection unit 12 to detect that latch-up has occurred in any one of the plurality of wells. Further, with such a configuration, it is possible to suppress an increase in circuit scale of the current detection unit and the power supply element control circuit due to an increase in the number of wells.

  In FIG. 9, a deep N well is shown. The deep N well is a well formed below the P well PW and the N well NW. This deep N well may not be formed depending on the layout of the semiconductor device.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, a current detector can be provided on the P well PW side. In this case, when the current detection unit is constituted by a transistor, an NMOS transistor is used. That is, the connection location of the current detection unit can be changed as appropriate according to which well the current flowing in is detected.

1 is a circuit diagram of a semiconductor device according to a first embodiment; 1 is a schematic diagram of a planar layout of a semiconductor device according to a first embodiment; 1 is a schematic diagram of a cross section of a semiconductor device according to a first embodiment; 3 is a graph showing current-voltage characteristics of the PMOS transistor according to the first exemplary embodiment; FIG. 3 is a circuit diagram of a semiconductor device according to a second embodiment; FIG. 6 is a circuit diagram of a semiconductor device according to a third embodiment. FIG. 6 is a circuit diagram of a semiconductor device according to a fourth embodiment. FIG. 10 is a circuit diagram showing a modification of the semiconductor device according to the fourth embodiment; FIG. 9 is a schematic diagram of a planar layout of a semiconductor device according to a fourth embodiment.

Explanation of symbols

1, 2, 3, 4, 4a, 5 Semiconductor device 10 Power supply element 11, 11a Power supply element control circuit 12, 12a Current detector 13 Internal circuit 14 Power control circuit 15 Signal synthesis circuit 101 Determination potential generation circuit COMP Comparator R1 , R2, Rm Resistors M1-M3 PMOS transistors MN1-MN3 NMOS transistors MP1-MP3 PMOS transistors ND, PD Back gate terminal PD Back gate terminal NW N well PW P well STI Trench insulation film S Source D Drain G Gate S1 Current detection signal S2 Latch-up detection signal S2 Signal S3 Power supply control signal S4 Block control signal Vref Determination potential GND Ground node VDD Operation power supply node VDDw Well potential supply node

Claims (9)

A power supply element for supplying a first power to the internal circuit;
A current detector connected between a well in which the internal circuit is formed and a well potential supply terminal for supplying a well potential to the well;
A semiconductor device comprising: a power supply element control circuit that controls a conduction state of the power supply element based on a current detected by the current detection unit.   The semiconductor device according to claim 1, wherein at least one of the power supply element, the current detection unit, and the power supply element control circuit is formed on a different well from the internal circuit.   The power supply element has a source connected to a first power supply terminal for supplying the first power supply, a drain connected to the internal circuit, and a gate connected to the power supply element control circuit. The semiconductor device according to claim 1, further comprising a power switch transistor.   The current detection unit includes a source connected to the well potential supply terminal, a drain connected to the well, and a gate connected to a second power supply different from the first power supply. 4. The semiconductor device according to claim 1, wherein the well current detection transistor outputs a potential generated at the drain based on a current flowing through the well as a current detection signal.   The current detection unit is a resistance element, and the resistance element outputs a potential generated at a terminal connected to the well based on a current flowing through the well as a current detection signal. 2. A semiconductor device according to item 1.   The semiconductor device includes a power control circuit that performs power control for each circuit block in the semiconductor device, and a signal synthesis circuit that synthesizes and outputs a signal from the power supply element control circuit and a signal from the power control circuit 6. The semiconductor device according to claim 1, wherein a conduction state of the power supply element is controlled based on a signal from the signal synthesis circuit.   The power supply element control circuit includes the control transistor between a control transistor whose conduction state is controlled based on a signal from the current detection unit and a second power supply different from the first power supply. The semiconductor device according to claim 1, further comprising a resistor connected in series with the transistor for use.   The power supply element control circuit includes a determination potential generation circuit that outputs a determination potential for determining latch-up, an output terminal connected to the power supply element, and a first input terminal connected to the current detector. And a comparator provided with a second terminal connected to the determination potential generation circuit.   The semiconductor device according to claim 1, wherein the current detection unit detects a current flowing through a plurality of wells.

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