JP2009088110A

JP2009088110A - Mounting structure of semiconductor device

Info

Publication number: JP2009088110A
Application number: JP2007253751A
Authority: JP
Inventors: Kazuyoshi Arai; 一能新井
Original assignee: Casio Computer Co Ltd
Current assignee: Casio Computer Co Ltd
Priority date: 2007-09-28
Filing date: 2007-09-28
Publication date: 2009-04-23

Abstract

【課題】ＣＳＰと呼ばれる半導体構成体を複数個回路基板上に実装しても、実装面積を小さくすることができるようにする。
【解決手段】回路基板１の上面の第１の半導体構成体搭載領域２には第１の半導体構成体１１ａがフェースアップ方式で搭載され、第１の半導体構成体１１ａおよび回路基板１の上方には第２の半導体構成体１１ｂがフェースダウン方式で搭載されている。これにより、第１の半導体構成体１１ａと第２の半導体構成体１１ｂとに互いに重なり合う部分が生じ、実装面積を小さくすることができる。また、第１の半導体構成体１１ａの上面中央部に第３の半導体構成体１１ｃをフェースダウン方式で搭載すると、第３の半導体構成体１１ｃをさらに回路基板１上に実装しても、実装面積が増加しないようにすることができる。
【選択図】図２PROBLEM TO BE SOLVED: To reduce a mounting area even when a plurality of semiconductor structures called CSP are mounted on a circuit board.
A first semiconductor structure 11a is mounted in a face-up manner on a first semiconductor structure mounting region 2 on an upper surface of a circuit board 1, and above the first semiconductor structure 11a and the circuit board 1. The second semiconductor structure 11b is mounted in a face-down manner. As a result, overlapping portions are generated in the first semiconductor structure 11a and the second semiconductor structure 11b, and the mounting area can be reduced. Further, when the third semiconductor structure 11c is mounted in the center of the upper surface of the first semiconductor structure 11a by the face-down method, the mounting area can be increased even if the third semiconductor structure 11c is further mounted on the circuit board 1. Can be prevented from increasing.
[Selection] Figure 2

Description

この発明は半導体装置の実装構造に関する。 The present invention relates to a mounting structure of a semiconductor device.

従来の半導体装置には、ＣＳＰ(chip size psckage)と呼ばれるものがある（例えば、特許文献１参照）。この半導体装置は、上面に複数の接続パッドが設けられた半導体基板を備えている。半導体基板上に設けられた絶縁膜の上面には配線が接続パッドに接続されて設けられている。配線の接続パッド部上面には柱状電極が設けられている。配線を含む絶縁膜の上面には封止膜がその上面が柱状電極の上面と面一となるように設けられている。柱状電極の上面には半田ボールが設けられている。 Some conventional semiconductor devices are called CSP (chip size psckage) (see, for example, Patent Document 1). This semiconductor device includes a semiconductor substrate provided with a plurality of connection pads on the upper surface. On the upper surface of the insulating film provided on the semiconductor substrate, wirings are provided connected to connection pads. A columnar electrode is provided on the upper surface of the connection pad portion of the wiring. A sealing film is provided on the upper surface of the insulating film including the wiring so that the upper surface thereof is flush with the upper surface of the columnar electrode. Solder balls are provided on the upper surfaces of the columnar electrodes.

特開２００４−２８１６１４号公報JP 2004-281614 A

ところで、上記従来の半導体装置を回路基板上に実装する場合には、上記従来の半導体装置の半田ボールを回路基板の上面に設けられた接続端子に接合することにより、上記従来の半導体装置を回路基板上にフェースダウン方式で実装することになる。したがって、上記従来の半導体装置を複数個回路基板上に実装する場合には、回路基板上に適宜に離間させて平面的に実装することになる。 By the way, when the conventional semiconductor device is mounted on a circuit board, the solder ball of the conventional semiconductor device is joined to a connection terminal provided on the upper surface of the circuit board, whereby the conventional semiconductor device is circuitized. It will be mounted on the substrate in a face-down manner. Therefore, when mounting a plurality of the above-described conventional semiconductor devices on a circuit board, they are mounted on the circuit board in a plane with appropriate separation.

このように、上記従来の半導体装置では、回路基板上にフェースダウン方式で実装するため、複数個回路基板上に実装する場合には、回路基板上に適宜に離間させて平面的に実装することになるので、実装面積が大きくなってしまうという問題があった。 As described above, since the conventional semiconductor device is mounted on the circuit board in a face-down manner, when mounting on a plurality of circuit boards, they should be mounted on the circuit board in a plane with appropriate separation. Therefore, there is a problem that the mounting area becomes large.

そこで、この発明は、半導体構成体の実装面積を小さくすることができる半導体装置の実装構造を提供することを目的とする。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device mounting structure that can reduce the mounting area of the semiconductor structure.

請求項１に記載の発明は、上面において第１の半導体構成体搭載領域の周囲に複数の接続端子が設けられた回路基板と、前記回路基板の上面の第１の半導体構成体搭載領域にフェースアップ方式で搭載され、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する第１の半導体構成体と、前記第１の半導体構成体および前記回路基板の上方にフェースダウン方式で搭載され、半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する第２の半導体構成体とを備え、前記第２の半導体構成体の一部の外部接続用電極は前記第１の半導体構成体の外部接続用電極に第１の導電接合部材を介して接合され、前記第２の半導体構成体の残りの外部接続用電極は前記回路基板の接続端子に前記第１の導電接合部材よりも高さが高い第２の導電接合部材を介して接合されていることを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記第１の半導体構成体は前記回路基板の上面の第１の半導体構成体搭載領域に接着層を介して接着されていることを特徴とするものである。
請求項３に記載の発明は、請求項１に記載の発明において、前記第１の導電接合部材は半田ボールからなり、前記第２の導電接合部材はそれよりも大きい半田ボールからなることを特徴とするものである。
請求項４に記載の発明は、請求項３に記載の発明において、前記第１、第２の半導体構成体は、前記外部接続用電極としての柱状電極を有し、且つ、前記柱状電極間に設けられた封止膜を有することを特徴とするものである。
請求項５に記載の発明は、請求項１に記載の発明において、前記第１の半導体構成体の上方において前記第２の半導体構成体の配置領域以外の領域に、半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する第３の半導体構成体がフェースダウン方式で搭載され、前記第３の半導体構成体の外部接続用電極は前記第１の半導体構成体の外部接続用電極に第３の導電接合部材を介して接合されていることを特徴とするものである。
請求項６に記載の発明は、請求項５に記載の発明において、前記第１、第３の導電接合部材は同一の大きさの半田ボールからなり、前記第２の導電接合部材はそれよりも大きい半田ボールからなることを特徴とするものである。
請求項７に記載の発明は、請求項６に記載の発明において、前記第１〜第３の半導体構成体は、前記外部接続用電極としての柱状電極を有し、且つ、前記柱状電極間に設けられた封止膜を有することを特徴とするものである。
請求項８に記載の発明は、上面において第３の半導体構成体搭載領域の周囲に複数の外部接続用電極が設けられた第１の半導体構成体と、前記第１の半導体構成体の上面の第３の半導体構成体搭載領域にフェースアップ方式で搭載され、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する第３の半導体構成体と、前記第３の半導体構成体および前記第１の半導体構成体の上方にフェースダウン方式で搭載され、半導体基板および該半導体基板下に設けられた複数の外部接続用電極を有する第４の半導体構成体とを備え、前記第４の半導体構成体の一部の外部接続用電極は前記第３の半導体構成体の外部接続用電極に第３の導電接合部材を介して接合され、前記第４の半導体構成体の残りの外部接続用電極は前記第１の半導体構成体の外部接続用電極に前記第３の導電接合部材よりも高さが高い第４の導電接合部材を介して接合されていることを特徴とするものである。
請求項９に記載の発明は、請求項８に記載の発明において、前記第３の半導体構成体は前記第１の半導体構成体の上面の第３の半導体構成体搭載領域に接着層を介して接着されていることを特徴とするものである。
請求項１０に記載の発明は、請求項８に記載の発明において、前記第１、第３の導電接合部材は同一の大きさの半田ボールからなり、前記第４の導電接合部材はそれよりも大きい半田ボールからなることを特徴とするものである。
請求項１１に記載の発明は、請求項１０に記載の発明において、前記第１、第３、第４の半導体構成体は、前記外部接続用電極としての柱状電極を有し、且つ、前記柱状電極間に設けられた封止膜を有することを特徴とするものである。 According to the first aspect of the present invention, there is provided a circuit board having a plurality of connection terminals provided around the first semiconductor structure mounting region on the upper surface, and a face facing the first semiconductor structure mounting region on the upper surface of the circuit board. A first semiconductor structure mounted by an up system and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and a face-down system above the first semiconductor structure and the circuit board And a second semiconductor structure having a semiconductor substrate and a plurality of external connection electrodes provided under the semiconductor substrate, wherein a part of the external connection electrodes of the second semiconductor structure is The external connection electrode of the first semiconductor structure is bonded to the external connection electrode via a first conductive bonding member, and the remaining external connection electrodes of the second semiconductor structure are connected to the connection terminal of the circuit board. Conductive joint It is characterized in that the height is bonded via a high second conductive bonding members than.
According to a second aspect of the invention, in the first aspect of the invention, the first semiconductor structure is bonded to the first semiconductor structure mounting region on the upper surface of the circuit board via an adhesive layer. It is characterized by this.
According to a third aspect of the present invention, in the first aspect of the invention, the first conductive bonding member is made of a solder ball, and the second conductive bonding member is made of a larger solder ball. It is what.
According to a fourth aspect of the present invention, in the third aspect of the invention, the first and second semiconductor structural bodies have a columnar electrode as the external connection electrode, and the columnar electrode is interposed between the columnar electrodes. It has the provided sealing film, It is characterized by the above-mentioned.
According to a fifth aspect of the present invention, in the first aspect of the present invention, a semiconductor substrate and a region under the semiconductor substrate are provided above the first semiconductor structure in a region other than the arrangement region of the second semiconductor structure. A third semiconductor structure having a plurality of external connection electrodes provided on the surface is mounted in a face-down manner, and the external connection electrodes of the third semiconductor structure are for external connection of the first semiconductor structure. The electrode is bonded to the electrode via a third conductive bonding member.
According to a sixth aspect of the invention, in the fifth aspect of the invention, the first and third conductive joining members are composed of solder balls of the same size, and the second conductive joining member is more than that. It consists of a large solder ball.
The invention according to claim 7 is the invention according to claim 6, wherein the first to third semiconductor constructs have columnar electrodes as the external connection electrodes, and between the columnar electrodes. It has the provided sealing film, It is characterized by the above-mentioned.
According to an eighth aspect of the present invention, there is provided a first semiconductor structure in which a plurality of external connection electrodes are provided around the third semiconductor structure mounting region on the upper surface, and an upper surface of the first semiconductor structure. A third semiconductor structure mounted on the third semiconductor structure mounting region in a face-up manner and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and the third semiconductor structure And a fourth semiconductor structure that is mounted in a face-down manner above the first semiconductor structure and has a semiconductor substrate and a plurality of external connection electrodes provided under the semiconductor substrate, A part of the external connection electrodes of the semiconductor structure is bonded to the external connection electrode of the third semiconductor structure via a third conductive bonding member, and the remaining external connection of the fourth semiconductor structure Electrode for the first And is characterized in that it is bonded via the fourth conductive bonding member is higher height than the third conductive bonding member to the external connection electrodes of the semiconductor constructing body.
The invention according to claim 9 is the invention according to claim 8, wherein the third semiconductor structure is disposed on the third semiconductor structure mounting region on the upper surface of the first semiconductor structure via an adhesive layer. It is characterized by being bonded.
According to a tenth aspect of the present invention, in the eighth aspect of the invention, the first and third conductive joining members are made of solder balls of the same size, and the fourth conductive joining member is more than that. It consists of a large solder ball.
According to an eleventh aspect of the present invention, in the tenth aspect of the present invention, the first, third, and fourth semiconductor structural bodies have a columnar electrode as the external connection electrode, and the columnar shape. It has a sealing film provided between electrodes.

この発明によれば、回路基板の上面の第１の半導体構成体搭載領域に第１の半導体構成体をフェースアップ方式で搭載し、第１の半導体構成体および回路基板の上方に第２の半導体構成体をフェースダウン方式で搭載しているので、第１の半導体構成体と第２の半導体構成体とに互いに重なり合う部分が生じ、これにより半導体構成体の実装面積を小さくすることができる。 According to the present invention, the first semiconductor structure is mounted on the first semiconductor structure mounting region on the upper surface of the circuit board by the face-up method, and the second semiconductor is disposed above the first semiconductor structure and the circuit board. Since the structure body is mounted in a face-down manner, the first semiconductor structure body and the second semiconductor structure body are overlapped with each other, whereby the mounting area of the semiconductor structure body can be reduced.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の実装構造の要部の平面図を示し、図２は図１のII−II線に沿う断面図を示す。この半導体装置の実装構造では、簡単に説明すると、回路基板１の上面に第１の半導体構成体１１ａがフェースアップ方式で搭載され、第１の半導体構成体１１ａの４辺部の各中央部およびその各外側における回路基板１の上方に４つの第２の半導体構成体１１ｂがフェースダウン方式で搭載され、第１の半導体構成体１１ａの上面中央部に第３の半導体構成体１１ｃがフェースダウン方式で搭載されている。 (First embodiment)
FIG. 1 shows a plan view of the main part of a mounting structure of a semiconductor device as a first embodiment of the present invention, and FIG. 2 shows a cross-sectional view taken along line II-II in FIG. In this semiconductor device mounting structure, in brief, the first semiconductor structure 11a is mounted on the upper surface of the circuit board 1 in a face-up manner, and each central part of the four sides of the first semiconductor structure 11a and Four second semiconductor structures 11b are mounted on the outside of the circuit board 1 on each outer side in a face-down manner, and a third semiconductor structure 11c is face-down in the center of the upper surface of the first semiconductor structure 11a. It is mounted with.

このうち、回路基板１の上面において平面正方形状の第１の半導体構成体搭載領域２の周囲には複数の接続端子３が設けられている。接続端子３は、回路基板１の上面に設けられた配線（図示せず）の一端部に接続されている。 Among these, a plurality of connection terminals 3 are provided around the first semiconductor structure mounting region 2 having a planar square shape on the upper surface of the circuit board 1. The connection terminal 3 is connected to one end of a wiring (not shown) provided on the upper surface of the circuit board 1.

第１〜第３の半導体構成体１１ａ、１１ｂ、１１ｃは、一般的にはＣＳＰと呼ばれるものであり、基本的な構成は同じである。すなわち、第１〜第３の半導体構成体１１ａ、１１ｂ、１１ｃは、平面正方形状または長方形状のシリコン基板（半導体基板）１２ａ、１２ｂ、１２ｃを備えている。シリコン基板１２ａ（１２ｂ、１２ｃ）の上面（下面）には所定の機能の集積回路（図示せず）が設けられ、上面（下面）周辺部にはアルミニウム系金属等からなる複数の接続パッド１３ａ（１３ｂ、１３ｃ）が集積回路に接続されて設けられている。 The first to third semiconductor structures 11a, 11b, and 11c are generally called CSPs, and the basic structure is the same. That is, the first to third semiconductor constructs 11a, 11b, and 11c include silicon substrates (semiconductor substrates) 12a, 12b, and 12c having a planar square shape or a rectangular shape. An integrated circuit (not shown) having a predetermined function is provided on the upper surface (lower surface) of the silicon substrate 12a (12b, 12c), and a plurality of connection pads 13a (such as aluminum-based metal) are provided on the periphery of the upper surface (lower surface). 13b, 13c) are provided connected to the integrated circuit.

接続パッド１３ａ（１３ｂ、１３ｃ）の中央部を除くシリコン基板１２ａ（１２ｂ、１２ｃ）の上面（下面）には絶縁膜１４ａ（１４ｂ、１４ｃ）が設けられ、接続パッド１３ａ（１３ｂ、１３ｃ）の中央部は絶縁膜１４ａ（１４ｂ、１４ｃ）に設けられた開口部１５ａ（１５ｂ、１５ｃ）を介して露出されている。絶縁膜１４ａ（１４ｂ、１４ｃ）は、酸化シリコン等からなる単層であってもよく、その上面にポリイミド系樹脂等からなる絶縁膜（保護膜）が設けられた２層構造であってもよい。 An insulating film 14a (14b, 14c) is provided on the upper surface (lower surface) of the silicon substrate 12a (12b, 12c) excluding the central portion of the connection pad 13a (13b, 13c), and the center of the connection pad 13a (13b, 13c). The part is exposed through the opening 15a (15b, 15c) provided in the insulating film 14a (14b, 14c). The insulating film 14a (14b, 14c) may be a single layer made of silicon oxide or the like, or may have a two-layer structure in which an insulating film (protective film) made of polyimide resin or the like is provided on the upper surface thereof. .

絶縁膜１４ａ（１４ｂ、１４ｃ）の上面（下面）には配線１６ａ（１６ｂ、１６ｃ）が設けられている。配線１６ａ（１６ｂ、１６ｃ）は、詳細には図示していないが、絶縁膜１４ａ（１４ｂ、１４ｃ）の上面（下面）に設けられた銅等からなる下地金属層と、下地金属層の上面（下面）に設けられた銅からなる上部金属層との２層構造となっている。配線１６ａ（１６ｂ、１６ｃ）の一端部は、絶縁膜１４ａ（１４ｂ、１４ｃ）の開口部１５ａ（１５ｂ、１５ｃ）を介して接続パッド１３ａ（１３ｂ、１３ｃ）に接続されている。 A wiring 16a (16b, 16c) is provided on the upper surface (lower surface) of the insulating film 14a (14b, 14c). Although not shown in detail, the wiring 16a (16b, 16c) includes a base metal layer made of copper or the like provided on the upper surface (lower surface) of the insulating film 14a (14b, 14c), and an upper surface ( It has a two-layer structure with an upper metal layer made of copper provided on the lower surface. One end of the wiring 16a (16b, 16c) is connected to the connection pad 13a (13b, 13c) through the opening 15a (15b, 15c) of the insulating film 14a (14b, 14c).

配線１６ａ（１６ｂ、１６ｃ）の接続パッド部上面（下面）には銅からなる柱状電極（外部接続用電極）１７ａ（１７ｂ、１７ｃ）が設けられている。配線１６ａ（１６ｂ、１６ｃ）を含む絶縁膜１４ａ（１４ｂ、１４ｃ）の上面（下面）にはエポキシ系樹脂等からなる封止膜１８ａ（１８ｂ、１８ｃ）がその上面（下面）が柱状電極１７ａ（１７ｂ、１７ｃ）の上面（下面）と面一となるように設けられている。ここまでが、第１〜第３の半導体構成体１１ａ、１１ｂ、１１ｃの基本的な構成が同じ部分である。 Columnar electrodes (external connection electrodes) 17a (17b, 17c) made of copper are provided on the upper surface (lower surface) of the connection pad portion of the wiring 16a (16b, 16c). On the upper surface (lower surface) of the insulating film 14a (14b, 14c) including the wiring 16a (16b, 16c), the sealing film 18a (18b, 18c) made of epoxy resin or the like is formed on the upper surface (lower surface) of the columnar electrode 17a (the lower surface). 17b, 17c) and the upper surface (lower surface). Up to this point, the basic configurations of the first to third semiconductor structures 11a, 11b, and 11c are the same.

次に、第２、第３の半導体構成体１１ｂ、１１ｃの構成が第１の半導体構成体１１ａの構成と異なる点について説明する。第２の半導体構成体１１ｂでは、一部の柱状電極１７ｂの下面に第１の半田ボール（第１の導電接合部材）２０ｂが設けられ、残りの柱状電極１７ｂの下面に第２の半田ボール（第２の導電接合部材）２１ｂが設けられている。この場合、第２の半田ボール２１ｂの大きさ（高さ）は第１の半田ボール２０ｂの大きさ（高さ）よりも大きく（高く）なっている。 Next, the difference between the configuration of the second and third semiconductor structures 11b and 11c and the configuration of the first semiconductor structure 11a will be described. In the second semiconductor structure 11b, the first solder balls (first conductive bonding members) 20b are provided on the lower surfaces of some of the columnar electrodes 17b, and the second solder balls (first conductive balls) are provided on the lower surfaces of the remaining columnar electrodes 17b. A second conductive joining member) 21b is provided. In this case, the size (height) of the second solder ball 21b is larger (higher) than the size (height) of the first solder ball 20b.

第３の半導体構成体１１ｃでは、柱状電極１７ｃの下面に半田ボール（第３の導電接合部材）２０ｃが設けられている。この場合、半田ボール２０ｃの大きさ（高さ）は、第２の半導体構成体１１ｂの第１の半田ボール２０ｂの大きさ（高さ）と同じとなっている。 In the third semiconductor structure 11c, a solder ball (third conductive bonding member) 20c is provided on the lower surface of the columnar electrode 17c. In this case, the size (height) of the solder ball 20c is the same as the size (height) of the first solder ball 20b of the second semiconductor structure 11b.

そして、第１の半導体構成体１１ａは、そのシリコン基板１２ａの下面に予め設けられたダイボンド材からなる接着層１９ａが回路基板１の上面の第１の半導体構成体搭載領域２に接着されていることにより、回路基板１の上面の第１の半導体構成体搭載領域２にフェースアップ方式で搭載されている。 The first semiconductor structure 11a is bonded to the first semiconductor structure mounting region 2 on the upper surface of the circuit board 1 by an adhesive layer 19a made of a die bond material provided in advance on the lower surface of the silicon substrate 12a. Thus, the circuit board 1 is mounted on the first semiconductor component mounting region 2 on the upper surface in a face-up manner.

第２の半導体構成体１１ｂは、その第１の半田ボール２０ｂが第１の半導体構成体１１ａの周辺部に配置された柱状電極１７ａの上面に接合され、且つ、その第２の半田ボール２１ｂが回路基板１の接続端子３に接合された状態で、第１の半導体構成体１１ａの４辺部の各中央部およびその各外側における回路基板１の上方にフェースダウン方式で搭載されている。 In the second semiconductor structure 11b, the first solder ball 20b is joined to the upper surface of the columnar electrode 17a disposed in the peripheral portion of the first semiconductor structure 11a, and the second solder ball 21b is In a state of being joined to the connection terminal 3 of the circuit board 1, the first semiconductor structure 11 a is mounted in a face-down manner on each central part of the four sides and on the outer side of the circuit board 1.

第３の半導体構成体１１ｃは、その半田ボール２０ｃが第１の半導体構成体１１ａの中央部に配置された柱状電極１７ａの上面に接合された状態で、第１の半導体構成体１１ａの上面中央部にフェースダウン方式で搭載されている。 The third semiconductor structure 11c has the upper center of the first semiconductor structure 11a in a state where the solder ball 20c is joined to the upper surface of the columnar electrode 17a disposed at the center of the first semiconductor structure 11a. It is mounted in the face down method.

以上のように、この半導体装置の実装構造では、回路基板１の上面の第１の半導体構成体搭載領域２に第１の半導体構成体１１ａをフェースアップ方式で搭載し、第１の半導体構成体１１ａおよび回路基板１の上方に第２の半導体構成体１１ｂをフェースダウン方式で搭載しているので、第１の半導体構成体１１ａと第２の半導体構成体１１ｂとに互いに重なり合う部分が生じ、これにより第１、第２の半導体構成体１１ａ、１１ｂを回路基板１上に実装しても、実装面積を小さくすることができる。 As described above, in the mounting structure of the semiconductor device, the first semiconductor structure 11a is mounted on the first semiconductor structure mounting region 2 on the upper surface of the circuit board 1 by the face-up method, and the first semiconductor structure is formed. Since the second semiconductor structure 11b is mounted in a face-down manner above the circuit board 1 and the circuit board 1, there is an overlapping portion between the first semiconductor structure 11a and the second semiconductor structure 11b. Therefore, even if the first and second semiconductor structures 11a and 11b are mounted on the circuit board 1, the mounting area can be reduced.

また、この半導体装置の実装構造では、第１の半導体構成体１１ａの上面中央部に第３の半導体構成体１１ｃをフェースダウン方式で搭載しているので、第３の半導体構成体１１ｃをさらに回路基板１上に実装しても、第１、第２の半導体構成体１１ａ、１１ｂを回路基板１上に実装した場合と比較して、実装面積が増加しないようにすることができる。 In this semiconductor device mounting structure, since the third semiconductor structure 11c is mounted in a face-down manner at the center of the upper surface of the first semiconductor structure 11a, the third semiconductor structure 11c is further circuitized. Even when mounted on the substrate 1, the mounting area can be prevented from increasing as compared with the case where the first and second semiconductor constructs 11 a and 11 b are mounted on the circuit substrate 1.

ここで、第２の半導体構成体１１ｂにおける第１、第２の半田ボール２０ｂ、２１ｂの形成方法の一例について簡単に説明する。まず、第１、第２の半田ボール２０ｂ、２１ｂを有しない状態における第２の半導体構成体１１ｂをその柱状電極１７ｂ、１７ｂが上側に位置する状態とする。次に、第２の半導体構成体１１ｂの柱状電極１７ｂ、１７ｂの上面にスクリーン印刷法等によりフラックスを塗布する。 Here, an example of a method of forming the first and second solder balls 20b and 21b in the second semiconductor structure 11b will be briefly described. First, the second semiconductor structure 11b without the first and second solder balls 20b and 21b is in a state in which the columnar electrodes 17b and 17b are positioned on the upper side. Next, a flux is applied to the upper surfaces of the columnar electrodes 17b and 17b of the second semiconductor structure 11b by a screen printing method or the like.

次に、小径半田ボール搭載マスクを用い、第２の半導体構成体１１ｂの一部の柱状電極１７ｂの上面のフラックス上に小径半田ボールを搭載する。次に、大径半田ボール搭載マスクを用い、第２の半導体構成体１１ｂの残りの柱状電極１７ｂの上面のフラックス上に大径半田ボールを搭載する。次に、半田リフロー装置を用いて半田付けを行なうリフロー法により、第２の半導体構成体１１ｂの柱状電極１７ｂ、１７ｂの上面に第１、第２の半田ボール２０ｂ、２１ｂを形成する。 Next, using a small-diameter solder ball mounting mask, small-diameter solder balls are mounted on the flux on the upper surface of the columnar electrodes 17b of a part of the second semiconductor structure 11b. Next, using a large-sized solder ball mounting mask, large-sized solder balls are mounted on the flux on the upper surface of the remaining columnar electrodes 17b of the second semiconductor structure 11b. Next, the first and second solder balls 20b and 21b are formed on the upper surfaces of the columnar electrodes 17b and 17b of the second semiconductor structure 11b by a reflow method in which soldering is performed using a solder reflow apparatus.

次に、第１〜第３の半導体構成体１１ａ、１１ｂ、１１ｃの実装方法の一例について簡単に説明する。まず、回路基板１の上面の第１の半導体構成体搭載領域２に、第１の半導体構成体１１ａのシリコン基板１２ａの下面に予め設けられた接着層１９ａを接着することにより、第１の半導体構成体１１ａをフェースアップ方式で搭載する。 Next, an example of a mounting method of the first to third semiconductor structures 11a, 11b, and 11c will be briefly described. First, an adhesive layer 19a provided in advance on the lower surface of the silicon substrate 12a of the first semiconductor structure 11a is bonded to the first semiconductor structure mounting region 2 on the upper surface of the circuit board 1 to thereby form the first semiconductor. The structure 11a is mounted in a face-up manner.

次に、第１の半導体構成体１１ａの柱状電極１７ａの上面および回路基板１の接続端子３の上面にスクリーン印刷法等によりフラックスを塗布する。次に、フリップチップマウンターまたはフリップチップボンダーを用い、第１、第２の半田ボール２０ｂ、２１ｂを有する第２の半導体構成体１１ｂを搭載し、また半田ボール２０ｃを有する第３の半導体構成体１１ｃを搭載する。この場合、第２、第３の半導体構成体１１ｂ、１１ｃの搭載はいずれを先に行なってもよい。 Next, flux is applied to the upper surface of the columnar electrode 17a of the first semiconductor structure 11a and the upper surface of the connection terminal 3 of the circuit board 1 by screen printing or the like. Next, using a flip chip mounter or a flip chip bonder, the second semiconductor structure 11b having the first and second solder balls 20b and 21b is mounted, and the third semiconductor structure 11c having the solder balls 20c is mounted. Is installed. In this case, the mounting of the second and third semiconductor structures 11b and 11c may be performed first.

なお、第２の半導体構成体１１ｂの一部の柱状電極１７ｂ下に小径の第１の半田ボール２０ｂを形成し、且つ、回路基板１の接続端子３上に大径の第２の半田ボール２１ｂを形成しておいて、第２の半導体構成体１１ｂの搭載を行なうようにしてもよい。また、第１の半導体構成体１１ａの周辺部に配置された柱状電極１７ａ上に小径の第１の半田ボール２０ｂを形成し、且つ、回路基板１の接続端子３上に大径の第２の半田ボール２１ｂを形成しておいて、第２の半導体構成体１１ｂの搭載を行なうようにしてもよい。 A first solder ball 20b having a small diameter is formed below a part of the columnar electrodes 17b of the second semiconductor structure 11b, and a second solder ball 21b having a large diameter is formed on the connection terminal 3 of the circuit board 1. The second semiconductor structure 11b may be mounted. A first solder ball 20b having a small diameter is formed on the columnar electrode 17a disposed in the periphery of the first semiconductor structure 11a, and a second large diameter is formed on the connection terminal 3 of the circuit board 1. The solder ball 21b may be formed and the second semiconductor structure 11b may be mounted.

（第２実施形態）
図３はこの発明の第２実施形態としての半導体装置の実装構造の図２同様の断面図を示す。この半導体装置の実装構造において、図２に示す半導体装置の実装構造と大きく異なる点は、第１の半導体構成体１１ａの上面中央部に、サイズが比較的小さくて半田ボールを有しない第３の半導体構成体１１ｃをフェースアップ方式で搭載し、第３の半導体構成体１１ｃおよびその周囲における第１の半導体構成体１１ａの上方に第４の半導体構成体１１ｄをフェースダウン方式で搭載した点である。 (Second Embodiment)
FIG. 3 is a cross-sectional view similar to FIG. 2 of a semiconductor device mounting structure according to a second embodiment of the present invention. This semiconductor device mounting structure is significantly different from the semiconductor device mounting structure shown in FIG. 2 in that the third size of the semiconductor device 11a is relatively small and has no solder balls at the center of the upper surface of the first semiconductor structure 11a. The semiconductor structure 11c is mounted by the face-up method, and the fourth semiconductor structure 11d is mounted by the face-down method above the third semiconductor structure 11c and the first semiconductor structure 11a around it. .

この場合、第３の半導体構成体１１ｃは、そのシリコン基板１２ｃの下面に予め設けられたダイボンド材からなる接着層１９ｃが第１の半導体構成体１１ａの中央部の封止膜１８ａの上面に接着されていることにより、第１の半導体構成体１１ａの上面中央部にフェースアップ方式で搭載されている。 In this case, in the third semiconductor structure 11c, an adhesive layer 19c made of a die bond material provided in advance on the lower surface of the silicon substrate 12c is bonded to the upper surface of the sealing film 18a at the center of the first semiconductor structure 11a. As a result, it is mounted in a face-up manner at the center of the upper surface of the first semiconductor structure 11a.

第４の半導体構成体１１ｄは、その下面中央部に配置された柱状電極１７ｄの下面に設けられた比較的小径の第１の半田ボール（第３の導電接合部材）２０ｄが第３の半導体構成体１１ｃの柱状電極１７ｃの上面に接合され、且つ、その下面周辺部に配置された柱状電極１７ｄの下面に設けられた比較的大径の第２の半田ボール（第４の導電接合部材）２１ｄが第１の半導体構成体１１ａの柱状電極１７ａの上面に接合された状態で、第３の半導体構成体１１ｃおよびその周囲における第１の半導体構成体１１ａの上方にフェースダウン方式で搭載されている。 In the fourth semiconductor structure 11d, the first solder ball (third conductive bonding member) 20d having a relatively small diameter provided on the lower surface of the columnar electrode 17d disposed at the center of the lower surface is the third semiconductor structure. A second solder ball (fourth conductive bonding member) 21d having a relatively large diameter, which is bonded to the upper surface of the columnar electrode 17c of the body 11c and provided on the lower surface of the columnar electrode 17d disposed around the lower surface thereof. Is mounted in a face-down manner above the third semiconductor structure 11c and the first semiconductor structure 11a around the third semiconductor structure 11c in a state of being bonded to the upper surface of the columnar electrode 17a of the first semiconductor structure 11a. .

以上のように、この半導体装置の実装構造では、第１の半導体構成体１１ａの上面中央部に第３の半導体構成体１１ｃをフェースアップ方式で搭載し、第３の半導体構成体１１ｃおよびその周囲における第１の半導体構成体１１ａの上方に第４の半導体構成体１１ｄをフェースダウン方式で搭載しているので、第３、第４の半導体構成体１１ｃ、１１ｄをさらに回路基板１上に実装しても、第１、第２の半導体構成体１１ａ、１１ｂを回路基板１上に実装した場合と比較して、実装面積が増加しないようにすることができる。 As described above, in this semiconductor device mounting structure, the third semiconductor structure 11c is mounted in a face-up manner at the center of the upper surface of the first semiconductor structure 11a, and the third semiconductor structure 11c and its surroundings are mounted. Since the fourth semiconductor structure 11d is mounted in a face-down manner above the first semiconductor structure 11a in FIG. 3, the third and fourth semiconductor structures 11c and 11d are further mounted on the circuit board 1. However, compared with the case where the 1st, 2nd semiconductor structure 11a, 11b is mounted on the circuit board 1, it can prevent a mounting area increasing.

ところで、この実施形態においても、第４の半導体構成体１１ｄの一部の柱状電極１７ｄ下に小径の第３の半田ボール２０ｄを形成し、且つ、第１の半導体構成体１１ａの所定の柱状電極１７ａ上に大径の第４の半田ボール２１ｄを形成しておいて、第４の半導体構成体１１ｄの搭載を行なうようにしてもよい。また、第３の半導体構成体１１ｃの柱状電極１７ｃ上に小径の第３の半田ボール２０ｄを形成し、且つ、第１の半導体構成体１１ａの所定の柱状電極１７ａ上に大径の第４の半田ボール２１ｄを形成しておいて、第４の半導体構成体１１ｄの搭載を行なうようにしてもよい。 By the way, also in this embodiment, the third solder ball 20d having a small diameter is formed under a part of the columnar electrode 17d of the fourth semiconductor structure 11d, and the predetermined columnar electrode of the first semiconductor structure 11a is formed. A fourth solder ball 21d having a large diameter may be formed on 17a, and the fourth semiconductor structure 11d may be mounted. Further, a third solder ball 20d having a small diameter is formed on the columnar electrode 17c of the third semiconductor structure 11c, and a fourth electrode having a large diameter is formed on the predetermined columnar electrode 17a of the first semiconductor structure 11a. The solder ball 21d may be formed, and the fourth semiconductor structure 11d may be mounted.

なお、第２の実施形態において、第１の半導体構成体１１ａの周縁部に配置された第２の半導体構成体１１ｂを搭載せずに、フレキシブル基板等を用いて、第１の半導体構成体１１ａの柱状電極１７ａを回路基板１の接続端子３に接続するようにしてもよい。すなわち、第１の半導体構成体１１ａの上面の第３の半導体構成体搭載領域に第３の半導体構成体１１ｃをフェースアップ方式で搭載し、第３の半導体構成体１１ｃおよび第１の半導体構成体１１ａの上方に第４の半導体構成体１１ｄをフェースダウン方式で搭載しているので、第１の半導体構成体１１ａ、第３の半導体構成体１１ｃおよび第４の半導体構成体１１ｄとに互いに重なり合う部分が生じ、これにより半導体構成体の実装面積を小さくすることができる。 In the second embodiment, the first semiconductor structure 11a is formed using a flexible substrate or the like without mounting the second semiconductor structure 11b disposed on the peripheral portion of the first semiconductor structure 11a. The columnar electrode 17 a may be connected to the connection terminal 3 of the circuit board 1. That is, the third semiconductor structure 11c is mounted in a face-up manner on the third semiconductor structure mounting region on the upper surface of the first semiconductor structure 11a, and the third semiconductor structure 11c and the first semiconductor structure are mounted. Since the fourth semiconductor structure 11d is mounted in a face-down manner above 11a, the first semiconductor structure 11a, the third semiconductor structure 11c, and the fourth semiconductor structure 11d overlap each other. As a result, the mounting area of the semiconductor structure can be reduced.

（第３実施形態）
図４はこの発明の第３実施形態としての半導体装置の実装構造の図２同様の断面図を示す。この半導体装置の実装構造において、図２に示す半導体装置の実装構造と大きく異なる点は、第１〜第３の半導体構成体１１ａ、１１ｂ、１１ｃが柱状電極１７ａ、１７ｂ、１７ｃおよび封止膜１８ａ、１８ｂ、１８ｃを備えていない点である。 (Third embodiment)
FIG. 4 is a sectional view similar to FIG. 2 of a semiconductor device mounting structure as a third embodiment of the present invention. This semiconductor device mounting structure differs greatly from the semiconductor device mounting structure shown in FIG. 2 in that the first to third semiconductor constructs 11a, 11b, and 11c are columnar electrodes 17a, 17b, and 17c and a sealing film 18a. , 18b, 18c are not provided.

この場合、第１〜第３の半導体構成体１１ａ、１１ｂ、１１ｃにおいては、配線１６ａ、１６ｂ、１６ｃを含む絶縁膜１４ａ、１４ｂ、１４ｃの上面または下面にソルダーレジスト等からなるオーバーコート膜３１ａ、３１ｂ、３１ｃが設けられている。配線１６ａ、１６ｂ、１６ｃの接続パッド部に対応する部分におけるオーバーコート膜３１ａ、３１ｂ、３１ｃには開口部３２ａ、３２ｂ、３２ｃが設けられている。 In this case, in the first to third semiconductor constructs 11a, 11b, and 11c, the overcoat film 31a made of a solder resist or the like is formed on the upper surface or the lower surface of the insulating films 14a, 14b, and 14c including the wirings 16a, 16b, and 16c. 31b and 31c are provided. Openings 32a, 32b, and 32c are provided in the overcoat films 31a, 31b, and 31c in portions corresponding to the connection pad portions of the wirings 16a, 16b, and 16c.

第２の半導体構成体１１ｂにおいては、オーバーコート膜３１ｂの開口部３２ｂ内およびその下方に第１、第２の半田ボール２０ｂ、２１ｂが配線１６ｂ、１６ｂの接続パッド部に接続されて設けられている。第３の半導体構成体１１ｃにおいては、オーバーコート膜３１ｃの開口部３２ｃ内およびその下方に半田ボール２０ｃが配線１６ｃの接続パッド部に接続されて設けられている。 In the second semiconductor structure 11b, first and second solder balls 20b and 21b are provided in and below the opening 32b of the overcoat film 31b so as to be connected to the connection pads of the wirings 16b and 16b. Yes. In the third semiconductor structure 11c, solder balls 20c are provided in and below the opening 32c of the overcoat film 31c so as to be connected to the connection pad portion of the wiring 16c.

そして、第２の半導体構成体１１ｂは、その第１の半田ボール２０ｂが第１の半導体構成体１１ａの周辺部に配置された配線１６ａの接続パッド部上面に接合され、且つ、その第２の半田ボール２１ｂが回路基板１の接続端子３に接合された状態で、第１の半導体構成体１１ａの４辺部の各中央部およびその各外側における回路基板１の上方に搭載されている。 In the second semiconductor structure 11b, the first solder ball 20b is bonded to the upper surface of the connection pad portion of the wiring 16a disposed in the periphery of the first semiconductor structure 11a, and the second semiconductor structure 11b In a state where the solder balls 21 b are joined to the connection terminals 3 of the circuit board 1, the solder balls 21 b are mounted above the circuit board 1 at the center of each of the four sides of the first semiconductor structure 11 a and outside thereof.

第３の半導体構成体１１ｃは、その半田ボール２０ｃが第１の半導体構成体１１ａの中央部に配置された配線１６ａの接続パッド部上面に接合された状態で、第１の半導体構成体１１ａの上面中央部に搭載されている。 The third semiconductor structure 11c has the solder ball 20c bonded to the upper surface of the connection pad portion of the wiring 16a disposed at the center of the first semiconductor structure 11a. It is mounted on the top center.

（その他の実施形態）
例えば、図２において、半田ボール２０ｂ、２１ｂ、２０ｃを用いずに、半田ペーストや導電性接着剤等からなる導電接合部材を用いるようにしてもよい。この場合、例えば、第２の半導体構成体１１ｂにおいて、柱状電極１７ｂ、１７ｂの下面に半田ペーストや導電性接着剤等からなる導電接合部材を一様に塗布し、且つ、回路基板１の接続端子３の上面に半田ペーストや導電性接着剤等からなる導電接合部材を塗布し、これにより、高さの異なる第１、第２の半田ボール２０ｂ、２１ｂの代わりとして、高さの異なる第１、第２の導電接合部材を得るようにしてもよい。 (Other embodiments)
For example, in FIG. 2, instead of using the solder balls 20b, 21b, and 20c, a conductive bonding member made of a solder paste, a conductive adhesive, or the like may be used. In this case, for example, in the second semiconductor structure 11b, a conductive bonding member made of solder paste, conductive adhesive, or the like is uniformly applied to the lower surfaces of the columnar electrodes 17b and 17b, and the connection terminals of the circuit board 1 3 is coated with a conductive bonding member made of a solder paste, a conductive adhesive, or the like, so that the first and second solder balls 20b, 21b having different heights can be replaced with the first, A second conductive joining member may be obtained.

この発明の第１実施形態としての半導体装置の実装構造の要部の平面図。The top view of the principal part of the mounting structure of the semiconductor device as 1st Embodiment of this invention. 図１のII−II線に沿う断面図。Sectional drawing which follows the II-II line | wire of FIG. この発明の第２実施形態としての半導体装置の実装構造の図２同様の断面図。Sectional drawing similar to FIG. 2 of the mounting structure of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の実装構造の図２同様の断面図。Sectional drawing similar to FIG. 2 of the mounting structure of the semiconductor device as 3rd Embodiment of this invention.

Explanation of symbols

１回路基板
２第１の半導体構成体搭載領域
３接続端子
１１ａ第１の半導体構成体
１１ｂ第２の半導体構成体
１１ｃ第３の半導体構成体
１１ｄ第４の半導体構成体
１２ａ、１２ｂ、１２ｃシリコン基板
１６ａ、１６ｂ、１６ｃ配線
１７ａ、１７ｂ、１７ｃ、１７ｄ柱状電極
１８ａ、１８ｂ、１８ｃ封止膜
１９ａ、１９ｃ接着層
２０ｂ第１の半田ボール
２１ｂ第２の半田ボール
２０ｃ半田ボール
２０ｄ第３の半田ボール
２１ｄ第４の半田ボール DESCRIPTION OF SYMBOLS 1 Circuit board 2 1st semiconductor structure mounting area | region 3 Connection terminal 11a 1st semiconductor structure 11b 2nd semiconductor structure 11c 3rd semiconductor structure 11d 4th semiconductor structure 12a, 12b, 12c Silicon substrate 16a, 16b, 16c Wirings 17a, 17b, 17c, 17d Columnar electrodes 18a, 18b, 18c Sealing films 19a, 19c Adhesive layer 20b First solder ball 21b Second solder ball 20c Solder ball 20d Third solder ball 21d Fourth solder ball

Claims

A circuit board provided with a plurality of connection terminals around the first semiconductor structure mounting region on the upper surface, and mounted in a face-up manner on the first semiconductor structure mounting region on the upper surface of the circuit board; A first semiconductor structure having a plurality of external connection electrodes provided on the semiconductor substrate, and mounted in a face-down manner on the first semiconductor structure and the circuit board, the semiconductor substrate and the semiconductor And a second semiconductor structure having a plurality of external connection electrodes provided under the substrate, wherein some of the external connection electrodes of the second semiconductor structure are external connections of the first semiconductor structure. And the remaining external connection electrodes of the second semiconductor structure are higher in the connection terminals of the circuit board than the first conductive bonding members. Second Mounting structure of a semiconductor device characterized by being bonded via a conductive bonding member.

2. The semiconductor device mounting according to claim 1, wherein the first semiconductor structure is bonded to a first semiconductor structure mounting region on an upper surface of the circuit board via an adhesive layer. Construction.

2. The semiconductor device mounting structure according to claim 1, wherein the first conductive bonding member is made of a solder ball, and the second conductive bonding member is made of a solder ball larger than the solder ball.

The invention according to claim 3, wherein the first and second semiconductor structural bodies have columnar electrodes as the external connection electrodes and have a sealing film provided between the columnar electrodes. A mounting structure of a semiconductor device.

2. The semiconductor substrate according to claim 1, wherein the semiconductor substrate and a plurality of external connections provided under the semiconductor substrate are provided above the first semiconductor structure in a region other than the arrangement region of the second semiconductor structure. A third semiconductor structure having electrodes is mounted in a face-down manner, and an external connection electrode of the third semiconductor structure has a third conductive bonding member applied to the external connection electrode of the first semiconductor structure. A mounting structure of a semiconductor device, wherein

The invention according to claim 5 is characterized in that the first and third conductive joint members are made of solder balls of the same size, and the second conductive joint member is made of solder balls larger than that. Mounting structure of a semiconductor device.

The invention according to claim 6, wherein the first to third semiconductor structures have columnar electrodes as the external connection electrodes and have a sealing film provided between the columnar electrodes. A mounting structure of a semiconductor device.

A first semiconductor structure in which a plurality of external connection electrodes are provided around the third semiconductor structure mounting region on the upper surface; and a third semiconductor structure mounting region on the upper surface of the first semiconductor structure. A third semiconductor structure mounted in a face-up manner and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and the third semiconductor structure and the first semiconductor structure A semiconductor substrate and a fourth semiconductor structure having a plurality of external connection electrodes provided under the semiconductor substrate, the semiconductor device including a part of the fourth semiconductor structure The connection electrode is bonded to the external connection electrode of the third semiconductor structure via a third conductive bonding member, and the remaining external connection electrodes of the fourth semiconductor structure are the first semiconductor structure. Body external connection Mounting structure of a semiconductor device, wherein a height is bonded via a high fourth conductive joining member than the the electrode third conductive bonding member.

The invention according to claim 8 is characterized in that the third semiconductor structure is bonded to a third semiconductor structure mounting region on the upper surface of the first semiconductor structure via an adhesive layer. Semiconductor device mounting structure.

The invention according to claim 8 is characterized in that the first and third conductive joint members are made of solder balls of the same size, and the fourth conductive joint member is made of solder balls larger than that. Mounting structure of a semiconductor device.

11. The sealing film provided in the invention according to claim 10, wherein the first, third, and fourth semiconductor structural bodies have columnar electrodes as the external connection electrodes, and are provided between the columnar electrodes. A mounting structure of a semiconductor device, comprising: