JPH11204565A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device having a wide wiring area, a plurality of semiconductor elements mounted and mounted at high density, and suppressing deformation such as warpage. SOLUTION: In the semiconductor device of the present invention, a copper wiring layer 12 is formed on both surfaces of an insulating resin film 11 having a thickness similar to that of a semiconductor chip, and a group of inner leads 13 is provided on a lower surface. Further, via holes 14 are provided at predetermined positions for conducting the copper wiring layers 12 on both surfaces, and solder bumps 18 are arranged on the lower surface of the copper wiring layers 12 in a grid pattern. Then, the upper and lower two-stage semiconductor chips 16b and 16a are mounted, and the lower-stage chip is fitted into the device hole 11a and subjected to ILB.
The upper chip is flip-chip connected to the copper wiring layer 12 on the upper surface. Further, a resin sealing layer 17 is provided so as to cover these joints and the like, and a metal cover plate 19 is further integrally provided thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a resin-sealed semiconductor device in which a plurality of semiconductor elements are mounted in a multi-layer and at a high density.

[0002]

2. Description of the Related Art Conventionally, a TCP (tape carrier package) in which a semiconductor element is mounted on a film carrier tape and mounted for the purpose of reducing costs and simplifying the configuration.
As a film carrier tape, a single-layer wiring tape in which a wiring pattern such as a copper foil is provided only on one surface of an insulating resin film is used. In such a TCP, a ball grid array (hereinafter, referred to as an array) in which balls of solder or the like are arranged in a grid (array) as external connection terminals from the viewpoints of increasing the number of connection terminals, miniaturizing the outer shape, and facilitating mounting. , BGA) are employed.

Conventional tape carrier type BGA
An example of the structure of a (T-BGA) type semiconductor device is shown in FIG. 7 and FIG.

In the figure, reference numeral 1 denotes a device hole 1
a, an insulating resin film (eg, a polyimide resin film) having a, reference numeral 2 denotes a wiring layer such as a copper foil disposed on one surface (the lower surface in the figure) of the insulating resin film 1;
Is an inner lead having one end connected to the wiring layer 2 and the other end protruding into the device hole 1a;
Reference numeral 4 denotes a semiconductor chip arranged face-down, and each electrode terminal is electrically connected (inner lead bonding) to the tip of the corresponding inner lead 3;
Indicates a resin sealing layer that covers and seals the semiconductor chip 4, the inner leads 3, and their joints. Reference numeral 6 denotes a bump made of solder or the like provided on a pad on the other end side of the wiring layer 2, and reference numeral 7 denotes a cover formed on the wiring layer 2 to prevent a short circuit between wirings and to form a bump 6 made of solder or the like. The reference numeral 8 denotes a solder resist layer formed, a reference numeral 8 denotes a stiffener (shape holding plate) made of metal or the like joined to the other main surface (the upper surface in the figure) of the insulating resin film 1 via an adhesive layer 9, and a reference numeral 10 denotes And a cover plate made of copper or the like, which is integrally provided on the other main surface side of the semiconductor chip 4 and the other main surface side of the stiffener 8 and is joined via an adhesive layer (not shown). .

[0005]

However, such a semiconductor device has the following problems.
That is, a single-layer wiring tape in which the wiring layer 2 such as a copper foil is provided only on one surface of the insulating resin film 1 is used, and since the area where the wiring layer 2 is formed is narrow, the bump 6 made of solder or the like is used. However, it has not been possible to sufficiently cope with a tendency to increase the number of wiring pads to be connected and to reduce the pad pitch.

Further, as an insulating base material, a thin (usually thick
50 to 125 μm) Not only is the insulating resin film 1 used, but the solder resist layer 7 having poor flexibility is provided on the wiring layer 2, so that the entire device is likely to be warped. Therefore, stiffener 8 made of metal or the like is used.
Are joined to strengthen and maintain the shape, but there is a problem that the structure is complicated and the cost is high.

The present invention has been made to solve these problems, and has a wide wiring area to cope with an increase in the number of pads. In addition, a plurality of semiconductor elements are mounted and mounted at high density. It is another object of the present invention to provide a semiconductor device in which deformation such as warpage is suppressed.

[0008]

According to the present invention, there is provided a semiconductor device comprising:
A plate-shaped or sheet-shaped insulating base having a device hole, wiring layers respectively disposed on both surfaces of the insulating base, and disposed in a thickness direction with an insulating layer interposed therebetween, and each electrode terminal is The semiconductor device includes a plurality of semiconductor elements respectively connected to wiring layers on different surfaces of the insulating base, and a plurality of external connection terminals provided at an end of the outer wiring layer of the insulating base arranged outside. Wherein the insulating base material has a thickness equal to or greater than the thickness of at least one semiconductor element arranged face-down among the semiconductor elements, and the semiconductor arranged face-down. An element is fitted in the device hole.

In the present invention, as a plate-shaped or sheet-shaped insulating substrate having device holes, for example, an insulating resin film such as a polyimide resin film or a glass cloth impregnated with a resin such as an epoxy resin is used. A glass cloth-resin impregnated substrate formed by laminating a prepreg in one layer or by laminating may be used. The thickness of such an insulating substrate is preferably equal to or greater than the thickness of the semiconductor element arranged face-down and fitted in the device hole, and is preferably 200 to 500 μm. Further, the size and planar shape of the device holes provided in these insulating base materials are set in accordance with the size and planar shape of the semiconductor element fitted therein.

The wiring layers respectively provided on both sides of such a plate-shaped or sheet-shaped insulating base material include, for example, Cu, C
u-based alloys, Ni-based alloys such as 42 alloy, etc., and vapor deposition patterning of these metals on the insulating substrate surface,
Alternatively, it is formed by photo-etching a Cu foil or the alloy foil provided on both surfaces of the insulating base material. In addition, it is desirable that the wiring layers on both sides be electrically connected via the via hole.
After forming a hole penetrating the insulating base material by punching (punching) with a drill or the like, the inner wall surface of the hole is plated with copper, tin, or the like.

Further, in the present invention, an inner lead group having one end connected to the wiring layer and the other end protruding into the device hole can be provided on one side of the insulating base. , Can be performed in the same manner as the above-described wiring layer.

In the present invention, as the external connection terminal,
For example, bumps such as Pb / Sn-based solder may be used, and it is desirable that the bumps are arranged in a grid pattern on the outer layer surface of the insulating substrate disposed on the outermost side. The solder bumps are formed, for example, by applying a soldering flux to the wiring pads formed in a predetermined arrangement on the substrate on which the bumps are to be formed by a printing method or the like, and placing a spherical solder ball thereon to reflow. It is done by doing.

In the semiconductor device of the present invention, a wiring layer is formed on both sides of a plate-shaped or sheet-shaped insulating base material which is thicker than usual, and at least one semiconductor element is provided in a device hole. Is completely fitted, and the second semiconductor element is disposed so as to overlap with the semiconductor element. Therefore, it is possible to sufficiently cope with an increase in the number of wiring pads and a reduction in pad pitch, and a plurality of A compact semiconductor device mounted at a high density can be obtained.

Further, even if a stiffener made of metal or the like is not provided, the entire device does not warp, and the structure can be simplified and the cost can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention, and FIG. 2 is an enlarged view of a portion A in FIG.

In these figures, reference numeral 11 denotes a thickness (about 5 mm) which is equal to or larger than a semiconductor chip described later.
), And an insulating resin film such as a polyimide resin film having a device hole 11a at the center thereof. A copper wiring layer 12 is formed on both surfaces of the insulating resin film 11 by photo-etching of a copper foil. Is formed. On one main surface (the lower surface in the figure), a group of inner leads 13 having one end connected to the copper wiring layer 12 and the other end (tip) projecting into the device hole 11a is provided. Here, these inner leads 13
Is formed in a gull-wing shape to facilitate connection with an electrode terminal of a semiconductor chip described later.

At predetermined positions of the insulating resin film 11, via holes 14 are provided, respectively.
Through these via holes 14, copper wiring layers 12 on both sides are formed.
Is conducted. Further, a solder resist layer 15 is formed on the copper wiring layer 12 on the lower surface of the insulating resin film 11 to prevent a short circuit between the wirings. The land (via land) of the via hole 14, the pad surface of the copper wiring layer 12 and the inner lead 1
It is desirable that tin tip or gold plating be applied to the tip of 3 in order to facilitate connection.

Then, two semiconductor chips 1 arranged face down on such a wiring film, respectively.
6 is mounted and mounted as described below. That is, the lower semiconductor chip 16a in which each side is formed smaller than the corresponding side of the device hole 11a is fitted in the device hole 11a, and each electrode terminal of the semiconductor chip 16a and the inner lead 13 are connected to the metal. (Inner lead bonding) via bumps 13a. The upper semiconductor chip 16b is
Each side is formed to be larger than the corresponding side of the device hole 11a, such a semiconductor chip 16b is disposed immediately above the device hole 11a, and each electrode terminal and the copper wiring layer 12 on the upper surface of the film are connected to the solder bump 12a. For flip-chip connection. The two upper and lower semiconductor chips 16b, 16a thus mounted and mounted are
A suitable gap is provided between them. In the case where a protective insulating layer is directly provided on the opposing surfaces (one or both surfaces) of these semiconductor chips 16b, 16a, the semiconductor chips 16b, 16a are arranged in an overlapping manner without an appropriate interval between the semiconductor chips. Is also good.

A resin sealing layer of epoxy resin or the like is provided outside the upper and lower semiconductor chips 16b and 16a and outside the joint between the semiconductor chip and the inner leads 13 and the copper wiring layer 12 on the upper surface of the film. 17 are provided. The resin sealing layer 17 is interposed also in the gap between the upper and lower semiconductor chips 16b and 16a to maintain sufficient insulation.

Further, on the copper wiring layer 12 (via land and wiring pad) on the lower surface of the film, solder bumps 18 as external connection terminals are provided in a grid pattern. It is electrically connected to the copper wiring layer 12 on the upper surface of the film via a via hole 14 provided in the conductive resin film 11. A cover plate 19 made of metal such as copper is integrally disposed on the copper wiring layer 12 on the upper surface of the film and the upper semiconductor chip 16b, and is adhered through an adhesive layer 19a.

In the semiconductor device of the first embodiment configured as described above, the copper wiring layers 12 are formed on both surfaces of the insulating resin film 11, respectively, and the wiring area is enlarged from one side to both sides of the base material. Since the semiconductor chips 16b and 16a which are arranged in the upper and lower two stages are mounted, the number of pads for bump connection is increased due to the increase in the number of chips and the pitch of the pads is reduced. Semiconductor device is obtained.

Further, since the insulating resin film 11 having a thickness equal to or larger than that of the semiconductor chip is used, the entire device does not warp without the stiffener, and the structure is simplified. Cost can be reduced.

Further, two semiconductor element chips are mounted, but since a cover plate 19 made of copper or the like is provided on the upper surface of the upper semiconductor chip 16b, heat generated from the chips causes the cover plate 19 to be heated. It is easy to conduct and release, exhibiting good characteristics.

Next, another embodiment of the present invention will be described with reference to FIGS. In these figures, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted.

In the semiconductor device of the second embodiment, as shown in FIGS. 3 and 4, the semiconductor device is fitted into the device hole 11a of the insulating resin film 11 and is bonded to the inner lead 13 on the lower surface of the film. A semiconductor chip 16 b of substantially the same size is mounted face-up on the lower semiconductor chip 16 a, and is bonded with an insulating adhesive paste 20. The upper semiconductor chip 16b is also almost buried in the device hole 11a, and its electrode terminals and the copper wiring layer 12 on the upper surface of the film are connected (wire-bonded) by bonding wires 21 such as gold wires. ing.

In the semiconductor device of the second embodiment configured as described above, similarly to the first embodiment, semiconductor chips are stacked and mounted at a high density, and the device is warped. There is no need to provide a stiffener, and the structure is simplified. Further, the semiconductor chips 16b and 16a which are arranged in a two-tiered manner in the upper and lower stages are all provided in the device holes 11a of the insulating resin film 11.
Since the semiconductor device is almost buried therein, a thinner and more compact semiconductor device can be obtained.

In the first and second embodiments, the insulating resin film 11 such as a polyimide resin film is used as the insulating base material.
Alternatively, a glass cloth-resin impregnated substrate formed by laminating a prepreg in which a glass cloth is impregnated with a resin can be used.

In the semiconductor device of the third embodiment, as shown in FIGS. 5 and 6, respectively, it has a thickness (about 500 μm) which is about the same as or larger than a semiconductor chip described later, and has a device hole 22a. A first glass cloth-resin impregnated substrate (hereinafter simply referred to as an insulating substrate) 22
And a second insulating substrate 23 having no device hole are laminated and integrated with a copper wiring layer (intermediate wiring layer) 24 interposed therebetween, and the upper surface of the first insulating substrate 22 and the second insulating substrate 23 also has an outer wiring layer (upper wiring layer 25).
And a lower wiring layer 26). In such a multilayer wiring board, a plurality of via holes 14a that conduct between the upper wiring layer 25 and the lower wiring layer 26, and a plurality of via holes that conduct between the intermediate wiring layer 24 and the lower wiring layer 26. Holes 14b are provided respectively. On the lower wiring layer 26 (via land and wiring pad) on the lower surface of the second insulating substrate 23, solder bumps 18 as external connection terminals are provided in a grid pattern.

The lower semiconductor chip 16a, each side of which is formed smaller than the corresponding side of the device hole 22a of the first insulating substrate 22, is arranged face down and fitted into the device hole 22a. The electrode terminals and the intermediate wiring layer 24 are flip-chip connected by solder bumps 24a. Further, above the lower semiconductor chip 16a mounted in this manner, the upper semiconductor chip 16b having each side formed larger than the device hole 22a is arranged face down,
The electrode terminals and the upper wiring layer 25 are flip-chip connected by solder bumps 25a. Further, a third semiconductor chip 27 is arranged below the second insulating substrate 23, and its electrode terminals and the lower wiring layer 26 are flip-chip connected by solder bumps 26a. Note that the other parts are configured in the same manner as in the first embodiment, and a description thereof will be omitted.

In the third embodiment configured as described above,
Under the first insulating substrate 22, the second
The insulating substrate 23 is laminated with the intermediate wiring layer 24 interposed therebetween, and the third semiconductor chip 27 is mounted on the wiring area further enlarged in this manner. A device is obtained. Also,
Since the device does not warp, there is no need to provide a stiffener, so that the structure can be simplified and the cost can be reduced. In this example, a glass cloth-resin impregnated film substrate was used as the first and second insulating base materials, but one or both of them may be replaced with an insulating resin film such as a polyimide resin film. It is possible. The upper and lower two-stage semiconductor chips 16b, 1
6a and the mounting of the third semiconductor chip 27,
Although the electrode terminals and the wiring layer are flip-chip connected, one or two or more of the three semiconductor chips can be connected by wire bonding.

[0032]

As is apparent from the above description, in the present invention, the wiring area is increased, it is possible to sufficiently cope with the increase in the number of wiring pads, etc., and a plurality of semiconductor elements are mounted and mounted at high density. Semiconductor device can be obtained. Further, since deformation such as warpage is suppressed, there is no need to provide a stiffener, so that the structure can be simplified and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is an enlarged view showing a portion A in FIG. 1;

FIG. 3 is a sectional view showing a second embodiment of the semiconductor device of the present invention.

FIG. 4 is an enlarged view showing a portion B in FIG. 3;

FIG. 5 is a sectional view showing a third embodiment of the semiconductor device of the present invention.

FIG. 6 is an enlarged view of a portion C in FIG. 5;

FIG. 7 is a sectional view showing the structure of a conventional T-BGA type semiconductor device.

FIG. 8 is an enlarged view showing a portion D in FIG. 7;

[Explanation of symbols]

11: Insulating resin film 11a: Device hole 12: Copper wiring layer 13: Inner lead 13a: Bump such as gold 14: Via hole 15: Solder resist layer 16: … Semiconductor chip 17… Resin sealing layer 18… Solder bump 19… Cover plate 21… Bonding wire 22… First insulating substrate (glass cloth-resin impregnated substrate) 23… ... Second insulating substrate 27... Third semiconductor chip

Claims (6)

[Claims] 1. A plate-shaped or sheet-shaped insulating base having a device hole, wiring layers provided on both sides of the insulating base, and an insulating layer arranged in a thickness direction with an insulating layer interposed therebetween. A plurality of semiconductor elements in which each electrode terminal is connected to a wiring layer on a different surface of the insulating base, and a plurality of external connection terminals provided at an end of an outer wiring layer of the insulating base disposed outside Wherein the insulating base has a thickness equal to or greater than the thickness of at least one semiconductor element arranged face-down among the semiconductor elements, and The semiconductor element disposed in the device hole is fitted into the device hole. 2. The semiconductor device according to claim 1, wherein the insulating base is a polyimide resin film. 3. The semiconductor device according to claim 1, wherein the insulating base is a glass cloth-resin impregnated substrate. 4. The semiconductor device according to claim 1, wherein the wiring layers on both surfaces of the insulating base are electrically connected via via holes. 5. An inner lead group having one end connected to a wiring layer and the other end protruding into the device hole is formed on one side of the insulating base material. 5. The semiconductor device according to claim 1, wherein an electrode of the semiconductor element arranged down is electrically connected. 6. The external connection terminal according to claim 1, wherein the external connection terminals are ball-shaped bumps mainly composed of Pb / Sn-based solder, and these are arranged in a lattice. The semiconductor device according to claim 1.