JP2008135628A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide a mounting structure that has a height sufficient for face-down mounting and prevents deterioration of electrical characteristics and can maintain sufficient strength during mounting, and has excellent mounting reliability. A semiconductor device is provided.
A semiconductor device includes a semiconductor substrate having an electrode disposed on one surface, an electronic component disposed on one surface of the semiconductor substrate and electrically connected to the electrode, and a semiconductor substrate. A plurality of structures 8 on one surface side and disposed around the electronic component, the structure having a projecting resin post 9 having a flat top, and a top It is comprised from the solder bump 11 mounted, It has the space | gap between the said structure and the said electronic component, It is characterized by the above-mentioned.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device excellent in mounting reliability suitable for a CSP (chip scale package) or the like.

  Conventionally, in a semiconductor package, for example, a so-called dual inline package or quad flat package in which a silicon chip is sealed with a resin, metal is applied to the side surface and the peripheral portion of the resin package. Peripheral terminal arrangement type with leads arranged is the mainstream.

  In contrast, in a CSP (chip scale package), particularly a semiconductor package called “wafer level CSP” (hereinafter sometimes referred to as WLCSP), an insulating resin layer, a wiring layer, a sealing layer, and the like are formed on the wafer. Further, after forming solder bumps, a plurality of chips are obtained by dicing.

  In WLCSP, since the chip becomes a semiconductor chip packaged with the same size, the occupied area can be reduced and high-density mounting is possible. The WLCSP is mounted on an external circuit board using solder bumps formed on a semiconductor chip. This type of semiconductor chip has a structure in which conductive columnar members called “posts” are provided and terminal portions are formed on the end surfaces of the columnar members (see, for example, Patent Document 1).

  In order to mount the chip mounting component using the rewiring as a pad and mount the surface thereof face down on the substrate, the bump height for mounting must be at least higher than the height of the mounting component. Therefore, as shown in FIG. 7, a structure is proposed in which the height of the bump 50 is slightly higher than the height of the mounting component 51 and the upper portion of the bump 50 is exposed from the sealing resin 52 (for example, Patent Document 2).

  However, with such a method, it is expected that sufficient strength cannot be obtained during mounting. Further, as shown in FIG. 8, a method of forming a second bump 53 after forming the first bump 50 has also been proposed. In order to reduce the height of the connection bump portion as an extension of the technology, as shown in FIG. 9, the first bump 50 is processed to form a notch portion 54, and the second bump 53 is formed at that portion. A structure has also been proposed that forms In such a method, it is necessary to form a sealing resin at least as much as the height of the mounted component, which causes an increase in module weight and an increase in manufacturing cost due to the sealing resin. .

In addition, the bump is a structure whose high-frequency characteristics cannot be grasped in nature, and arranging two such structures has a risk of increasing uncertainties in electrical characteristics. Further, the bump formed by the printing method has a cavity called a void, and the influence of this on the electrical characteristics is not clear. In this way, the technique of stacking two bumps with uncertain characteristics is difficult to say in the present and future where high frequencies are increasing. In addition, no mechanism to relieve stress is found in this proposal.
JP 2002-190550 A Japanese Patent Laid-Open No. 2006-4401

  The present invention has been proposed in view of such conventional circumstances, and while maintaining a sufficient height for face-down mounting, it prevents electrical characteristics from deteriorating and maintains sufficient strength during mounting. An object of the present invention is to provide a semiconductor device having a bump structure that can be used and having excellent mounting reliability.

According to a first aspect of the present invention, there is provided a semiconductor device having an electrode disposed on one surface, an electronic component disposed on one surface of the semiconductor substrate and electrically connected to the electrode, and the semiconductor substrate. A plurality of structures disposed around the electronic component, the structure having a protruding resin post having a flat top, and mounted on the top. The solder bumps are placed, and there is a gap between the structure and the electronic component.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein when the one surface of the semiconductor substrate is used as a reference surface, the height of the structural body is higher than the height of the electronic component when viewed from the reference surface. It is characterized by being expensive.
According to a third aspect of the present invention, there is provided a semiconductor device according to the first or second aspect, further comprising an opening that is disposed between the one surface of the semiconductor substrate and the electronic component and the structure, and exposes the electrode. It further comprises an insulating part, and a conductive part disposed on the insulating part, one end of which is electrically connected to the electrode and the other end is electrically connected to the electronic component.
According to a fourth aspect of the present invention, there is provided a semiconductor device according to any one of the first to third aspects, wherein the resin post and the electronic component are embedded on one surface side of the semiconductor substrate. The sealing part is further provided.

  In the present invention, the structure is composed of a protruding resin post having a flat top, and a solder bump placed on the top, so that the resin post can increase the height and can be mounted. Time stress can be relaxed. As a result, a bump structure is provided that has a height sufficient for face-down mounting, while preventing deterioration in electrical characteristics and maintaining sufficient strength during mounting. As a result, a semiconductor device having excellent mounting reliability can be provided.

  Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view showing a modification of the semiconductor device of FIG.
A semiconductor device 1A (1) includes a semiconductor substrate 2 having an electrode 3 disposed on one surface and an insulating resin layer 4 (insulating) disposed on one surface side of the semiconductor substrate 2 and having an opening 4a exposing the electrode 3. Part), a first wiring layer 5 (conductive part) disposed on the insulating resin layer 4, an electronic component 6 provided on the first wiring layer 5 and electrically connected to the electrode 3, and insulation A plurality of structures 8 are provided on the resin layer 4 and arranged around the electronic component 6.

In the present invention, the structure 8 includes a protruding resin post 9 having a flat top portion, a second wiring layer 10, and a solder bump 11 placed on the top portion. And a gap S between the electronic component 6 and the electronic component 6.
When the one surface 2 a of the semiconductor substrate 2 is used as a reference surface, the height h ₂ of the structure 8 is higher than the height h ₁ of the electronic component 6 when viewed from the reference surface.

As described above, in the present invention, a plurality of structures 8 are arranged around the electronic component 6, and the structures 8 are placed on the protruding resin posts 9 having a flat top and the top. In addition, the height h ₂ of the solder bump 11 is higher than the height h ₁ of the electronic component 6, whereby the resin post 9 can increase the height and relieve stress during mounting. be able to. Thus, for example, as shown in FIG. 3, when the semiconductor device 1A (1) is mounted on the substrate 20, the electrical characteristics are prevented from deteriorating while having a height sufficient for face-down mounting and mounting. A bump structure capable of maintaining sufficient strength sometimes can be obtained. As a result, a semiconductor device having excellent mounting reliability can be provided.

  In addition to a semiconductor wafer made of silicon or the like, the semiconductor substrate 2 may be, for example, a semiconductor wafer on which various semiconductor elements, ICs, induction elements, etc. are formed, or a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. .

  The electrode 3 is an electrode that is electrically connected to the electronic component 6 formed on the semiconductor substrate 2. The electrode 3 is made of a conductive metal such as aluminum, copper, chromium, titanium, gold, or titanium-tungsten alloy.

The insulating resin layer 4 has an opening 4 a formed at a position aligned with the electrode 3. The insulating resin layer 4 is made of, for example, polyimide resin, epoxy resin, silicone resin, etc., and the thickness thereof is, for example, 1 to 30 μm.
The insulating resin layer 4 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. The opening 4a can be formed by patterning using a photolithography technique, for example.

  The first wiring layer 5 is a rewiring layer (underpass) that electrically connects the electrode 3 and the electronic component 6. One end of the first wiring layer 5 penetrates the insulating resin layer 4 through the opening and is electrically connected to the electrode 3. The other end of the first wiring layer 5 is electrically connected to the electronic component 6 via the external connection terminal mounting electrode 7.

  For the first wiring layer 5, for example, copper, chromium, aluminum, titanium, gold, titanium-tungsten alloy or the like is suitably used, and the thickness is preferably 2 to 40 μm, more preferably 5 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The first wiring layer 5 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

  Examples of the electronic component 6 include passive components such as a chip inductor, a chip capacitor, a balun, and a filter. That is, the configuration of the present invention is suitable for passive component and element integration (passive integration). However, the electronic component 6 is a functional element having a fine three-dimensional structure, for example, a MEMS device (MEMS: Micro Electro Mechanical System) as required. The MEMS device may be, for example, a micro relay, a micro switch, a pressure sensor, an acceleration sensor, a high frequency filter, a micro mirror, or the like.

  The resin post 9 is an approximately frustoconical insulating resin formed at a predetermined position on the insulating resin layer 4. For example, an insulating resin such as a polyimide resin, an epoxy resin, a silicon resin (silicone), or a novolac resin is used. In particular, a positive or negative photosensitive resin is preferable. The resin post 9 has, for example, a height of 10 to 100 μm and a diameter of 50 to 500 μm.

The second wiring layer 10 is formed on the upper surface of the resin post 9 in order to mount the solder bump 11.
For the second wiring layer 10, for example, copper, chromium, aluminum, titanium, gold, titanium-tungsten alloy or the like is suitably used, and the thickness is preferably 2 to 40 μm, and more preferably 5 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The second wiring layer 10 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

  For the solder bump 11, eutectic solder, high-temperature solder not containing lead, or the like can be used. The solder bump 11 can be formed by, for example, a solder ball mounting method, an electrolytic solder plating method, a solder ball mounting method, a solder paste printing method, a solder paste dispensing method, a solder vapor deposition method, or the like.

Further, as shown in FIGS. 2 and 4, the semiconductor device 1A (1) includes a seal disposed on one surface side of the semiconductor substrate 2 so that the resin post 9 and the electronic component 6 are embedded. It is preferable to further include a stopping resin layer 12 (sealing portion).
The sealing resin layer 12 is for protecting the electronic component 6, the electrode 3, and the resin post 9, and is made of, for example, a polyimide resin, an epoxy resin, a silicon resin (silicone), and the thickness is 5 About 50 μm.
Such a sealing resin layer 12 can be formed, for example, by patterning a photosensitive resin such as a photosensitive polyimide resin by a photolithography technique. In addition, the formation method of the sealing resin layer 12 is not limited to this method. For example, a spray coating method may be used.

Further, a third wiring layer 14 (metal wiring layer) and a second insulating resin layer 13 (insulating layer) are newly formed on the insulating resin layer 4 as in the semiconductor device 1B (1) shown in FIG. May be. One end of the third wiring layer 14 penetrates the second insulating resin layer 13 through the opening 13 a and is connected to the other end of the first wiring layer 5.
Thereby, a passive element can be comprised by the 3rd wiring layer 14 formed on the insulating resin layer 4. FIG.
As shown in FIG. 6, the semiconductor device 1 </ b> B (1) of FIG. 5 also includes a sealing resin layer 12 (sealing portion), similarly to the configuration example shown in FIGS. 2 and 4. It is good.

  Although the semiconductor device of the present invention has been described above, the present invention is not limited to this, and can be appropriately changed without departing from the spirit of the invention.

  The present invention is applicable to various semiconductor devices having electronic components.

It is a schematic sectional drawing which shows an example of the semiconductor device which concerns on this invention. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG. 1. FIG. 2 is a schematic cross-sectional view showing a state where the semiconductor device of FIG. 1 is mounted face-down. FIG. 4 is a cross-sectional view showing a modification of the semiconductor device of FIG. 3. It is a schematic sectional drawing which shows another example of the semiconductor device which concerns on this invention. FIG. 6 is a cross-sectional view showing a modification of the semiconductor device of FIG. 5. It is a schematic sectional drawing which shows an example of the conventional semiconductor device. It is a schematic sectional drawing which shows another example of the conventional semiconductor device. It is a schematic sectional drawing which shows another example of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Semiconductor substrate, 3 Electrode, 4 Insulating resin layer, 5 1st wiring layer, 6 Electronic component, 7, 8 Structure, 9 Resin post, 10 2nd wiring layer, 11 Solder bump, 12 Sealing resin layer.

Claims (4)

A semiconductor substrate with electrodes on one side;
An electronic component disposed on one side of the semiconductor substrate and electrically connected to the electrode;
A plurality of structures on one side of the semiconductor substrate and disposed around the electronic component;
The structure is composed of a projecting resin post having a flat top and a solder bump placed on the top, and a gap is provided between the structure and the electronic component. A semiconductor device. When one surface of the semiconductor substrate is a reference surface,
The semiconductor device according to claim 1, wherein a height of the structure is higher than a height of the electronic component when viewed from the reference plane. An insulating part provided between one surface of the semiconductor substrate and the electronic component and the structure, and having an opening exposing the electrode;
A conductive portion disposed on the insulating portion, one end electrically connected to the electrode and the other end electrically connected to the electronic component;
The semiconductor device according to claim 1, further comprising: The sealing portion disposed on one surface side of the semiconductor substrate so that the resin post and the electronic component are embedded,
The semiconductor device according to claim 1, further comprising:

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