JP2008227161A - Semiconductor device - Google Patents

Abstract

A semiconductor device having a bump structure capable of preventing deterioration of electrical characteristics while maintaining a sufficient height for face-down mounting and maintaining a sufficient strength during mounting, and having excellent mounting reliability.
A semiconductor device includes a semiconductor substrate having an electrode disposed on one surface, a first electronic component disposed on one surface of the semiconductor substrate and electrically connected to the electrode, and a semiconductor substrate. 2 and a plurality of structures 8 disposed around the first electronic component. The structure 8 includes a resin post 9 and a solder bump 11 placed on the top of the resin post 9, and has a gap S between the structure 8 and the first electronic component 6. The second electronic component 14 arranged on the other surface side of the semiconductor substrate 2 and a part formed through the semiconductor substrate 2 at a part having the air gap S or a part opposite to the air gap S across the resin post 9 An electrode 16. The first electronic component 6 and the second electronic component 14 are electrically connected via the through electrode 16.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having excellent electrical characteristics and mounting strength and high mounting reliability during face-down mounting.

  Conventionally, in a semiconductor package, for example, a so-called dual inline package or quad flat package in which a silicon chip is sealed with a resin, metal is applied to the side surface and the peripheral portion of the resin package. Peripheral terminal arrangement type with leads arranged is the mainstream.

  On the other hand, in a semiconductor package called CSP (chip scale package), particularly “wafer level CSP” (hereinafter sometimes referred to as WLCSP), an insulating resin layer, a wiring layer, a sealing layer, etc. are formed on the wafer. Further, after forming solder bumps, a plurality of chips are obtained by dicing.

  In WLCSP, since the chip becomes a semiconductor chip packaged with the same size, the occupied area can be reduced and high-density mounting is possible. The WLCSP is mounted on an external circuit board using solder bumps formed on a semiconductor chip. This type of semiconductor chip has a structure in which conductive columnar members called “posts” are provided and terminal portions are formed on the end surfaces of the columnar members (see, for example, Patent Document 1).

  In order to mount the chip mounting component using the rewiring as a pad and mount the surface thereof face down on the substrate, the bump height for mounting must be at least higher than the height of the mounting component. Therefore, as shown in FIG. 5, a structure is proposed in which the height of the bump 50 is slightly higher than the height of the mounting component 51 and the upper portion of the bump 50 is exposed from the sealing resin 52 (for example, Patent Document 2).

  However, with such a method, it is expected that sufficient strength cannot be obtained during mounting. Further, as shown in FIG. 6, a method of forming a second bump 53 after forming the first bump 50 has also been proposed. In order to reduce the height of the connection bump portion as an extension of the technique, as shown in FIG. 7, the first bump 50 is processed to form a cutout portion 54, and the second bump 53 is formed at that portion. A structure has also been proposed that forms In such a method, it is necessary to form a sealing resin at least as much as the height of the mounted component, which causes an increase in module weight and an increase in manufacturing cost due to the sealing resin. .

Further, the bump is a structure in which the high-frequency characteristics cannot be accurately grasped, and arranging two such structures may increase an uncertain element in the electric characteristics. Further, the bump formed by the printing method has a cavity called a void, and the influence of this on the electrical characteristics is not clear. Therefore, in view of the technical trend that requires higher frequency, it is difficult to say that the technique of stacking two bumps with uncertain characteristics is very effective. In addition, no mechanism to relieve stress is found in this proposal.
JP 2002-190550 A Japanese Patent Laid-Open No. 2006-4401

  The present invention has been proposed in view of such conventional circumstances, and while maintaining a sufficient height for face-down mounting, it prevents electrical characteristics from deteriorating and maintains sufficient strength during mounting. An object of the present invention is to provide a semiconductor device having a bump structure that can be used and having excellent mounting reliability.

The semiconductor device according to claim 1 of the present invention is a semiconductor substrate having an electrode disposed on one surface thereof, a first electronic component disposed on one surface side of the semiconductor substrate and electrically connected to the electrode, A plurality of structures on one side of the semiconductor substrate and arranged around the first electronic component, and the structure includes a projecting resin post having a flat top, and A semiconductor device comprising a solder bump placed on the top, and having a gap between the structure and the first electronic component, the second being disposed on the other surface side of the semiconductor substrate An electronic component; and a penetrating electrode formed through the semiconductor substrate at a portion having the void or the portion opposite to the void across the resin post, and the first electronic component and the The second electronic component is the through electrode Characterized in that it is electrically connected to Te.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein when the one surface of the semiconductor substrate is used as a reference surface, the height of the structural body is the height of the first electronic component when viewed from the reference surface. It is characterized by being higher than the height.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein an opening is provided between the one surface of the semiconductor substrate and the first electronic component and the structure, and exposes the electrode. And an electrically conductive portion that is disposed on the insulating portion and has one end electrically connected to the electrode and the other end electrically connected to the first electronic component.
A semiconductor device according to a fourth aspect of the present invention is characterized in that, in any one of the first to third aspects, an insulating layer is provided on an inner surface of the semiconductor substrate in contact with the through electrode.
A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the resin post and the first electronic component are embedded on one surface side of the semiconductor substrate. It is further characterized by further comprising an arranged sealing portion.

In the present invention, the structure is composed of a protruding resin post having a flat top, and a solder bump placed on the top, so that the resin post can increase the height and can be mounted. Time stress can be relaxed. As a result, a bump structure is provided that has a height sufficient for face-down mounting, while preventing deterioration in electrical characteristics and maintaining sufficient strength during mounting. As a result, a semiconductor device having excellent mounting reliability can be provided. Further, according to the present invention, the first electronic component and the second electronic component respectively disposed on both surfaces of the semiconductor substrate are electrically connected via the through electrodes provided on the semiconductor substrate, so that both surfaces of the semiconductor substrate are connected. Thus, it becomes possible to mount more electronic components.
In addition, the through electrode may be disposed in a part having a gap located between the structure in which the solder bump is superimposed on the resin post and the first electronic component, or the gap between the resin post. You may arrange | position in the site | part on the opposite side.

  Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention.
A semiconductor device 1A (1) of the present invention includes a semiconductor substrate 2 having an electrode 3 disposed on one surface, and a first insulating resin having an opening 4a disposed on one surface side 2a of the semiconductor substrate 2 and exposing the electrode 3 A layer 4 (insulating portion), a first wiring layer 5 (conductive portion) disposed on the first insulating resin layer 4, and a first wiring layer disposed on the first wiring layer 5 and electrically connected to the electrode 3. One electronic component 6 and a plurality of structures 8 on the first insulating resin layer 5 and disposed around the first electronic component 6 are provided.
In the semiconductor device 1 </ b> A (1) shown in FIG. 1, the through electrode 16 has a gap S positioned between the structure 8 in which the solder bump 11 is superimposed on the resin post 9 and the first electronic component 6. The example of composition arranged at the part is shown. However, the penetrating electrode 16 may be disposed on the opposite side of the gap S across the resin post 9 (in FIG. 1, outside the resin post 9).

The semiconductor device 1A (1) of the present invention includes a second insulating resin layer 12 disposed on the other surface side 2b of the semiconductor substrate 2, and a second wiring layer 13 disposed on the second insulating resin layer 12. The second electronic component 14 disposed on the second wiring layer 13 and the part having the gap S or the part opposite to the gap across the resin post are formed through the semiconductor substrate 2. The first electronic component 6 and the second electronic component 14 are electrically connected via the through electrode 16.
Thus, in the present invention, the through electrode 16 is provided on the semiconductor substrate 2, and the first electronic component 6 and the second electronic component 14 respectively disposed on both surfaces of the semiconductor substrate 2 are electrically connected via the through electrode 16. As a result of the connection, more electronic components can be mounted on both sides of the semiconductor substrate 2.

The structure 8 includes a protruding resin post 9 having a flat top, a second wiring layer 10, and a solder bump 11 placed on the top, and the structure 8 and the first There is a gap S between one electronic component 6.
When the one surface 2 a of the semiconductor substrate 2 is used as a reference surface, the height h ₂ of the structure 8 is higher than the height h ₁ of the electronic component 6 when viewed from the reference surface.

Thus, in the present invention, a plurality of structures 8 are arranged around the first electronic component 6, and the structures 8 are mounted on the protruding resin posts 9 having a flat top and the top. It is composed of the solder bumps 11 placed, and the height h ₂ is made higher than the height h ₁ of the first electronic component 6, so that the height can be gained by the resin post 9 and at the time of mounting. Stress can be relaxed. As a result, for example, as shown in FIG. 2, when the semiconductor device 1A (1) is mounted on the substrate 30, it has a height sufficient for face-down mounting, while preventing a decrease in electrical characteristics and mounting. A bump structure that can sometimes maintain sufficient strength can be obtained. As a result, a semiconductor device having excellent mounting reliability can be provided.

  In addition to a semiconductor wafer such as a silicon wafer, the semiconductor substrate 2 may be a semiconductor wafer formed with various semiconductor elements, ICs, induction elements, or the like, or a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions.

  The electrode 3 is an electrode that is electrically connected to the first electronic component 6 formed on the semiconductor substrate 2. The electrode 3 is made of a conductive metal such as aluminum, copper, chromium, titanium, gold, or titanium-tungsten alloy.

The first insulating resin layer 4 has an opening 4 a formed at a position aligned with the electrode 3. The first insulating resin layer 4 is made of, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like, and has a thickness of, for example, 1 to 30 μm.
The first insulating resin layer 4 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. The opening 4a can be formed by patterning using a photolithography technique, for example.

  The first wiring layer 5 is a rewiring layer that electrically connects the electrode 3 and the first electronic component 6. One end of the first wiring layer 5 penetrates the first insulating resin layer 4 through the opening and is electrically connected to the electrode 3. The other end of the first wiring layer 5 is electrically connected to the first electronic component 6 via the external connection terminal mounting electrode 7.

  For the first wiring layer 5, for example, copper, chromium, aluminum, titanium, gold, titanium-tungsten alloy or the like is suitably used, and the thickness is preferably 2 to 40 μm, more preferably 5 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The first wiring layer 5 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

  Examples of the first electronic component 6 include passive components such as a chip inductor, a chip capacitor, and a filter. That is, the configuration of the present invention is suitable for passive component and element integration (Passive Integration). However, the first electronic component 6 may be a fine three-dimensional functional element such as a MEMS device (MEMS = Micro Electro Mechanical System). Examples of the MEMS device include a micro relay, a micro switch, a pressure sensor, an acceleration sensor, a high frequency filter, and a micro mirror.

  The resin post 9 is a substantially frustoconical insulating resin formed at a predetermined position on the first insulating resin layer 4. For example, a polyimide resin, an epoxy resin, a silicon resin (silicone), a novolac resin, or the like. In particular, it is preferably made of a positive or negative photosensitive resin. The resin post 9 has, for example, a height of 10 to 100 μm and a diameter of 50 to 500 μm.

The second wiring layer 10 is formed on the upper surface of the resin post 9 in order to mount the solder bump 11.
For the second wiring layer 10, for example, copper, chromium, aluminum, titanium, gold, titanium-tungsten alloy or the like is suitably used, and the thickness is preferably 2 to 40 μm, and more preferably 5 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The second wiring layer 10 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

  For the solder bump 11, eutectic solder, high-temperature solder not containing lead, or the like can be used. The solder bump 11 can be formed by, for example, a solder ball mounting method, an electrolytic solder plating method, a solder paste printing method, a solder paste dispensing method, a solder vapor deposition method, or the like.

  The second insulating resin layer 12 is made of, for example, polyimide resin, epoxy resin, silicone resin, etc., and the thickness thereof is, for example, 1 to 30 μm. The second insulating resin layer 12 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like.

  One end of the third wiring layer 13 is electrically connected to the conductive layer 18 of the through electrode 16. The other end of the third wiring layer 13 is electrically connected to the second electronic component 14 via the external connection terminal mounting electrode 15.

  For the third wiring layer 13, for example, copper, chromium, aluminum, titanium, gold, titanium-tungsten alloy or the like is suitably used, and the thickness is preferably 2 to 40 μm, more preferably 5 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The third wiring layer 13 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

  As the second electronic component 14, like the first electronic component 6, for example, passive components such as a chip inductor, a chip capacitor, and a filter can be cited. The second electronic component 14 may be a fine functional element having a three-dimensional structure, like the first electronic component 6. Examples of such a functional element include an image sensor including a solid-state imaging element (CCD) in addition to the MEMS device.

  The through electrode 16 is formed by forming a through hole 17 (fine hole) from one surface of the semiconductor substrate 2 to the other surface, and arranging a conductive layer 18 on a side surface portion of the through hole 17. . The conductive layer 18 is electrically connected to a wiring layer (second wiring layer 10) disposed on the resin post 9 of the structure 8 on one surface side of the semiconductor substrate 2. In addition, the other surface side of the semiconductor substrate 2 extends on the second insulating resin layer 12.

Further, as in the semiconductor device 1B (1) shown in FIG. 3, the insulating layer 19 is disposed on the inner surface of the semiconductor substrate 2 in contact with the through electrode 16, that is, the insulating layer 19 is provided on the wall surface of the through hole 17. A structure in which is formed is preferable. Thereby, the leakage current from the conductive layer 18 to the semiconductor substrate 2 can be reduced, and the withstand voltage can be increased.
The through electrode 16 may be formed by filling the through hole 17 with a conductive material.

Further, as in the semiconductor device 1C (1) shown in FIG. 4, the sealing resin disposed on the one surface side of the semiconductor substrate 2 so that the resin post 9 and the first electronic component 6 are embedded. It is preferable that the layer 20 (sealing part) is further provided.
The sealing resin layer 20 is for protecting the first electronic component 6, the electrode 3, and the resin post 9, and is made of, for example, a polyimide resin, an epoxy resin, a silicon resin (silicone), and the thickness thereof. Is about 5 to 50 μm.
Such a sealing resin layer 20 can be formed, for example, by patterning a photosensitive resin such as a photosensitive polyimide resin by a photolithography technique. In addition, the formation method of the sealing resin layer 20 is not limited to this method. For example, a spray coating method or the like may be used.
The second wiring layer 13 and the external connection terminal mounting electrode 15 are preferably protected by providing a sealing portion.

  Although the semiconductor device of the present invention has been described above, the present invention is not limited to this, and can be appropriately changed without departing from the spirit of the invention.

  The present invention is applicable to various semiconductor devices having electronic components.

It is sectional drawing which shows an example of the semiconductor device which concerns on this invention. FIG. 2 is a cross-sectional view showing a state where the semiconductor device of FIG. 1 is mounted face-down. It is sectional drawing which shows another example of the semiconductor device which concerns on this invention. It is sectional drawing which shows another example of the semiconductor device which concerns on this invention. It is sectional drawing which shows an example of the conventional semiconductor device. It is sectional drawing which shows another example of the conventional semiconductor device. It is sectional drawing which shows another example of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Semiconductor substrate, 3 Electrode, 4 1st insulating resin layer, 5 1st wiring layer, 6 1st electronic component, 7 External connection terminal mounting electrode, 8 Structure, 9 Resin post, 10 2nd wiring Layer, 11 solder bump, 12 second insulating resin layer, 13 second wiring layer, 14 second electronic component, 15 external connection terminal mounting electrode, 16 through electrode, 17 through hole, 18 conductive layer, 19 insulating layer, 20 Sealing resin layer.

Claims (5)

A semiconductor substrate having an electrode disposed on one surface; a first electronic component disposed on one surface of the semiconductor substrate and electrically connected to the electrode; and the first electron on the one surface of the semiconductor substrate. A plurality of structures arranged around the component, and
The structure includes a protruding resin post having a flat top and a solder bump placed on the top, and a semiconductor having a gap between the structure and the first electronic component A device,
A second electronic component disposed on the other side of the semiconductor substrate;
A penetration electrode formed through the semiconductor substrate at a portion having the void or a portion opposite to the void across the resin post; and
The first electronic component and the second electronic component are electrically connected via the through electrode. When one surface of the semiconductor substrate is a reference surface,
2. The semiconductor device according to claim 1, wherein a height of the structure is higher than a height of the first electronic component when viewed from the reference plane. An insulating part provided between the one surface of the semiconductor substrate and the first electronic component and the structure, and having an opening exposing the electrode;
A conductive portion disposed on the insulating portion, one end electrically connected to the electrode and the other end electrically connected to the first electronic component;
The semiconductor device according to claim 1, further comprising:   The semiconductor device according to claim 1, further comprising an insulating layer on an inner surface of the semiconductor substrate in contact with the through electrode.   5. The device according to claim 1, further comprising a sealing portion disposed on one surface side of the semiconductor substrate so that the resin post and the first electronic component are embedded. The semiconductor device according to item.

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