JP2008131407A - Solid-state imaging device and imaging apparatus using the same - Google Patents

Abstract

A solid-state imaging device capable of reading a pixel state from a MOS image sensor in an arbitrary region without increasing the circuit scale and an imaging device using the same.
A start pulse (1127) of a shift register circuit is connected to reset circuits (1116, 1119, 1120,...) Of all bootstrap capacitors of each stage circuit, and the start pulse (1127) of the shift register circuit is connected. ) To control the scanning start position and scanning end position of the sensor unit by the shift register circuit.
[Selection] Figure 10

Description

  The present invention relates to a solid-state imaging device used as an image sensor for obtaining a captured image of a subject and an imaging apparatus using the same.

  Conventionally, various solid-state image sensors have been used as image sensors for obtaining a captured image of a subject. A MOS (Metal Oxide Semiconductor) type image sensor, which is one of these solid-state image sensors, has been improved in terms of noise due to technological progress. Since the manufacturing cost is low and the manufacturing cost is low, the CCD (Charge Coupled Device) image sensor has rapidly spread as an imaging device in the field of digital camera systems.

  Among MOS type image sensors, there are a “decoding method” and a “shift register method”, which are roughly classified into driving methods. The former “decoding method” enables “arbitrary reading” in which the user can specify the position where the scanning of the imaging unit starts and the position where scanning is stopped by using a decoding circuit in the area to be read. Compared to the “shift register method”, there is a demerit that the scale of the decoding circuit becomes large. An increase in circuit scale leads to an increase in cost, and it becomes difficult to construct a small camera system.

  On the other hand, the latter “shift register method” can reduce the scale of the drive circuit by using a shift register circuit (dynamic circuit), but has a demerit that “arbitrary read” cannot be performed.

The case of the “shift register system” among the MOS type image sensors as described above will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a conventional solid-state imaging device and an imaging apparatus using the same, and is a diagram simply showing a “shift register type” MOS image sensor and a digital camera system using the same. is there. As shown in FIG. 1, a solid-state imaging device (MOS-type image sensor) (101) includes a sensor unit (102) including a plurality of unit pixels that photoelectrically convert incident light into an electrical signal, and a signal for selecting the unit pixel. The horizontal shift register unit (103) and the vertical shift register unit (104) for generating the noise, the noise canceller unit (105) for removing the noise component of the electric signal output from the sensor unit (102), and the electric signal from which the noise component has been removed An AMP unit (output unit) (106) for amplifying the signal and outputting the amplified signal to the subsequent signal processing circuit (116) is provided.

  The subsequent signal processing circuit (116) includes an AFE (analog front end) unit (112) for processing an output signal (sensor output signal) (111) of the MOS image sensor (101), and an AFE unit (112). A signal processing unit (114) that performs digital signal processing on the output (113) of the sensor, and a sensor driving pulse (108) and an AFE unit (112) for driving the horizontal shift register unit (103) and the vertical shift register unit (104) It comprises an AFE (analog front end) drive pulse (109) for driving the signal and a TG unit (107) for generating and outputting a synchronization pulse (110) for synchronizing with the signal processing unit (114).

  The horizontal shift register unit (103) and the vertical shift register unit (104) used in the MOS image sensor (101) are configured by a MOS dynamic circuit (see, for example, Patent Document 1) as shown in FIG. .

  FIG. 2 is a circuit diagram showing a circuit configuration of a shift register circuit in a conventional solid-state imaging device, and is an example of a four-stage shift register circuit. Further, one of the dotted lines in FIG. 2 represents one stage of the shift register circuit. The operation of the MOS dynamic circuit will be described with reference to FIG. 2, but each drive pulse signal is input from the TG section (107) in FIG.

  When the shift register transfer pulse 1: V1 (202) is High as shown in FIG. 3 and the start pulse: VST (201) is inputted High (timing of the dotted line portion 301 in FIG. 3), the shift register input circuit The transistor (204) is turned on and charges are accumulated in the bootstrap capacitor (205).

  Next, when the shift register transfer pulse 1: V1 (202) becomes Low and the shift register transfer pulse 2: V2 (203) becomes High (timing of the dotted line portion 302 in FIG. 3), the transistor (204) is turned off. Then, the transistor (206) is turned on by the voltage generated by the electric charge accumulated in the bootstrap capacitor (205), and the shift register transfer pulse 2: V2 (203) becomes the shift register pulse 1: VSOUT1 (212). At the same time, the transistor (207) is turned on, so that the bootstrap capacitor (209) passes through the transistor (208) of the next shift register input circuit turned on by the shift register transfer pulse 2: V2 (203). ) Is accumulated.

  Similarly, when the shift register transfer pulse 2: V2 (203) becomes Low (timing of the dotted line portion 303 in FIG. 3), the transistor (208) is turned off, and the charge accumulated in the bootstrap capacitor (209). As a result, the transistor (210) is turned on, the shift register transfer pulse 1: V1 (202) is output as the shift register pulse 2: VSOUT2 (213), and the transistor (211) is turned on, so that the shift register transfer pulse 1 : Charge is accumulated in the bootstrap capacitor (217) via the transistor (216) turned on by V1 (202).

  The charge stored in the bootstrap capacitor (209) is output from the transistor (208) turned on by the shift register transfer pulse 2: V2 (203) and the shift register pulse 3: VSOUT3 (214). At this time, by turning on the transistor (215), it is discharged to GND.

  As shown in the timing chart of FIG. 3, by repeating these shift operations, the start pulse: VST is shifted to the shift register pulse 1: VSOUT1, the shift register pulse 2: VSOUT2, and the MOS dynamic circuit (shift register circuit). ) Can generate a pulse for selecting a unit pixel (row and column).

  However, in a MOS dynamic circuit (shift register circuit), it is impossible to generate a drive pulse that stops pulse transfer (shift) for selecting a unit pixel in the middle of the transfer path or starts in the middle of the transfer path. It is not possible to stop at an arbitrary position or start a screen scan from an arbitrary position.

Therefore, as another conventional technique (see, for example, Patent Document 2), even in a “shift register type” MOS image sensor, a screen is obtained by using a plurality of vertical shift register units and a plurality of horizontal shift register units. Attempts are also being made to stop imaging at arbitrary locations in the screen or to start imaging from arbitrary locations on the screen.
JP 2003-101406 A JP 2005-333265 A

  However, in the conventional "shift register type" MOS image sensor as described above, it is necessary to use a plurality of vertical shift register units and a plurality of horizontal shift register units, that is, the circuit scale increases. There is a problem that the merit of the small sensor by the small drive circuit, which is the greatest feature of the “shift register type” MOS image sensor, cannot be utilized.

  In addition, for markets that require miniaturization of camera systems, such as camera-equipped mobile phones, medical small cameras, and in-vehicle cameras, the increase in the sensor chip area due to the increase in circuit scale has led to an increase in camera shape. There is also a problem that the screen scanning drive of the image sensor becomes complicated.

  The present invention solves the above-mentioned conventional problems, and realizes a dynamic circuit capable of starting and stopping the screen scanning of a MOS type image sensor from an arbitrary position without increasing the circuit scale. A solid-state imaging device capable of arbitrarily setting a readout area when reading out the pixel state on the screen and increasing the degree of freedom regarding the readout area of the pixel state with respect to the MOS type image sensor and the same An imaging device is provided.

  In order to solve the above problems, in the solid-state imaging device according to claim 1 of the present invention, a plurality of pixel cells that accumulate signal charges according to the luminance of incident light are formed on a semiconductor substrate, and the pixel cells are A solid-state imaging device comprising: a horizontal scanning unit and a vertical scanning unit that scan; and an output unit that outputs an image signal read as a result of scanning the pixel cells by the horizontal scanning unit and the vertical scanning unit, It is composed of a dynamic circuit composed of a multi-stage circuit, and the voltage of the drive start pulse input to the first stage circuit is accumulated in the bootstrap capacitor of each stage circuit, and the post-stage circuit of the accumulated voltage of the drive start pulse The shift register pulse corresponding to the drive start pulse is sequentially output from each of the stage circuits, and the pixel is generated by the shift register pulse. And a signal transmission circuit connected to a circuit for resetting the bootstrap capacitance of each stage circuit is connected to one of the horizontal scanning section and the vertical scanning section. Or in both the horizontal scanning unit and the vertical scanning unit.

  According to a second aspect of the present invention, in the solid-state imaging device, a plurality of pixel cells that accumulate signal charges according to the luminance of incident light are formed on a semiconductor substrate, and a horizontal scanning unit that scans the pixel cells and a vertical one. A solid-state imaging device comprising: a scanning unit; and an output unit that outputs an image signal read out as a result of scanning the pixel cell by the horizontal scanning unit and the vertical scanning unit, and a dynamic circuit including a multi-stage circuit The voltage of the drive start pulse input to the first stage circuit is stored in the bootstrap capacitor of each stage circuit, and the transfer of the stored drive start pulse voltage to the subsequent stage circuit is repeated, A shift register pulse corresponding to the drive start pulse is sequentially output from each stage circuit, and the pixel cell is scanned by the shift register pulse. A signal transmission circuit in which a start pulse different from the drive start pulse input to the first stage circuit is connected to the input section of each stage circuit is provided in one of the horizontal scanning section and the vertical scanning section, or in the horizontal scanning section. And the vertical scanning unit.

  According to a third aspect of the present invention, in the solid-state imaging device, a plurality of pixel cells that accumulate signal charges according to the luminance of incident light are formed on a semiconductor substrate, and a horizontal scanning unit that scans the pixel cells and a vertical one. A solid-state imaging device comprising: a scanning unit; and an output unit that outputs an image signal read out as a result of scanning the pixel cell by the horizontal scanning unit and the vertical scanning unit, and a dynamic circuit including a multi-stage circuit The voltage of the drive start pulse input to the first stage circuit is stored in the bootstrap capacitor of each stage circuit, and the transfer of the stored drive start pulse voltage to the subsequent stage circuit is repeated, A shift register pulse corresponding to the drive start pulse is sequentially output from each stage circuit, and the pixel cell is scanned by the shift register pulse. A drive start pulse input to the first stage circuit is connected to a circuit for resetting a bootstrap capacitor of each stage circuit, and a start pulse different from the drive start pulse input to the first stage circuit is connected to each stage circuit. A signal transmission circuit connected to the input unit is used in one of the horizontal scanning unit and the vertical scanning unit, or in both the horizontal scanning unit and the vertical scanning unit.

  According to a fourth aspect of the present invention, in the solid-state imaging device, a plurality of pixel cells that accumulate signal charges according to the luminance of incident light are formed on a semiconductor substrate, and a horizontal scanning unit that scans the pixel cells and a vertical one. A solid-state imaging device comprising: a scanning unit; and an output unit that outputs an image signal read out as a result of scanning the pixel cell by the horizontal scanning unit and the vertical scanning unit, and a dynamic circuit including a multi-stage circuit The voltage of the drive start pulse input to the first stage circuit is stored in the bootstrap capacitor of each stage circuit, and the transfer of the stored drive start pulse voltage to the subsequent stage circuit is repeated, A shift register pulse corresponding to the drive start pulse is sequentially output from each stage circuit, and the pixel cell is scanned by the shift register pulse. A signal transmission circuit that individually resets the bootstrap capacitance of each stage circuit by a photoelectric effect by light incidence control is provided in one of the horizontal scanning unit and the vertical scanning unit, or in the horizontal scanning unit and the vertical scanning unit. It was used for both parts.

  Moreover, the solid-state image sensor according to claim 5 of the present invention is the solid-state image sensor according to any one of claims 1 to 4, wherein the solid-state image sensor is a fixed time interval with respect to the non-scanning region of the pixel cell. Scanning is performed.

  A solid-state imaging device according to claim 6 of the present invention is the solid-state imaging device according to any one of claims 1 to 4, wherein a luminance level of a pixel adjacent to a non-scanning region of the pixel cell is determined. , And when the calculated value reaches a predetermined constant level, a pulse for executing scanning of the non-scanning region of the pixel cell is output.

A solid-state image sensor according to claim 7 of the present invention is the solid-state image sensor according to claim 5 or 6, characterized by issuing an instruction to scan a non-scanning region.
The solid-state imaging device according to claim 8 of the present invention is the solid-state imaging device according to any one of claims 1 to 7, wherein the scanning area of the pixel cell is “even line × even pixel”. The scanning start position and the scanning end position are set so that

  An image pickup apparatus according to a ninth aspect of the present invention is an image pickup apparatus configured using the solid-state image pickup element according to any one of the first to eighth aspects, wherein the image pickup apparatus is provided for the solid-state image pickup element. A sensor driving pulse for driving and controlling scanning of the pixel cell is output, and an image signal corresponding to the scanning result of the pixel cell is output based on a sensor output output from the solid-state imaging device according to the sensor driving pulse. And a signal processing circuit.

  As described above, according to the present invention, the start pulse of the shift register circuit is connected to the bootstrap capacitor reset circuit of all the shift register circuits, and the period of the start pulse of the shift register circuit is controlled, thereby scanning the image sensor. The end position can be controlled.

  Therefore, it is possible to realize a dynamic circuit that can start and stop the screen scanning of the MOS type image sensor from an arbitrary position without increasing the circuit scale, and to read out the pixel state on the screen of the MOS type image sensor. Can be arbitrarily set, and the degree of freedom of the pixel state readout region for the MOS image sensor can be increased.

  Also, a shift register circuit using a dynamic circuit that can start and stop scanning from an arbitrary position without increasing the number of shift register circuits, and a “shift register system” MOS type using the shift register circuit It is possible to provide an image sensor and a camera system, which realizes a high frame rate by arbitrarily setting and reading out only necessary images, and a low power consumption camera by not performing signal processing of the parts that are not read out. A system can be provided.

  In addition, it is possible to propose an optimal camera system for a market that requires miniaturization of camera systems such as camera-equipped mobile phones, medical small cameras, and in-vehicle cameras.

Hereinafter, a solid-state imaging device and an imaging apparatus using the solid-state imaging device according to embodiments of the present invention will be specifically described with reference to the drawings.
(Basic configuration 1)
The solid-state imaging device of the present invention shown in the embodiments described later is configured by a multi-stage circuit as means for stopping scanning of the sensor unit at an arbitrary position, and the voltage of the drive start pulse is set as a bootstrap capacitance of each stage circuit. In a shift register circuit (signal transmission circuit) in which shift register pulses are sequentially output from each stage circuit according to the drive start pulse by repeatedly transferring the accumulated drive start pulse voltage to the subsequent stage circuit. A shift register circuit composed of a MOS dynamic circuit is used, in which a drive start pulse input to the first stage circuit is connected to a circuit for resetting the bootstrap capacitance of each stage circuit.

With this configuration, the drive start pulse of the shift register circuit to be input to the first stage circuit is periodically input according to the position where the scanning of the sensor unit is to be stopped, and the charge accumulated in the bootstrap capacitor by the drive start pulse. The shift register pulse can be stopped at an arbitrary position by turning on the circuit for resetting and removing the charge accumulated in the bootstrap capacitor.
(Basic configuration 2)
In addition, as a means for starting scanning of the sensor unit from an arbitrary position, it is composed of a multi-stage circuit, and the voltage of the drive start pulse is accumulated in the bootstrap capacitor of each stage circuit, and the accumulated drive in the subsequent stage circuit A shift register circuit (signal transmission circuit) in which shift register pulses are sequentially output from each stage circuit according to the drive start pulse by repeating transfer of the start pulse voltage, and the drive start pulse is input to each stage circuit. A shift register circuit composed of a MOS dynamic circuit characterized by being connected is used.

With this configuration, the shift register pulse can be started from an arbitrary position by inputting the drive start pulse input to the first stage circuit from the number of stages corresponding to the position where the scanning of the sensor unit is to be started.
(Basic configuration 3)
In addition, as a solid-state imaging device capable of stopping horizontal and vertical scanning at an arbitrary position, solid-state imaging in which a plurality of pixel cells having photoelectric conversion units that generate signal charges according to the luminance of incident light are formed on a semiconductor substrate A horizontal scanning unit and a vertical scanning unit that scan the pixel cells, and an output unit that outputs an image signal read as a result of scanning the pixel cells by the horizontal scanning unit and the vertical scanning unit, The shift register circuit having the above configuration 1 is used for both of the scanning unit and the vertical scanning unit.

With this configuration, it is possible to stop horizontal and vertical scanning at an arbitrary position by using a solid-state imaging device that scans the sensor unit with sequentially output shift register pulses.
(Basic configuration 4)
In addition, as a solid-state imaging device capable of stopping horizontal or vertical scanning at an arbitrary position, a solid-state imaging in which a plurality of pixel cells having photoelectric conversion units that generate signal charges according to the luminance of incident light are formed on a semiconductor substrate A horizontal scanning unit and a vertical scanning unit that scan the pixel cells, and an output unit that outputs an image signal read as a result of scanning the pixel cells by the horizontal scanning unit and the vertical scanning unit, The shift register circuit having the above configuration 1 is used for one of the scanning unit and the vertical scanning unit.

With this configuration, it is possible to stop horizontal or vertical scanning at an arbitrary position by using a solid-state imaging device that scans the sensor unit with sequentially output shift register pulses.
(Basic configuration 5)
In addition, as a solid-state imaging device capable of starting horizontal and vertical scanning from any position, a solid-state imaging in which a plurality of pixel cells having photoelectric conversion units that generate signal charges according to the luminance of incident light are formed on a semiconductor substrate A horizontal scanning unit and a vertical scanning unit that scan the pixel cells, and an output unit that outputs an image signal read as a result of scanning the pixel cells by the horizontal scanning unit and the vertical scanning unit, The shift register circuit having the above-described configuration 2 is used for both the scanning unit and the vertical scanning unit.

With this configuration, it is possible to start horizontal and vertical scanning from an arbitrary position by using a solid-state imaging device that scans the sensor unit with sequentially output shift register pulses.
(Basic configuration 6)
In addition, as a solid-state imaging device capable of starting horizontal or vertical scanning from an arbitrary position, a solid-state imaging in which a plurality of pixel cells having photoelectric conversion units that generate signal charges according to the luminance of incident light are formed on a semiconductor substrate A horizontal scanning unit and a vertical scanning unit that scan the pixel cells, and an output unit that outputs an image signal read as a result of scanning the pixel cells by the horizontal scanning unit and the vertical scanning unit, The shift register circuit having the above configuration 2 is used for one of the scanning unit and the vertical scanning unit.

With this configuration, it is possible to start horizontal or vertical scanning from an arbitrary position by using a solid-state imaging device that scans the sensor unit with sequentially output shift register pulses.
(Basic configuration 7)
In addition, as a solid-state imaging device in which horizontal and vertical scanning positions can be arbitrarily set, a solid-state imaging device in which a plurality of pixel cells having photoelectric conversion units that generate signal charges according to the luminance of incident light are formed on a semiconductor substrate. A horizontal scanning unit and a vertical scanning unit that scan the pixel cells, and an output unit that outputs an image signal read as a result of scanning the pixel cells by the horizontal scanning unit and the vertical scanning unit, The shift register circuit having the above-described configuration 1 is used for both the vertical scanning units, or the shift register circuit having the above-described configuration 2 is used for one of the horizontal scanning unit and the vertical scanning unit.

With this configuration, it is possible to arbitrarily set the horizontal and vertical scanning positions by using the solid-state imaging device that determines the location where the sensor unit is scanned by the sequentially output shift register pulses.
(Basic configuration 8)
In addition, as a means to stop the scanning of the sensor unit at an arbitrary position by light incidence, it is composed of a multi-stage circuit, and the voltage of the drive start pulse is accumulated in the bootstrap capacitor of each stage circuit and accumulated in the subsequent circuit. The shift register circuit (signal transmission circuit) sequentially outputs the shift register pulse according to the drive start pulse by repeating the transfer of the drive start pulse voltage, and the photoelectric effect by the light incident control Thus, a shift register circuit characterized by individually resetting the bootstrap capacitance of each stage circuit is used.

With this configuration, the shift register pulse can be stopped at an arbitrary position.
(Basic configuration 9)
In addition, as a solid-state imaging device that can stop horizontal and vertical scanning at an arbitrary position by light incidence, a plurality of pixel cells having a photoelectric conversion unit that generates signal charges according to the luminance of incident light are formed on a semiconductor substrate. A solid-state imaging device comprising a horizontal scanning unit and a vertical scanning unit that scan pixel pixels, and an output unit that outputs an image signal read out as a result of scanning the pixel cells by the horizontal scanning unit and vertical scanning unit The shift register circuit having the above-described configuration 8 is used for both the horizontal scanning unit and the vertical scanning unit.

With this configuration, it is possible to stop horizontal and vertical scanning at arbitrary positions by using a solid-state imaging device that determines a location where the sensor unit is scanned by sequentially output shift register pulses.
(Basic configuration 10)
In addition, as a solid-state imaging device that can stop horizontal or vertical scanning at an arbitrary position by light incidence, a plurality of pixel cells having a photoelectric conversion unit that generates signal charges according to the luminance of incident light are formed on a semiconductor substrate. A solid-state imaging device comprising a horizontal scanning unit and a vertical scanning unit that scan pixel pixels, and an output unit that outputs an image signal read out as a result of scanning the pixel cells by the horizontal scanning unit and vertical scanning unit The shift register circuit having the above-described configuration 8 is used for one of the horizontal scanning unit and the vertical scanning unit.

With this configuration, it is possible to stop horizontal or vertical scanning at an arbitrary position by using a solid-state imaging device that determines a place where the sensor unit is scanned by sequentially output shift register pulses.
(Basic configuration 11)
In addition, as an arbitrarily readable camera device (imaging device), an area for scanning the imaging unit of any one of the configuration 3 to the configuration 7 and the configuration 9 to the configuration 10 is set, and solid-state imaging is performed. A timing generator circuit that generates and outputs a synchronization signal only for a set image area of a scanning unit and a non-scanning unit that does not perform signal processing for a circuit that performs signal processing of element outputs. A circuit that performs signal processing on the output of the solid-state imaging device and a camera device including them are used.

With this configuration, it is possible to improve the frame rate and reduce power consumption by not performing signal processing in the non-scanning area other than the scanning area.
(Basic configuration 12)
Further, as a means for setting a scanning area (imaging area) of the screen, the scanning area of the imaging section is set based on a result of motion detection by a signal processing circuit at a subsequent stage for the solid-state imaging device having the configuration 7. The timing generator circuit having the above-described configuration 11, the circuit for processing the output of the solid-state imaging device, and the camera device including them are used.

With this configuration, if it is determined that the subject being photographed is likely to move in the horizontal direction, the frame rate is improved by narrowing the scanning area in the vertical direction of the screen, and the subject being photographed is oriented vertically. If it is determined that there is a high possibility that the frame has moved to the frame rate, the frame rate can be improved by narrowing the scanning area in the horizontal direction of the screen.
(Basic configuration 13)
In addition, as a means for resetting the photodiode, the non-scanning region of the imaging unit is scanned at regular intervals for the solid-state imaging device having the configuration 7; A circuit that performs signal processing on the image sensor output and a camera device including them are used.

With this configuration, it is possible to reset the charge accumulated in the photodiodes of the non-scanning portion of the solid-state imaging device having the above-described configuration 7 by scanning the image region of the non-scanning portion at regular intervals.
(Basic configuration 14)
As a means for formatting a scanned image, a scanning start position and a scanning end position are set so that the scanning line (row) or scanning pixel (column) of the imaging unit is “even” for the solid-state imaging device having the above-described configuration 7. Are used, and a timing generator circuit, a circuit that performs signal processing on the output of the solid-state imaging device, and a camera device including them.

With this configuration, a hue shift does not occur.
(Basic configuration 15)
Further, as means for automatically resetting the photodiode, the brightness level of the pixel adjacent to the non-scanning region of the pixel cell is calculated for the solid-state imaging device having the above-described configuration 7, and the calculated value reaches a constant level set from the outside. A timing generator circuit configured to output a pulse for executing scanning of the non-scanning region of the pixel cell, and a circuit for integrating the luminance level, and scanning the non-scanning region with the timing generator circuit. A circuit that performs signal processing on the output of the solid-state imaging device that outputs an instruction, and a camera device including them are used.

With this configuration, the reset operation can be automatically executed by scanning the non-scanning region when the charge of the photodiode in the non-scanning unit exceeds a set threshold value.
(Embodiment 1)
FIG. 4 shows a “shift register type” dynamic circuit (shift register circuit) for “scanning the screen at an arbitrary position” for the MOS image sensor. This configuration example is an example when the shift register circuit is first driven immediately after the system is started. An example in which the shift register circuit is already driven and the screen scanning is stopped at an arbitrary position will be described later in the third embodiment.

  4 represents one stage of the shift register circuit, and FIG. 4 is an example of a shift register circuit having a four-stage configuration. However, the number of stages of the shift register circuit of the present invention is restricted by this. It is not something.

  Start pulse: A circuit (transistor (416)) that resets the charge stored in the bootstrap capacitor (409) through the wiring (421), and the charge stored in the bootstrap capacitor (418). Connected to a circuit for resetting the charge of the bootstrap capacitor such as a reset circuit (transistor (419)). The other configuration of FIG. 4 is the same as that of the conventional example of FIG. That is, except for the wiring (421), the circuit scale does not increase from the conventional circuit example.

  As shown in the timing chart of FIG. 5, for example, start pulse: VST (401) is input every cycle similar to shift register transfer pulse 1: V1 (402) and shift register transfer pulse 2: V2 (403). Then, each time the shift register transfer pulse 1: V1 (402) and the start pulse: VST (401) become High, the electric charge accumulated in the bootstrap capacitor (418) becomes high in the transistors (417) and (419). Since the gate is turned on and discharged to GND, shift register pulse 3: VSOUT3 (414) is not output, shift register pulse 1: VSOUT1 (412) and shift register pulse 2: VSOUT2 (413) are output, The two lines selected by are scanned and output. When the number of shift register drive pulses = m (integer) and the period of the start pulse of the shift register circuit synchronized with the shift register transfer pulse = n (n ≧ 1 is an integer), the relationship 2n = m is established.

  As described above, by wiring the start pulse: VST (401) to the circuit for resetting the charge of the bootstrap capacitor so as to be input, and periodically inputting the start pulse according to the number of lines to be scanned, Since only the shift register driving pulse used for scanning can be output, scanning of the screen can be stopped at an arbitrary position.

  FIG. 6 shows a screen scanning image using an image sensor in which the shift register circuit is mounted. Reference numeral 701 denotes an example in which the shift register circuit of FIG. 4 is used only for the horizontal shift register unit (103), and the horizontal shift register unit 103 stops the horizontal shift register unit (103) at 703 with respect to the scanning unit (702). This is an example in which the start pulse (401) of (103) is periodically input, and 704 is a non-scanning region. By outputting the horizontal synchronization signal (714) and the vertical synchronization signal (715) as the video synchronization signal from the TG unit (107) in FIG. 1, it is possible to synchronize with the signal processing unit (114) at the subsequent stage.

  Reference numeral 705 denotes an example in which the shift register circuit of FIG. 4 is used only for the vertical shift register unit 104, and the vertical shift register unit 104 stops the vertical shift register unit 104 at 707 with respect to the scanning unit 706. In this example, the start pulse (401) of (104) is periodically input, and 708 is a non-scanning region. By outputting the horizontal synchronization signal (716) and the vertical synchronization signal (717) as the video synchronization signal from the TG unit (107) in FIG. 1, it is possible to synchronize with the signal processing unit (114) at the subsequent stage.

  Reference numeral 709 denotes an example in which the shift register circuit of FIG. 4 is used for the horizontal shift register unit (103) and the vertical shift register unit (104), and the horizontal shift register path (103) is stopped at 711 with respect to the scanning unit (710). Thus, the start pulse (401) of the horizontal shift register unit (103) is periodically input, and the start pulse (401) of the vertical shift register unit (104) is stopped so that the vertical shift register unit (104) is stopped at 712. ) Is periodically input, and 713 is a non-scanning region.

  By outputting the horizontal synchronization signal (718) and the vertical synchronization signal (719) as the video synchronization signal from the TG unit (107) in FIG. 1, it is possible to synchronize with the signal processing unit (114) in the subsequent stage.

  FIG. 1 shows a configuration of a “MOS type image sensor” and an example of a camera system. The horizontal shift register unit and the vertical shift register unit are the same as the horizontal shift register unit (103) and the vertical shift register in FIG. 4 is input from the TG (timing generation) unit (107), the start pulse (401), the shift register transfer pulse 1: V1 (402), and the shift register transfer pulse 2: V2 (403). Is done. The horizontal shift register unit (103) and the vertical shift register unit (104) select a row (in the case of the vertical shift register unit) or a column (in the case of the horizontal shift register unit) such as the shift register pulse 1: VSOUT1 (412). A pulse is output, and “only the selected scanning section” is scanned.

  In the example of FIG. 6, reference numeral 720 denotes an image operation area of K pixels × M lines. By setting the image operation area of K pixels × N lines (M: N = 2: 1) as 721, the frame rate is set. Can be doubled.

  Therefore, as shown in FIG. 6, the frame rate can be varied by setting the non-scanning area, and the frame rate can be improved by increasing the non-scanning area.

  At this time, the timing generation unit (107) in FIG. 1 performs signal processing on the outputs of the AFE (analog front end 112) and the AFE (112) which perform CDS (correlated double sampling) or A / D conversion on the sensor output (111). The output video signal (115) is synchronized by outputting a pulse that matches the AFE drive pulse (109) and the synchronization pulse (110) to the selected scanning unit to the signal processing unit (114). In addition, the power consumption can be reduced by stopping the signal processing and scanning of the portion of the area that has become the non-scanning area.

The above is an effective technique for a medical capsule camera or the like that requires low power consumption and needs to capture a required image size in a high-speed frame.
(Embodiment 2)
FIG. 7 shows a shift register circuit using a “shift register system” dynamic circuit for “starting screen scanning from an arbitrary position” for a MOS image sensor. Note that one of the dotted lines in FIG. 7 represents one stage of the shift register circuit, and FIG. 7 is an example of a shift register circuit having a four-stage configuration. However, the number of stages of the shift register circuit of the present invention is It is not bound.

  Reference numerals 801 to 820 are the same as 401 to 420 in FIG. Each of the start pulses VST (822), (823), (824), and (825) can be input from the VST output circuit (821) to each input of each stage circuit. The VST output circuit (821) inputs a start pulse: VST from the shift register circuit in the row or column where scanning is to be started.

  FIG. 8 is an example (timing chart) in which a start pulse: VST (823) is input. The input start pulse: VST (823) is sequentially output as a shift register pulse 2: VSOUT2 (813), a shift register pulse 3: VSOUT3 (814), and a shift register pulse 4: VSOUT4 (815), and is thereby selected. Scan a row or column. Further, since the start pulse: VST (822) is not input, the shift register pulse 1: VSOUT1 (812) is not output, and the row or column selected by the shift register pulse 1: VSOUT1 (812) is not scanned.

  At this time, when the start pulses: VST (822) and (824) in FIG. 7 are input to the shift register circuit, they are not input unless the transistors (804) and (817) are turned on. : When V1 (802) is High and when the start pulses: VST (823) and (825) are input to the shift register circuit, the transistors (808) and (826) are not input unless they are turned on. When the shift register transfer pulse 2: V2 (803) is High, it is necessary to input the start pulse: VST to the shift register circuit. The start pulse: VST (823) shown in FIG. 8 is an example inputted when the shift register transfer pulse 2: V2 (803) is High.

  As described above, the start pulse: VST can be input to each stage circuit of the shift register circuit, and the start pulse is periodically input to the stage number circuit corresponding to the number of lines to be scanned. It is possible to “start scanning of the screen from an arbitrary position”.

  When the number of shift register drive pulses = m (integer) and the period of the start pulse of the shift register circuit synchronized with the shift register transfer pulse = n (n ≧ 1 is an integer), the relationship 2n = m is established.

  As in the first embodiment, FIG. 1 shows “a configuration of a MOS type image sensor” and an example of a camera system. The horizontal shift register unit and the vertical shift register unit in FIG. Part (103) and vertical shift register part (104), from TG (timing generation) part (107), start pulse (823 to 825) and shift register transfer pulse 1: V1 (802) and shift register transfer in FIG. Pulse 2: V2 (803) is input. The horizontal shift register unit (103) and the vertical shift register unit (104) select a row (in the case of the vertical shift register unit) or a column (in the case of the horizontal shift register unit) such as shift register pulse 2: VSOUT2 (813). A pulse is output, and “only the selected scanning section” is scanned.

  In the example of FIG. 9D, reference numeral 1020 denotes an image operation area of K pixels × M lines. By setting the image operation area of K pixels × N lines (M: N = 2: 1) like 1021, The frame rate can be doubled. Therefore, as shown in FIG. 9D, the frame rate can be varied by setting the non-scanning area, and the frame rate can be improved by increasing the non-scanning area.

  FIG. 9 shows a screen scanning image using an image sensor in which the present shift register circuit is mounted. Reference numeral 1001 denotes an example in which the shift register circuit of FIG. 7 is used only for the horizontal shift register unit (103). The horizontal shift register unit 103 starts the horizontal shift register unit 103 so that the scanning unit 1002 starts scanning by the horizontal shift register unit 103. In this example, the start pulse of the register unit (103) is periodically input, and 1004 is a non-scanning region. By outputting a horizontal synchronizing signal (1014) and a vertical synchronizing signal (1015) as video synchronizing signals from the TG unit (107) in FIG. 1, it becomes possible to synchronize with the signal processing unit (114) in the subsequent stage. .

  Reference numeral 1007 denotes an example in which the shift register circuit of FIG. 7 is used only for the vertical shift register unit (104). The vertical shift register unit 1044 starts the vertical shift register unit (104) so that scanning by the vertical shift register unit (104) starts from 1006. This is an example in which the start pulse of the register unit (104) is periodically input, and 1008 is a non-scanning region. By outputting the horizontal synchronizing signal (1016) and the vertical synchronizing signal (1017) as the video synchronizing signal from the TG unit (107) in FIG. 1, it becomes possible to synchronize with the signal processing unit (114) in the subsequent stage. .

  Reference numeral 1010 denotes an example in which the shift register circuit of FIG. 7 is used for the horizontal shift register unit (103) and the vertical shift register unit (104). The scanning unit (1022) is scanned by the horizontal shift register unit (103) from 1011. The start pulse of the horizontal shift register unit (103) is periodically inputted so as to start, and the start pulse of the vertical shift register unit (104) is started so as to start scanning by the vertical shift register unit (104) from 1012 This is an example of periodic input, and 1009 is a non-scanning area. By outputting the horizontal synchronizing signal (1018) and the vertical synchronizing signal (1019) as the video synchronizing signal from the TG unit (107) in FIG. 1, it becomes possible to synchronize with the signal processing unit (114) in the subsequent stage. .

  At this time, the timing generator (107) in FIG. 1 outputs the sensor output (111) to the CDS (correlated double sampling) or A / D conversion AFE (analog front end) (112) and the output of the AFE (112). The video signal (115) to be output is output by outputting a pulse matching the selected scanning unit, such as the AFE drive pulse (109) and the synchronization pulse (110), to the signal processing unit (114) that performs signal processing. ) And the signal processing and scanning of the area portion that has become the non-scanning area can be stopped, thereby reducing the power consumption.

This is an effective technique for a medical capsule camera or the like that requires low power consumption and needs to capture a required image size in a high-speed frame.
(Embodiment 3)
FIG. 10 shows a shift register circuit using a “shift register system” dynamic circuit for “starting scanning at an arbitrary position and stopping at an arbitrary position” for a MOS image sensor. The shift register circuit configuration is a mixture of the shift register circuit of the first embodiment (FIG. 4) and the shift register circuit of the second embodiment (FIG. 7).

  The VST output circuit (1121) can input the start pulses VST (1122), (1123), (1124), and (1125) of FIG. 10 to the input part of each stage (dotted line part) of the shift register circuit. In addition, the wiring (1127) is connected to the reset circuits (1116), (1119), (1119), (1119), (1119), (1119), (1119), resetting the charges of the bootstrap capacitors (1109), (1118), (1128). 1120), and can be reset by the same start pulse: VST. However, this configuration requires a diode (1129) as shown in FIG.

  For example, if the start pulse: VST (1122) is inputted when the shift register transfer pulse 1: V1 (1102) is High without the diode (1129), the start pulse: VST (1124) is routed. Charge is also accumulated in the bootstrap capacitor (1118) via the transistor (1117), and then when the shift register transfer pulse 2: V2 (1103) becomes High, the shift register pulse 1: VSOUT1 (1112) Shift register pulse 3: VSOUT3 (1114) is output at the same time. Since the diode (1129) as shown can be formed by one transistor, the circuit scale does not increase.

  In FIG. 11, a start pulse: VST (1123) is input every cycle similar to the shift register transfer pulse 1: V1 (1102) and the shift register transfer pulse 2: V2 (1103), and only two lines can be selected. A chart is shown. Since the start pulse: VST (1122) in FIG. 10 is not input, the shift register pulse 1: VSOUT1 (1112) is not output, and the start pulse: VST (1123) is supplied to the reset circuit (1120) of the bootstrap capacitor (1128). Since the transfer pulse capacity stored in the bootstrap capacitor (1128) is reset every time the input is input, the shift register pulse 4: VSOUT4 (1115) is not output, and the shift register pulse 2: VSOUT2 (1113) Shift register pulse 3: Since only VSOUT3 (1114) can be output, only two lines can be selected.

Here, a case where the scanning stop position is changed during the shift operation is shown.
When a new start pulse: VST (1123) is input in FIG. 10, in the past shift operation, if the bootstrap capacitor (1128) is used as a bootstrap capacitor in which charges are accumulated, the start pulse: VST (1123) ), The shift register transfer pulse 2: If V2 (1103) is not High, the transistor (1126) is not turned on, so the charge of the bootstrap capacitor (1128) cannot be reset and stopped at an arbitrary position. I can't. When the start pulse: VST is input to the even stage of the shift register circuit, the odd stage cannot be reset, and when the start pulse: VST is input to the odd stage of the shift register circuit, the even stage is Cannot reset.

  Therefore, as in the period (1803) in FIG. 17, the shift register transfer pulse 1: V1 (1202) and the shift register transfer pulse 2: V2 (1203) are started in the high periods (1802) and (1801), respectively: All bootstrap capacitors are reset by entering VST (1223). However, unlike 1804, shift register pulse 2: VSOUT2 (1213) to shift register pulse 4: VSOUT4 (1215) are not output during this period.

  After resetting all the bootstrap capacitors, as in 1805, the shift register transfer pulse 2: V2 (1203) is inputted with the start pulse: VST (1223) during the high period, so that the shift register pulse 2 similar to the previous example is obtained. : Only VSOUT2 (1213) and shift register pulse 3: VSOUT3 (1214) can be output, so only two lines can be selected.

FIG. 12 shows a screen scanning image using an image sensor in which the present shift register circuit (FIG. 10) is mounted.
Reference numeral 1301 denotes an example in which the shift register circuit of FIG. 10 is used only for the horizontal shift register unit (103). Scanning by the horizontal shift register unit (103) is started from 1303 for the scanning unit (1302), and horizontal shift is performed at 1305. This is an example in which the start pulse of the horizontal shift register unit (103) is periodically input so as to stop scanning by the register unit (103). Reference numeral 1302 denotes a scanning area, and 1304 denotes a non-scanning area (left and right).

  By outputting the horizontal synchronizing signal (1306) and the vertical synchronizing signal (1307) as the video synchronizing signal, it is possible to synchronize with the signal processing unit (114) at the subsequent stage. Further, it is effective for a system that does not require an image area in the horizontal direction rather than the normal image size, such as a mobile phone camera that displays on a vertically long liquid crystal display.

  Similarly, reference numeral 1308 is an example in which the shift register circuit of FIG. 10 is used only for the vertical shift register unit (104). Scanning of the scanning unit (1309) by the vertical shift register unit is started from 1310, and vertical shift is performed by 1312. This is an example in which the start pulse of the vertical shift register unit (104) is periodically input so as to stop scanning by the register unit. Reference numeral 1309 denotes a scanning area, and reference numeral 1311 denotes a non-scanning area (up and down).

  By outputting the horizontal synchronizing signal (1313) and the vertical synchronizing signal (1314) as the video synchronizing signal, it is possible to synchronize with the signal processing unit (114) at the subsequent stage. Moreover, it is effective for a camera system that does not require an image area in the vertical direction rather than a normal image size, such as a vehicle camera for rear monitoring.

  Similarly, reference numeral 1315 denotes an example in which the shift register circuit of FIG. 10 is used for the horizontal shift register unit (103) and the vertical shift register unit (104), and from 1319 to the vertical shift register unit (104) for the scanning unit (1325). The start pulse of the vertical shift register unit (104) is periodically input so that the scanning by the vertical shift register unit (104) is stopped and terminated at 1322, and the horizontal shift register unit (103) is started from 1316. This is an example in which the start pulse of the horizontal shift register unit (103) is periodically input so that the scanning by the horizontal shift register unit (103) is stopped and terminated at 1318. Reference numeral 1325 denotes a scanning area, and reference numeral 1317 denotes a non-scanning area (up / down / left / right).

By outputting the horizontal synchronizing signal (1323) and the vertical synchronizing signal (1324) as the video synchronizing signal, it becomes possible to synchronize with the signal processing unit (114) at the subsequent stage. Further, it is effective for a camera system such as a medical capsule camera that requires a frame rate without requiring an image area as compared with a normal image size depending on a photographing location.
(Embodiment 4)
FIG. 13 shows a “shift register type” solid-state imaging device having a shift register circuit for “stopping scanning of the screen at an arbitrary position” with respect to the MOS type image sensor by the incidence of light, and the solid-state imaging device. An example of the configuration of a camera system is shown.

  Shift register pulse 2: VSOUT2 (1413) and subsequent shift register pulse 3: VSOUT3 (1414) and shift register pulse 4: VSOUT4 (1423) are not output, and the area selected by shift register pulse 2: VSOUT2 (1413) This is an example of scanning the sensor unit (102).

  Reference numerals 1418, 1419, and 1420 denote incident light selection portions for selecting whether light is incident or shielded from the input transistors (1404), (1408), and (1416) of each stage circuit of the shift register circuit. 1420) allows the light (1422) to be incident on the transistor (1416), and the other light shielding portions (1419 and the like) shield the light (1424).

  When a certain amount of light (1422) enters the input transistor (1416) of the shift register circuit, a photoelectric effect occurs at the PN junction of the input transistor (1416), and the generated electrons (1425) cause a bootstrap capacitor (1417). ) Is reduced, the transistor (1426) cannot be turned on, and the shift register pulse 3: VSOUT3 (1414) is not output. Further, since the charge stored in the bootstrap capacitor (1417) is reduced, the transistor (1428) is not turned on, so that the charge cannot be transferred to the bootstrap capacitor (1427), and the shift register pulse 3: Shift register pulse 4 after VSOUT3 (1414): Shift register pulse output such as VSOUT4 (1423) is also stopped.

  It should be noted that on / off of light incidence on the input transistor of the shift register circuit may be determined by electrical control in a programmable manner, and the incident light selection portions (1418), (1419), (1420), etc. are solid-state imaging. Whether or not light is shielded during manufacture on the element may be fixed by a mask pattern.

  Thus, by controlling the incidence of light without increasing the circuit scale of the shift register circuit, horizontal and vertical scanning with respect to the sensor unit can be stopped at an arbitrary position.

As in the first to third embodiments, the timing generation unit (107) in FIG. 1 performs CDS (correlated double sampling) and A / D conversion (AFE (analog front end)) (112) for the sensor output (111). And the signal processing unit (114) that performs signal processing on the output (113) of the AFE unit (112), and synchronizes with the AFE drive pulse (109) and the scanning unit selected on the sensor unit (102). By outputting the pulse (110), the output video signal (115) can be synchronized, and the signal processing and scanning of the portion of the area that has become the non-scanning area can be stopped, so that Power consumption can be reduced.
(Embodiment 5)
FIG. 14 is an explanatory diagram of an operation example of a camera system using a “shift register type” MOS image sensor. Here, an example in which the frame rate is improved by controlling the scanning area of the screen by detecting the motion of the image in the camera system will be described with reference to FIGS. 14 and 1.

  When the motion vector (1502) of the subject (1505) is moving in the horizontal direction (arrow direction) on the screen (1501) in FIG. 14A, the movement is shown in FIG. When detected by the signal processing unit (114) of the camera system using the image sensor), the TG unit (107) outputs a sensor driving pulse (108) to the solid-state image sensor (101), and the solid-state image sensor ( 101), a vertical shift register unit (104) (described in the third embodiment) is used to provide non-scanning units (1504) at the top and bottom of the screen as in the screen (1503) of FIG. By reducing the frame rate, the frame rate can be improved.

  Further, when the motion vector (1507) of the subject (1508) is moving in the vertical direction (arrow direction) on the screen (1506) in FIG. 14B, the movement is indicated by the signal processing unit (114) in FIG. , The TG unit (107) outputs a sensor driving pulse (108) to the solid-state image sensor (101), and the horizontal shift register unit (103) (implementation) in the solid-state image sensor (101). The frame rate can be improved by providing non-scanning portions (1510) on the left and right sides of the screen as in the screen (1509) of FIG. Become.

  For example, in recent years, there is a mobile phone with a camera corresponding to 1 segment, and the mounting of chips capable of processing a moving image encoded signal such as MPEG-4 is increasing. The motion detection information from the moving image coding processing chip may be given to the TG unit (107) as information for determining the scanning region via the signal processing unit (114).

In the case of a built-in surveillance camera (security camera) or a vehicle-mounted camera installed in a vehicle interior, the movement of the subject is often limited to the same direction. It is possible to improve the frame rate by detecting the movement of the subject and narrowing down the imaging area for the subject.
(Embodiment 6)
Next, by using FIG. 15, the non-scanning portion is scanned once every several frames to accumulate in the non-scanning period in the photodiode that forms each unit pixel in the sensor portion (102) of the solid-state imaging device. An example of resetting the generated charge will be described.

  FIG. 15 is an explanatory diagram of an example of a scanning range when the non-scanning portion is scanned once every three frames in the solid-state imaging device of the sixth embodiment and an imaging apparatus using the same. Although an example in which the entire screen is scanned once every three frames is shown here, the present invention is not limited to the cycle.

  Screens (1601) to (1605) in FIG. 15 are image frames obtained by sequentially photographing the subject (1606). Screen regions (1607) and (1609) in the frames of screens (1602) and (1603) are non-scanning portions. And

  The scanning unit of the solid-state image sensor reads out the charge accumulated in the photodiode by driving the shift register circuit, but the non-scanning unit does not read out and the charge continues to accumulate in the photodiode. Like the frame (1611), the charge accumulated in the photodiode in the non-scanning region (1610) may leak into the region (1608) of the scanning portion.

  In the camera system using the “shift register type” MOS image sensor of FIG. 1, the TG unit (107) outputs a sensor drive pulse (108) to the solid-state image sensor (101), and the solid-state image sensor (101). ) In the horizontal shift register unit (103) and the vertical shift register unit (104) (both described in the third embodiment), as shown in a screen (1604), every predetermined frame (for example, 3 frames) All the pixels are scanned at a rate of once every), and the pixels that were the non-scanning portion in the previous frame are read out, thereby resetting the charge accumulated in the photodiode.

  Even if read out in this way, the synchronization pulse is not output, and the signal processor (114) does not execute the processing, and the effective period of the synchronization pulse on the screen (1604) is set to the period (1613) of the screen (1603), for example. 1), the output signal (115) has the same image size as that of the frame including the non-scanning portion, so that the power consumption of the signal processing portion (114) in FIG. 1 does not increase. That is, it represents the “original reset region” in which the region (1612) is read from the solid-state imaging device (101) but no signal processing is performed.

  Further, a circuit for calculating the luminance level of the adjacent pixel in the non-scanning region and comparing it with a threshold that can be set by the user from the outside is provided in the signal processing unit (114) in FIG. When the threshold value exceeds the set threshold value, it is determined that the charge of the photodiode in the non-scanning region is overflowing, and an operation of scanning and resetting the non-scanning region can be executed.

As described above, when the non-scanning region is scanned every predetermined period, when a strong light amount is suddenly incident, it is not possible to cope with a certain period of time.
(Embodiment 7)
Next, the number of lines and the number of pixels from the start of scanning to the end of scanning for the sensor unit (102) will be described with reference to FIG.

  FIG. 16 shows a diagram of the number of lines and the number of pixels in the solid-state imaging device of the seventh embodiment and an imaging apparatus using the same. Reference numeral 1701 denotes an example in which a region of 4 lines × 8 pixels is scanned on the sensor unit (102) which is a Bayer array in the solid-state imaging device (101) of FIG. 1, and R (red) · For each pixel of G (green) and B (blue), image processing is performed for the missing pixel information according to the interpolation algorithm. Normally, the pixel array of the solid-state imaging device has a configuration of even lines × even pixels, and the interpolation algorithm performs image processing according to a certain rule of each company.

  As shown by 1702 in FIG. 16, the scanning start line starts one line later than the normal case (1701) and the number of lines to be scanned becomes an odd number of lines (3 lines in the example), or as shown by 1703. When the pixel to start scanning starts one pixel later than the normal case (1701) and the number of pixels to be scanned is an odd number (7 pixels in the example), the signal processing unit (114) in FIG. When the interpolation algorithm is formed on the assumption that the sensor output (111) is output from the solid-state imaging device (101) in a pattern like 1701, there is a possibility that the interpolation processing is shifted in the signal processing unit (114). is there. In particular, when the signal processing unit (114) of FIG. 1 does not support flexible interpolation processing with another chip, the processing cannot be performed.

  Therefore, in the first to fifth embodiments, when the sensor drive pulse (108) is output from the TG unit (107) in FIG. 1 and the scan start position and the scan end position are set, the configuration is even lines × even pixels. It is desirable to do so.

  The solid-state imaging device of the present invention and the imaging apparatus using the same realize a dynamic circuit capable of starting and stopping the screen scanning of the MOS image sensor from an arbitrary position without increasing the circuit scale. The readout area for reading out the pixel state on the screen can be arbitrarily set, and the degree of freedom for the readout area of the pixel state with respect to the MOS type image sensor can be increased. ) And mobile camera systems such as camera-equipped mobile phones, security cameras such as in-vehicle cameras and network cameras, and medical capsule cameras, which are effective for small, low power consumption and high frame rate camera systems.

A block diagram showing a configuration of a conventional solid-state imaging device and an imaging apparatus using the same The circuit diagram which shows the circuit structure of the shift register circuit in the solid-state image sensor of the conventional example Waveform diagram of each part showing the operation of the shift register circuit in the solid-state image sensor of the conventional example 1 is a circuit diagram showing a circuit configuration of a shift register circuit using a configuration example 1 of a dynamic circuit in a solid-state imaging device and an imaging apparatus using the same according to Embodiment 1 of the present invention; Waveform diagram of each part showing the operation of the shift register circuit (Embodiment 1) of FIG. Output image showing operation of shift register circuit (first embodiment) of FIG. FIG. 7 is a circuit diagram showing a circuit configuration of a shift register circuit using a configuration example 2 of a dynamic circuit in a solid-state imaging device and an imaging apparatus using the same according to a second embodiment of the present invention. Waveform diagram of each part showing the operation of the shift register circuit (Embodiment 2) of FIG. Output image showing the operation of the shift register circuit (Embodiment 2) of FIG. FIG. 9 is a circuit diagram showing a circuit configuration of a shift register circuit using a configuration example 3 of a dynamic circuit in a solid-state imaging device and an imaging apparatus using the same according to a third embodiment of the present invention. FIG. 10 is a waveform diagram of each part showing the operation of the shift register circuit (Embodiment 3) of FIG. Output image showing the operation of the shift register circuit (Embodiment 3) of FIG. FIG. 7 is a circuit diagram showing a circuit configuration of a shift register circuit using a configuration example 4 of a dynamic circuit in a solid-state imaging device and an imaging apparatus using the solid-state imaging device according to Embodiment 4 of the present invention, and waveform diagrams showing each operation. Explanatory drawing of the example of the scanning range by the motion detection in the solid-state image sensor of Embodiment 5 of this invention, and an imaging device using the same Explanatory drawing of the example of a scanning range in the case of scanning a non-scanning part once in 3 frames in the solid-state image sensor of Embodiment 6 of this invention and an imaging device using the same Explanatory drawing of the number of lines and the number of pixels in the solid-state imaging device of Embodiment 7 of this invention and an imaging device using the same FIG. 2 is a waveform diagram of each part showing the operation of the shift register circuit (Embodiment 3) of FIG.

Explanation of symbols

101 Solid-state image sensor (MOS type image sensor)
DESCRIPTION OF SYMBOLS 102 Sensor part 103 Horizontal shift register part 104 Vertical shift register part 105 Noise canceller part 106 AMP part (output part)
107 TG (timing generation) unit 108 sensor driving pulse (for shift register type MOS image sensor) 109 AFE (analog front end) driving pulse 110 synchronization pulse 111 sensor output (for shift register type MOS image sensor) 112 AFE (Analog front end) unit 113 (AFE unit) output 114 Signal processing unit 115 (Signal processing unit) output 116 Signal processing circuit 201 (Shift register circuit) Start pulse: VST
202 Shift register transfer pulse 1: V1
203 Shift register transfer pulse 2: V2
204, 208, 216 Shift register input circuit 205, 209, 217 Bootstrap capacitor 206, 210 Transistor A
207, 211 Transistor B
212 Shift register pulse 1: VSOUT1
213 Shift register pulse 2: VSOUT2
214 Shift register pulse 3: VSOUT3
215 Bootstrap capacitor reset circuit 401 (shift register circuit) start pulse: VST
402 Shift register transfer pulse 1: V1
403 Shift register transfer pulse 2: V2
404, 408, 417 Shift register input circuit 405, 409, 418 Bootstrap capacitor 406, 410 Transistor A
407, 411 Transistor B
412 Shift register pulse 1: VSOUT1
413 Shift register pulse 2: VSOUT2
414 Shift register pulse 3: VSOUT3
415 Shift register pulse 4: VSOUT4
416, 419, 420 Bootstrap capacitor reset circuit 421 (Connect shift register circuit start pulse: VST to bootstrap capacitor reset circuit) Wiring 701 (When shift register circuit of FIG. 4 is used for horizontal shift register unit) Scanning image 702, 706, 710 Scanning unit 703, 711 Horizontal scanning stop position 704, 708, 713 Non-scanning unit 705 Scanning image 707, 712 (when the shift register circuit of FIG. 4 is used for the vertical shift register unit) Vertical scanning stop position 709 Scanning image 714, 716, 718 Horizontal synchronization signal 715, 717, 719 Vertical synchronization signal 720 (M line × K pixel) (when the shift register circuit of FIG. 4 is used for the horizontal and vertical shift register units) Scanning area 721 M: N = 2: the N lines × K pixels when 1) scanning area 801,822,823,824,825 (shift register circuit) start pulse: VST
802 Shift register transfer pulse 1: V1
803 Shift register transfer pulse 2: V2
804, 808, 817, 826 Shift register input circuit 805, 809, 818 Bootstrap capacitor 806, 810 Transistor A
807, 811 Transistor B
812 Shift register pulse 1: VSOUT1
813 Shift register pulse 2: VSOUT2
814 Shift register pulse 3: VSOUT3
815 Shift register pulse 4: VSOUT4
816, 819, 820 Bootstrap capacitor reset circuit 821 VST output circuit 1001 Scanning image (when the shift register circuit of FIG. 7 is used in the horizontal shift register unit) 1002, 1005, 1022 Scan unit 1003, 1011 Horizontal scan start position 1004, 1008, 1009 Non-scanning unit 1007 Scanning image (when the shift register circuit of FIG. 7 is used for the vertical shift register unit) 1006, 1012 Vertical scanning start position 1010 (The shift register circuit of FIG. Scanning image 1014, 1016, 1018 Horizontal synchronization signal 1015, 1017, 1019 Vertical synchronization signal 1020 (M lines × K pixels) scanning region 1021 (M: N = 2: 1 N line) X K pixels) Area 1101,1122,1123,1124,1125 (of the shift register circuit) start pulse: VST
1102 Shift register transfer pulse 1: V1
1103 Shift register transfer pulse 2: V2
1104, 1108, 1117, 1126 Shift register input circuit 1105, 1109, 1118, 1128 Bootstrap capacitor 1106, 1110 Transistor A
1107, 1111 Transistor B
1112 Shift register pulse 1: VSOUT1
1113 Shift register pulse 2: VSOUT2
1114 Shift register pulse 3: VSOUT3
1115 Shift register pulse 4: VSOUT4
1116, 1119, 1120 Bootstrap capacitor reset circuit 1121 VST output circuit 1127 (Start pulse of shift register circuit input to all bootstrap capacitor reset circuits: connect VST) wiring 1129 diode 1301 (shift of FIG. 10 Scanning image 1302, 1309, 1325 Scanning unit 1303, 1316 Horizontal scanning start position 1305, 1318 Horizontal scanning end position 1304, 1311, 1317 Non-scanning unit 1308 (shift of FIG. 10) Scanning image 1310, 1319 Vertical scanning start position 1312, 1322 Vertical scanning end position 1315 (when register circuit is used for vertical shift register unit) Scanning image 1306, 1313, 1323 Horizontal sync signal 1307, 1314, 1324 Vertical sync signal 1401 (for shift register circuit) Start pulse: VST
1402 Shift register transfer pulse 1: V1
1403 Shift register transfer pulse 2: V2
1404, 1408, 1416 Shift register input circuit 1405, 1409, 1417, 1427 Bootstrap capacitor 1406, 1410, 1426 Transistor A
1407, 1411, 1428 Transistor B
1412 Shift register pulse 1: VSOUT1
1413 Shift register pulse 2: VSOUT2
1414 Shift register pulse 3: VSOUT3
1423 Shift register pulse 4: VSOUT4
1415 Bootstrap capacitor reset circuit 1418, 1419, 1421 Light-shielding part 1420 Incident part 1422, 1424 Incident light 1425 Electron generated by photoelectric effect 1501, 1506 (motion detection target) frame 1502 (moves in the detected horizontal direction) Motion vector 1503 (with reduced vertical scanning range) Frames 1504, 1510 Non-scanning unit 1505 (moving in the horizontal direction) Subject 1507 (moving in the detected vertical direction) Motion vector 1508 (moving in the vertical direction) Subject 1509 Frame 1 with reduced horizontal scanning range Frame 1601 Frame 1 with all areas as scanning areas
1602 Frame 2 (with non-scanning area)
1603 Frame 3 (with non-scanning area)
1604 Frame 4 (with all areas as scanning areas)
1605 (there is a non-scanning area where frame 1 is the most temporally past) frame 5
1606 Subject 1607, 1609, 1610 Non-scanning portion 1608 (Leaked from photodiode in non-scanning portion) Area 1611 (Leaked) frame 1701 (Even number line (4 lines) × Even number pixel (8 pixels)) frame 1702 (odd line (3 lines) × even pixel (8 pixels)) frame 1703 (even line (4 lines) × odd pixel (7 pixels)) frame

Claims (9)

A plurality of pixel cells for accumulating signal charges according to the luminance of incident light are formed on a semiconductor substrate, and the horizontal scanning unit and the vertical scanning unit that scan the pixel cells, and the pixel by the horizontal scanning unit and the vertical scanning unit A solid-state imaging device including an output unit that outputs an image signal read out as a result of scanning a cell;
It is composed of a dynamic circuit composed of a multi-stage circuit, and the voltage of the drive start pulse input to the first stage circuit is accumulated in the bootstrap capacitor of each stage circuit, and the post-stage circuit of the accumulated voltage of the drive start pulse The shift register pulse corresponding to the drive start pulse is sequentially output from each stage circuit, the pixel cell is scanned by the shift register pulse, and the drive start pulse input to the first stage circuit is repeated. Is connected to a circuit that resets the bootstrap capacitance of each stage circuit,
A solid-state imaging device, which is used for one of the horizontal scanning unit and the vertical scanning unit, or for both the horizontal scanning unit and the vertical scanning unit. A plurality of pixel cells for accumulating signal charges according to the luminance of incident light are formed on a semiconductor substrate, and the horizontal scanning unit and the vertical scanning unit that scan the pixel cells, and the pixel by the horizontal scanning unit and the vertical scanning unit A solid-state imaging device including an output unit that outputs an image signal read out as a result of scanning a cell;
It is composed of a dynamic circuit composed of a multi-stage circuit, and the voltage of the drive start pulse input to the first stage circuit is accumulated in the bootstrap capacitor of each stage circuit, and the post-stage circuit of the accumulated voltage of the drive start pulse The shift register pulse corresponding to the drive start pulse is sequentially output from each stage circuit, the pixel cell is scanned by the shift register pulse, and the drive start pulse input to the first stage circuit is repeated. A signal transmission circuit in which a start pulse different from the above is connected to the input part of each stage circuit,
A solid-state imaging device, which is used for one of the horizontal scanning unit and the vertical scanning unit, or for both the horizontal scanning unit and the vertical scanning unit. A plurality of pixel cells for accumulating signal charges according to the luminance of incident light are formed on a semiconductor substrate, and the horizontal scanning unit and the vertical scanning unit that scan the pixel cells, and the pixel by the horizontal scanning unit and the vertical scanning unit A solid-state imaging device including an output unit that outputs an image signal read out as a result of scanning a cell;
It is composed of a dynamic circuit composed of a multi-stage circuit, and the voltage of the drive start pulse input to the first stage circuit is accumulated in the bootstrap capacitor of each stage circuit, and the post-stage circuit of the accumulated voltage of the drive start pulse The shift register pulse corresponding to the drive start pulse is sequentially output from each stage circuit, the pixel cell is scanned by the shift register pulse, and the drive start pulse input to the first stage circuit is repeated. Is connected to a circuit for resetting the bootstrap capacitance of each stage circuit, and a signal transmission circuit in which a start pulse different from the drive start pulse inputted to the first stage circuit is connected to the input part of each stage circuit But,
A solid-state imaging device, which is used for one of the horizontal scanning unit and the vertical scanning unit, or for both the horizontal scanning unit and the vertical scanning unit. A plurality of pixel cells for accumulating signal charges according to the luminance of incident light are formed on a semiconductor substrate, and the horizontal scanning unit and the vertical scanning unit that scan the pixel cells, and the pixel by the horizontal scanning unit and the vertical scanning unit A solid-state imaging device including an output unit that outputs an image signal read out as a result of scanning a cell;
It is composed of a dynamic circuit composed of a multi-stage circuit, and the voltage of the drive start pulse input to the first stage circuit is accumulated in the bootstrap capacitor of each stage circuit, and the post-stage circuit of the accumulated voltage of the drive start pulse The shift register pulse corresponding to the drive start pulse is sequentially output from each stage circuit by repeating the transfer to the stage circuit, the pixel cell is scanned by the shift register pulse, and the photoelectric effect by the light incidence control, A signal transmission circuit that individually resets the bootstrap capacitance of each stage circuit,
A solid-state imaging device, which is used for one of the horizontal scanning unit and the vertical scanning unit, or for both the horizontal scanning unit and the vertical scanning unit.   5. The solid-state imaging device according to claim 1, wherein the non-scanning region of the pixel cell is scanned at regular intervals.   Calculating a luminance level of a pixel adjacent to the non-scanning area of the pixel cell, and outputting a pulse for executing scanning of the non-scanning area of the pixel cell when the calculated value reaches a predetermined constant level; The solid-state imaging device according to claim 1, wherein:   The solid-state imaging device according to claim 5 or 6, wherein an instruction to scan the non-scanning region is issued.   8. The solid-state imaging device according to claim 1, wherein a scanning start position and a scanning end position are set so that a scanning area of the pixel cell becomes “even number lines × even number pixels”. . An imaging apparatus configured using the solid-state imaging device according to any one of claims 1 to 8,
A sensor driving pulse for driving and controlling scanning of the pixel cell is output to the solid-state imaging device, and the scanning result of the pixel cell is based on a sensor output output from the solid-state imaging device according to the sensor driving pulse. An image pickup apparatus having a signal processing circuit that outputs an image signal corresponding to the above.

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