JP2002152597A - Solid-state image pickup device and solid-state image pickup equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device the power consumption of which can be suppressed significantly when the device is driven and which does not require complicated phase adjustment, and to provide image pickup equipment. SOLUTION: A CCD image sensor 10 converts incident light into signal charges by means of two-dimensionally arranged image pickup device 12, stores the signal charges, and makes a vertical transfer section 14 transfer the stored signal charges to a D/A-converting section 16 connected on the end section side in the direction of rows by reading out the charges to the transfer section 14. The D/A-converting section 16 converts the signal charges into analog voltage signals in response to the control by means of a control section 22 and an A/D-converting section 18 converts the analog voltage signals into digital signals and stores the signals under the control of the control section 22. The control section 22 reads out the stored digital signals by controlling a horizontal readout scanning section 20 and outputs the signals through an output circuit (not shown in the Fig.). Consequently, the power consumption of the image sensor 10 is reduced, because the sensor 10 does not require an external CDS circuit, phase adjustment regarding the CDS circuit, or wide-band analog amplifier which consumes large electric power.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and a solid-state imaging device, and is suitably applied to, for example, a digital camera or an image input device.

[0002]

2. Description of the Related Art In a solid-state imaging device used for image input, light receiving elements are arranged as pixels in a two-dimensional array.
Further, a signal reading section for reading signal charges generated by the light receiving element is provided. The signal readout unit uses a CCD (Charge Coupled Device) type, which reads out signal charges by moving them through a semiconductor substrate like a bucket brigade, and an external signal line that directly generates charges at each light-receiving element by XY addressing like a memory device. MOS (Metal Oxide Sem
iconductor) type.

The former CCD type solid-state image pickup device can read out signal charges with low noise, and is particularly applicable to many image input devices such as digital video cameras and digital still cameras which require high sensitivity and high image quality. Have been.

On the other hand, the latter MOS-type solid-state imaging device is in principle susceptible to switching noise and fixed pattern noise, and thus is not suitable for applications with high sensitivity and high image quality. LSI (Large-Scale Int
egrated circuit) It has the advantage of low power consumption because it can be diverted without major changes to the process and can operate with a single low voltage power supply. For this reason, it is used especially for an inexpensive image input device with small pixels.

In order to improve the drawbacks of the MOS type solid-state imaging device, CMOS (Complementary Metal Oxide Semicon
ductor) types have been proposed (eg, US Patent No.
5,841,126). Since the CMOS type solid-state imaging device can use a mainstream general-purpose CMOS process at present, it is possible to improve usability by integrating peripheral circuits such as a signal processing circuit on the same device. For example, there is an advantage that the A / D converter can be easily on-chip. But,
In order to increase the sensitivity, you can have an amplification function for each pixel,
Even if a circuit for suppressing noise is added, the area of a unit pixel becomes large, and the area occupied by peripheral circuits other than the light receiving section cannot be ignored. As a result, a CCD solid-state imaging device has been achieved. At present, it is below the sensitivity and image quality.

As described above, CCDs will continue to be used in applications requiring high sensitivity and high image quality such as digital still cameras.
The solid-state imaging device is considered to be the mainstream. However, in the case of high-quality camera applications where the operating frequency (pixel readout rate) exceeds 20 MHz as the number of pixels increases, the following improvements are made to the conventional CCD solid-state imaging device. There is a need.

The first improvement is to reduce the power consumption of a digital still camera using a CCD solid-state imaging device and extend the battery life. Therefore, it is desired to avoid an increase in power consumption due to a higher frequency and to reduce the power consumption of the CCD solid-state imaging device itself.

[0008] Further, with the increase in the number of pixels (multiple pixels), a CDS (C
orrelated Double Sampling) It becomes difficult to adjust the phase of the circuit. Therefore, it is desired that the second improvement can easily perform this.

As an attempt to reduce the power consumption described above, various new element configurations have been proposed (for example, Japanese Patent Application Laid-Open No. 60-500396 and Japanese Patent Application Laid-Open No. 9-51485). These two proposals are about 1/1 of the power consumption of the CCD solid-state image sensor.
Since there is no horizontal CCD section that occupies 2, power consumption is reduced.

[0010]

However, since the output signal of the CCD type solid-state imaging device is an analog voltage signal, in the case of a high operating frequency (pixel reading rate), the analog output section becomes a wide band amplifier, and the consumption of this amplifier is reduced. The power becomes very large and low power consumption cannot be realized. Also, CC
CD that reduces analog signal output of D-type solid-state image sensor
The difficulty of adjusting the phase of the S circuit is not improved.

For applications requiring high sensitivity and high image quality, such as digital still cameras, CCD type solid-state imaging devices will be used in the future. However, the use of a digital still camera with several million pixels has a problem of high power consumption. The CCD solid-state imaging device needs to read out signals within a predetermined time, and further high-speed operation is unavoidable as the number of pixels increases, so that the power consumption further increases. This is fatal because the life of the battery is shortened in a digital still camera using a battery. Therefore, it is desired that the CCD type solid-state imaging device has lower power consumption than the configuration of the two documents without the horizontal CCD section described above.

The present invention solves the above-mentioned drawbacks of the prior art, and provides a solid-state image pickup device and a solid-state image pickup apparatus capable of largely suppressing power consumption for driving elements and avoiding complicated phase adjustment. The purpose is to provide.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention converts a plurality of two-dimensionally arranged imaging light into a signal charge according to the intensity of the incident light. An element, a plurality of transfer electrodes arranged adjacent to each of the image sensors, for transferring the signal charges accumulated in the image sensors in the column direction, and a predetermined transfer electrode for storing the signal charges accumulated in the image sensors. Vertical transfer means including a plurality of readout gate means for controlling the supply to the image pickup device and the transfer electrode, and converting the signal charge transferred and supplied to the end in the column direction via the transfer electrode into an analog voltage signal A plurality of analog conversion means for performing analog signal processing on the analog voltage signal; and a plurality of digital conversion means for converting an output signal from the analog conversion means into a digital signal and storing the digital signal. Conversion means, a plurality of horizontal read means for controlling reading of digital signals stored in the digital conversion means in a desired order, and output means for outputting a digital signal read out in accordance with the control of the horizontal readout to the outside And control means for controlling the operations of the analog conversion means, the digital conversion means, the horizontal reading means, and the output means.

In the solid-state imaging device of the present invention, incident light is photoelectrically converted into signal charges by an image pickup device arranged two-dimensionally, the signal charges are stored, and the stored signal charges are read out to the vertical transfer means to be read in the column direction. The signal is transferred to the analog conversion means connected to the end, converted into an analog voltage signal by the analog conversion means in accordance with the control by the control means, and controlled by the control means to the digital conversion means to convert the analog voltage signal into a digital signal. After conversion, the digital signal is stored, and the stored digital signal is read out using the horizontal readout means controlled by the control means and output via the output means, whereby the external CDS circuit and the phase adjustment related thereto are adjusted. And a low power consumption is achieved by eliminating the need for a wideband analog amplifier with large power consumption.

According to the present invention, in order to solve the above-mentioned problems, a plurality of image pickup devices for converting incident light from an object field into an electric signal are arranged two-dimensionally, and a signal converted from this image pickup device is provided. In the signal readout method for reading out, the method comprises converting the incident light into signal charges in each image sensor and storing the signal charges, and reading out the stored signal charges,
A second step of sequentially transferring the signal charges in the column direction to an end in the column direction, a third step of converting the transferred signal charges into an analog voltage signal, and a second step of removing a noise component included in the analog voltage signal. A fourth step, a fifth step of converting the analog voltage signal from which the noise component has been removed into a digital signal, a sixth step of temporarily storing the obtained digital signal, and an address to which the stored digital signal is supplied. And a seventh step of reading horizontally in response to a signal.

According to the signal reading method of the present invention, incident light is photoelectrically converted and stored as signal charges, and the stored signal charges are sequentially transferred to the end in the column direction to be converted into an analog voltage signal.
Remove the noise component contained in this analog voltage signal,
By converting this analog voltage signal to a digital signal, temporarily storing this digital signal, and reading out the stored digital signal horizontally according to the supplied address signal, there is no need for an external CDS circuit and phase adjustment related to it The power consumption is reduced by eliminating the need for a wideband analog amplifier that consumes a large amount of power.

Further, in order to solve the above-mentioned problem, the present invention converts a plurality of two-dimensionally arranged image pickup elements which convert incident light into signal charges in accordance with the intensity of the incident light and accumulate the signal charges. A plurality of transfer electrodes arranged adjacent to each of the image sensors and for transferring the signal charges stored in the image sensors in the column direction, and a control for supplying the signal charges stored in the image sensors to predetermined transfer electrodes Vertical transfer means including a plurality of read gate means for performing between the image sensor and the transfer electrode, and converts the signal charge transferred and supplied in the column direction via the transfer electrode into an analog voltage signal, A plurality of analog conversion means for performing analog signal processing; a plurality of digital conversion means for converting an output signal from the analog conversion means into a digital signal and storing the digital signal; A plurality of horizontal reading means for controlling reading of digital signals stored in digital conversion means in a desired order; an output means for outputting a digital signal read out according to the control of the horizontal reading to the outside; and an analog conversion means The difference between the reference level set for the element and the level output by each pixel column of the element using a solid-state imaging device including a control unit for controlling the operations of the digital conversion means, the horizontal readout means, and the output means And a signal processing means for performing signal processing on the digital signal with the level difference eliminated.

In the solid-state image pickup device of the present invention, incident light is photoelectrically converted into signal charges by an image pickup device arranged two-dimensionally, the signal charges are accumulated, and the accumulated signal charges are read out to the vertical transfer means to be read in the column direction. The signal is transferred to the analog conversion means connected to the end, converted into an analog voltage signal by the analog conversion means in accordance with the control by the control means, and controlled by the control means to the digital conversion means to convert the analog voltage signal into a digital signal. After conversion, the digital signal is stored, the stored digital signal is read out using the horizontal readout means controlled by the control means, and output via the output means, and the level difference contained in the digital signal for each column is reduced in noise. The signal processing means performs signal processing based on this digital signal, so that the external CDS circuit and the phase associated therewith can be processed. This eliminates the need for adjustment and eliminates the need for a wideband analog amplifier that consumes large amounts of power, thereby reducing power consumption and removing the effects of fixed pattern noise caused by level differences.

Finally, in order to solve the above-mentioned problem, the present invention converts a plurality of two-dimensionally arranged image pickup elements which convert incident light into signal charges according to the intensity of the incident light and accumulate the signal charges. A plurality of transfer electrodes arranged adjacent to each of the image sensors and for transferring the signal charges stored in the image sensors in the column direction, and a control for supplying the signal charges stored in the image sensors to predetermined transfer electrodes Vertical transfer means including a plurality of read gate means for performing between the image sensor and the transfer electrode,
A plurality of analog conversion means for converting the signal charges transferred and supplied in the column direction via the transfer electrodes into analog voltage signals and performing analog signal processing on the analog voltage signals, and converting the output signals from the analog conversion means into digital signals A plurality of digital conversion means for converting the digital signal into a digital signal and storing the digital signal; a plurality of horizontal reading means for controlling the digital conversion means to read the stored digital signal in a desired order; Output means for outputting a digital signal read out according to
A solid-state imaging device including analog conversion means, digital conversion means, horizontal readout means, and control means for controlling the operation of the output means is disposed at a position where an image is formed by an optical system for condensing incident light, and Noise reduction means for converting a digital signal having a difference between a reference level set for the element and a level output from each pixel column of the element into a digital signal, and signal processing means for performing signal processing on the digital signal having the level difference eliminated Display means for displaying an image of a signal obtained by the signal processing means, recording means for recording an output from the signal processing means on a recording medium, and transmission means for transmitting an output from the signal processing means. It is characterized by.

According to the digital camera of the present invention, incident light is condensed through an optical system and sent to a solid-state imaging device, and the incident light is converted into signal charges by a plurality of two-dimensionally arranged imaging devices.
The accumulated signal charge is subjected to analog conversion and digital conversion, a digital signal is directly extracted from this element, and noise in fixed patterns caused by extracting the signal charge in the column direction by noise reduction means has been reduced to suppress noise. By supplying the digital signal to the signal processing means and supplying the image signal processed by the signal processing means to any of the display means, the recording means, and the transmission means, there is no need for an external CDS circuit and phase adjustment related thereto. In addition, power consumption is suppressed by eliminating the need for a wideband analog amplifier that consumes a large amount of power. Since a level difference generated according to reading of the solid-state imaging device, that is, a fixed pattern noise is removed, a high-quality image signal can be obtained.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a solid-state imaging device and a solid-state imaging device according to the present invention will be described in detail with reference to the accompanying drawings.

In this embodiment, an image sensor 10 to which the solid-state imaging device of the present invention is applied will be described. Illustrations and descriptions of parts not directly related to the present invention are omitted. Here, the reference numerals of the signals are represented by the reference numbers of the connecting lines in which they appear.

The image sensor 10 includes an image sensor 12, a vertical transfer unit 14, an analog processing unit 16, a digital processing unit 18, a horizontal readout scanning unit 20, and a control unit 22 (see FIG. 1). The imaging element 12 is a photoelectric conversion element that generates signal charges by performing photoelectric conversion in accordance with the intensity of incident light, and is actually provided with a light receiving element or an optical sensor. The imaging elements 12 are two-dimensionally arrayed. By the way, as shown in this embodiment, the image sensor 12 has a rectangular shape in FIG. 1, but may have a polygonal shape. Also,
The imaging elements 12 are arranged in a grid at predetermined intervals in the row direction and the column direction. The number of pixels is typically 8 × for convenience.
Although eight array arrangements are shown, it goes without saying that the actual number of pixels is about several hundred thousand to several million.

The vertical transfer section 14 is a vertical CCD register. The vertical transfer section 14 has a transfer electrode 140 and a read gate section 142. The read gate section 142 is connected to the transfer electrode 14
It may be shared with 0. The present embodiment is a case of this dual use, and the read gate portion 142 does not show itself, but is shown by the arrow 142 as its function. Vertical transfer unit
14 is formed adjacent to the image sensor 12. Since the image sensor 12 and the vertical transfer unit 14 are alternately arranged two-dimensionally in this manner, such a device is called an interline type. The transfer electrodes 140 are formed so that two transfer electrodes per one image sensor 12 are transferred in one row direction.

In this embodiment, drive pulses 24 to 30 are connected for every four transfer electrodes so that four transfer electrodes 140 are operated as a set, and each drive pulse is supplied. The driving pulses 24, 26, 28, and 30 respectively correspond to φ _V1 ,
φ _V2 , φ _V3 , φ _V4 . The vertical transfer unit 14 includes the image sensor 12
The signal charge stored in the memory is read out to the transfer electrode 140, and the analog processing unit is operated in accordance with the supplied drive pulses 24 to 30.
The signal charges are transferred in the 16 directions. Signal charges are supplied to the analog processing unit 16 for each column via the transfer electrode 140 at the end in the column direction.

The analog processing section 16 converts the supplied signal charge into an analog voltage signal (charge / voltage (Q / V) conversion).
It has a function of sampling the analog voltage signal and removing basic noise. Analog processing unit 16
Is a Q / V converter corresponding to each column so that this function can perform analog processing on the signal charge supplied for each column.
16a and one set of noise removing units 16b. Q /
The V conversion unit 16a is a floating diffusion amplifier (FDA: Floating Diffusion Amplifier) and a source follower circuit, and the noise removal unit 16b is a correlated double sampling circuit (CDS: Correlated Double Sampling). This set of configurations is shown in FIG. This configuration will be described later. The analog processing unit 16 converts the supplied signal charge into an analog voltage signal from which noise has been removed for each column, and supplies the analog voltage signal to the digital processing unit 18.

The digital processing section 18 has a function of converting an analog voltage signal supplied for each column into a digital signal, temporarily storing the converted digital signal, and outputting digital data corresponding to reading. . The digital processing unit 18 includes a comparison circuit 18a and a memory.
18b are provided one by one. This configuration is shown in FIG. 2 similarly to the analog processing unit 16, and this configuration will be described later. The digital processing unit 18 stores the converted digital signal in the memory 18b for each column. Further, the digital processing unit 18 outputs a stored digital signal (data) according to the address signal supplied from the horizontal readout scanning unit 20.

The horizontal read scanning section 20 includes an address signal generating circuit 20a for each column. Address signal generation circuit
20a generates an address signal in accordance with the reading order based on the control from the control unit 22, and sequentially outputs it to the digital processing unit 18. Further, the horizontal readout scanning unit 20 outputs a digital output of the digital processing unit 18 to an output circuit (not shown).
Through the digital imaging signal 46 of the CCD image sensor 10.
Output as The horizontal reading scanning unit 20 will be further described later.

As described above, in the analog processing section 16, the digital processing section 18, and the horizontal readout scanning section 20, the above-described set of configurations can be regarded as one unit when combined in the column direction. It goes without saying that these units are equal to the number of vertical transfer units 14 (ie, the number of columns).

The control section 22 has a function of controlling the above-described analog processing section 16, digital processing section 18, and horizontal readout scanning section 20 in accordance with the supplied input signal 32. The control unit 22 generates and supplies a reset pulse 33, a sampling signal 34 used for noise removal, and a clamp signal 36 to each set of the analog processing unit 16. Control unit
The reference numeral 22 generates and supplies a reference voltage signal 38 indicating the reference of each bit in the digital conversion and a count value 40 to each set of the digital processing unit 18. The control unit 22 includes a sweep function for changing a voltage and a counter (not shown). Then, the control section 22 supplies a horizontal read control signal 42 as a horizontal scan signal to each address signal generation circuit 20a of the horizontal read scanning section 20.

From the analog processing section 16 to the horizontal read-out scanning section 20
A series of units up to this point will be further described (see FIG. 2). As shown in the cross section of the vertical transfer section 14 in FIG. 2, a buried channel (n-layer) 14 is provided immediately below the transfer electrode 140a at the end.
4 is formed. An output gate 160a of the analog processing section 16 is formed adjacent to the end transfer electrode 140a. Q /
The V conversion unit 16a includes an output gate 160a and a reset gate
A buried channel (n-layer) 144 is formed immediately below 160b. A region is provided between the output gate 160a and the reset gate 160b, and a floating junction region, that is, a floating diffusion layer 160 (n ⁺ ) is formed immediately below this region. Further, a reset drain 164a is formed in a region adjacent to the reset gate 162b. The reset drain 164a is formed at the same n ⁺ as the floating junction region.

The floating diffusion layer 160 has an output MOS (Metal Oxide S
emiconductor) is connected to the gate of the transistor 166a. The reset drain 164a is an output MOS transistor
It is connected to the drain side of 166a. The source of the output MOS transistor 166a is connected to the drain of the load MOS transistor 168a. The load MOS transistor 168a plays the same role as a resistor, is connected to a gate and a source, and is grounded. Output MOS transistor connected in this way
The source follower circuit 166a is formed. The injected signal charge is converted into an analog voltage proportional to the signal charge amount by passing through this circuit. Q / V converter 16a
Supplies the analog voltage signal extracted via the terminal 170 to the noise removing unit 16b.

The noise removing section 16b is a sampling MOS
It includes a transistor 160b, a sampling capacitor 162b, a clamping capacitor 164b, and a clamping MOS transistor 166b. The terminal 170 described above is connected to the drain of the sampling MOS transistor 160b, and the source of the transistor 160b is connected to the sampling capacitor 162b.
Connected. The sampling signal 34 is supplied from the control unit 22 to the transistor 160b. Transistor
When 160b is turned off from the on state by the sampling signal 34, the voltage is supplied to the capacitor 162b at this timing and held. The capacitor 162b has an input terminal connected to a terminal 172, and an output terminal connected to one end of the clamping capacitor 164b and the source of the clamping MOS transistor 166b. The other end of the clamping capacitor 164b is grounded.

The clamp signal 36 from the control unit 22 is supplied to the gate terminal of the clamp MOS transistor 166b. Further, a control unit is provided on the drain side of the transistor 166b.
Reference voltage signal 38 is supplied from 22. Noise removal unit
16b clamps the field through level of the signal with the reference voltage supplied according to the clamping timing,
The sampled analog voltage signal 174 is compared with the comparison circuit 18a.
To one end 180. The analog voltage signal is converted into an analog voltage signal 174 in which 1 / f noise and reset noise are reduced by passing through the noise removing unit 16b.

In the digital processing section 18, an analog voltage signal 174 is supplied to one end 180 of a comparison circuit 18a, and the other end 182
Is supplied with a reference voltage signal 38 from the control unit 22. The reference voltage signal 38 is a voltage that changes into a sawtooth wave. The comparison circuit 18a detects a zero level at which the level difference between the two disappears. Output signal (latch signal) when this zero is detected
184 is supplied to one end 186 of the memory 18b. The control section 22 starts counting when the sawtooth wave of the reference voltage 38 starts to change, and supplies the count value 40 to the other end 188 of the memory 18b. The count value is counted in units of one clock, and is proportional to the analog signal. That is, the count value at the time of zero detection represents a digital signal.
This count value is stored in the memory 18b as a digital value for each pixel.

The control section 22 generates a horizontal read control signal 42 in parallel with the above-mentioned A / D conversion processing, and supplies it to the address signal generation circuit 20a. Address signal generation circuit 20a
Generates an address signal in response to the control signal. The address signal generated here corresponds to a position when the photosensitive element is viewed in the column direction, that is, a column address of the photosensitive element. The generated address signal 190 is supplied to the memory 18b. The memory 18b stores the supplied address signal 190
Memory contents (digital data) at the address corresponding to
Is read out to the output line 192. Output line 192 is connected to output circuit 44 (dashed line). The output circuit 44 amplifies the supplied digital data and outputs it as digital data 46.

Although it has been described that the analog processing section 16, the digital processing section 18, and the horizontal readout scanning section 20 are treated as a set of units in the row direction, adjacent units are alternately shifted in the column direction. May be.

The operation of the CCD image sensor 10
This will be described with reference to a mining chart (see FIG. 3).
In FIG. 1, the photographing operation in the photosensitive area is performed from the analog processing unit 16 side.
The image element 12 is divided into a first pixel row, a second pixel row,
Action, ... After imaging in the present embodiment, the imaging device
The signal charge accumulated in 12 is divided into odd and even fields.
The pixel rows included in one of the rows are alternately read. for example
For example, when reading out the first, third, fifth, and seventh pixel rows,
Field shift gate pulse during direct blanking
Drive pulse 30 (φ_V4) Is applied. Each of these
Signal charges converted by imaging from the image sensor 12 in the pixel row
Is read out to the vertical transfer unit 14 of each column. Then vertical rotation
A drive pulse for a 180 ° phase is applied to the sending unit 14. Drive
Dynamic pulse φ _V1, φ_V2Signal level becomes H level.
The signal charges in the vertical transfer unit 14 are transferred until the state shown in FIG.

Next, during the horizontal blanking period of the horizontal synchronizing signal (HD) of FIG. 3A, drive pulses 24 to 30 (FIGS. 3B to 3E)
Supplies, and supplies the reset gate 162a positive polarity of the reset pulse RS (Fig. 3 (f)) at the timing T _1. The reset gate 162a is closed and turned on to charge the potential of the floating diffusion layer 160 to the power supply voltage. When the reset pulse RS disappears, the reset gate 162a opens and turns off.

Next, signal charges are supplied from the transfer electrode 140a via the output gate 160a. The potential of the floating diffusion layer 160 changes from this. A potential proportional to the amount of the supplied signal charge is applied to the gate of the output MOS transistor 166a. The signal is amplified by a source follower circuit using an output MOS transistor 166a and a load MOS transistor 168a and is extracted as an analog output voltage signal at a terminal 170 (FIG.
(See (j)). Analog output voltage signal of period 194 until the rising timing T ₂ of the drive pulse from the falling of the reset pulse RS φ _V3 (28) (FIG. 3 (j)) indicates the reference level of zero signal. Clamp signal at the timing T ₃ in the period 194
The analog output voltage signal of the reference level of the zero signal is clamped by CL (36) (see FIG. 3 (g)). At the same time, the sampling signal SH (34) also rises (see FIG. 3 (h)). The analog output voltage of the clamped terminal 174 in FIG. 3 (k) matches the starting voltage level of the reference voltage signal RV (38).

The output voltage of the analog output voltage signal starts to fall after the fall of the drive pulse φ _V3 (28), and after the fall of the drive pulse φ _V4 (30) (timing T ₄ ), the actual analog voltage Is represented. This analog output voltage represents the same signal level at the terminals 170 and 174a (see FIGS. 3 (j) and 3 (k)). Strictly speaking, the capacitance of the sampling capacitor 162b is
The analog voltage at terminal 174a is slightly lower than the analog voltage at terminal 170 because it is very difficult to increase the capacitance of 64b. And holding the actual analog output voltage signal at terminal 174a to fall sampling signal SH (34) to the timing T ₄ and later. Hold period 19
6 is from the falling of the sampling signal SH (34) to the end of the supply of the reference voltage signal RV (38).

The control unit 22 includes a reference voltage signal at a timing T ₅
Apply RV. The reference voltage signal RV has a sawtooth waveform (see FIG. 3 (i)). Although not shown in the timing chart, the control unit 22 simultaneously starts the operation of the counter with the supplied clock. The control unit 22 sequentially outputs the count value 40 and supplies it to the memory 18b.

[0043] Thus clamped, by sample-and-hold, the reference level of zero signal in the timing T ₅ of the terminal 172 are equal to the reference voltage signal RV (38), the reference voltage signal at this point RV The level difference ΔV (198) between (38) and the actual analog voltage signal 174 is substantially equal to the analog signal itself. The reference voltage signal RV changes in a saw-tooth shape over time. As a result, the level difference ΔV
(198) becomes smaller. The comparison circuit 18a compares the levels of these two signals. In FIG. 3, the comparison circuit 18a
Is to detect the position of the timing T ₆ the level difference becomes zero. Accordingly, the level of the analog signal is large, for example, in the case of the timing T _7, it takes time to this detection. Upon this detection, the comparison circuit 18a outputs a latch signal 184 to the memory 18b. The memory 18b has a latch signal
The count value 40 supplied from the control unit 22 is stored at the supplied timing of 184. Accordingly, the count value 40 is the period from time T ₅ in which the 1 clock units to zero detection, can be considered to be proportional to the analog signal. From this, the count value 40 can be regarded as a value obtained by converting an analog signal into a digital signal. The digital conversion is carried out until the timing T ₈ which to one pixel level reaches the maximum level of the reference voltage signal RV.

The control section 22 outputs a horizontal read control signal 42 to the address signal generating circuit 20a of the horizontal read scanning section 20 in parallel with the A / D conversion operation. Address signal generation circuit
20a generates an address signal 190 based on the supplied horizontal read control signal 42. Address signal generation circuit 20a
Supplies the generated address signal 190 to the memory 18b.
The memory 18b reads out the count value 40 stored at the time of zero detection one horizontal line (HD) corresponding to the address signal 190 as a digital signal to the output line 192. In this embodiment, the readout is performed at the end of the horizontal blanking period, and the digital imaging signal 46 is read out during the horizontal scanning period. The digital signal 192 is output to the outside via the output circuit 44 as the digital image signal 46.

[0045] Here, the counter provided in the control unit 22 (not shown), for example, using the 10-bit counter 1024 counts the timing T ₅ to T _8, the other hand, the reference voltage signal RV (38) is the digital processor 18 will perform a / D conversion of the 10-bit accuracy by equalizing the saturation output voltage of the analog output at a timing T ₈ from the reference level at the timing T _5.

In the next horizontal blanking period, the same operation as described above is repeated, and thereafter, the immediately preceding digital image pickup signal 46 is read. This series of operations is repeated for the remaining pixel rows, and the output operation of the first field is completed. In this series of operations, there is no digital signal during the first A / D conversion, so there is no digital output during this conversion.
In addition, since there is no analog signal to be converted at the time of the last digital output, A / D conversion is not performed at this time.

In the next vertical blanking period, for example, the second, fourth, sixth, and eighth pixel rows are read. In this case, a drive pulse 30 (φ _V2 ) including a field shift gate pulse is applied during the vertical blanking period. The signal charges converted by the imaging from the imaging elements 12 in each pixel row are read out to the vertical transfer units 14 in each column. Thereafter, a driving pulse for a phase of 360 ° is applied, and the vertical transfer section is driven until the driving pulses of the first and second phases become high level.
The read signal charges are transferred to 14. In the next horizontal blanking period, analog processing, digital processing, and horizontal reading operation are performed on the signal charge that has reached the end of the vertical transfer unit 14 in the same manner as in the first field, to obtain the digital imaging signal 46 in the second field. Reading.

The CCD image sensor 10 according to the present embodiment does not have the horizontal transfer unit 52, but includes the analog processing unit 16, the digital processing unit 18, and the horizontal readout scanning unit 20 as one unit for each column. Is used to convert signal charges into digital signals. This eliminates the need for an external CDS circuit and the related phase adjustment, and eliminates the need for a wideband analog amplifier that consumes a large amount of power, thereby achieving low power consumption.

Next, a digital camera 60 to which the CCD image sensor 10 of this embodiment is applied will be briefly described (see FIG. 4). To simplify the description, an imaging optical system (hereinafter, simply referred to as an optical system), a display unit, a recording unit, and a transmission unit are omitted. The digital camera 60 includes an optical system (not shown), an imaging unit 62, a system control unit 64, a timing signal generation unit 66, a driver unit 68, a signal processing unit 70, a display unit (not shown), a recording unit, and a transmission unit. In. Imaging unit 62
Is a microlens 62a that efficiently condenses incident light on the incident side of the incident light 58 of the image pickup device 12,
A color filter 62b in which color filter segments for separating the color image into a plurality of types of colors are arranged in a pattern, and the CCD image sensor 10 (solid-state imaging device).

The system control unit 64 includes a central processing unit (Central Processing Unit), and controls the operation according to a ROM (Read Only Memory) program in which control and processing procedures are written. In the still image capturing mode, the start timing of the exposure operation and the like are performed according to a pressing operation of a shutter button of an operation unit (not shown). Further, in the moving image capturing mode for displaying on the display unit and recording a moving image, the system control unit 64 supplies a control signal 64a to the timing signal generating unit 66 at a predetermined timing after the power is turned on.

The timing signal generator 66 generates a timing signal 66 including the timing of the field shift gate pulse.
a to the driver unit 68, and the input signal 32 to the imaging unit 62. Further, the timing signal generator 66 supplies a clock signal 66b for causing the signal processor 70 to perform a processing operation.

The driver section 68 generates vertical drive pulses (φ _V1 ) 24 to (φ _V4 ) 30 corresponding to the four-phase driving by the V driver 68 a and supplies the generated vertical drive pulses to the image pickup section 62. Further, as described in the above-mentioned timing chart, the driver unit 68 also supplies a driving pulse including a field shift gate pulse for reading a signal charge from the image sensor 12 to the vertical transfer unit 14. The imaging unit 62 captures an image in accordance with the supplied drive pulses 24 to 30 and the input signal 32, vertically transfers the signal charge obtained by the imaging, and adjusts the timing of the input signal 32 supplied to the control unit 22. In response, the signal charge is subjected to analog processing, digital processing is thereafter performed and temporarily stored, the stored data is read out as a digital imaging signal 46, and the signal processing unit 70
Output to

The signal processing section 70 is controlled by a control signal 64b from the system control section 64. The signal processing unit 70 performs gamma correction, automatic white balance adjustment, and the like on each pixel of the supplied digital imaging signal 46, for example,
The pixel data of the three primary colors RGB is temporarily stored as image data in a non-destructive memory. Thereafter, matrix processing is performed based on the stored imaging data to generate luminance data Y and color difference data C _r and C _b . The signal processing unit 70 supplies data 72 sampled from, for example, data near the center of the screen to the system control unit 64 while performing the above-described processing. Note that the signal processing unit 70 may calculate data related to exposure control on the data 7. In this case, the information of the calculation result is supplied to the system control unit 64. The signal processing unit 70 the generated luminance data Y and color difference data C _r,
Outputs C _b (74).

On the other hand, the digital camera 80 to which the CCD image sensor cited in the prior art is applied is shown in FIG.
Shown in Parts common to the digital camera 60 are denoted by the same reference numerals. Explaining the difference, the micro lens 82a and the color filter 82b of the imaging unit 82 may have the same color arrangement and the same shape lens as the micro lens 62a and the color filter 62b, respectively. However, the imaging unit 82 is characterized by using a CCD image sensor 50 without a horizontal CCD unit.

In the case of the CCD image sensor cited in Japanese Patent Application Laid-Open No. 9-51485, the V driver is unnecessary since it is built in. The imaging unit 82 supplies the captured analog voltage signal 82d to the CDS circuit 84.

A timing signal for clamping and sampling the analog voltage signal 82d supplied to the CDS circuit 84.
66c are each supplied. The CDS circuit 84 supplies the A / D converter 86 with an analog voltage signal 84a from which noise components such as 1 / f noise included in the analog voltage signal 82d have been removed. At this time, since the CDS circuit 84 operates at the frequency described above, the phase is adjusted in nanosecond units. The phase adjustment in this unit is very troublesome. A / D
The converter 86 converts the analog voltage signal 84a into a digital image signal 46 and outputs the digital image signal 46 to the signal processor 70. Timing signal 66
c and 66d are supplied from the timing signal generator 66.

When the digital cameras 60 and 80 are compared, the digital camera 80 is difficult to finely adjust the phase in addition to the large power consumption described above. On the other hand, in the digital camera 60 to which the present invention is applied, since a digital output is directly obtained, an external CDS circuit and phase adjustment related thereto are not required. In addition, power consumption can be reduced by eliminating the need for a wideband analog amplifier having large power consumption.

Next, a so-called honeycomb interlaced scanning interline transfer type CCD image sensor 90 in which the array arrangement of the image sensor 12 is offset and shifted in the vertical and horizontal directions by half the pixel pitch, respectively.
Will be described (see FIG. 6). Parts common to the CCD image sensor 10 of FIG. 1 are denoted by the same reference numerals. The imaging device 12, the pixel pitch PP _H in the horizontal direction, the vertical direction as well as the pixel pitch PP _V, shifting component in the horizontal direction to the pixel pitch of the adjacent pixels | PP _H | / 2, perpendicular to the pixel pitch | PP _V | / 2. The imaging element 12 has a rhombus-shaped photosensitive portion. This shape
The shape is not limited to a rhombus but may be a polygon such as a hexagon or an octagon. In the CCD image sensor 90 of the present embodiment, the pixel array is indicated by 4 × 8. One horizontal line (row) of each pixel is a first pixel row from the analog processing unit 16 side,
It is assumed that a second pixel row,...

In the vertical transfer section 14, a transfer electrode 140 and a read gate section 142 are formed. The transfer electrode 140 is formed to have a constant width by effectively utilizing a space formed between adjacent pixels. As a result, the transfer electrode 140
It is formed to meander. The read gate section 142 is represented by an arrow as described above. One of the drive pulses 24 to 30 is supplied to the vertical transfer unit 14 for each two adjacent pixel rows. For example, the same drive pulse 30 is supplied to the first and second pixel rows. Vertical transfer unit 14
Transfers the signal charges read from the image sensor 12 by four-phase driving.

Since the image pickup device 12 and the vertical transfer unit 14 are formed in the above-described relationship, the shape including the vertical transfer units 14 arranged on both sides of each image pickup device 12 becomes hexagonal. It can be seen that the CCD image sensor 90 is arranged and formed in a honeycomb shape. The other analog processing unit 16, digital processing unit 18, horizontal readout scanning unit 20, and control unit 22 have the same configuration as the above-described embodiment.

The operation of the CCD image sensor 90 will be briefly described. After imaging, a drive pulse 30 including a field shift gate pulse for reading is applied during a vertical blanking period. By this application, the signal charges accumulated in the first, second, fifth, and sixth pixel rows are transferred to the transfer electrodes 140 of the vertical transfer unit 14.
Is read. Thereafter, a drive pulse for a phase of 180 ° is applied, and the signal charge is transferred until the drive pulses 24 and 26 become H level. Since the signal charges are supplied for one line for each two pixel rows, a digital image pickup signal 46 for two pixel rows is obtained by one A / D conversion process and one horizontal read scan. The A / D conversion processing and the horizontal read scanning are performed at the operation timing shown in FIG. After reading out the signal charges, the vertical transfer, A / D conversion processing, and horizontal readout scanning are repeated to finish the readout operation of the first field.

In the next vertical blanking period, the driving pulse 26
Is applied with a field shift gate pulse. With this application, the signal charges accumulated in the third, fourth, seventh, and eighth pixel rows are read. Thereafter, a drive pulse for a phase of 360 ° is applied, and the drive pulses 24 and 26 are at level H.
Until the signal charge is transferred. During the next horizontal blanking period, analog processing, digital processing, and horizontal read scanning are performed at the operation timing shown in FIG. By repeating this series of operations, the digital imaging signal of the second field is obtained.
46 is being read.

Since the CCD image sensor 90 has pixels arranged in an offset manner, the resolution in the horizontal and vertical directions is better than that of the CCD image sensor 10, and furthermore, the arrangement area effectively utilizes the area of the photosensitive section. Therefore, the sensitivity of the imaging element 12 can be increased, and the saturation output voltage can be increased.

Next, other embodiments of the CCD image sensor 10 will be described as some modifications. These modifications can also be applied to the CCD image sensor 90. In the first modified example, as shown in FIG. 7, the configuration of the CCD image sensor 10 of FIG. 1 is used as it is, and the supply of the driving pulse to each pixel row is partially different. That is, the driving pulses 24, 26,
28 is supplied in the same connection relationship as in the case of the CCD image sensor 10. The driving pulse 30 includes the first, third, fifth, and seventh drive pulses.
In the present embodiment, the driving pulse 30 is changed to the driving pulse 30.
a and 30b are supplied separately. The connection relationship with the transfer electrode 140 applied in response to this supply is also divided into two groups. The two groups include a group that supplies a drive pulse 30a for every eight transfer electrodes from the transfer electrode of the first pixel row (1), and a group that supplies a drive pulse for every eight transfer electrodes from the transfer electrode of the third pixel row (3). 30
The group that supplies b. Each group is connected so that drive pulses 30a and 30b are supplied.

When a still image is picked up, the driving pulses 30a, 30a
0b, the first, third, fifth, and seventh pixel rows ((1), (3), (5),
The signal charge is read from (7)). In addition, when performing preliminary image capturing for capturing a moving image (movie display) or exposure control, drive pulses 30a and 30b including a field shift gate pulse are alternately applied. With this application, the first and fifth pixel rows are read out in the first field. In the second field, the third and seventh pixel rows are read. Although the resolution is low because only half is read as compared with the still image capturing in which four pixel rows are read in one field, the reading in the vertical direction is double the rate.

When reading out only one of the fields, the frame rate is quadrupled because all pixels are thinned out by 1/4. CCD image sensor
10 can be read at a high frame rate by considering the connection to which the drive pulse is supplied.

In the CCD image sensor 10, the timing signal generator 66 and the driver 68 of FIG. 4 may be formed on-chip (see FIG. 8). The CCD image sensor 10 is characterized in that only a vertical drive is performed without forming a horizontal transfer unit. On-chip conversion requires only circuits related to vertical driving.
As a result, a new vertical drive generator 76 is added to the CCD image sensor 10 on-chip. The vertical drive generation unit 76 is controlled by a drive control signal 78 from the control unit 22 regarding drive timing generation and the like. With this on-chip configuration, the digital camera 60 does not need to externally include the timing signal generator 66 and the driver 68. In the digital camera 60, the number of mounted chips is reduced, and the size of the camera can be reduced.

The vertical drive generating section 76 may be a single generating section or a distributed type (see FIG. 9). The vertical drive generator 76 includes a vertical drive timing generator 760 and a vertical drive signal generator 762. The vertical drive timing generator 760 generates vertical drive timing signals 760a to 760d according to the supplied drive control signal 78, and supplies the signals to the vertical drive signal generator 762. Vertical drive timing signal 76
0a to 760d also include a timing signal for generating a field shift gate pulse, which is a signal charge readout pulse. The drive pulse generation circuit 7620 generates and outputs drive pulses 24 to 30 according to the supplied vertical drive timing signals 760a to 760d. As described above, the vertical drive generation unit 76 in FIG. 9 shows a case where a plurality of drive pulse generation circuits 7620 are provided in the vertical drive signal generation unit 762 and distributed.

The vertical drive generator 76 is not limited to the case where the four-phase drive pulses 24 to 30 are generated, but may generate eight-phase drive pulses 92 to 106 (FIG. 10).
See). As described above, by using a multi-phase drive as compared with the four-phase drive, it is possible to lower the drive pulse voltage. However, in this case, the number of read fields increases.

The vertical drive generator 76 uses ternary values (H, M, L) to drive the transfer electrode 140 including reading out signal charges (field shift). The readout gate 146 may be formed between the image pickup device 12 and the transfer electrode 140 so that the vertical transfer is driven in binary (H, L) and the gate is turned on / off for reading out signal charges. Good (figure
11).

Next, another embodiment of the CCD image sensor 10 will be described (see FIG. 12). CCD image sensor
As described above, the basic configuration of 10 is to transfer the signal charge obtained by the image pickup device 12 by the vertical transfer unit 14, perform analog processing and digital processing of this signal charge for each column, and perform horizontal readout. The point of scanning and outputting is the same. Therefore, the reference numerals are assigned the same numbers. However, the circuit configurations for analog processing and digital processing are different. The different parts will be described in detail.

The analog processing section 16 includes a Q / V conversion section (FDA)
16a has the same configuration as that described above, and the Q / V converter (FD
A) The output terminal 170 of 16a is connected to the drain of the sampling MOS transistor 160b. Q / V converter 16
In a, the source of the sampling MOS transistor 160b is connected to one end of a sampling capacitor 162b and a clamp capacitor 164. The sampling capacitor 162b is for the other end of the capacitor 162b and the RV switch.
Connected to the drain of MOS transistor 168b. MO
The S transistor 168b has a function as an RV switch. In order to exhibit this function, the source of the RV switch MOS transistor 168b is connected to the signal line to which the reference voltage signal RV (38) is supplied, and the RV switch control signal 108 is supplied to the gate of the MOS transistor 168b. Connected.

With such connection, the output voltage after reset and before the reference voltage RV is applied becomes the reference level of the zero signal. Then, at the terminal 176, there appears an analog output voltage signal 110 in which the reference voltage RV when the control signal 108 is supplied and the analog output voltage obtained by sampling the analog output voltage at the terminal 170 are superimposed. This analog output voltage signal is supplied to the digital processing unit 18 via the clamp capacitor 164.

The digital processing section 18 includes a clamping MOS
It includes a transistor 180d, a level inversion detecting section 182d, and a memory 18b. In the digital processing unit 18, the analog output voltage signal 110 is supplied to the drain of the clamping MOS transistor 180d and the input terminal of the level inversion detecting unit 182d via the capacitor 164. MOS transistor 18
The source of 0d is connected to the output terminal of the level inversion detection unit 182d. The clamp signal 36 is supplied to the gate of the MOS transistor 180d. When the clamp signal 36 is supplied, the voltage of the terminal 178 is clamped. Level inversion detector
182d is a high gain amplifier. Level inversion detector 182d
Outputs the latch signal 112 to the input 186 of the memory 18b at the time of level inversion or crossing the zero reference level. When the latch signal 112 is supplied, the memory 18b
The count value 40 supplied to the other end 188 is stored.
The count value 40 is a digital signal obtained from the image sensor 12. The count value 40 is supplied by the control unit 22 starting counting simultaneously with the application of the reference voltage signal RV, as in the case described above.

The horizontal read scanning unit 20 generates an address signal in an address signal generation circuit 20a based on a horizontal read control signal 42 supplied from the control unit 22. The generated address signal 190 is supplied to the memory 18b. The memory 18b stores a digital signal 192 corresponding to the supplied address signal 190.
And outputs it to the output circuit 44. The output circuit 44 outputs the amplified signal as the digital imaging signal 46.

The operation timing of the CCD image sensor 10 of this embodiment will be described (see FIG. 13). Fig. 13 (a) ~
Each signal up to (h) is the same as the corresponding signal in FIG. The operation of reading the signal charge from the image sensor 12 and the operation of the vertical transfer unit 14 are the same as those described above. Regarding the operation after the signal charge is converted to an analog voltage signal in the analog processing unit 16, various signals and an analog output voltage (FIG. 13)
(k)) will be briefly described while focusing on the relationship. Applying the reset signal RS at the timing T _1. A period 194 from the end of the reset to the rise (timing T ₂ ) of the drive pulse 28 (φ _V3 ) is the reference level of the zero signal of the analog output voltage. From the fall of the sample hold SH (34) to the point at which the reference voltage signal RV reaches, for example, the saturation level, the actual A / A
The D conversion period is 196.

The sampling signal 34 (SH) and the control signal 108 for the reference voltage signal RV switch rise in synchronization with the rising of the clamp signal CL (36), and are brought to the level H (timing T ₃ ). The period 194 is applied to the terminal 170 by the clamp signal CL.
Of zero signal voltage. Therefore, at this stage, the input terminal 178 of the level inversion detecting unit 182d becomes the initial reference level. The analog output voltage signal 11 at the terminal 176 is synchronized with the falling edge of the sampling signal 34 (SH) shown in FIG.
0 is held. Accordingly, a voltage 198 appears at the terminal 178. Voltage 198 is the voltage difference between the analog signal and the initial reference level.

[0078] The reference voltage signal of the sawtooth waveform at the timing T ₅
While RV is applied, a counter (not shown) of the control unit 22 starts counting by a clock. This count value 40 is supplied to the other end 188 of the memory 18b. The level of the sawtooth wave of the reference voltage signal RV increases with time. Accordingly, the reference voltage signal RV is superimposed on the analog signal. The voltage at terminal 178 gradually increases over time. The level inversion detection unit 182d detects the timing when the superimposed signal returns to the initial reference level (zero level). This timing is detected by level inversion. At zero level detection, for example, the level inversion detection unit 182d at the timing T ₆ is a latch signal 11
2 is output to the memory 18b.

[0079] Memory 18b stores the count value 40 which has been supplied to the timing T _6. As described above, the counting is performed in parallel with the A / D conversion. Memory 18b
Reads out the stored count value as a digital signal of the image sensor 12. Reading from the memory 18b is performed according to the address signal 190 supplied from the address signal generating circuit 20a. Digital signal in FIG. 13 (l) are read out at the timing T ₅₎ after the data stored in the previous 1H.

With this configuration, the detection sensitivity is higher than that of the previous embodiment, and a highly accurate A / D conversion process can be performed.

By the way, as shown in FIG. 3 and FIG.
In the CCD image sensor 10, the A / D conversion period and the digital output period overlap. There is a concern that the overlap of the output periods may affect the A / D-converted data as noise particularly in the digital output. Therefore,
When the CCD image sensor 10 of FIG. 3 is used, FIG.
operation procedure before A / D conversion as shown in (h) is carried out as it is, by shortening the A / D conversion period of the timing T ₅ and later,
For example, it is done in half the period of the past.
The A / D conversion period is shortened by doubling the slope of the sawtooth wave of the reference voltage signal RV. The digital output is to perform at the timing T ₈ or later.

By operating as described above, the A / D converted digital imaging signal 46 can have a high S / N ratio. Since the data is output immediately after the conversion by shortening the time, the memory 18b holds data for 1H, so that no memory is required. With this reduction, the cost can be reduced.

Further, the CCD image sensor 10 halves the changing speed of the sawtooth wave indicating the reference voltage signal RV. FIG.
The slope of the reference voltage signal RV is the same as that shown in FIG.
15 (i)). On the other hand, for example, the slope is set to a half of that of the reference voltage signal RV indicated by the broken line 114 (see the solid line 116). By suppressing the slope of the reference voltage signal RV by half, the saturation output voltage of the analog output signal is halved. As a result, the digital signal can be amplified up to two times when it is used effectively up to the saturation output voltage. That is, the sensitivity is 2
Can be doubled.

As described above, when the amplitude of the reference voltage signal RV is reduced, a high-sensitivity output can be obtained, and the sensitivity can be set freely according to the shooting scene. It is particularly effective in dark scenes.

Further, the reference voltage signal RV is not limited to a waveform (dashed line 114) in which the signal level monotonically increases or monotonously decreases like a sawtooth wave. That is, the reference voltage signal RV may be changed by the curve 118 (see FIG. 16).
Reference voltage signal RV is the voltage gradient at the timing T ₅ vicinity are very small, the voltage gradient is changing so rapidly increases from the vicinity of the timing T _6. To realize such a voltage change in which the voltage gradient is not constant, the control unit 22
Preferably have a non-volatile memory and a D / A converter (not shown). The control unit 22 writes and stores the data corresponding to each step as a table in the nonvolatile memory in advance, reads the data at a predetermined timing, and
A converter generates an analog voltage equivalent to the reference voltage,
Supply.

By not changing the reference voltage to a constant value, for example, A / D conversion can be performed on a dark portion with high accuracy, and conversion can be performed on a bright portion with coarse accuracy. That is, the knee characteristic with respect to the input light amount can be easily obtained. This characteristic can be freely set by changing the value of the table. As a result, it is possible to select and set characteristics according to the scene and obtain a high-quality image even in an image in a wide brightness range.

The CCD image sensor 10, to which the present invention is applied,
Numeral 90 can reduce power consumption and facilitate processing for phase adjustment. In addition, the image sensor 10,
Since the noise removal unit 16b removes noise such as 1 / f noise and reset noise for each column by 90, the signal quality of each digital imaging signal 46 output for each column is excellent. However, this digital imaging signal 46
When an image is created by using, there is a possibility that a fixed pattern appears in the image. In the case of the MOS type image sensor, the fixed pattern has a problem in the variation of the output gain of the output amplifier disposed adjacent to each image sensor. In the case of the CCD image sensors 10 and 90, similar variations may cause image noise.

The cause is considered to be two noises. The first cause is noise caused by the zero level fluctuating for each column during A / D conversion. Although significant reduction has been achieved by clamping the analog output voltage signal during A / D conversion, slight fluctuations in each column remain (offset level fluctuations). This fluctuation appears in the image as a vertical line flaw when the image is taken in a low illuminance level situation. The second cause is due to gain variation of Q / V conversion in each column (sensitivity variation). This variation appears as vertical line flaws on the screen at relatively bright illumination levels.

The solid-state imaging device 120 to which the CCD image sensor 10 is applied is provided with a noise reduction unit 122 as a countermeasure against this (see FIG. 17). The solid-state imaging device 120 other than the noise reduction unit 122 includes the same components as the solid-state imaging device 60 in FIG. Each element is represented using the same reference numeral as the solid-state imaging device 60.

The noise reduction unit 122 includes a memory (not shown) for storing data of a variation and a gain adjustment of each column with respect to a preset reference (zero level / normal gain value), and a memory. And a multiplier for multiplying the output from the subtractor by a conversion gain for the gain adjustment to the output from the subtractor for each column. The noise reduction unit 122 includes a timing signal generation unit.
A timing signal 66d is supplied from 66 so as to adjust the operation timing of each section. The noise reduction unit 122 supplies the digital image pickup signal 124 from which the fixed pattern noise based on two causes has been removed to the signal processing unit 70.

By performing signal processing using this signal 124, it is possible to obtain a high quality image with extremely little fixed pattern noise.

The noise reduction section 122 may be configured to make the CCD image sensor 10 on-chip as shown in FIG. In the CCD image sensor 10, a correction memory 126 and a noise correction unit 128 are newly added. The correction memory 126 and the noise correction unit 128 are components corresponding to the noise reduction unit 122.

The correction memory 126 stores a level variation (offset variation) with respect to a previously measured zero level and a correction coefficient of conversion gain, one set for each column.
The correction memory 126 is controlled by a control signal 130 from the control unit 22. Under the control, the correction memory 126 supplies the correction data 132 for each column to one end of the noise correction unit 128.

Although not shown, the noise correction unit 128 is provided with a subtractor and a multiplier for each column. Noise correction unit
128, the memory 18b is scanned by the horizontal readout scanning unit 20.
Is supplied to the other end side. As described above, the noise correction unit 128 supplies the level change amount to the digital image pickup signal 46 for each column to the subtractor, and the subtractor subtracts the level change amount from the digital image pickup signal 46. This subtracted digital image signal is supplied to the multiplier. The multiplier multiplies the supplied imaging signal by a conversion gain value for the same column to perform sensitivity correction in charge / voltage conversion. By performing the correction in this manner, the digital imaging signal 12 from which the fixed pattern has been removed is provided.
4 is supplied to a signal processing unit 70 (not shown). Needless to say, the vertical drive generation unit 76 is also provided for the on-chip implementation if there is enough space.

A color filter 62b is provided in the image pickup section 62 (see FIG. 4) to which the CCD image sensor 10 is applied.
And are formed correspondingly to each. As described above, when evaluating the variation of the charge / voltage conversion gain in the Q / V conversion unit 16a for each column of the analog processing unit 16, if the color filter 62b is provided and formed, for example, the three primary colors RGB
Since it is affected by the spectral characteristics of the color filter segments, accurate evaluation becomes difficult. In order to give an accurate evaluation in such a case, as shown in FIG. 19, a color filter segment of the color filter 62b arranged on the incident light side of the CCD image sensor 10 is arranged.

The color filter 62b uses a color filter segment of three primary colors RGB. Here, the color filter segments are represented by a G filter segment 134, an R filter segment 136, and a B filter segment 138, respectively. A colorless and transparent filter segment 150 is also provided. As is clear from FIG. 19, the CCD image sensor 10 arranges the filter segments in a color filter segment arrangement region 152 and a transparent filter arrangement region 154 in accordance with the array arrangement of the image sensor 12. The color filter segment arrangement area 152 arranges the color filter segments in a Bayer pattern. This area 15
The digital color image signal can be obtained by performing the signal processing using the digital imaging signal based on the signal charge obtained from Step 2. The transparent filter placement area 154 includes a plurality of pixel rows, for example, about two
Set to 0. The signal obtained from this area 154 is a signal of a white pixel without color. This signal is a reference white signal. Since the reference white signal is a signal that is not affected by color,
Using this signal, the conversion gain in the Q / V converter 16a of the analog processor 16 can be easily obtained. CCD image sensor
10 can obtain a color image from the digital image pickup signal from the region 152, and also obtain a coefficient to be corrected for each column based on the output data from the pixel rows in the region 154. It can also respond to aging.

Next, another embodiment of the CCD image sensor 10 to which the present invention is applied will be described (see FIG. 20). In the present embodiment, a unit having a set of an analog processing unit 16, a digital processing unit 18, and a horizontal readout scanning unit 20 is a vertical transfer unit.
CCD image sensor 10 halved from 14
A will be described. Although the number of the above-described units is only half of the vertical transfer unit 14 in spite of the same number, the signal read is selected to effectively read the read signal charges. In order to make this selection, a selection CCD register unit 200 is provided between the transfer electrode 140 and the analog processing unit 16.

The selected CCD register section 200 includes a memory gate section 202 and a junction gate section 204. In the memory gate unit 202, memory gates 202a and 202b are provided and formed for a pair of two adjacent vertical transfer units 14, respectively. In the case of the CCD image sensor 10A of FIG. 21, the drive pulse 30 is supplied to the memory gate 202a. The drive pulse 206 (φ _MB ) is supplied to the memory gate 202b at a timing when the drive pulse 30 is not supplied, as described later.

The junction gate 204 is connected to the memory gates 202a, 20
Branch gates receiving signal charges supplied from 2b respectively
It includes a merging gate 204c that receives the signal charge of one of the branch gates 204a and 204b and one of the branch gates 204a and 204b. The branch gates 204a and 204b can form a potential barrier with respect to the junction gate 204c. This is realized, for example, by making the impurity concentration of the buried channel immediately below the junction gate 204c higher than that immediately below the branch gate. The formation and removal of the potential barrier is determined by the timing at which the drive pulse 208 (φ _T ) is supplied. As a result, the direction in which the signal charge flows is selected. As a result, 1
One pixel row is read out as a digital imaging signal 46 through two readout procedures.

Next, the operation of the CCD image sensor 10A will be briefly described (see FIG. 21). Among the horizontal synchronizing signal HD in FIG. 21 (a), the following input of the reset signal RS at the timing T ₁ in odd horizontal blanking (HBLK), FIG. 21 (b)
The drive pulses 24 (φ _V1 ) to 30 (φ _V4 ) shown in (e) to (e) are supplied to transfer the signal charges in the vertical transfer unit 14 by a phase of 360 °. Further, a drive pulse 208 (φ _T ) is supplied to the junction gate 204c. Due to this transfer, of the signal charges in the first pixel row closest to the analog processing unit 16, only the signal charges in the even-numbered columns counted from the left end are stored in the memory gate 202a.
Is supplied to the analog processing unit 18 via Since the driving pulse 206 (φ _MB ) supplied at this time is at the level H, the signal charges in the odd columns remain stored in the memory gate 202b.

Thereafter, the analog processing section 16 converts the even-numbered signal charges into an analog output voltage signal, clamps this signal, and holds it with the sampling signal SH. The digital processing unit 16 performs detection processing of a count value at which the sampled signal matches the reference voltage signal RV, and stores the count value in the memory 18b. During this digital conversion (between the timing T ₅ through T ₈₎ odd column of data stored by converting this before is read (see FIG. 21 (l)).

In the next even-numbered horizontal blanking period, the drive pulse 206 (φ _MB ) goes to level L, causing the memory gate 202b to transfer the signal charges in the odd-numbered columns. (φ _T ) is level H
, The signal charges in the even and odd columns are transferred to the analog processing unit 16. However, since the signal charges in the even columns are transferred in the immediately preceding field, only the signal charges in the odd columns are actually transferred. Transferred signal charges are to an analog voltage by an analog processing, the analog voltage after this is digital conversion between the timing T ₉ through T _10. Data of the even-numbered columns are stored in the memory 18b during the period (timing T ₉ through T ₁₀₎ is read out (see Figure 21 (l)).

In this manner, A /
D conversion and data output of the conversion result are performed. This series of operations is repeated to read one field. As a result, it takes twice as long to read the signal.
However, the analog processing unit 16 and the digital processing unit 1
Since the number of units that make up the set 8 and the horizontal readout scanning unit 20 is half, fine processing in the horizontal direction can be omitted. Therefore, the CCD image sensor
10A has the advantage that it can be manufactured at low cost.

In consideration of this, the image pickup device 12
A similar configuration can be considered in a so-called honeycomb-arranged CCD image sensor 10B in which are arranged (see FIG. 22). As is clear from FIG. 22, the vertical transfer unit
14 has only one of the even-numbered rows and the odd-numbered rows as compared with the arrangement of FIG. This arrangement eliminates the need for the selection CCD register section 200 for selecting either the even-numbered column or the odd-numbered column. Since the number of the vertical transfer units 14 is halved, only one half of the pixel row can be read out by the CCD image sensor 90 of FIG.

The CCD image sensor 10B performs four driving pulses 210 to 216. Each drive pulse includes a field shift gate pulse. CCD image sensor 10
B reads out signal charges from the image sensor 12 through four vertical blanking periods. Read this signal
This is called field interlace.

The operation of the CCD image sensor 10B will be described. Here, each pixel row is referred to as a first, second,..., Eighth pixel row from a pixel row close to the analog processing unit 16. First, when the drive pulse 216 including the field shift gate pulse is applied in the first vertical blanking, the signal charges accumulated from the imaging elements 12 in the first and fifth pixel rows are read out to the vertical transfer unit 14. The read signal charges are transferred from the vertical transfer unit 14 to the analog processing unit 16. And a series of
A / D conversion processing is performed, and the obtained data is stored and output.

Next, a driving pulse is generated in the second vertical blanking.
When the signal 214 is applied including the field shift gate pulse, the signal charges accumulated from the imaging elements 12 in the second and sixth pixel rows are read out to the vertical transfer unit 14. Subsequent processing is the same as the procedure described above. When the driving pulse 212 including the field shift gate pulse is applied in the third vertical blanking, the signal charges accumulated from the imaging elements 12 in the third and seventh pixel rows are read out to the vertical transfer unit 14. Finally, when the drive pulse 210 including the field shift gate pulse is applied in the fourth vertical blanking, the signal charges accumulated from the imaging elements 12 in the fourth and eighth pixel rows are read out to the vertical transfer unit 14.

As described above, since the vertical transfer section 14 is formed only every other column, the four drive pulses 210 to 21 are provided.
6 is provided for only one pixel row, the arrangement of a unit including the analog processing section 16, the digital processing section 18, and the horizontal readout scanning section 20 as a set is shown in FIG. Since only half of the sensor 90 is required, the unit can be manufactured at low cost and easily without using fine processing for forming this unit in the horizontal direction.

Although the CCD image sensor to which the present invention has been applied has been described for signal reading by interlaced scanning and four-field interlaced scanning, progressive scanning (all-pixel reading) can also be performed (see FIG. 11).
23). The CCD image sensor 10D shown in FIG.
It is performed with the phase drive pulses 218, 220, 222. The CCD image sensor 10D is exactly the same as the signal reading of a normal progressive scan interline transfer type CCD image sensor. The signal charges supplied from the vertical transfer unit 14 are converted into digital data through analog processing and digital processing. The obtained data is temporarily stored, subjected to horizontal readout scanning, and output as a digital image signal 46.

The vertical transfer section 14 of the CCD image sensor 10D
In FIG. 3, three transfer electrodes 140 are provided for one image sensor 12. Driving pulses 218, 220, and 222 for performing vertical transfer corresponding to the transfer electrode 140 are the same as those of the previous four.
It is not a phase drive but a three-phase drive (not shown). In the CCD image sensor 10D, in addition to the pulse waveforms of the drive pulses 218, 220, and 222, control signals and pulse waveforms for driving each unit are performed at the operation timing shown in FIG.

Finally, an interlaced scanning frame interline transfer type CCD image sensor 10E to which the present invention is applied.
(See FIG. 24). CCD image sensor 10E
Is a light receiving unit 224 in which the imaging elements 12 are arranged and a vertical transfer unit 14
, A unit (16, 18, 20) arranged for each column, and a control unit 22. Portions of the CCD image sensor 10E other than the light receiving unit 224 are subjected to light shielding processing. Image sensor
The signal charges stored in 12 are read out using the drive pulses 30 and 26 during the vertical blanking period. The read signal charges are transferred to the memory 226 through the vertical transfer unit 14, respectively.

The memory 226 is transferred to the analog processing section during the horizontal blanking period. This transfer is performed with drive pulses 24A to 30A different from the clock at the time of vertical transfer. Further, drive pulses 24 to 30 shown in the timing chart of FIG. 3 may be supplied. After the analog processing, A / D conversion is performed for each column as described above, and the temporarily stored data is output as a digital imaging signal 46 by horizontal read scanning. As a result, a digital image signal having less influence of smear can be obtained.

With the above configuration, even if the number of pixels increases, the operating frequency increases in response to the increase. However, since the A / D conversion process is performed for each column to generate a digital signal, an external Eliminates the need for CDS circuits and related phase adjustments. In addition, power consumption can be reduced by eliminating the need for a wideband analog amplifier having large power consumption. Therefore, even if it is mounted on a portable device, it can contribute to prolonging the operation time.

[0114]

As described above, according to the solid-state imaging device and the solid-state imaging device of the present invention, even if the number of pixels increases, the operating frequency increases in accordance with the increase, but the A / D conversion processing is performed for each column. The digital signal eliminates the need for an external CDS circuit and phase adjustment related to it. In addition, a wideband analog amplifier that consumes a large amount of power is not required, and can contribute to prolonged operation time even when mounted on a portable device.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of a CCD image sensor to which a solid-state imaging device of the present invention is applied.

FIG. 2 is a block diagram showing a circuit configuration of each unit provided in a set corresponding to each vertical transfer unit in the CCD image sensor of FIG. 1;

FIG. 3 is a timing chart illustrating the operation of the CCD image sensor of FIG. 1;

FIG. 4 is a block diagram showing a schematic configuration of a digital camera to which the CCD image sensor of FIG. 1 is applied.

FIG. 5 is a block diagram showing a schematic configuration of a digital camera of a comparative example with respect to the digital camera of FIG. 4;

FIG. 6 is a schematic diagram showing a schematic configuration of a so-called honeycomb CCD image sensor in which the image pickup device of FIG. 1 is arranged offset in the horizontal and vertical directions.

FIG. 7 is a schematic diagram showing a wiring connection relationship of a driving pulse when thinning driving is performed in the CCD image sensor of FIG. 1;

FIG. 8 is a schematic diagram showing a schematic configuration in a case where a vertical drive generation unit is provided on-chip in the CCD image sensor of FIG. 1;

9 is a block diagram illustrating an example of a configuration when the vertical drive generation unit in FIG. 8 is of a distributed type.

FIG. 10 is a schematic diagram showing a wiring connection relationship in the case of eight-phase driving in the CCD image sensor of FIG. 8;

FIG. 11 is a schematic diagram showing a positional relationship when a read gate is provided in the CCD image sensor of FIG.

FIG. 12 is a functional circuit diagram showing a schematic configuration of another embodiment in which A / D conversion is performed by another circuit in the solid-state imaging device of the present invention.

FIG. 13 is a timing chart illustrating the operation of the CCD image sensor of FIG.

14 is a timing chart illustrating an operation of the CCD image sensor of FIG. 1 for avoiding overlap between an A / D conversion period and a digital output period.

FIG. 15 is a timing chart illustrating an operation of doubling the sensitivity in the CCD image sensor of FIG. 1;

FIG. 16 is a timing chart illustrating an operation when the reference voltage signal is changed in a curve in the CCD image sensor of FIG. 1;

FIG. 17 is a schematic block diagram in which a noise reduction unit is added to the digital camera of FIG. 4;

18 is a schematic diagram showing a schematic configuration when the CCD image sensor of FIG. 17 is on-chip including a noise reduction unit.

FIG. 19 is a schematic diagram showing a color filter segment arrangement of a color filter used in the CCD image sensor of FIG. 1;

20 is a schematic diagram including a configuration in which two columns are set as a set and the vertical transfer units are alternately selected among the vertical transfer units of the CCD image sensor of FIG. 1;

21 is a timing chart showing a relationship between operation timings of the CCD image sensor of FIG.

FIG. 22 is a schematic diagram showing a relationship in which vertical transfer units are arranged every other row in a honeycomb CCD image sensor and four-field interlaced scanning is performed.

FIG. 23 is a schematic diagram showing a configuration of a progressive scan interline transfer type of a CCD image sensor to which the present invention is applied.

FIG. 24 is a schematic diagram showing a configuration of an interlaced scanning frame interline transfer type of a CCD image sensor to which the present invention is applied.

[Explanation of symbols]

 10 CCD image sensor 12 Image sensor 14 Vertical transfer unit 16 Analog processing unit 16a Q / V conversion unit 16b Noise removal unit 18 Digital processing unit 18a Comparison circuit 18b Memory 20 Horizontal reading scanning unit 20a Address signal generation circuit 22 Control unit

Continuation of the front page (72) Inventor Kazuyuki Masuki 1-6-6 Matsuzakadaira, Yamato-cho, Kurokawa-gun, Miyagi Prefecture F-term in Fujifilm Micro Devices Co., Ltd. 4M118 AA10 AB01 BA13 CA19 CA20 DB08 DD04 DD07 FA06 GC07 GC08 GC14 5C024 AX01 CX06 CY42 DX07 GY01 GZ01 HX13 HX17 HX23 HX58 JX25

Claims (36)

[Claims] 1. A plurality of two-dimensionally arranged image sensors for converting incident light into signal charges in accordance with the intensity of the incident light and storing the signal charges, and arranged adjacent to each of the image sensors. A plurality of transfer electrodes for transferring the signal charges accumulated in the image sensor in the column direction, and controlling the signal charges accumulated in the image sensor to a predetermined transfer electrode between the image sensor and the transfer electrode. Vertical transfer means including a plurality of read gate means, and converts the signal charge transferred and supplied to the end in the column direction via the transfer electrode into an analog voltage signal, and performs analog signal processing on the analog voltage signal A plurality of analog conversion means; a plurality of digital conversion means for converting an output signal from the analog conversion means into a digital signal and storing the digital signal; A plurality of horizontal reading means for performing control to read stored digital signals in a desired order; an output means for outputting a digital signal read out according to the control of the horizontal reading to the outside; the analog conversion means; and the digital conversion means A solid-state imaging device, comprising: a horizontal readout unit; and a control unit that controls an operation of the output unit. 2. The device according to claim 1, wherein the image sensor has a pixel row corresponding to a first pitch in a row direction in a two-dimensional array and a pixel corresponding to a second pitch in a column direction. A plurality of columns, and the vertical transfer means are also arranged at intervals of a first pitch. 3. The device according to claim 1, wherein the image sensor includes a first pixel row separated by a third pitch in a row direction in a two-dimensional array, and the imaging of the first pixel row. A second pixel row shifted half a third pitch apart for each of the elements and a half pitch shifted a fourth pitch apart in the column direction for each of the first pixel rows; Are arranged alternately adjacent to each other in the column direction, and the interval between the first pixel rows and the interval between the second pixel rows are set to a fourth pitch. A solid-state imaging device provided at every third pitch. 4. The device according to claim 1, wherein the device includes a color separation unit including a plurality of color filter segments for separating the incident light for each color, and the incident light. And a micro-condensing means for condensing light and supplying the condensed light to each of the image pickup devices. 5. The solid-state imaging device according to claim 4, wherein the color separation means is provided with a transparent or predetermined same color filter segment over a plurality of pixel rows. 6. The device according to claim 1, wherein the vertical transfer means includes a three-phase drive,
Alternatively, the solid-state imaging device includes the transfer electrode corresponding to multi-phase driving of four or more phases. 7. The device according to claim 1, wherein said vertical transfer means stores a signal charge for one frame or one field of signal charges read out before said analog conversion means. A solid-state imaging device comprising charge storage means. 8. The device according to claim 1, wherein the vertical transfer unit partially connects a signal line of a drive pulse supplied to the transfer electrode included in the vertical transfer unit. A solid-state imaging device which is divided and wired. 9. A device according to claim 1, wherein each of said vertical transfer means comprises:
A solid-state imaging device connected to the analog conversion means corresponding to each column. 10. The device according to claim 1, wherein a plurality of columns are set as one set of each of the vertical transfer means, and the vertical transfer means is provided as one of the analog conversion means. A solid-state imaging device, comprising: a column selection unit that supplies one of the signal charges supplied from each column and supplies the signal charge in a corresponding manner. 11. The device according to claim 1, wherein said analog conversion means comprises: charge / voltage conversion means for converting said signal charges into said analog voltage signal; A solid-state imaging device comprising: 12. The device according to claim 11, wherein
The charge / voltage conversion unit includes a floating junction type charge detection unit that converts the signal charge into an analog voltage signal, and a first amplification unit that amplifies the analog voltage signal. A solid-state imaging device, comprising: first clamp means for clamping a zero potential portion in an analog voltage signal; and first sampling means for sampling the analog voltage signal clamped by the first clamp means. 13. The device according to claim 1, wherein the digital converter compares a reference voltage signal supplied from the controller with an analog voltage signal from the analog converter. And a comparing means for outputting a latch signal in accordance with the coincidence of the two signals; and a memory means for storing a count value supplied from the control means as a digital signal in accordance with the latch signal. Imaging device. 14. The device according to claim 1, wherein said analog conversion means comprises: a floating junction type charge detection means for converting said signal charge into an analog voltage signal; A first amplifying means for amplifying, further comprising: a second sampling means for sampling and holding the amplified analog voltage signal; and an analog voltage for sampling and holding the reference voltage signal supplied from the control means. Signal superimposing means for superimposing on a signal, and a second means for clamping a superimposed voltage signal from the signal superimposing means.
A solid-state imaging device comprising: 15. The device according to claim 14, wherein
A second amplifying means for amplifying a superimposed voltage signal supplied from the analog converting means; a means for clamping the superimposed voltage signal appearing at an input / output terminal of the second amplifying means; Memory means for receiving an output of the second amplifying means as a latch signal after holding, and storing a count value supplied from the control means as a digital signal. 16. The device according to claim 1, wherein said horizontal read means supplies an address signal for reading a digital signal stored in said digital means. . 17. The device according to claim 1, wherein said digital conversion means converts a supplied analog voltage signal into said digital signal during a period during which the supplied analog voltage signal is converted into said digital signal, and reads out from said memory means. A solid-state imaging device, wherein the periods overlap. 18. The device according to claim 1, wherein the digital conversion means completely converts the supplied analog voltage signal into the digital signal during a period during which the analog voltage signal is converted into the digital signal. A solid-state imaging device for reading the image data while shifting the reading period from the means. 19. The device according to claim 1, wherein the control unit supplies the reference voltage signal while changing the reference voltage signal at a predetermined gradient according to time. Imaging device. 20. The device according to claim 1, wherein the control unit changes the predetermined gradient in the reference voltage signal according to an amount of incident light from the object scene, A solid-state imaging device having a function of outputting a reference voltage according to the change. 21. The solid-state imaging device according to claim 1, wherein the control unit outputs a reference voltage signal in which an absolute value of a voltage gradient with respect to time increases. . 22. The solid-state imaging device according to claim 21, wherein the control unit changes the voltage gradient with time. 23. The device according to claim 1, wherein the device eliminates a difference between a reference level set for the element and a level output from each pixel column of the element. A solid-state imaging device, comprising: 24. The device according to claim 23, wherein the noise reduction unit includes a first reference level set for a charge / voltage conversion gain of the device and a level output by each pixel column of the device. Sensitivity difference storage means for storing the difference between the two as a sensitivity variation value, and sensitivity corresponding multiplication means for multiplying the digital signal from the corresponding pixel row by the sensitivity variation value read from the sensitivity difference storage means in accordance with each pixel row. And a solid-state imaging device. 25. The device according to claim 23, wherein the noise reduction unit calculates a second reference level set with respect to a zero level of the element and a level output by each pixel column of the element. An offset storage means for storing the difference as an offset level associated with the charge / voltage conversion means, and an offset level read from the offset storage means and a digital signal from each pixel row supplied in accordance with each pixel row. A solid-state imaging device comprising: an offset removing unit configured to cancel an offset component included in the digital signal. 26. The device according to claim 1, wherein the device includes a timing generating unit configured to generate a signal indicating a driving timing of the vertical transfer unit, and And a drive signal generating means for generating a drive signal for driving the vertical transfer means, wherein the timing generating means and the drive signal generating means are on-chip. 27. The device according to claim 26,
The solid-state imaging device according to claim 1, wherein the drive signal generation unit is arranged in a distributed manner while combining a plurality of types of supplied drive timing signals. 28. The device according to claim 1, wherein the device comprises an optical system for condensing the incident light and signal processing means for performing signal processing on a supplied digital signal. A solid-state imaging device, which is disposed between them. 29. The apparatus according to claim 28, wherein the apparatus includes a display unit that displays an image of the signal obtained by the signal processing unit, and a recording unit that records an output from the signal processing unit on a recording medium. And a transmission unit for transmitting an output from the signal processing unit. 30. The apparatus according to claim 29, wherein the device is arranged at a position where an image is formed by an optical system for condensing the incident light, and further, a signal for performing signal processing on the supplied digital signal. A solid-state imaging device, wherein a noise reduction unit that eliminates a difference between a reference level set for the element and a level output by each pixel column is provided at a stage preceding the processing unit. 31. The apparatus according to claim 30, wherein the noise reduction unit calculates a difference between a first reference level set for a charge / voltage conversion gain of the element and a level output by each pixel column. Sensitivity difference storage means for storing as a sensitivity variation value; sensitivity-corresponding multiplication means for respectively multiplying a digital signal from a corresponding pixel row by a sensitivity variation value read from the sensitivity difference storage means in accordance with each pixel row; Offset storage means for storing the difference between the second reference level set for the zero level of the element and the level output by each pixel column as an offset level associated with the charge / voltage conversion means; The offset level read from the offset storage means and the digital signal from each pixel column are supplied to cancel the offset component contained in the digital signal. The solid-state imaging device which comprises an offset removing means that. 32. A signal reading method in which a plurality of image sensors for converting incident light from an object field into an electric signal are two-dimensionally arranged and a signal converted from the image sensor is read.
The method comprises the steps of: converting the incident light into signal charges in each imaging element and storing the signal charges; and reading out the stored signal charges and sequentially transferring the signal charges in the column direction to the ends in the column direction. A second step, a third step of converting the transferred signal charge into an analog voltage signal, a fourth step of removing a noise component included in the analog voltage signal, and a step of converting the analog voltage signal from which the noise component has been removed. A fifth step of converting the digital signal into a digital signal; a sixth step of temporarily storing the obtained digital signal; and a seventh step of reading the stored digital signal horizontally in accordance with the supplied address signal. A signal reading method characterized by the above-mentioned. 33. The method according to claim 32, wherein the method includes, after the seventh step, an eighth step of removing a fixed pattern of noise included in the digital signal. Read method. 34. A plurality of two-dimensionally arranged image sensors for converting incident light into signal charges in accordance with the intensity of the incident light and storing the signal charges, and arranged adjacent to each of the image sensors. A plurality of transfer electrodes for transferring the signal charges accumulated in the image sensor in the column direction, and controlling the signal charges accumulated in the image sensor to a predetermined transfer electrode between the image sensor and the transfer electrode. Vertical transfer means including a plurality of read-out gate means, and a plurality of analogs for converting signal charges transferred and supplied in the column direction via the transfer electrodes into analog voltage signals and performing analog signal processing on the analog voltage signals Converting means; a plurality of digital converting means for converting an output signal from the analog converting means into a digital signal and storing the digital signal; A plurality of horizontal reading means for performing control to read out the read digital signals in a desired order; an output means for outputting a digital signal read out according to the horizontal reading control to the outside; the analog conversion means, the digital conversion means; A solid-state imaging device including the horizontal readout unit and a control unit that controls the operation of the output unit, is disposed at a position where an image is formed by an optical system that condenses the incident light, and is set for the element. Noise reduction means for converting a reference level and a level output by each pixel column of the element into a digital signal in which the difference is eliminated; and signal processing means for performing signal processing on the digital signal in which the level difference has been eliminated. A solid-state imaging device characterized by the above-mentioned. 35. A plurality of two-dimensionally arranged image sensors for converting incident light into signal charges according to the intensity of the incident light and storing the signal charges, and arranged adjacent to each of the image sensors. A plurality of transfer electrodes for transferring the signal charges accumulated in the image sensor in the column direction, and controlling the signal charges accumulated in the image sensor to a predetermined transfer electrode between the image sensor and the transfer electrode. Vertical transfer means including a plurality of read-out gate means, and a plurality of analogs for converting signal charges transferred and supplied in the column direction via the transfer electrodes into analog voltage signals and performing analog signal processing on the analog voltage signals Converting means; a plurality of digital converting means for converting an output signal from the analog converting means into a digital signal and storing the digital signal; A plurality of horizontal reading means for performing control to read out the read digital signals in a desired order; an output means for outputting a digital signal read out according to the horizontal reading control to the outside; the analog conversion means, the digital conversion means; A solid-state imaging device including the horizontal readout unit and a control unit that controls the operation of the output unit, is disposed at a position where an image is formed by an optical system that condenses the incident light, and is set for the element. Noise reduction means for converting a reference level and a level output by each pixel column of the element into a digital signal in which the difference is eliminated; signal processing means for performing signal processing on the digital signal in which the level difference has been eliminated; Display means for displaying an image of the signal obtained by the processing means, recording means for recording an output from the signal processing means on a recording medium, and signal processing A digital camera, which comprises a transmitting means for transmitting the output from the stage. 36. The camera according to claim 35, wherein the noise reduction unit determines a difference between a first reference level set for a charge / voltage conversion gain of the element and a level output by each pixel column. Sensitivity difference storage means for storing as a sensitivity variation value; sensitivity-corresponding multiplication means for respectively multiplying a digital signal from a corresponding pixel row by a sensitivity variation value read from the sensitivity difference storage means in accordance with each pixel row; Offset storage means for storing the difference between the second reference level set for the zero level of the element and the level output by each pixel column as an offset level associated with the charge / voltage conversion means; To supply the offset level read from the offset storage means and the digital signal from each pixel column, and offset the offset component contained in the digital signal. A digital camera which comprises an offset removing means for.