JP2008124680A - High frequency receiver - Google Patents

Abstract

A high-frequency receiver having a small size is realized.
A tuner unit 102 includes a mixer 109 to which a high-frequency signal from an antenna 105 is supplied to one input, an oscillator 115 to be supplied to the other input of the mixer 109, and the high-frequency signal from the mixer 109. An intermediate frequency converted to a frequency different from the signal is output, an output terminal 107 to which the output of the mixer 109 is supplied, and a PLL control circuit 118 for controlling the oscillator 115 are provided. A demodulation circuit 119 to which a signal output from the output terminal 107 is supplied, an error correction circuit 120, a TS output terminal 122, a control circuit 124, and a reference oscillator 125 are provided, and an input of the output terminal 107 and the demodulation circuit 119 is provided. Filter 1 that blocks the frequency band of the high-frequency signal received by tuner unit 102 and passes the intermediate frequency between 0 in which the provided.
[Selection] Figure 1

Description

  The present invention relates to a high frequency receiving apparatus that receives a television broadcast signal.

  Hereinafter, a conventional high-frequency receiving device will be described with reference to FIG. In FIG. 4, the high frequency receiving apparatus 1 includes a tuner unit 2 and a demodulation unit 3.

  The tuner unit 2 is provided with an input terminal 6 to which an antenna 5 is connected and an output terminal 7 from which an output signal is output. A high frequency amplifier 8, a mixer 9, a filter 10, a mixer 11, a filter 12, and an amplifier 13 are connected in order from the input terminal 6 to the output terminal 7.

  Further, oscillators 15 and 16 are connected to the other inputs of the mixers 9 and 11, respectively. Further, a PLL control circuit 18 for controlling the oscillation frequency of the oscillators 15 and 16 is connected.

  The high-frequency amplifier 8, the mixers 9 and 11, the filters 10 and 12, the amplifier 13, and the oscillator 15 constitute a tuner circuit 2a.

  The demodulator 3 includes a demodulation circuit 19 to which the output of the output terminal 7 is connected, an error correction circuit 20 to which the output of the demodulation circuit 19 is connected, and a TS to which a signal output from the error correction circuit 20 is supplied. The control circuit 24 includes an output terminal 22, a demodulation circuit 19, and a PLL control circuit 18, and a reference oscillator 25 that supplies a reference signal to the control circuit 24.

  About the high frequency receiver 1 comprised as mentioned above, the operation | movement is demonstrated below. The digital broadcast signal input from the antenna 5 is supplied to the tuner circuit 2a. In this tuner circuit 2 a, it is amplified by the high frequency amplifier 8, further converted to an intermediate frequency of, for example, 57 MHz by the mixer 9, then converted to an intermediate frequency of, for example, 4 MHz, which is a lower frequency, by the mixer 11, and Amplified.

  The 4 MHz intermediate frequency signal is input to the demodulation circuit 19. The demodulated signal output from the demodulating circuit 19 is error-corrected by the error correcting circuit 20 and a TS signal is output from the output terminal 22.

  The PLL control circuit 18, the demodulation circuit 19, and the error correction circuit 20 are controlled by a control circuit 24 that receives a control signal from a control signal terminal 26. Further, a reference signal for operating the control circuit 24 is supplied from a reference oscillator 25.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP-A-8-228191

  In such a conventional high frequency receiving apparatus, the demodulating circuit 19 uses a demodulating circuit 19 capable of inputting a frequency as low as 4 MHz, for example, due to the relationship between semiconductor manufacturing technology and cost. The output signal from the tuner unit 2 with respect to the input of the demodulator circuit 19 has an intermediate frequency of 4 MHz, for example.

  For this reason, the frequency is converted to 57 MHz by the mixer 9 and further converted to 4 MHz by the mixer 11. This is because, for example, if the frequency of UHF, which is a television broadcast signal, is directly converted to an intermediate frequency of 4 MHz, interference due to an image signal or the like occurs.

  Further, the sampling frequency at the time of demodulation of the demodulation circuit 19 needs to be twice or more the frequency of the intermediate frequency signal of 4 MHz. In order to create a frequency more than twice this (for example, 8 MHz or more), for example, a 4 MHz crystal oscillator is used as the reference oscillator 25.

  For this reason, since it is necessary to use the two mixers 9 and 11, the shape of the tuner part 2 will become large. Furthermore, since the reference oscillator 25 uses a 4 MHz crystal oscillator having a low frequency, the shape of the demodulator is large. For this reason, it has been impossible to realize a high-frequency receiving apparatus having a reduced size.

  Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to realize a high-frequency receiving device with a reduced size.

  In order to achieve this object, in the high-frequency receiving device of the present invention, the first tuner circuit includes a first input terminal to which a high-frequency signal from an antenna is input, and the high-frequency signal input to the first input terminal. A mixer in which a signal is supplied to one input, an oscillator supplied to the other input of the mixer, an intermediate frequency converted to a frequency different from the high-frequency signal is output from the mixer, and this A first output terminal to which an output of the mixer is supplied, and the demodulator receives a demodulator circuit to which a signal output from the first output terminal is supplied, and a demodulated signal from the demodulator circuit. And an error correction circuit for correcting an error, a TS output terminal from which a TS signal is output from the error correction circuit, a control circuit for controlling the demodulation circuit, the error correction circuit, and a PLL control circuit, A reference oscillator serving as a reference signal for the control circuit is provided to block a frequency band of the high-frequency signal received by the first tuner circuit between the first output terminal and the input of the demodulation unit and A first filter that passes the frequency is provided.

  Thereby, the intended purpose can be achieved.

  As described above, in the high frequency receiving device of the present invention, the first tuner circuit includes the first input terminal to which the high frequency signal from the antenna is input, and the high frequency signal input to the first input terminal. A mixer supplied to one input, an oscillator supplied to the other input of the mixer, an intermediate frequency converted to a frequency different from the high-frequency signal is output from the mixer, and the mixer And a demodulator that receives a signal output from the first output terminal, and receives a demodulated signal from the demodulator. An error correction circuit for correcting an error, a TS output terminal from which a TS signal is output from the error correction circuit, a control circuit for controlling the demodulation circuit, the error correction circuit, and a PLL control circuit, and a reference for the control circuit A reference oscillator serving as a signal, and blocking a frequency band of the high-frequency signal received by the first tuner circuit between the first output terminal and the input of the demodulator and passing the intermediate frequency. A first filter is provided.

  As a result, an intermediate frequency signal of, for example, 57 MHz output from one mixer can be directly demodulated by the demodulator, so the number of mixers in the tuner is one, and a miniaturized size is possible.

  Further, as a reference oscillator which is a reference signal of the demodulator, for example, a crystal oscillator having a downsized size of 25.4 MHz can be incorporated in one housing. Therefore, a miniaturized high-frequency receiving device can be realized.

  Further, since the first filter is used, the harmonics of the reference oscillator do not disturb the input side of the tuner section.

(Embodiment 1)
FIG. 1 is a block diagram of a high frequency receiving apparatus according to Embodiment 1 of the present invention. The high-frequency receiving device 101 includes a tuner unit 102 and a demodulation unit 103. The tuner unit 102 and the demodulation unit 103 are mounted on a substrate and can be covered with a high frequency shield case 103a.

  The tuner unit 102 is provided with an input terminal 106 to which an antenna 105 is connected and an output terminal 107 from which an output signal is output. A high frequency amplifier 108, a mixer 109, a filter 110, and an amplifier 113 are connected in this order from the input terminal 106 to the output terminal 107.

  An oscillator 115 is connected to the other input of the mixer 109. Further, a PLL control circuit 118 for controlling the oscillation frequency of the oscillator 115 is connected.

  The high frequency amplifier 108, the mixer 109, the filter 110, the amplifier 113, and the oscillator 115 constitute a tuner circuit 117.

  The demodulation unit 103 includes a demodulation circuit 119 to which the output of the output terminal 107 is connected, an error correction circuit 120 to which the output of the demodulation circuit 119 is connected, and a TS to which a signal output from the error correction circuit 120 is supplied. The control circuit 124 controls the output terminal 122, the demodulation circuit 119 and the PLL control circuit 118, and a reference oscillator 125 that supplies a reference signal to the control circuit 124.

  The PLL control circuit 118, the demodulation circuit 119, and the error correction circuit 120 are controlled by a control circuit 124 that receives a control signal from a control signal terminal 126.

  Further, a reference signal for operating the control circuit 124 is supplied from the reference oscillator 125.

  Further, the demodulation circuit 119, the error correction circuit 120, and the control circuit 124 can be configured as one integrated circuit 119a.

  The operation of the high frequency receiving apparatus 101 configured as described above will be described below. A digital broadcast signal that is a high-frequency signal input from the antenna 105 is supplied to the tuner circuit 117. In the tuner circuit 117, the signal is amplified by the high-frequency amplifier 108, further converted to an intermediate frequency of, for example, 57 MHz by the mixer 109, and the intermediate frequency is suppressed by the filter 110, further amplified by the amplifier 113, and output to the output terminal 107. Is output from.

  The 57 MHz intermediate frequency signal from the output terminal 107 is input to a filter 130 that blocks the frequency band of the high frequency signal received by the tuner circuit and passes the 57 MHz intermediate frequency signal. A signal output from the filter 130 is input to the demodulation circuit 119.

  In this demodulation circuit 119, a high intermediate frequency of 57 MHz can be directly input and demodulated. Thus, a technique capable of demodulating a high intermediate frequency has been made possible by recent improvements in semiconductor technology.

  Since the 57 MHz intermediate frequency signal is input to the demodulation circuit 119, the reference oscillator 125 requires a frequency that is twice or more to sample a 57 MHz signal, for example. In order to create this sampling frequency, for example, the oscillation frequency of a crystal oscillator of 25.4 MHz is doubled and used. As described above, the crystal oscillator having a high frequency can be reduced in size because the vibrator can be made smaller by the higher frequency.

  However, the reference oscillator 125 using 25.4 MHz for this crystal oscillator has a higher harmonic signal in the UHF band than the 4 MHz crystal oscillator. The reason for this will be described below.

  For example, the case where the received signal of the antenna 105 is in the UHF band of 470 to 770 MHz will be described. 19 to 30 times the oscillation frequency 25.4 MHz of the reference oscillator 125 is changed from 482.6 MHz to 762.0 MHz, which is a frequency close to UHF of 15 cH to 61 cH.

  On the other hand, in the reference oscillator 25 having the oscillation frequency of 4 MHz of the conventional example, 118 times to 192 times of the oscillation frequency 4 MHz is changed from 472 MHz to 768 MHz, and the frequency is close to UHF 13 cH to 62 cH.

  Thus, the order of the harmonics in the harmonic signal is smaller in the reference oscillator 125 having the oscillation frequency of 25.4 MHz than in the reference oscillator 25 having the oscillation frequency of 4 MHz. When this order is small, a harmonic component signal close to the reference oscillation frequency is generated, so that the level of the harmonic signal due to the oscillation frequency 25.4 MHz of the reference oscillator 125 increases.

  For this reason, the reference oscillator 125 using 25.4 MHz for the crystal oscillator has a higher harmonic signal in the UHF band than the 4 MHz crystal oscillator. This harmonic signal leaks from the input of the demodulation circuit 119, for example. This leaked signal leaks to the input section of the tuner circuit 117, resulting in interference.

  In order to improve this, a filter 130 is inserted between the output terminal 107 and the input of the demodulation circuit 119. The filter 130 is a filter that blocks the frequency band of the high-frequency signal received by the tuner circuit 117 and passes the intermediate frequency signal from the output terminal 107. For example, an LPF (low pass filter) that attenuates the UHF band and passes the intermediate frequency signal from the output terminal 107 may be used.

  Further, a shield plate 150 that shields high frequencies is provided between the tuner unit 102 and the demodulation unit 103. By providing the filter 130 between the shield plate 150 and the demodulator 103, the occurrence of interference due to the harmonic signal of the reference oscillator 125 can be further suppressed.

  In this case, it is important to provide the filter 130 close to the input of the demodulation circuit 119. That is, since the connection portion between the filter 130 and the demodulation circuit 119 can be minimized, the radiation component of the harmonic signal of the reference oscillator 125 can be reduced.

  A ground pattern is provided on the inner layer of the printed circuit board, a high frequency amplifier 108, a mixer 109, and an oscillator 115 are mounted on one surface of the printed circuit board, and a reference oscillator 125 is mounted on the other surface of the printed circuit board. Also good. In this case, the high frequency signal of the reference oscillator 125 is shielded in high frequency by the ground pattern, so that the tuner circuit 117 is not disturbed.

  Furthermore, a tuner circuit 117, a PLL control circuit 118, an integrated circuit 119a, and a reference oscillator 125 are attached to the printed circuit board. In this case, the height of the reference oscillator 125 from the printed board is set lower than the height of the integrated circuit 119a from the printed board. As a result, the reference oscillator 125 and the filter 130 are separated by the integrated circuit 119a. This makes it difficult for the harmonic signal of the reference oscillator 125 to flow into the filter 130. Therefore, the occurrence of interference is suppressed.

(Embodiment 2)
FIG. 2 is a block diagram of high-frequency receiving apparatus 201 according to Embodiment 2 of the present invention. In the first embodiment, single reception using an output signal from one tuner circuit 117 is performed. On the other hand, the present embodiment is different in that diversity reception using output signals from the two tuner circuits 117 and 202 is performed.

  In addition, about what has the structure similar to the structure of Embodiment 1, the same code | symbol is attached | subjected and the description is simplified.

  In FIG. 2, a high-frequency receiving apparatus 201 includes a tuner unit 203 and a demodulating unit 204 that are configured in one high-frequency shield case 201a. The tuner unit 203 and the demodulation unit 204 are mounted on a substrate and covered with a high frequency shield case 201a.

  A tuner unit 203 includes tuner circuits 117 and 202 to which antennas 105 and 206 are connected via input terminals 106 and 208, respectively, and output terminals 107 and 211 to which output signals from these tuner circuits 117 and 202 are connected, respectively. , Power supplies 218 a and 218 b supplied to the tuner circuits 117 and 202, and a PLL control circuit 218 that controls the oscillation frequency of the oscillator 115.

  The tuner circuit 202 is provided with an input terminal 208 to which an antenna 206 is connected and an output terminal 211 from which an output signal is output. A high frequency amplifier 228, a mixer 229, a filter 230, and an amplifier 233 are connected in order from the input terminal 208 to the output terminal 211. The oscillator 115 is connected to the other input of the mixer 229.

  Next, the demodulation unit 204 includes filters 130 and 236 connected to the output terminals 107 and 211, a demodulation circuit 238 to which outputs of the filters 130 and 236 are respectively connected, and a demodulation output from the demodulation circuit 238. Diversity circuit 240 to which each signal is input, signal selected and synthesized by diversity circuit 240 is supplied, error correction circuit 242 that corrects an error, and TS signal output from error correction circuit 242 is output. Output terminal 244, diversity circuit 240 or error correction circuit 242, and a control circuit 246 that supplies a control signal by I2C or the like to PLL control circuit 218, and I2C or the like to this control circuit 246 from the outside An input terminal 249 for supplying control data according to the And a reference oscillator 125 which is a issue of the reference.

  Note that the demodulation circuit 238, the diversity circuit 240, the error correction circuit 242, and the control circuit 246 are mounted in one integrated circuit 204a.

  An operation of single reception or diversity reception in the high-frequency receiving apparatus 201 configured as described above will be described below.

  Note that single reception means that one of the tuner circuits 117 and 202 is input to the demodulation circuit 238 for reception. For example, the following description will be made assuming that the tuner circuit 117 is used.

  In the diversity reception, two output signals of the tuner circuits 117 and 202 are input to the demodulation circuit 238, and the two demodulation signals from the demodulation circuit 238 are combined by the diversity circuit 240 and received.

  First, the operation of diversity reception using two demodulated signals will be described below. That is, it is a reception state when the reception quality is poor.

  First, control data is supplied from the control circuit 246 to the PLL control circuit 218. The PLL control circuit 218 supplies power sources 218a and 218b to the tuner circuits 117 and 202, respectively. At the same time, the oscillation frequency of the oscillator 115 is controlled so that the same desired signal is selected in the tuner circuits 117 and 202.

  The digital broadcast signals input from the antennas 105 and 206 are amplified by the high frequency amplifiers 108 and 228 and input to the mixers 109 and 229, respectively.

  An oscillator 115 is supplied to the other input of the mixers 109 and 229 so that the same reception channel is selected. In this way, the selected desired signals are output from the mixers 109 and 229. This output signal is input to the filters 110 and 230, and the interference signal is suppressed.

  Output signals from these filters 110 and 230 are input to amplifiers 113 and 233, respectively. The amplified signals output from the amplifiers 113 and 233 are output from the output terminals 107 and 211.

  These output signals are input to the demodulation circuit 238, respectively. Respective demodulated signals output from the demodulating circuit 238 are input to the diversity circuit 240, respectively.

  The diversity circuit 240 detects the signal quality of subcarriers included in these demodulated signals. Based on the detected signal quality information, a weighting coefficient for each subcarrier is calculated. Subcarriers are combined by this weighting coefficient. This combined subcarrier combined signal is output from diversity circuit 240. The signal synthesized in this way has a C / N improved by a maximum of 4 times by the weighting coefficient.

  The signal quality of the demodulated signal may be determined using the C / N value or BER value output from the error correction circuit 242.

  Next, an operation for switching from diversity reception to single reception will be described. Note that, when switching to single reception, the tuner circuit 117 is in an operating state and the tuner circuit 202 is in a non-operating state.

  Diversity circuit 240 detects the signal quality of the subcarrier, and when this signal quality is good, only the output signal from tuner circuit 117 is input to demodulation circuit 238 for single reception. By using one demodulated signal in this way, the power source 218a is supplied only to the tuner circuit 117, so that power consumption can be reduced.

  However, in this high frequency receiving apparatus 201, the problem of interference occurs as in the first embodiment. That is, the harmonic signal of the reference oscillator 125 flows backward from the input of the demodulation circuit 238 to the output of the tuner circuits 117 and 202 via the output terminals 107 and 211. The back-flowed interference signal jumps into the input portions of the high-frequency amplifiers 108 and 228, and is further frequency-converted by the mixers 109 and 229 in the same manner as the reception signal, thereby generating interference.

  In order to improve this, filters 130 and 236 are inserted between the inputs of the output terminals 107 and 211 and the demodulation circuit 238, respectively. These filters 130 and 236 are filters that block the frequency band of the high-frequency signal received by the tuner circuits 117 and 202. For example, if the high-frequency signal to be received is the UHF band, an LPF (low-pass filter) that attenuates the UHF band and passes the intermediate frequency signal from the output terminals 107 and 211 may be used.

  Further, a high-frequency shield plate 250 is provided between the tuner unit 203 and the demodulation unit 204. By providing the filters 130 and 236 between the shield plate 250 and the demodulation circuit 238, the occurrence of interference due to the harmonic signal of the reference oscillator 125 can be further suppressed.

  In this case, it is important that the filters 130 and 236 are provided close to the input of the demodulation circuit 238. That is, since the connection portion between the filters 130 and 236 and the demodulation circuit 238 can be minimized, the radiation component of the harmonic signal of the reference oscillator 125 can be reduced.

  A ground pattern is provided on the inner layer of the printed circuit board, high frequency amplifiers 108 and 228, mixers 109 and 229, and an oscillator 115 are mounted on one surface of the printed circuit board, and a reference oscillator 125 is mounted on the other surface of the printed circuit board. May be installed. In this case, the high frequency signal of the reference oscillator 125 is shielded in high frequency by the ground pattern formed on the inner layer of the printed circuit board, so that the tuner circuits 117 and 202 are not disturbed.

  Further, tuner circuits 117 and 202, PLL control circuit 218, integrated circuit 204a, and reference oscillator 125 are attached to the printed circuit board. In this case, the height of the reference oscillator 125 from the printed board is set lower than the height of the integrated circuit 204a from the printed board. As a result, the reference oscillator 125 and the filters 130 and 236 are separated in high frequency by the integrated circuit 204a. This makes it difficult for the harmonic signal of the reference oscillator 125 to flow into the filters 130 and 236. Therefore, the occurrence of interference is suppressed.

  Furthermore, tuner circuits 117 and 202 are provided in parallel in this order as an arrangement of the printed circuit board, and the reference oscillator 125 is arranged far from the tuner circuit 117. By doing so, the distance between the tuner circuit 117 and the reference oscillator 125 can be separated from the tuner circuit 202 and the reference oscillator 125. Therefore, when the diversity circuit 240 selects a demodulated signal, the reception quality can be improved by using the tuner circuit 117 with priority.

(Embodiment 3)
FIG. 3 is a block diagram of high-frequency receiving apparatus 301 according to Embodiment 3 of the present invention. In the second embodiment, single reception using output signals from the two tuner circuits 117 and 202 is performed. On the other hand, the present embodiment is different in that diversity reception using output signals from the four tuner circuits 117, 202, 303, and 305 is performed.

  In addition, about the thing which has the structure similar to the structure of Embodiment 2, the same code | symbol is attached | subjected and the description is simplified.

  In FIG. 3, the high frequency receiving apparatus 301 includes tuner units 306 and 307 and a demodulating unit 308 that are configured in one high frequency shield case 301a. The tuner units 306 and 307 and the demodulating unit 308 are mounted on a substrate and covered with a high frequency shield case 301a.

  The tuner unit 306 includes tuner circuits 117 and 202 to which the antennas 105 and 206 are connected via the input terminals 106 and 208, respectively, and output terminals 107 and 211 to which output signals from the tuner circuits 117 and 202 are connected, respectively. The power supply 309a and 309b are supplied to the tuner circuits 117 and 202, and the PLL control circuit 309 that controls the oscillation frequency of the oscillator 115 is included.

  The tuner unit 307 includes tuner circuits 303 and 305 to which antennas 311 and 312 are connected via input terminals 314 and 315, respectively, and output terminals 317 and 318 to which output signals from the tuner circuits 303 and 305 are respectively connected. It is composed of

  The tuner circuit 303 is provided with an input terminal 314 to which an antenna 311 is connected and an output terminal 317 to which an output signal is output. A high frequency amplifier 320, a mixer 321, a filter 322, and an amplifier 323 are connected in this order from the input terminal 314 to the output terminal 317. The oscillator 115 is connected to the other input of the mixer 321.

  The tuner circuit 305 is provided with an input terminal 315 to which the antenna 312 is connected and an output terminal 318 from which an output signal is output. A high frequency amplifier 330, a mixer 331, a filter 332, and an amplifier 333 are connected in order from the input terminal 315 to the output terminal 318. The oscillator 115 is connected to the other input of the mixer 331.

  Further, power supplies 309c and 309d output from the PLL control circuit 309 supply power to the tuner circuits 303 and 305, respectively.

  Next, the demodulation unit 308 includes filters 130, 236, 335, and 336 connected to the output terminals 107, 211, 317, and 318, respectively, and demodulation circuits to which outputs of these filters 130, 236, 335, and 336 are connected, respectively. 338, a diversity circuit 340 to which a demodulated signal output from the demodulation circuit 338 is input, an error correction circuit 342 to which a signal selected and combined by the diversity circuit 340 is supplied, and the error correction circuit 342 An output terminal 344 for outputting an output TS signal, a control circuit 346 for inputting / outputting a signal from the diversity circuit 340 or the error correction circuit 342 and supplying a control signal by I2C or the like to the PLL control circuit 309, and this control Data for control by I2C or the like is supplied to the circuit 346 from the outside The force terminal 348, and a reference oscillator 125 as a reference clock signal.

  Note that the demodulation circuit 338, the diversity circuit 340, the error correction circuit 342, and the control circuit 346 are mounted in one integrated circuit 308a.

  In the high frequency receiving apparatus 301 configured as described above, an operation of single reception or diversity reception will be described below.

  Note that single reception refers to input of any one of the tuner circuits 117, 202, 303, and 305 to the demodulation circuit 338 for reception. For example, the following description will be made assuming that the tuner circuit 117 is used.

  In diversity reception, two or more output signals from the tuner circuits 117, 202, 303, and 305 are input to the demodulation circuit 338, and two or more demodulation signals from the demodulation circuit 338 are combined by the diversity circuit 340. Is received.

  The basic operation of diversity reception using single reception or two tuner circuits 117 and 202 is the same as that of the second embodiment.

  In diversity reception using the four tuner circuits 117, 202, 303, and 305, the output signals from the tuner circuits 117, 202, 303, and 305 are input to the demodulation circuit 338, and the four demodulation signals from the demodulation circuit 338 are input. The data is synthesized by the diversity circuit 340 and received.

  In this case, the PLL control circuit 309 is supplied with control data from the control circuit 346. With this control data, the PLL control circuit 309 supplies the power supplies 309a, 309b, 309c, and 309d to the tuner circuits 117, 202, 303, and 305, respectively. At the same time, the oscillation frequency of the oscillator 115 is controlled so that the same desired signal can be selected for the tuner circuits 117, 202, 303, and 305.

  In this way, single reception and diversity reception can be selected according to the reception quality, and the reception quality of the high-frequency receiving apparatus 301 can be ensured. That is, when the reception quality is the worst, the output signals from the four tuner circuits 117, 202, 303, and 305 are used. Next, when the reception quality is poor, the output signals from the two tuner circuits 117 and 202 are used, When reception quality is good, single reception can be selected using the output signal of the tuner circuit 117.

  The signal quality of the demodulated signal may be determined using the C / N value or BER value output from the error correction circuit 342 instead of the subcarrier detection signal of the demodulation circuit 338.

  However, in this high frequency receiving apparatus 301, the problem of interference occurs as in the second embodiment. That is, the harmonic signal of the reference oscillator 125 flows from the input of the demodulation circuit 338 to the tuner circuits 117, 202, 303, 305 through the output terminals 107, 211, 317, 318. The inflowing interference signal jumps into the input portion of the high frequency amplifier 108, 228, 320, 330, for example, and as a result, the frequency is converted by the mixers 109, 229, 321, 331 in the same manner as the reception signal, thereby generating interference. .

  In order to improve this, filters 130, 236, 335, and 336 are inserted between the input terminals of the output terminals 107, 211, 317, and 318 and the demodulation circuit 338. These filters 130, 236, 335, and 336 are filters that block the frequency band of the high-frequency signal received by the tuner circuits 117, 202, 303, and 305 and pass the intermediate frequency signal from the output terminals 107, 211, 317, and 318. It is said.

  For example, if the received high-frequency signal is a UHF band, an LPF (low-pass filter) that attenuates the UHF band and passes intermediate frequency signals from the output terminals 107, 211, 317, and 318 may be used.

  Further, a shield plate 350 for high frequency is provided between the tuner unit 306 and the demodulation unit 308. By providing the filters 130, 236, 335, and 336 between the shield plate 350 and the demodulation circuit 338, the occurrence of interference due to the harmonic signal of the reference oscillator 125 can be further suppressed.

  In this case, it is important to provide the filters 130, 236, 335, and 336 close to the input of the demodulation circuit 338. That is, since the connection portion between the filters 130, 236, 335, and 336 and the demodulation circuit 338 can be made shortest, the radiation component of the harmonic signal of the reference oscillator 125 can be reduced.

  A ground pattern is provided on the inner layer of the printed circuit board, and high frequency amplifiers 108, 228, 320, 330, mixers 109, 229, 321, 331, and an oscillator 115 are mounted on one surface of the printed circuit board. A reference oscillator 125 may be mounted on the other surface of the. In this case, since the high frequency signal of the reference oscillator 125 is shielded in a high frequency by the ground pattern, the tuner circuits 117, 202, 303, and 305 are not disturbed.

  Further, the tuner circuits 117, 202, 303, and 305, the PLL control circuit 309, the integrated circuit 308a, and the reference oscillator 125 are mounted on the printed circuit board. The height of the integrated circuit 308a from the printed circuit board is set. On the other hand, the height of the reference oscillator 125 from the printed board is set low. As a result, the reference oscillator 125 and the filters 130, 236, 335, and 336 are separated at high frequency by the integrated circuit 308a. This makes it difficult for the harmonic signal of the reference oscillator 125 to flow into the filters 130, 236, 335, and 336. Therefore, the occurrence of interference is suppressed.

  Furthermore, tuner circuits 117, 202, 303, and 305 are provided in parallel in this order as an arrangement of the printed circuit board, and the reference oscillator 125 is disposed farthest from the tuner circuit 117 among these tuner circuits. By doing so, the distance between the reference oscillator 125 and the tuner circuits 117, 202, 303, and 305 can be separated from the reference oscillator 125 in the order of the tuner circuits 117, 202, 303, and 305.

  Therefore, when the diversity circuit 240 selects the demodulated signal, the reception quality can be improved by preferentially using the output signals from the tuner circuits 117, 202, 303, and 305 in order.

  The high-frequency receiver of the present invention can improve the interference caused by the harmonic signal of the reference oscillator having a high frequency when using a demodulator capable of inputting a high intermediate frequency. Can be applied.

Block diagram of the high-frequency receiving device according to Embodiment 1 of the present invention The block diagram of the high frequency receiver in the second embodiment The block diagram of the high frequency receiver in Embodiment 3 Block diagram of a conventional high frequency receiver

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 High frequency receiver 102 Tuner part 103 Demodulator part 105 Antenna 106 Input terminal 107 Output terminal 109 Mixer 115 Oscillator 117 Tuner circuit 118 PLL control circuit 119 Demodulator circuit 120 Error correction circuit 122 TS output terminal 124 Control circuit 125 Reference oscillator 130 Filter

Claims (10)

A first tuner unit including a first tuner circuit to which a high-frequency signal is input and a PLL control circuit for controlling the first tuner circuit, and a demodulator unit to which an output of the first tuner unit is connected. The first tuner circuit includes a first input terminal to which a high-frequency signal from an antenna is input, and the high-frequency signal input to the first input terminal is one of the first input terminals. A mixer supplied to the input, an oscillator supplied to the other input of the mixer, an intermediate frequency converted from the mixer to a frequency different from the high-frequency signal, and an output of the mixer The demodulator is supplied with a demodulator circuit to which a signal output from the first output terminal is supplied, and a demodulated signal from the demodulator circuit is input and an error occurs. Revision Error correction circuit, TS output terminal for outputting a TS (transport) signal from the error correction circuit, a control circuit for controlling the demodulation circuit, the error correction circuit, and the PLL control circuit, and the control circuit And a reference oscillator that serves as a reference signal of the high frequency signal received by the first tuner circuit between the first output terminal and the input of the demodulator, and the intermediate frequency is A high frequency receiver provided with a first filter to be passed. A tuner unit and a demodulating unit are built in the first housing, and a partition plate for shielding a high frequency signal is provided between the tuner unit and the demodulating unit, and the first filter includes the demodulating unit and the partition plate. The high-frequency receiving device according to claim 1, wherein the high-frequency receiving device is provided near the input of the demodulation circuit. A demodulation circuit, an error correction circuit, and a control circuit are mounted on a substrate as an integrated circuit. In the integrated circuit, a first filter is provided on one side where the input terminal of the demodulation circuit is provided, and a reference is provided on a different side. The high frequency receiver according to claim 1, wherein an oscillator is provided, and a height of the reference oscillator is lower than a height of the integrated circuit. The high-frequency receiver according to claim 1, wherein a high-frequency amplifier, a mixer, and an oscillator are mounted on one surface of the substrate, and a reference oscillator is mounted on the other surface of the substrate. The tuner unit is provided with a second tuner circuit having the same configuration as the first tuner circuit, and a second output terminal connected to the output of the second tuner circuit. The second tuner circuit is provided with the second tuner circuit. The output of the oscillator of the first tuner circuit is supplied to the other input of the second mixer, and the demodulator is supplied with the first and second output signals from the first and second output terminals, respectively. Output signals are supplied to the first and second inputs, respectively, and the first and second demodulated signals are output, respectively. The demodulating circuit is provided between the demodulating circuit and the error correcting circuit. A diversity circuit for selecting or combining the second demodulated signal, a first filter between the first and second output terminals and the first and second inputs of the demodulator circuit; A second filter having the same characteristics as the first filter By inserting the data respectively, the harmonic signal is the first reference oscillator, the high-frequency receiver according to claim 1 for preventing the flow into the second tuner circuit. The first and second tuner circuits are arranged in parallel, the reference oscillator has the first tuner circuit arranged farther than the second tuner circuit, and the diversity circuit has the first and second demodulated signals. The high-frequency receiving device according to claim 5, wherein when one is selected, the output from the first tuner circuit is preferentially selected. A C / N (carrier / noise) signal or a BER (bit error rate) signal output from the error correction unit is supplied to the control circuit, and the C / N signal or the BER signal is predetermined in this control circuit. 6. The high frequency receiving apparatus according to claim 5, wherein the diversity signal is selected / combined based on the signal determined by comparison with the value and based on the signal determined by comparison. The high frequency receiving apparatus according to claim 5, wherein the first and second tuner sections and the demodulating section are built in one housing. Third and fourth tuner circuits having the same configuration as the second tuner circuit are provided, and the outputs of the third and fourth tuner circuits are the third and fourth filters having the same characteristics as the first filter. To the third and fourth inputs of the demodulator circuit, and the inputs to the other of the second, third and fourth mixers respectively provided in the second, third and fourth tuner circuits are 6. The high frequency receiving apparatus according to claim 5, wherein an output signal of a first oscillator is supplied to prevent a harmonic signal of a reference oscillator from flowing into the first, second, third, and fourth tuner circuits. The first to fourth tuner circuits and the demodulator are built in one housing, the first to fourth tuner circuits are provided in parallel in this order, and the reference oscillators are arranged in the order of the first to fourth tuner circuits. When the diversity unit is arranged far away and the diversity unit selects or synthesizes the output signals from the first to fourth tuner circuits, the output signals from the first to fourth tuner circuits are preferentially used in this order. Item 11. The high frequency receiving device according to Item 9.

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