JP2004056367A - Tuner device - Google Patents

Abstract

An object of the present invention is to provide a tuner device which does not adversely affect reception characteristics even when a harmonic of a fundamental frequency of a crystal resonator returns to an RF circuit as a spurious signal.
An RF signal input from an input terminal is converted into an IF signal by a mixer and demodulated by a demodulation IC. The crystal oscillators 11 and 12 are connected to the demodulation IC 9 to generate a system clock for digital processing of a signal. The connection of the crystal oscillators 11 and 12 having different fundamental frequencies to the demodulation IC 9 is switched by the control of the switching circuit 13. The quartz oscillators 11 and 12 are selected according to the reception frequency so that the harmonic of the fundamental frequency returned to the RF circuit side of the tuner device does not enter the intermediate frequency band of the RF signal after the intermediate frequency conversion.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a tuner device having a built-in demodulator corresponding to each modulation system as a tuner for receiving digital broadcasting in digital broadcasting of CATV, terrestrial broadcasting, and satellite broadcasting.
[0002]
[Prior art]
As digital broadcast receiving tuners for digital broadcasting of CATV, terrestrial broadcasting, and satellite, tuners with built-in demodulation ICs corresponding to modulation schemes of respective broadcasts, so-called NIM (Network Interface Module) tuners are increasing. In such an NIM tuner, it is common to use a crystal oscillator as a system clock for each demodulator.
[0003]
Such a conventional tuner device is configured, for example, as shown in FIG. In this tuner device, an RF signal (high-frequency signal) input from an input terminal 1 is filtered by a high-pass filter 2 to remove low-frequency components, amplified by a first-stage RF amplifier 3, and then band-limited by a band-pass filter 4. You. The signal that has passed through the band-pass filter 4 is converted into an IF signal of an intermediate frequency by a mixer 5 and amplified by an IF amplifier 8. The amplified IF signal is further detected and demodulated by the demodulation IC, and then output from the output terminal 10 as a demodulated signal.
[0004]
In the mixer 5, the RF signal is converted into an IF signal (intermediate frequency signal) by mixing the local signal (having the oscillation frequency of the VCO 6) generated by the VCO 6 with the input signal. The oscillation frequency of the VCO 6 is controlled to a constant value corresponding to the designated channel by adjusting the capacity of a tank circuit (not shown) provided in the VCO 6 by the PLL-IC 7.
[0005]
Further, the demodulation IC 9 requires a system clock as a sampling clock to be supplied to an A / D converter for converting an input analog IF signal into a digital signal. For this reason, the crystal oscillator 11 is connected to the demodulation IC 9 as a system clock supply source.
[0006]
[Problems to be solved by the invention]
In the above-described tuner device, the oscillation circuit using the crystal resonator 11 oscillates not only a fundamental frequency originally required as a system clock but also a frequency which is a harmonic thereof. In addition, this frequency becomes an unnecessary spurious signal inside the tuner. In particular, when the harmonic oscillation level of the system clock is large, the spurious signal enters the reception band and becomes an interference signal depending on the reception frequency of the tuner, which adversely affects the reception characteristics.
[0007]
For example, in the case of a digital CATV tuner having the following specifications: reception frequency RF: 47 MHz to 862 MHz, intermediate frequency fo: 44 MHz, reception bandwidth Bw: 6 MHz (fo ± 3 MHz), and QAM demodulation system clock frequency fc: 35.2 MHz, The second harmonic is 70.4 MHz, and the third harmonic is 105.6 MHz. Therefore, when the RF frequency of 70 MHz or 105 MHz is received, the difference from the harmonic twice or three times the system clock becomes 400 kHz and 600 kHz, respectively. Then, the second harmonic 70.4 MHz at the time of receiving 70 MHz becomes 43.6 MHz after the intermediate frequency conversion, and the third harmonic 105.6 MHz at the time of receiving 105 MHz becomes 43.4 MHz after the intermediate frequency conversion, and both are 44 ± 3 MHz ( fo ± 3 MHz), and if the spurious signal level is large, it becomes an interference signal, which adversely affects the reception characteristics.
[0008]
Such a problem occurs because the spurious signal returns to the RF circuit of the tuner. In the past, this problem was addressed by devising the shield structure and ground pattern of the tuner, but these measures have become more difficult in the recent trend of miniaturization of tuners. ing.
[0009]
Note that the oscillation frequency of a crystal unit used in a PLL is generally lower than the oscillation frequency of a crystal unit used in a demodulation IC (eg, 4 MHz), so that a harmonic that is two to three times higher than the oscillation frequency enters the reception band. Never.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an improvement of a tuner device that does not adversely affect a reception characteristic even when a harmonic of a fundamental frequency of a crystal oscillator returns to an RF circuit as a spurious signal. It is intended to provide.
[0011]
[Means for Solving the Problems]
A tuner device of the present invention is a tuner device including a demodulation circuit, and a plurality of oscillation units that generate different oscillation frequencies to supply a system clock to the demodulation circuit, in order to solve the above problem, An oscillation selecting means for selecting one of the plurality of oscillating means according to a reception frequency and oscillating the same is provided. In the above tuner device, the number of the oscillating means may be two, and the oscillating selecting means may be configured to select any one of the oscillating means. In the above-described tuner device, the oscillating means may be a quartz oscillator.
[0012]
In the above configuration, even if the harmonic of the oscillation frequency generated by the oscillation unit returns to the input side of the tuner device, the oscillation selection unit selects the oscillation unit with the oscillation frequency such that the harmonic does not enter the reception band. By oscillating, it is possible to prevent a harmonic from becoming a spurious signal and hindering reception. In addition, by providing two oscillating means, when one of the oscillating means is affected by harmonics generated, the influence can be avoided by selecting the other oscillating means. If it is difficult to avoid the influence of harmonics by selecting one of the two oscillating means, an additional oscillating means may be provided.
[0013]
In the above tuner device, it is preferable that the oscillation selection means is a switching means for switching a connection of the oscillation means to the demodulation circuit in accordance with a switching signal. In such a configuration, the oscillation means can be easily selected by using the switching signal set according to the reception frequency.
[0014]
Further, in this tuner device, the demodulation circuit has a general-purpose I / O port, and outputs a high-level and a low-level voltage based on binary data for switching provided from outside. And a PLL circuit for outputting from the general-purpose I / O port or for controlling a local oscillation frequency. The PLL circuit has a general-purpose I / O port, and is provided with switching provided from outside. It is preferable that a high-level voltage and a low-level voltage are generated as the switching signal based on binary data for the above and output from the general-purpose I / O port. With such a configuration, it is not necessary to separately provide a circuit for generating a voltage as a switching signal.
[0015]
In any of the above tuner devices, it is preferable that the demodulation circuit is any of a QAM demodulation circuit, an OFDM demodulation circuit, a VSB demodulation circuit, a QPSK demodulation circuit, and an 8PSK demodulation circuit. As a result, a digital CATV tuner with a built-in QAM demodulation circuit as a demodulation circuit, a digital terrestrial tuner with a built-in OFDM demodulation circuit, a digital terrestrial tuner with a built-in VSB demodulation circuit, a digital satellite with a QPSK demodulation circuit or a 8PSK demodulation circuit built-in The present invention can be applied to a broadcast tuner.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS. Note that, in the tuner device of the present embodiment, components having functions equivalent to those of the above-described conventional tuner device shown in FIG. 6 are denoted by the same reference numerals.
[0017]
In the tuner device according to the present embodiment, as shown in FIG. 1, the input terminal 1, the high-pass filter 2, the RF amplifier 3, and the band-pass filter 4 are a mixer 5, a VCO (Voltage Controlled Oscillator) 6, a PLL-IC 7, It includes an IF amplifier 8, a demodulation IC 9, an output terminal 10, crystal oscillators 11 and 12, a switching circuit 13, and a control terminal 14.
[0018]
The high-pass filter 2 removes the low-frequency component of the 47 MHz to 862 MHz RF signal (high-frequency signal) input from the input terminal 1 and passes the high-frequency component. The RF amplifier 3 is a circuit that amplifies a signal from the high-pass filter 2 with a gain controlled based on an RF AGC signal generated by the demodulation IC 9. The band-pass filter 4 has a pass bandwidth substantially equal to the channel width, and limits the band of the signal from the RF amplifier 3.
[0019]
The mixer 5 is a circuit that converts an input signal into an IF signal (intermediate frequency signal) by mixing a local signal (having the oscillation frequency of the VCO 6) generated by the VCO 6 and an input signal that has passed through the band-pass filter 4. . The VCO 6 is a voltage-controlled oscillation circuit that generates the local signal.
[0020]
The PLL-IC 7 is an IC including a PLL (Phase Locked Loop) circuit that controls a local signal from the VCO 6 to match a plurality of frequency-divided signals generated based on a reference signal from a reference signal generator (not shown). is there. For this reason, the PLL-IC 7 controls the oscillation frequency (local oscillation frequency) of the VCO 6 to a value corresponding to the designated channel by adjusting the capacity of the tank circuit of the VCO 6.
[0021]
The IF amplifier 8 is a circuit that amplifies the IF signal from the mixer 5 with a gain controlled based on the IF AGC signal generated by the demodulation IC 9.
[0022]
The demodulation IC 9 detects and demodulates the IF signal from the IF amplifier 8 to output a demodulated signal, and based on the IF signal, an RF AGC control signal to be supplied to the RF amplifier 3 and an IF AGC to be supplied to the IF amplifier 8. This is an IC in which a demodulation circuit for generating a signal control signal is integrated. The demodulation IC 9 includes an A / D converter that converts an analog IF signal into a digital signal for digital processing. Further, a D / A converter for converting the generated both AGC control signals to analog is provided.
[0023]
The demodulation circuit integrated in the demodulation IC 9 includes a QAM (Quadrature Amplitude Modulation) demodulation circuit, an OFDM (Orthogonal Frequency Division Multiplexing) demodulation circuit, a VSB (Vestigial SideKampbank), and a VSB (Vestidal SideKamp). 8PSK (8 Phase Shift Keying) demodulation circuit.
[0024]
Further, crystal oscillators 11 and 12 as oscillation means are connected to the demodulation IC 9 via a switching circuit 13. The demodulation IC 9 has an oscillation circuit for generating a frequency signal (system clock) based on a constant frequency vibration of the quartz oscillators 11 and 12. An oscillator is configured. The system clock output from the crystal oscillator is provided to the above-described A / D converter, D / A converter, and the like.
[0025]
The quartz oscillators 11 and 12 as oscillating means generate oscillating frequencies different from each other. For example, when the demodulation IC 9 is a QAM demodulation IC of STV0297 (manufactured by ST Microelectronics), the oscillation frequency of the crystal oscillators 11 and 12 is set to 4/5 times the frequency of the IF signal input to the demodulation IC 9 and 4 times. / 9 times the frequency can be used. As in the case of the above-described prior art, when the receiving frequency RF is 47 MHz to 862 MHz, the intermediate frequency fo is 44 MHz, and the receiving bandwidth Bw is 6 MHz (fo ± 3 MHz) with the digital CATV tuner, the quartz oscillators 11 and 12 are used. A system clock frequency fc of 35.2 MHz and 19.556 MHz is obtained based on the two kinds of oscillation frequencies.
[0026]
As shown in FIG. 2, the switching circuit 13 as oscillation selection means includes diodes D1 and D2, resistors R1 to R6, and capacitors C1 and C2.
[0027]
The cathode of the diode D1 and the anode of the diode D2 are connected to one end of a resistor R1, and the other end of the resistor R1 is connected to one end of a resistor R2 and receives a switching signal H / L. The other end of the resistor R2 is connected to a power supply line for supplying a power supply voltage Vcc. A connection point between the resistor R1 and the diodes D1 and D2 is connected to a connection terminal Xout of the demodulation IC 9 via a capacitor C.
[0028]
The anode of the diode D1 is connected to the connection point of the resistors R3 and R4 connected in series. The other end of the resistor R3 is connected to the power supply line, and the other end of the resistor R4 is connected to a ground line. The connection point between the resistors R3 and R4 is connected to one end of the crystal unit 11 via the capacitor C1. On the other hand, the cathode of the diode D2 is connected to a connection point of the resistors R5 and R6 connected in series. The other end of the resistor R5 is connected to the power supply line, and the other end of the resistor R6 is connected to a ground line. The connection point between the resistors R5 and R6 is connected to one end of the crystal unit 12 via the capacitor C2.
[0029]
The other ends of the crystal units 11 and 12 are both connected to a connection terminal Xin of the demodulation IC. One end of each of the capacitors C3 and C4 is connected to both ends of the crystal unit 11, and the other end of each of the capacitors C3 and C4 is connected to the ground line. One end of each of the capacitors C5 and C6 is connected to both ends of the crystal unit 12, and the other end of each of the capacitors C5 and C6 is connected to the ground line. These capacitors C3 to C6 become a part of the oscillation circuit.
[0030]
When the switching signal H / L of “H” (high level) is input, the switching circuit 13 configured as described above allows the diode D2 to conduct while the diode D1 does not conduct. Select and connect to demodulation IC 9. On the other hand, when a switching signal H / L of “L” (low level) is input, the switching circuit 13 conducts the diode D1 and does not conduct the diode D2. Connect to
[0031]
The switching signal H / L is generated by a control signal generation circuit (not shown) based on control data “1” and “0” from a CPU provided outside the tuner device, for example, as shown in FIG. The signal is supplied to the switching circuit 13 via the control terminal 14 of the tuner device.
[0032]
In the tuner device configured as described above, one of the crystal unit 11 and the crystal unit 12 is selected by the switching circuit 13 and connected to the demodulation IC 9. The crystal oscillator 11 or the crystal oscillator 12 vibrates by being connected to the demodulation IC 9, and inside the demodulation IC 9, an oscillation circuit generates a system clock of the fundamental frequency generated by the crystal oscillator 11 or the crystal oscillator 12. Is done. In addition to the fundamental frequency, the crystal oscillators 11 and 12 generate harmonics such as twice and triple harmonics of the fundamental frequency.
[0033]
The switching circuit 13 is only required to be able to select the crystal oscillators 11 and 12 based on the switching signal H / L, and is not limited to the above configuration.
[0034]
In this tuner device, this harmonic wave goes to the RF circuit (high-pass filter 2, RF amplifier 3, band-pass filter 4) side, and after being converted to an intermediate frequency by the mixer 5, the intermediate of the received signal (RF signal) The crystal oscillator 11 or the crystal oscillator 12 is selected by the switching circuit 13 so as not to fall within the frequency band. As a result, it is possible to prevent higher harmonics of the fundamental frequency generated by the quartz oscillators 11 and 12 from entering the intermediate frequency band of the received signal as spurious signals after the intermediate frequency conversion. Therefore, in the tuner device, it is not necessary to improve the shield structure or the ground pattern for preventing such a spurious signal from entering, and the tuner device having good reception characteristics can be easily reduced in size.
[0035]
As described above, when two kinds of fundamental frequencies 35.2 MHz and 19.556 MHz by the crystal units 11 and 12 are used, the second harmonic of 19.556 MHz becomes 39.112 MHz and the third harmonic becomes 58. .668 MHz, and the 4th harmonic is 78.224 MHz. For example, when the receiving frequency is 70 MHz, after the 2nd and 3rd harmonics are converted to the intermediate frequency, 74.888 MHz, 18.556 MHz And does not enter 44 ± 3 MHz. On the other hand, the 2nd harmonic of 35.2 MHz becomes 70.4 MHz, the 3rd harmonic becomes 105.6 MHz, and the 4th harmonic becomes 140.8 MHz. For example, when the receiving frequency is 105 MHz, it becomes 2 times. , 3 times, and 2 times higher harmonics are converted to intermediate frequencies, then become 109.888 MHz, 90.332 MHz, 70.776 MHz, and do not enter 44 ± 3 MHz.
[0036]
[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. In the tuner device of the present embodiment, components having the same functions as the components of the tuner device shown in FIG. 1 are denoted by the same reference numerals.
[0037]
As shown in FIG. 3, the tuner device according to the present embodiment includes a mixer 5, a VCO 6, a PLL, and an input terminal 1, a high-pass filter 2, an RF amplifier 3, and a band-pass filter 4, similarly to the tuner device shown in FIG. -IC 7, IF amplifier 8, demodulation IC 9, output terminal 10, crystal oscillators 11 and 12, switching circuit 13 and control terminal 14. This tuner device differs from the tuner device of FIG. 1 in that a switching signal H / L is supplied from the demodulation IC 9 to the switching circuit 13.
[0038]
As shown in FIG. 4, the demodulation IC 9 has, as a terminal T, a general-purpose I / O port that can be used freely by a user. The general-purpose I / O port of the demodulation IC 9 is controlled by writing data transmitted from a CPU provided in a receiver having a built-in tuner device via an I2C bus (or a 3-Wire bus). Specifically, the demodulation IC 9 writes “1” or “0” as the above data in the bit allocated for controlling the general-purpose I / O port to be used in the write data format, so that the terminal T Is switched to “H” or “L”. At this time, the demodulation circuit IC9 reads a high-level voltage or a low-level voltage in the I2C read mode.
[0039]
The tuner device controls the switching circuit 13 using the output of the terminal T as the switching signal H / L.
[0040]
As shown in FIG. 5, another tuner device according to the present embodiment includes an input terminal 1, a high-pass filter 2, an RF amplifier 3, and a band-pass filter 4 similar to the tuner device shown in FIG. , A PLL-IC 7, an IF amplifier 8, a demodulation IC 9, an output terminal 10, crystal oscillators 11 and 12, a switching circuit 13, and a control terminal 14. This tuner device differs from the tuner device of FIG. 1 in that a switching signal H / L is supplied from the PLL-IC 7 to the switching circuit 13.
[0041]
As shown in FIG. 5, the PLL-IC 7 has a general-purpose I / O port as a terminal S that can be freely used by a user. The general-purpose I / O port of the PLL-IC 7 is controlled by writing data transmitted from the CPU via the I2C bus (or 3-Wire bus). Specifically, the PLL-IC 7 writes “1” or “0” as the above data in the bit allocated for controlling the general-purpose I / O port to be used in the write data format, similarly to the demodulation IC 9. As a result, the output of the terminal T is switched to “H” or “L”. At this time, the PLL-IC 7 reads a high-level voltage or a low-level voltage in the I2C read mode.
[0042]
The tuner device controls the switching circuit 13 using the output of the terminal S as the switching signal H / L.
[0043]
In the above two tuners, the switching signal H / L is generated by software using the general-purpose I / O ports of the demodulation IC 9 and the PLL-IC 7. Accordingly, it is not necessary to separately provide a dedicated circuit for generating the switching signal H / L (the voltage of “H” and “L”) as in the tuner device of FIG. 1, and the cost of the tuner device can be reduced. Can be.
[0044]
In the first and second embodiments, examples in which two crystal units 11 and 12 are used have been described. This is because, when one of the quartz oscillators 11 and 12 is affected by harmonics generated, the influence can be avoided as described above by selecting the other. The present invention is not limited to this, and if it is difficult to avoid the influence of harmonics even if one of the two crystal oscillators is selected, the switching circuit 13 may be provided using three or more crystal oscillators. , One of the quartz oscillators may be selected. In this case, in order to switch the crystal oscillators by software as in the present embodiment, one transistor is connected between one end of each crystal oscillator and the demodulation IC 9, and the data is not binary data. For example, the decoder decodes data of the number of bits corresponding to the number of crystal oscillators from the CPU and turns on the transistor with the decoded signal, thereby connecting only one crystal oscillator to the demodulation IC 9.
[0045]
Further, in both embodiments, a quartz oscillator is used, but the present invention is not limited to this, and a ceramic oscillator may be used. Further, a CR oscillator or an LR oscillator may be used as the oscillator, but it is most preferable to use a crystal oscillator from the viewpoint of frequency stability and face noise.
[0046]
【The invention's effect】
As described above, the tuner device of the present invention includes a demodulation circuit, a plurality of oscillation units that generate different oscillation frequencies for supplying a system clock to the demodulation circuit, and a plurality of the oscillation units according to a reception frequency. Oscillation selecting means for selecting one of the above and oscillating.
[0047]
Thereby, even if the harmonic of the oscillation frequency generated by the oscillation unit returns to the input side of the tuner device, the oscillation selection unit selects the oscillation unit with the oscillation frequency such that the harmonic does not enter the reception band. It is possible to prevent the harmonics from becoming spurious signals and disturbing reception. Therefore, it is not necessary to devise a shield structure or a ground pattern for preventing harmonics of the oscillation frequency from entering the reception band. It has the effect of being able to do it.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a tuner device according to Embodiment 1 of the present invention.
FIG. 2 is a block diagram showing a configuration of a switching circuit in the tuner device of FIG.
FIG. 3 is a block diagram showing a configuration of a tuner device according to Embodiment 2 of the present invention.
FIG. 4 is a block diagram illustrating a configuration of a switching circuit in the tuner device of FIG. 3;
FIG. 5 is a block diagram showing a configuration of a tuner device according to Embodiment 2 of the present invention.
FIG. 6 is a block diagram showing a configuration of a conventional tuner device.
[Explanation of symbols]
7 PLL-IC (PLL circuit)
9 Demodulation IC (demodulation circuit)
11,12 crystal oscillator (oscillation means)
13 Switching means H / L Switching signal S, T terminal (general purpose I / O port)

Claims (11)

A tuner device comprising: a demodulation circuit; and a plurality of oscillating units that generate different oscillation frequencies to supply a system clock to the demodulation circuit,
A tuner device comprising: oscillation selection means for selecting one of the plurality of oscillation means and oscillating according to a reception frequency. 2. The tuner device according to claim 1, wherein the number of the oscillating means is two, and the oscillating selecting means selects one of the oscillating means. 3. The tuner device according to claim 1, wherein said oscillating means includes a quartz oscillator. 4. The tuner device according to claim 1, wherein the oscillation selection unit is a switching unit that switches connection of the oscillation unit to the demodulation circuit according to a switching signal. 5. The demodulation circuit has a general-purpose I / O port, generates a high-level voltage and a low-level voltage as the switching signal based on binary data for externally supplied switching, and 5. The tuner device according to claim 4, wherein the signal is output from an / O port. A PLL circuit for controlling a local oscillation frequency;
The PLL circuit has a general-purpose I / O port, generates a high-level voltage and a low-level voltage as the switching signal based on binary data for externally supplied switching, and generates the general-purpose I / O port. 5. The tuner device according to claim 4, wherein the signal is output from an / O port. 7. The tuner device according to claim 1, wherein the demodulation circuit is a QAM demodulation circuit. The tuner device according to any one of claims 1 to 6, wherein the demodulation circuit is an OFDM demodulation circuit. The tuner device according to any one of claims 1 to 6, wherein the demodulation circuit is a VSB demodulation circuit. The tuner device according to claim 1, wherein the demodulation circuit is a QPSK demodulation circuit. The tuner device according to any one of claims 1 to 6, wherein the demodulation circuit is an 8PSK demodulation circuit.

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