JP2008103076A - Semiconductor nonvolatile memory with partial data rewrite function - Google Patents

Abstract

To partially rewrite written data without erasing.
In a semiconductor non-volatile memory in which a rewriting operation for changing a part of already written data is performed in a simple manner without an erasing operation, a flag indicating whether data before rewriting or data after rewriting is valid is set. A valid data storage unit for storing data, and when the first flag for validating the data before rewriting is stored in the valid data storage unit during the read operation, the data corresponding to the supplied read address is stored When a second flag for reading from the main memory cell array and validating the rewritten data is stored in the valid data storage unit, when the read address matches the first address of the correspondence information, the corresponding first flag is stored. 2 address data is read from the sub-memory cell array, and when there is no match, the read address data is read from the main memory It is read from Ruarei.
[Selection] Figure 12

Description

  The present invention relates to a semiconductor nonvolatile memory such as a flash memory, and more particularly to a semiconductor nonvolatile memory capable of rewriting a part of data without an erasing operation.

  A semiconductor non-volatile memory such as a flash memory is composed of a memory cell including a transistor having a floating gate and a trap gate. The state in which charge is not injected into the floating gate or trap gate is the erased state (data 1), and the state in which charge is injected into them is the programmed state (data 0). In the erased state, the threshold voltage of the cell transistor is low and the programmed state Then, the threshold voltage becomes high. Data “1” is changed to data “0” by a write operation (or program operation) for injecting charges into a floating gate or the like, and data “0” is changed to data “1” by an erase operation for extracting or neutralizing charges. Change to

  FIG. 1 is a configuration diagram of a conventional nonvolatile memory. The memory device 100 includes a memory cell array 10, a row decoder 12, a column decoder 14, and a data input / output circuit 16. The memory cell array 10 is composed of a plurality of blocks each having a plurality of memory cells. In such a nonvolatile memory, write data is written at a specified address in a write operation, and is changed to an erase state all at once in a block unit in an erase operation.

  FIG. 2 is a flowchart of a write operation of a conventional nonvolatile memory. First, an address ADD and write data DA are input from the outside together with a write command (S1), and the decoders 12 and 16 select a word line or bit line (not shown) according to the address ADD, and the selected word line and bit line are selected. Write data is written to the memory cell at the intersection (S6). After the data write operation, if it is confirmed that the data in the memory matches the write data (S2), the write operation ends normally (S3). If the data is not confirmed, the write count reaches the predetermined number ( S4), the write operation S6 is repeated. If the number of times of writing exceeds the predetermined number of times (S4), the writing is abnormally terminated (S5).

  As described above, in the flash memory, data is written in the memory cell corresponding to the address. That is, the unit of writing is a 1-bit memory cell selected by an address, or a memory cell group of 1 byte or 1 word selected by an address. Alternatively, it is a memory cell group in units of word lines selected by an address. The write operation is performed by changing the memory cell in the erased state (data 1) to data “0”. On the other hand, the erase unit is performed in units of blocks (or sectors) or chips each having a plurality of write unit memory cells. Specifically, in the erase operation, after all the memory cells in the block to be erased are set to the programmed state (data 0), all the memory cells are simultaneously changed to the erased state (data 1). The same applies to erasing in units of chips.

  A program and predetermined data are written in the flash memory. Thereafter, when it is desired to change only a part of the written program or data, it is necessary to erase the memory block and rewrite all the partly changed program or data. In other words, since only erasing can be performed in units of blocks, even if only a part of data in a block is changed, all data in that block must be erased and all data including the part that has not changed must be rewritten. .

  Therefore, when a partial rewrite request occurs, in a conventional nonvolatile memory, it is necessary to erase the memory block in which the data to be rewritten is recorded and rewrite the new partially rewritten data. The rewriting process becomes complicated, and it takes a long time for rewriting, and the number of erasures increases. Even if only a part of the data is rewritten, the need for erasing and writing as described above impairs the convenience of the user.

  Accordingly, an object of the present invention is to provide a semiconductor nonvolatile memory having a partially rewriting function.

  It is a further object of the present invention to provide a semiconductor nonvolatile memory that enables partial modification of written data without memory block erasure or chip erasure.

  In order to achieve the above object, according to one aspect of the present invention, a semiconductor nonvolatile memory includes a main memory cell array and a sub memory cell array, and changes a part of data written in the main memory cell array. Without writing to the main memory cell array, the change data is written to the sub memory cell array, the first address of the main memory cell array in which the change target data is stored, and the second address of the sub memory cell array in which the change data is stored The information corresponding to the address is recorded. At the time of reading, the read address is compared with the first address of the correspondence information. If they match, the data in the sub-memory cell array at the second address corresponding to the first address is read. Reads data in the main memory cell array corresponding to the read address.

  According to the above invention, when only a part of the already written data is changed, the changed data is written into the sub memory cell array without erasing the memory block, and the first data of the main memory cell array of the change target data is written. Correspondence information between the address and the second address of the sub memory cell array in which the change data is stored is recorded. Therefore, since only the change data needs to be written into the sub memory cell array, the rewriting operation is simple and performed at high speed. In addition, an increase in the number of erases can be suppressed.

In the above aspect of the present invention, in a more preferred embodiment, the erase-unit memory block has a main memory cell array and a sub memory cell array, and when the memory block is erased, not only the main memory cell array but also the sub memory The cell array is also erased at the same time. Therefore, when the main memory cell array is in the erased state, the sub memory cell array is also in the erased state, and the rewriting function can be used again.

  As described above, according to the present invention, in a semiconductor nonvolatile memory, a rewriting operation for changing a part of already written data can be performed by a simple method without an erasing operation.

  Embodiments of the present invention will be described below with reference to the drawings. However, the protection scope of the present invention is not limited to the following embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 3 is a configuration diagram of the nonvolatile memory in the present embodiment. In this nonvolatile memory device (hereinafter referred to as a flash memory device as an example) 100, a memory cell array is composed of a main memory cell array 10 and a sub memory cell array 20. The memory blocks MB0 and MB1, which are erase units, have the main memory cell array 10 and the sub memory cell array 20, respectively. In this example, the sub memory cell array 20 is provided in the row direction. Similarly to the conventional example, the flash memory device 100 includes a row decoder 12, a column decoder 14, a data input / output circuit 16, and a control circuit (not shown) that controls writing, erasing, and reading in response to commands. ).

  The flash memory device 100 of FIG. 3 further shows correspondence information between the first address of the main memory cell array in which the data to be changed is stored at the time of rewriting and the second address of the sub memory cell array in which the changed data is stored. An address management circuit that compares the address storage unit 22 to be stored, writes the correspondence information into the address storage unit 22 at the time of writing, and compares the read address ADD supplied from the outside at the time of reading with the first address in the address storage unit 22 24.

  A rewrite operation in the flash memory device 100 will be described. Initially, the memory block has been erased, and both the main memory cell array 10 and the sub memory cell array 20 in the memory block are in an erased state. Then, predetermined data such as a program or a database is written in the erased main memory cell array 10. More precisely, when the data to be written is “0”, the cell transistor is changed from the erased state of data “1” to the programmed state of data “0”, and when the data to be written is “1”. The erased state is maintained.

  Next, when it is desired to rewrite only a part of the written data, the changed data is written to the sub-memory cell array 20 without erasing all the memory blocks in which the data is written as in the prior art. Correspondence information between the first address of the main memory cell array 10 in which the target data is stored and the second address of the sub memory cell array 20 in which the change data is stored is written in the address storage unit 22.

  FIG. 5 is a diagram showing a unit selected by an address in the memory cell array. As shown in FIG. 5, when the address ADD is decoded, the selected word line WL is driven. Therefore, a plurality of memory cells are selected in the row direction. However, the number of bits output at the same time depends on the configuration of the memory cell array. For example, an 8-bit or 16-bit access unit is selected and accessed for one address. This access unit is shown as an ellipse in FIG.

  In the above rewrite operation, the data D1 to be rewritten belonging to the word line WL in the main memory cell array 10 is maintained as it is in the main memory cell array, and the newly rewritten data D2 is stored in the word line SWL in the sub memory cell array 20. Is written in the memory cell of the access unit belonging to. Therefore, the address storage unit 22 stores correspondence information between the row address of the main memory cell array and the row address of the sub memory cell array.

  FIG. 6 is a diagram showing a specific configuration of the address storage unit 22. The address storage unit 22 records correspondence information between the first address ADD of the main memory cell array and the second address SADD of the sub memory cell array. In the example of FIG. 6, the address SADD of the sub memory cell array has eight addresses “000” to “111”, and each time change data is written to the sub memory cell array due to rewriting, Addresses ADD1 and ADD2 are written in the address storage unit 22 in order.

  In other words, in the rewrite operation, the address ADD of the data to be changed and the changed data are supplied to the memory device 100 together with the write command. Then, the address management circuit 24 writes the supply address ADD in the address storage unit 22 and outputs the corresponding address SADD in the sub memory cell array to the decoder 12. Accordingly, change data is written into the sub memory cell array 20.

  FIG. 7 is a flowchart of the read operation. In the read operation, an address to be read is input (S1). Accordingly, the address management circuit 24 compares the read address with the first address of the main memory cell array in the address storage unit 22 (S2). If they do not match, the address management circuit 24 outputs the supplied read address as it is to the decoder 12 and outputs the data in the main memory cell array 10 (S3, S5, S6). On the other hand, if they match, the read address data has been rewritten, and the address management circuit 24 outputs the address SADD of the sub memory cell array corresponding to the read address to the decoder 12. Thereby, the change data in the sub memory cell array is output (S4, S5, S6).

  As long as there are writable memory cells in the sub-memory cell array 20, the above-described rewrite operation can be performed. When the sub memory cell array 20 is completely written, the rewriting operation can no longer be performed. Therefore, in that case, a write error occurs and the memory block MB is erased. As a result of this erase operation, both the main memory cell array 10 and the sub memory cell array 20 in the memory block are erased. Therefore, after that, the rewriting operation using the sub memory cell array becomes possible again. During this erasing operation, the first address in the address storage unit is also erased.

  FIG. 4 is a configuration diagram of another nonvolatile memory according to the present embodiment. In this example, the sub memory cell array 20 is provided in the column direction. Therefore, in this example, correspondence information between the first column address of the main memory cell array in which the data to be changed is stored and the second column address of the sub memory cell array in which the change data is stored is the address storage unit. 22 is recorded. Then, the address management circuit 24 compares the column addresses and appropriately outputs the column address of the sub memory cell array to the decoder 14 in accordance with the correspondence information in the address storage unit 22.

  3 and 4 may be provided at the same time. In this case, the address storage unit needs to store correspondence information for both the row address and the column address.

  As described above, in this embodiment, a rewrite operation for changing a part of already written data is performed only on data to be changed in the sub-memory cell array without erasing operation and rewriting of data that does not need to be changed. It can be done simply by writing. Therefore, in the rewrite operation, the rewrite operation can be apparently performed only by giving the write command, the address of the data to be rewritten, and the change data from the outside.

  The rewrite operation can be performed in a special mode that is different from the normal write operation or in the same mode as the normal write operation.

  FIG. 8 is a configuration diagram of a nonvolatile memory device that performs a rewrite operation in a special mode. In the figure, the same reference numerals are given to the same components as in FIG. A configuration different from the memory device of FIG. 3 is a rewrite mode determination circuit 26. When a high voltage different from the normal operation is applied to a predetermined external pin or a rewrite mode command is supplied, the rewrite mode determination circuit 26 detects the mode and indicates that the address management circuit 24 has entered the rewrite mode. Notice.

  FIG. 9 is a flowchart of the write operation of the nonvolatile memory device of FIG. A normal writing operation is shown on the left side, and a rewriting operation for partial modification is shown on the right side. Each step S10 to S15 of the normal write operation is the same as the conventional write operation shown in FIG. That is, when the write address and the write data are supplied together with the write command (S10), the data write process S13 is repeated until the write data is written in the main memory cell array 10. If the written data matches the written data, the process ends normally (S14). If the writing is not completed even after the number of writing processes exceeds the predetermined number of times, it is assumed that some defect has occurred, and a writing error is output (S15).

  Next, when performing a rewrite operation, a rewrite mode is entered by applying a voltage higher than normal to a predetermined external terminal or inputting a predetermined rewrite mode command (S18). This mode determination is performed by the rewrite mode determination circuit 26. When the rewrite mode is detected, the address management circuit 24 is notified of it.

  Thereafter, the first address of the main memory cell array storing the data to be changed and the changed data are supplied together with the write command (S20). The address management circuit 24 detects the second address of the writable sub memory cell array in the address storage unit 22 and writes the supplied first address to the address storage unit 22 in correspondence with the second address. . Then, the address management circuit 24 outputs the second address to the decoder 12 and writes the change data to the second address of the sub memory cell array 20 (S23). This writing process is repeated until the write data is written in the sub memory cell array 20 and the first address is written in the address storage unit 22 (S21). If the writing process is completed, the process ends normally (S24). If the write process exceeds the predetermined number, the process ends abnormally (S25).

  As described above, in the memory device of FIG. 8, when a part of data is changed, the rewrite mode is once entered, and thereafter, the address of the data to be changed and the changed data are supplied in the same manner as the normal write operation. Accordingly, data to be changed is written into the sub memory cell array 20.

  FIG. 10 is a configuration diagram of a nonvolatile memory device that automatically performs a rewrite operation. FIG. 11 is a flowchart of the write operation. This memory device is provided with a rewrite determination circuit 28, and the rewrite determination circuit 28 determines whether or not write data should be written to the sub memory cell array.

  When the write address ADD and the write data DA are supplied together with the write command, the rewrite determination circuit 28 reads the data of the write address ADD of the main memory cell array 10 and determines whether or not the write data DA can be written to the address. To check. In this determination, the read data and the write data are compared to check whether there is a bit that needs to be changed from data “0” to data “1”. That is, it is checked whether or not an erase operation is necessary.

  The write operation is a change from data “1” in the erased state to data “0” in the programmed state. On the other hand, the erase operation performed in units of memory blocks is an operation for setting all memory cells to data “1”.

  When there is a bit that needs to be changed from data “0” to data “1”, the supplied write data cannot be written to the main memory cell array. Therefore, in this case, it is determined as a rewrite operation, and it is necessary to write the write data to the sub memory cell array. On the other hand, when the data is compared and only the bit that needs to be changed from data “1” to data “0” and the bit that does not need to be changed are written, the write data can be written to the main memory cell array. Is possible. Such a situation is typically the case when the main memory cell array is in an erased state. In some rare cases, such a situation may occur once writing has been performed.

  The write operation will be described with reference to the flowchart of FIG. The user supplies a write address ADD and write data DA together with a normal write command to the memory device (S10). Therefore, except for the case where the data at the write address of the main memory cell array matches the write data (S11), the rewrite determination circuit 28 performs the above data comparison determination. If the main memory cell array is in an erased state or a combination of data that can be written accidentally, writing to the main memory cell array 10 is executed in steps S12, S13, and S11.

  When the rewrite determination circuit 28 determines that some data has already been written to the write address of the main memory cell array 10 and cannot be rewritten to the write data in that state, the rewrite operation in steps S21 to S25 is executed. Steps S21 to S25 are the same as the rewrite operation described in FIG. That is, the address management circuit 24 supplies the second address of the sub memory cell array to the decoder 14 instead of the supplied first address of the main memory cell array 10, and the first address corresponding to the second address. Are written in the address storage unit 22. The supplied write data is written to the second address of the sub memory cell array 20 as change data.

  In the nonvolatile memory device of FIGS. 8 and 10, the read operation is the same as the operation shown in FIG. That is, the address management circuit 22 detects whether the read address supplied together with the normal read command matches the first address in the address storage unit 22. If they match, the second address corresponding to the first address is supplied to the decoder 12 and the data at the second address in the sub memory cell array 20 is read out. In the case of mismatch, data is read from the main memory cell array 10 according to the supplied read address.

  In the nonvolatile memory device of FIGS. 8 and 10, the erase operation is the same as that in FIGS. That is, when the main memory cell array 10 is erased, the sub memory cell arrays belonging to the memory block are also erased. Even if there is no free space in the sub memory cell array due to this erasing operation, after that, a rewriting operation with partial data change becomes possible using the sub memory cell array.

  FIG. 12 is a configuration diagram of a nonvolatile memory device according to another embodiment. Like the above embodiment, this memory device has a rewriting function with partial data change, and valid data selection that can validate either original data before rewriting or rewritten data after rewriting. It has a function. For this purpose, the valid data storage unit 30 is provided, and a valid flag indicating whether the original data or the rewritten data is validated is stored in the valid data storage unit 30.

  When the flag for validating the original data is written, the original data in the main memory cell array 10 is read in the read operation. When a flag for validating the rewrite data is written, the data in the sub memory cell array 20 is appropriately read out by the address management circuit 24 instead of the data in the main memory cell array.

  FIG. 13 is a flowchart of the read operation of the memory device of FIG. In this read operation, unlike the read operation in FIG. 7, when a read address is input together with a read command (S1), the address management circuit 24 checks the valid flag stored in the valid data storage unit 30 and validates it. It is detected whether the data is original data or rewritten data (S40). This step S40 is different from the flowchart of FIG.

  When the valid data is the data after rewriting, the address management circuit 24 compares the supplied read address with the first address stored in the address storage unit 22 as in FIG. At that time, the second address corresponding to the second address is output to read the change data in the sub memory cell array. If they do not match, the data in the main memory cell array corresponding to the first address is read. Therefore, when there is rewrite data, the data is read, and when there is no rewrite data, the original data is read.

  When the valid data is original data, the address management circuit 24 supplies the supplied read address to the decoder 12 as it is to read data in the main memory cell array. Therefore, even when there is rewrite data, the original data is forcibly read from the main memory cell array.

  As described above, the memory device of the present embodiment writes the changed data to the sub memory cell array 20 without erasing the original data during the rewriting operation. Therefore, both the original data and the rewritten data are recorded. Therefore, as described above, by setting a flag indicating which valid data is to be used in the valid data storage unit 30, any one of the data can be read out. Therefore, in program development, this function can be used when debugging by comparing an original program with a partially modified program.

  In the above embodiment, only one type of rewrite data can be rewritten. That is, original data is written in the main memory cell array, and a changed portion (rewrite data) of the original data is written in the sub memory cell array. Therefore, by providing a plurality of sets of sub memory cell arrays, the rewrite data can be converted into a plurality of versions. That is, the original data is written in the main memory cell array, and the first version of rewrite data is written in the first sub memory cell array. Also, the second version of the rewrite data is written into the second sub memory cell array. Then, any data can be read by recording in the valid data storage unit 20 a flag indicating whether the original data or the rewritten data of the first version or the second version should be validated. In that case, it is necessary to record the address correspondence information of the first version and the second version in the address storage unit 22 separately.

  Thus, in order to easily write a plurality of versions of rewrite data by a rewrite operation, it is necessary to provide a plurality of sets of sub memory cell arrays. However, by limiting the amount of change data that accompanies rewriting, the capacity of the sub memory cell array can be reduced. Therefore, even if a plurality of versions can be rewritten as described above, the capacity of the sub memory cell array does not become extremely large accordingly.

The exemplary embodiments are summarized as follows.
(Appendix 1) In a semiconductor nonvolatile memory,
A main memory cell array;
A sub-memory cell array;
An address storage unit,
In the case of a rewrite operation for changing a part of data written in the main memory cell array, the main memory in which change data is written to the sub memory cell array without erasing the main memory cell array. A semiconductor nonvolatile memory, wherein correspondence information between a first address of a cell array and a second address of the sub-memory cell array in which the change data is stored is recorded in the address storage unit.
(Appendix 2) In Appendix 1,
Further, at the time of read operation, the read address is compared with the first address of the correspondence information, and when it does not match, the read address is output, and when it matches, the second address of the correspondence information is output A semiconductor nonvolatile memory comprising a management circuit.
(Appendix 3) In Appendix 1,
Furthermore, it has a rewrite mode determination circuit that detects the rewrite operation mode in response to an external signal,
When the rewrite operation mode is detected, the semiconductor nonvolatile memory is characterized in that the change data is written into a sub-memory cell array and the correspondence information is recorded in the address storage unit.
(Appendix 4) In Appendix 1,
Further, the write data can be written to the main memory cell array by comparing the write data with the data in the main memory cell array corresponding to the write address in response to the supplied write data and write address. If the write data supplied to the main memory cell array is written, and the write data cannot be written to the main memory cell array, the supplied write data is written to the sub memory cell array. Is recorded in the address storage unit.
(Appendix 5) In Appendix 1,
A memory block having the main memory cell array and the sub memory cell array;
A semiconductor nonvolatile memory, wherein the main memory cell array and the sub memory cell array in the memory block are erased together during an erase operation.
(Appendix 6) In Appendix 5,
A plurality of the memory blocks;
A semiconductor nonvolatile memory, wherein selected memory blocks are erased all at once during an erasing operation.
(Appendix 7) In Appendix 1,
In the erase operation,
A semiconductor nonvolatile memory, wherein memory cells in the main memory cell array are erased all at once.
(Appendix 8) In Appendix 1,
Furthermore, it has an effective data storage unit for storing a flag indicating which of the data before rewriting and the data after rewriting is valid,
During a read operation, when the first flag for validating the data before rewriting is stored in the valid data storage unit, the data corresponding to the supplied read address is read from the main memory cell array,
When the second flag for validating the rewritten data is stored in the valid data storage unit, when the read address matches the first address of the correspondence information, the second flag corresponding to the second address is stored. A non-volatile semiconductor memory characterized in that address data is read from the sub-memory cell array and read address data is read from the main memory cell array when they do not match.
(Supplementary note 9) In a semiconductor nonvolatile memory,
A main memory cell array in which all memory cells are erased by an erase operation, and first data is written in the erase state;
A sub-memory cell array in which the second data to be changed is written in a rewrite operation for changing a part of the first data written in the main memory cell array to the second data;
When the second data is written to the sub memory cell array, a first address of the main memory cell array in which data to be changed is stored and a second address of the sub memory cell array in which the second data is stored A semiconductor nonvolatile memory comprising: an address storage unit that stores correspondence information with an address.
(Appendix 10) In Appendix 9,
Further, at the time of read operation, the read address is compared with the first address of the correspondence information, and when there is a mismatch, the first data corresponding to the read address is output, and when there is a match, the correspondence information A semiconductor non-volatile memory that outputs the second data corresponding to a second address.
(Appendix 11) In Appendix 9,
Furthermore, it has a rewrite mode determination circuit that detects the rewrite operation mode in response to an external signal,
When the rewrite operation mode is detected, the semiconductor nonvolatile memory is characterized in that the second data is written into the sub-memory cell array and the correspondence information is recorded in the address storage unit.
(Appendix 12) In Appendix 9,
Further, in response to the supplied write data and write address, the data in the main memory cell array corresponding to the write address is compared with the write data, and the second data is written into the main memory cell array. When possible, the supplied second data is written into the main memory cell array, and when the second data cannot be written into the main memory cell array, the supplied second data is supplied to the sub memory cell array. A non-volatile semiconductor memory, wherein the correspondence information is recorded in the address storage unit.
(Appendix 13) In Appendix 9,
A memory block having the main memory cell array and the sub memory cell array;
A semiconductor nonvolatile memory, wherein the main memory cell array and the sub memory cell array in the memory block are erased together during an erase operation.
(Appendix 14) In Appendix 9,
And a valid data storage unit for storing a flag indicating whether the first data or the second data is valid.
During the read operation, when the first flag for validating the first data is stored in the valid data storage unit, the first data corresponding to the supplied read address is read from the main memory cell array. When the second flag for validating the second data is stored in the valid data storage unit, the second address corresponding to the second address when the read address matches the first address of the correspondence information The semiconductor non-volatile memory, wherein the second data at the address is read from the sub-memory cell array, and the first data corresponding to the read address is read from the main memory cell array when they do not match.

It is a block diagram of the conventional non-volatile memory. It is a flowchart figure of the write-in operation | movement of the conventional non-volatile memory. It is a block diagram of the non-volatile memory in this Embodiment. It is a block diagram of another non-volatile memory in this Embodiment. It is a figure which shows the unit selected by the address in a memory cell array. 3 is a diagram illustrating a specific configuration of an address storage unit 22. FIG. It is a flowchart figure of read-out operation. It is a block diagram of a non-volatile memory device that performs a rewrite operation in a special mode. FIG. 9 is a flowchart of a write operation of the nonvolatile memory device of FIG. 8. It is a block diagram of a non-volatile memory device that automatically performs a rewrite operation. FIG. 11 is a flowchart of a write operation of the nonvolatile memory device of FIG. 10. It is a block diagram of the non-volatile memory device in another embodiment. FIG. 13 is a flowchart of a read operation of the memory device of FIG. 12.

Explanation of symbols

10 Main memory cell array 20 Sub memory cell array 22 Address storage unit 24 Address management circuit 26 Rewrite mode determination circuit 28 Rewrite determination circuit 30 Valid data storage unit MB0, MB1 Memory block

Claims (1)

A semiconductor non-volatile memory,
A main memory cell array;
A sub-memory cell array;
An address storage unit,
In the case of a rewrite operation for changing a part of data written in the main memory cell array, the main memory in which change data is written to the sub memory cell array without erasing the main memory cell array. In a semiconductor nonvolatile memory that records correspondence information between a first address of a cell array and a second address of the sub-memory cell array in which the change data is stored in the address storage unit,
Furthermore, it has an effective data storage unit for storing a flag indicating which of the data before rewriting and the data after rewriting is valid,
During a read operation, when the first flag for validating the data before rewriting is stored in the valid data storage unit, the data corresponding to the supplied read address is read from the main memory cell array,
When the second flag for validating the rewritten data is stored in the valid data storage unit, when the read address matches the first address of the correspondence information, the second flag corresponding to the second address is stored. A non-volatile semiconductor memory characterized in that address data is read from the sub-memory cell array and read address data is read from the main memory cell array when they do not match.

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