JP2006004478A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of preventing loss of initial setting data and performing rewriting in a short time.
A nonvolatile semiconductor memory device includes a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, and the same initial setting data is stored in at least two areas, and the memory cell array. A sense amplifier circuit for reading data, an initial setting data register for transferring and holding initial setting data read from the memory cell array to the sense amplifier circuit, and for defining a memory operating condition, and one command A controller for performing sequence control for sequentially rewriting initial setting data stored in the first and second areas of the memory cell array in accordance with the input.
[Selection] Figure 1

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM having an initial setting data storage area in a memory cell array.

  In a large-scale semiconductor memory, a redundant circuit system is usually used to repair a defective chip. That is, a redundant cell array is prepared as the memory cell array, and a fuse circuit for programming defective address information found by the wafer test is also prepared. When the fuse circuit is programmed, when a defective address is input, control is performed to automatically replace the defective column or defective row with the redundant column or redundant row by detecting coincidence with the defective address held by the fuse circuit.

  The fuse circuit is used for storing various initial setting data for determining the operation condition of the memory in addition to the defective address information as described above. The same applies to the EEPROM.

  However, once the fuse circuit is programmed, it cannot be undone. In view of this, as an initial setting data storage circuit that replaces the fuse circuit, a method using an electrically rewritable nonvolatile memory cell that is the same as an EEPROM memory cell is also used.

  In particular, the method of setting the initial setting data storage area in the EEPROM memory cell array has advantages that the circuit configuration is simple and that verification and correction are easy (see Patent Document 1). In Patent Document 1, it is also proposed to store initial setting data as a set of data having a complementary relationship. This is preferable for confirming and securing the validity of the initial setting data.

  Initial setting data written in the memory cell array is automatically read when the power is turned on, transferred to the initial setting data register, and held. Thereafter, the memory operates under operating conditions defined by the data held in the initial setting data register.

Furthermore, in order to make the initial setting data more reliable, a method of storing the same initial setting data in a plurality of blocks in the memory cell array has been proposed (see Patent Document 2). As a result, even if the initial setting data stored in one block is destroyed, the operation conditions of the flash memory can be set because another block has the same initial setting data.
JP 2001-176290 A Japanese Patent Application Laid-Open No. 2002-117692

  A method of storing the initial setting data in the memory cell array is preferable because the initial setting data can be easily verified or rewritten. In particular, it is convenient for the user that part of the initial setting data can be rewritten by the user.

  However, it takes time and effort to rewrite the initial setting data stored in a plurality of blocks in an independent sequence. Write data for one page loaded in the sense amplifier circuit is written in a lump. For example, if one page is composed of 8 × 66 bits and has eight input / output terminals, the write data for one page is written. Input requires 66 serial data inputs. If such serial data must be input for each page write for a plurality of blocks, a very long rewrite time is required.

  On the other hand, when initial setting data of a plurality of blocks is rewritten at once, destruction of the initial setting data becomes a problem. After erasing all of these blocks, the initial setting data will be lost if the power is cut off or the flash memory is removed from the system while writing new initial setting data. End up. In this case, even if the power is turned on again, the basic memory operation conditions are not initialized, and thereafter normal memory operation cannot be performed.

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can prevent the initial setting data from being lost and can be rewritten in a short time.

A nonvolatile semiconductor memory device according to one aspect of the present invention is provided.
A memory cell array in which electrically rewritable nonvolatile memory cells are arranged, and the same initial setting data is stored in at least two regions of the first and second,
A sense amplifier circuit for reading data from the memory cell array;
Initial setting data read out from the memory cell array to the sense amplifier circuit is transferred and held, and an initial setting data register that functions to define a memory operation condition;
And a controller for performing sequence control for sequentially rewriting initial setting data stored in the first and second areas of the memory cell array according to one command input.

It is possible to provide a nonvolatile semiconductor memory device which can prevent the initial setting data from being lost and can be rewritten in a short time.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a functional block configuration of a NAND flash memory according to an embodiment of the present invention, and FIG. 2 shows a configuration of a memory cell array 1. The memory cell array 1 is configured by arranging NAND cell units NU. Each NAND cell unit NU is connected to a plurality (16 in the illustrated example) of electrically rewritable nonvolatile memory cells M0 to M15 and both ends thereof connected to the source line CELSRC and the bit line BL, respectively. Select gate transistors S1 and S2.

  The control gates of the memory cells in the NAND cell unit are connected to different word lines WL0 to WL15. The gates of the selection gate transistors S1 and S2 are connected to selection gate lines SGS and SGD, respectively.

  A set of NAND cell units sharing one word line constitutes a block serving as a data erasing unit. As shown in FIG. 2, a plurality of blocks BLK0, BLK1,..., BLKn are arranged in the bit line direction. A set of memory cells sharing one word line constitutes one page (or two pages) as a unit of data reading and writing.

  The row decoder 2 selectively drives a word line and a selection gate line according to a row address, and includes a word line and a selection gate line driver. The sense amplifier circuit 3 is connected to the bit line to read data and also serves as a data latch for holding write data.

  Data exchange between the sense amplifier circuit 3 and the external input / output terminal I / O is performed via the I / O buffer 5 and the data bus 12. The sense amplifier circuit 3 is provided with a column gate for performing column selection, and the column decoder 4 performs this column gate control. By this column control, data transfer (reading and writing) is performed in units of one page between the sense amplifier circuit 3 and the memory cell array 1, whereas between the sense amplifier circuit 3 and the external input / output terminals, for example, Serial data transfer is performed in units of 1 byte.

  The address “Add” supplied via the input / output terminal I / O is transferred to the row decoder 2 and the column decoder 4 via the address register 6. The command “Com” supplied via the input / output terminal I / O is decoded by the controller 8. The controller 8 performs data write / erase sequence control and read operation control based on an external control signal and a command.

  The internal voltage generation circuit 9 is controlled by the controller 8 to generate various internal voltages necessary for write, erase and read operations. A booster circuit is used to generate an internal voltage higher than the power supply voltage. It is done. The status register 14 is for outputting a status signal R / B indicating whether the chip is in a read or write ready state or a busy state to the outside of the chip. The power-on reset circuit 13 detects power-on and causes the controller 8 to perform an initialization operation.

  The memory cell array 1 is set with an initial setting data storage area 13 for storing various initial setting data for determining the operating conditions of the memory. Specifically, the initial setting data includes (1) defective address data for replacing a defective cell, (2) voltage setting data such as a write voltage generated by the internal voltage generation circuit 9, and (3) process variation. It includes voltage adjustment data for adjusting the internal voltage generated by the internal voltage generation circuit 9, (4) control parameters for the number of control loops for writing and erasing, and the like. Although not related to the memory operating conditions, (5) ID codes such as manufacturer IDs and device IDs are also included.

  The initial setting data storage area 13 is programmed before shipping the memory. When the power is turned on, the power-on reset circuit 11 detects this, and the controller 8 automatically reads the initial setting data to the sense amplifier circuit 3 and transfers it to the initial setting data register 10 via the data bus 12. Perform initialization. Various initial setting data are held in the initial setting data register 10, and the operating conditions of the memory are defined by this.

  Specifically, various internal voltages output from the internal voltage generation circuit 9 are determined based on voltage setting data and voltage adjustment data held in the initial setting data register 10, and a control loop for writing and erasing based on control parameters. The number is determined. The address match detection circuit 7 detects a match between an externally input address and a defective address held in the initial setting data register 10, and performs replacement control of the defective address.

  FIG. 3 shows a control flow of the initial setting operation. When power-on is detected, a power-on reset is applied (step S1), and after waiting for a predetermined time (step S2), the status register 14 is set to a busy state of R / B = “L” (step S3). Then, the initial setting data storage area 13 is sequentially read, and operation control is performed to transfer it to the initial setting data register 10 (step S4). When the reading and transfer of all the initial setting data are completed, the ready state of R / B = “H” is set (step S5).

  The flash memory of this embodiment actually has at least two areas in which the same initial setting data is stored as the initial setting data storage area 13, and the initial setting is performed when rewriting the initial setting data in these two areas. It is characterized in that data is not destroyed by power interruption or the like and data can be rewritten in a short time. This point will be specifically described below.

  FIG. 4 specifically shows the case where the flash memory of this embodiment has two memory cell arrays 1 (that is, two planes PLANE0 and 1) each having a row decoder 2 and a sense amplifier circuit 3 independently of each other. The initial configuration data storage areas 13a and 13b to be set and the internal configuration of the controller 8 related to the data rewrite are shown. Each of the planes PLANE0 and 1 is composed of a plurality of blocks BLK0 to BLKn-1, and each of the blocks RF-BLK0 and RF-BLK1 stores an initial setting data storage area 13a for storing the same initial setting data. , 13b.

  The blocks RF-BLK0 and RF-BLK1, which are the initial setting data storage areas 13a and 13b, are hereinafter referred to as “ROM fuse blocks” in the sense that they are ROM areas of fuse substitute circuits that do not normally perform data rewriting.

  In the controller 8, a buffer memory (data register) 21 capable of temporarily storing data for one block of the memory cell array 1 is prepared.

  In order to rewrite the same initial setting data stored in the ROM fuse blocks RF-BLK0, 1, it is necessary to erase these blocks once. However, if all the ROM fuse blocks RF-BLK0, 1 are erased and then new initial setting data is written, the original initial setting data will be lost if the power is cut off during the writing.

  Therefore, in this embodiment, data rewriting of the two ROM fuse blocks RF-BLK0, 1 is performed sequentially by inputting one command. With reference to FIG. 5, the data rewriting operation of the ROM fuse blocks RF-BLK0, 1 will be specifically described.

  Data rewrite operation is started by command input. Following the command input, an address and initial setting data to be rewritten are sequentially input (step S11). The address includes, for example, a block address commonly assigned to the ROM fuse blocks RF-BLK 0 and 1 of the two planes PLANE 0 and 1 and a first page address in the block, and this is held in the address register 6. . All new initial setting data is transferred to the buffer memory 21 in the controller 8 via the data bus 12 and held until the rewrite sequence is completed.

  The selection of the two planes PLANE0, 1 is performed by the plane selection circuit 23. First, for example, the plane PLANE0 is selected. First, the erase operation of the ROM fuse block RF-BLK0 is performed (step S12). This block erasing is performed by applying 0 V to all the word lines in the block and applying an erase voltage Vera to the p-type well in which the cell array is formed. As a result, all the memory cells of the ROM fuse block RF-BLK0 are in the erased state of “1” data by releasing the electrons of the floating gate.

  However, actual data erasing is performed by repeating erasing voltage application and verify reading. Then, based on the verify read result by the sense amplifier circuit 3, the pass / fail judgment circuit 22 judges whether or not to erase or pass.

  If block erasure fails, a fail flag is output (step S31), and the data rewrite operation ends. If the block erase is passed, one page of the initial setting data held in the buffer memory 21 is transferred to the sense amplifier circuit 3 (step S13). Then, it is determined whether or not all pages have been written (step S14). If NO, page writing is performed (step S15).

  Specifically, in the page write, the channel of each NAND cell unit of the selected block is precharged based on the write data held by the sense amplifier circuit 3, the write voltage Vpgm is applied to the selected word line corresponding to the selected page, and the non-selected word line. And a pass voltage Vpass is applied to the selection gate line. As a result, in the memory cell to which “0” data is applied, electrons are injected into the floating gate and the threshold voltage is in the positive “0” data state. In the memory cell to which “1” data is applied, electron injection does not occur and the “1” data state is maintained.

  The actual writing is performed by repeating the writing voltage application and the verify reading. Then, the pass / fail judgment circuit 22 judges the write pass or fail based on the verify read result of the sense amplifier circuit 3.

  When writing is failed, a fail flag is output (step S31), and the sequence is terminated. When the writing of one page is passed, the page address is incremented (step S16), and the next page data is transferred to the sense amplifier circuit 3 (step S13). Thereafter, the same writing is repeated.

  When the writing of all pages is completed, the plane selection circuit 23 switches the plane (step S20). Specifically, the plane selection circuit 23 monitors the output of the pass / fail judgment circuit 22 and switches the access to the plane PLANE 1 in response to the write completion judgment result in step S14.

  Since this plane switching is performed upon completion of writing of all pages in the plane PLANE0, the page address held in the address register is initialized. Then, the ROM fuse block RF-BLK1 of the selected plane PLANE1 is erased (step S21). If the erasure is passed, the page data is transferred to the sense amplifier circuit 3 (step S22), and the page address is incremented (step S25), as in the case of data rewriting in the plane PLANE0. S23) and page writing (step S24) are repeated.

  When it is determined in step S23 that all pages have been written, a pass flag is output (step S30), and a series of data rewrite sequences is completed. If the erase (step S21) and write (step S24) fail, the fail flag is output (step S31), and the sequence is terminated.

  As described above, in this embodiment, the two ROM fuse blocks RF-BLK0, 1 in which the same initial setting data are stored are rewritten sequentially by a single command input. The initial setting data is held in the buffer memory 21 in the controller until the end of the sequence, and this is internally transferred page by page and used for rewriting the ROM fuse blocks RF-BLK0,1. Therefore, it is possible to rewrite the initial setting data in a short time compared to the case where the block is rewritten in a separate sequence.

  For example, even if the power is cut off during the rewriting operation of the ROM fuse block RF-BLK0, the original initial setting data remains in the ROM fuse block RF-BLK1. Accordingly, when the power is turned on again, the initial setting data of the ROM fuse block RF-BLK1 is read and the initialization operation of the flash memory is performed, and the initial setting data can be rewritten again without any trouble.

  The NAND flash memory has been described above. However, the present invention is not limited to this, and can be similarly applied to a NOR type, an AND type, and a DINOR type flash memory.

1 is a diagram showing a functional block configuration of a NAND flash memory according to an embodiment of the present invention. FIG. It is a figure which shows the structure of the memory cell array of the flash memory. It is a figure which shows the control flow of the pattern on reset operation | movement of the flash memory. It is a figure which shows the structure of the part relevant to ROM fuse block rewriting of the flash memory. It is a figure which shows the sequence of ROM fuse block rewriting of the flash memory.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Sense amplifier circuit, 4 ... Column decoder, 5 ... I / O buffer, 6 ... Address register, 7 ... Address coincidence detection circuit, 8 ... Controller, 9 ... Internal voltage generation circuit DESCRIPTION OF SYMBOLS 10 ... Initial setting data register, 11 ... Power-on reset circuit, 12 ... Data bus, 13 (13a, 13b) ... Initial setting data storage area, 14 ... Status register, 21 ... Buffer memory, 22 ... PASS / FAIL judgment circuit , 23: Plane selection circuit.

Claims (5)

A memory cell array in which electrically rewritable nonvolatile memory cells are arranged, and the same initial setting data is stored in at least two regions of the first and second,
A sense amplifier circuit for reading data from the memory cell array;
Initial setting data read out from the memory cell array to the sense amplifier circuit is transferred and held, and an initial setting data register that functions to define a memory operation condition;
A nonvolatile semiconductor memory device comprising: a controller that performs sequence control for sequentially rewriting initial setting data stored in the first and second areas of the memory cell array in accordance with one command input. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the controller performs control to detect power-on, read initial setting data of the memory cell array, and transfer the read data to the initial setting data register. Addresses for holding address data input following the command input and new initial setting data input for rewriting the initial setting data of the memory cell array until rewriting of the first and second areas is completed. The nonvolatile semiconductor memory device according to claim 1, further comprising a register and a buffer memory. A pass / fail judgment circuit for judging a pass or fail of the rewrite sequence of the first and second regions and outputting a flag;
2. The nonvolatile semiconductor memory device according to claim 1, further comprising a selection circuit that switches access to the first and second areas based on a flag output from the pass / fail judgment circuit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array has a plurality of blocks configured by arranging a plurality of NAND cell units, and the same initial setting data is stored in the plurality of blocks. .

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