JP2008182895A - Power circuit - Google Patents

Abstract

An object of the present invention is to provide a power supply circuit capable of stopping driving of a lower transistor and reducing current consumption when the load is light.
A high-order transistor and a low-order transistor connected in series between a power supply voltage and a reference potential, and the on-period is changed by turning on and off the drive of the two transistors with a pulse signal in accordance with a load change. Voltage generating means for generating a stabilized DC voltage to be supplied to the load, and load state determining means for detecting the magnitude of the load fluctuation and determining whether the load is heavier or lighter than a reference. And circuit means for turning off the driving of the lower transistor when a light load is determined.
[Selection] Figure 1

Description

The present invention relates to a power supply circuit, and more particularly to a power supply circuit that reduces current consumption in a synchronous rectification type power supply circuit or the like.

In recent years, mobile devices such as mobile phones have become widespread, and the opportunity to drive a circuit serving as a load with a battery has increased, and it is indispensable that the power consumption of a power supply circuit is small. In addition, it is indispensable for the power supply circuit to be able to respond to load fluctuations at high speed.

In particular, with the widespread use of electronic devices using integrated circuits, a stabilized DC power source with low voltage and low power consumption is required.

If the power supply is stabilized by switching on and off the transistor in accordance with the load and input fluctuations, the power consumption is wasted, so that the efficiency of the power supply becomes very good. In other words, the power supply can be stabilized by changing the on-period (or on-duty) of the transistor. As such an efficient power supply circuit, there is a synchronous rectification type switching regulator using a CMOS integrated circuit.

A CMOS integrated circuit is configured by combining two types of MOS transistors, an N-channel transistor (hereinafter abbreviated as NMOS) and a P-channel transistor (hereinafter abbreviated as PMOS). It has become mainstream.

FIG. 14 shows a configuration of a synchronous rectification type switching regulator using a CMOS integrated circuit.

In FIG. 14, the power supply circuit includes a high-side PMOS (hereinafter referred to as an upper transistor) (QP1) and a low-side NMOS (hereinafter referred to as a lower transistor) (QN1) between an input voltage VIN and a reference potential VSS. A synchronous rectification switching regulator circuit that outputs a DC voltage VOUT by alternately turning on and off these transistors using a PWM signal, and an output voltage of the switching regulator circuit as a voltage value of a reference voltage source E. And an error amplifier 40 that obtains an error signal by comparison, and a PWM circuit 30 that controls the pulse width of the PWM signal based on the error signal to control the output of the switching regulator circuit to be constant. It is configured.

The switching regulator circuit is provided between a terminal 1 to which a direct-current voltage VIN (= power supply voltage VDD, for example, 4V) as an input voltage is supplied and a terminal 2 to which a reference potential VSS (= ground potential GND, for example, 0V) is applied. The upper transistor (QP1) and the lower transistor (QN1) are connected in series with the drain D in common. The source S of the upper transistor (QP1) is connected to the terminal 1, and the source S of the lower transistor (QN1) is connected to the terminal 2.

High frequency pulses SH and SL are supplied as PWM signals from the PWM circuit 30 to the gates of the upper transistor (QP1) and the lower transistor (QN1), and the transistors are alternately turned on and off by the high frequency pulses SH and SL. As a result, an AC voltage VMA is generated at the intermediate node K, which is a connection point between the two transistors.

As shown in FIGS. 15A and 15B, the gate pulse SL of the lower transistor (QN1) is substantially synchronized with the gate pulse SH of the upper transistor (QP1). This period is formed to have a narrower width than the period during which the gate pulse SH is at the high level, and through current flows from the power supply VIN side to the reference potential VSS side by preventing the PMOS and NMOS from being turned on at the same time. Is prevented. In addition, a Schottky diode SD is connected between the source and drain of the lower transistor (QN1) to prevent overvoltage and power supply backup to the low side transistor when the low side transistor is off.

A rectifying coil L1 and a stabilizing capacitor C0 are connected in series between the intermediate node K where the AC voltage VMA is generated and the terminal 3 to which the reference potential VSS is applied, and the output terminal 4 connected to the series connection point. DC voltage VOUT (for example, 1.5 V) smoothed by the stabilization capacitor C0 is output to a load (not shown).

The output DC voltage VOUT is fed back to the negative terminal of the error amplifier 40 via a feedback line, and is compared with the voltage value of the reference voltage source E connected to the terminal 5 to which the reference potential VSS is applied.

An error (error) voltage Vb, which is a comparison result of the error amplifier 40, is supplied to the PWM circuit 30, and the pulse width of the PWM signal generated by the PWM circuit 33 is controlled by the error voltage. By this feedback control, the output voltage VOUT (for example, 1.5 V) supplied to a load (not shown) is controlled to be constant.

In the above configuration, the PWM circuit 30 outputs high-frequency (for example, 1 MHz) pulses SH and SL having appropriate pulse widths substantially synchronized with each other as PWM signals, and outputs each of the upper transistor (QP1) and the lower transistor (QN1). Apply to the gate. The high frequency pulses SH and SL are pulses as shown in FIGS. 15 (a) and 15 (b). When the upper transistor (QP1) and the lower transistor (QN1) are alternately turned on and off by the substantially synchronized high-frequency pulses SH and SL, the intermediate node K, which is the connection point, is switched to FIG. 15 (c). An AC voltage VMA as shown is generated. Based on the AC voltage VMA, the current passes through the coil L1 and is charged to the stabilization capacitor C0, whereby a DC voltage as the output voltage VOUT is obtained at the output terminal 4.

In the circuit of FIG. 14, the waveform of the PWM signal SH for driving the upper transistor (QP1) changes as shown in FIG. 16 due to the change of the load current. In the case of a light load, the pulse width is narrowed, and in the case of a heavy load, the pulse width is widened (however, a pulse in a low level period is described because of low active). When the load is light as in the lowermost stage of FIG. 16, the pulse signal SH is thinned out by the load. In such a situation, in the case of a high-speed switching frequency of about 1 MHz, in the case of a light load (for example, 10 mA or less), when the lower transistor (QN1) is driven (turned on), the driving current reduces the efficiency. Will be invited. The gate capacity of the NMOS is several hundred pF (for example, 500 pF), and its drive current (about 2 mA) is wasted.

In view of the above problems, an object of the present invention is to provide a power supply circuit that can stop the driving of the NMOS and reduce the current consumption when the load is light.

The power supply circuit according to the present invention has an upper transistor and a lower transistor connected in series between a power supply voltage and a reference potential, and according to the fluctuation of the load, the drive of the two transistors is turned on / off by a pulse signal and the on period is set. Voltage condition generating means for generating a stabilized DC voltage to be supplied to the load by changing the load, and a load condition determination for detecting the magnitude of the load fluctuation and determining whether the load is heavy or light relative to the reference Circuit means for turning off the driving of the lower transistor when a light load is determined.

According to such a configuration of the present invention, when the load becomes lighter than the reference, the driving of the lower transistor is stopped (off), so that the current consumption of the lower transistor can be reduced at a light load, It is possible to eliminate the inconvenience that has caused a decrease in efficiency due to the driving current of the lower transistors. As a result, power can be supplied with better efficiency from when the operation is stationary (when no load is applied) to when the operation is maximum (when the load is maximum).

The power supply circuit according to the present invention has an upper transistor and a lower transistor connected in series between a power supply voltage and a reference potential, and the two transistors are turned on / off by a pulse signal in accordance with a load change. A voltage generating means for generating a stabilized DC voltage to be supplied to the load by changing a period; an error detecting means for comparing the output of the voltage generating means with a reference value to obtain an error signal; and the error signal based on the error signal. When controlling the voltage generation means, it has load state determination means for detecting the magnitude of the fluctuation of the load and determining whether the load is heavy or light with respect to the reference. Comprises circuit means for turning off the driving of the lower transistors.

According to such a configuration of the present invention, when the load becomes lighter than the reference, the driving of the lower transistor is stopped (off), so that the current consumption of the lower transistor can be reduced at a light load, It is possible to eliminate the inconvenience that has caused a decrease in efficiency due to the driving current of the lower transistors. As a result, power can be supplied with better efficiency from when the operation is stationary (when no load is applied) to when the operation is maximum (when the load is maximum).

In the present invention, the load state determination means detects the length of a pulse width of a pulse signal that turns on the driving of the upper transistor with respect to the reference, and determines a light load when a short pulse is detected. preferable.

According to such a configuration, when the pulse width of the pulse signal that turns on the driving of the upper transistor is detected, a light load can be determined when a short pulse width is detected with respect to the reference.

The power supply circuit according to the present invention has an upper transistor and a lower transistor connected in series between a power supply voltage and a reference potential, and the two transistors are turned on / off by a pulse signal in accordance with a load change. Voltage generating means for generating a stabilized DC voltage to be supplied to the load by changing the period, and first and second references (the second reference is the first reference) when detecting the magnitude of the load fluctuation Load state determination means for determining whether the load is heavy or light using a larger load than the first reference, and when the load light weight is less than the first reference, the driving of the lower transistor is turned off, When the load weight is not less than the first reference and less than the second reference and the driving of the lower transistor is off, the driving of the lower transistor is kept off, and when the load weight is not less than the second reference, When the driving of the lower transistor is turned on / off by a pulse signal, the load weight is not less than the first reference and less than the second reference, and the driving of the lower transistor is turned on / off by the pulse signal, the driving of the lower transistor is performed by the pulse signal. Circuit means for maintaining on-off.

According to such a configuration of the present invention, the first and second references are provided, and a hysteresis characteristic is given to the drive control of the lower transistor, whereby a ripple (amplitude 0. It is possible to prevent generation of low-frequency oscillation such as 1 V and 22 KHz. In the case of one reference, when the load current fluctuates, the lower transistors are turned on and off before and after the reference, and the ripple may be generated in the output of the voltage generation means. Can be resolved.

The power supply circuit according to the present invention has an upper transistor and a lower transistor connected in series between a power supply voltage and a reference potential, and the two transistors are turned on / off by a pulse signal in accordance with a load change. A voltage generating means for generating a stabilized DC voltage to be supplied to the load by changing a period; an error detecting means for comparing the output of the voltage generating means with a reference value to obtain an error signal; and the error signal based on the error signal. Controls voltage generation means. When detecting the magnitude of the fluctuation of the load, the load is heavy or light using the first and second standards (the second standard is larger than the first standard). Load state determination means for determining the load state, and when the load weight is less than the first reference, the driving of the lower transistor is turned off, and the load weight is equal to or higher than the first reference and the second reference. Less than When the driving of the lower transistor is off, the driving of the lower transistor is kept off, and when the weight of the load is equal to or higher than the second reference, the driving of the lower transistor is turned on / off by a pulse signal, And a circuit means for maintaining driving of the lower transistor on and off by a pulse signal when the driving of the lower transistor is turned on and off by a pulse signal.

According to such a configuration of the present invention, the first and second references are provided, and a hysteresis characteristic is given to the drive control of the lower transistor, whereby a ripple (amplitude 0. It is possible to prevent generation of low-frequency oscillation such as 1 V and 22 KHz. In the case of one reference, when the load current fluctuates, the lower transistors are turned on and off before and after the reference, and the ripple may be generated in the output of the voltage generation means. Can be resolved.

In the present invention, the load state determining means detects the length of a pulse width of a pulse signal for turning on the driving of the upper transistor with respect to the first and second references, and the load state is determined according to the length. The light weight is determined, and the driving of the lower transistor is turned off until the light weight of the load rises from less than the first reference to less than the second reference, and when the light weight of the load rises above the second reference, the lower order The driving of the transistor is turned on / off by the pulse signal, and the driving of the lower transistor is turned on / off by the pulse signal until the light weight of the load drops from the second reference or higher to the first reference or higher. It is preferable to turn off the driving of the lower-order transistor when it falls below.

According to such a configuration, by determining the lightness of the load by the load state determination means, when the lightness of the load changes from light to heavy and until it rises from less than the first reference to less than the second reference Turns off the driving of the lower transistor, and turns on and off the driving of the lower transistor by a pulse signal until the load changes from heavy to light and falls from the second reference or higher to the first reference or higher. When the load weight is above the second reference, the driving of the lower transistor is turned on / off by a pulse signal, and when the load weight is less than the first reference, the driving of the lower transistor is turned off, Even if the pulse width of the pulse signal fluctuates (that is, the load current fluctuates) with respect to one reference, the lower transistor is prevented from oscillating, and the output of the voltage generating means is prevented. It is possible to suppress occurrence of a ripple voltage.

Furthermore, the power supply circuit according to the present invention includes a comparing means using a capacitor and an inverter, and when the lower transistor is turned on during the off period of the upper transistor, the intermediate node potential at the connection point of the upper transistor and the lower transistor is And a detection circuit for outputting a detection signal indicating that the undershoot returns to a state exceeding the reference potential after undershooting to a level lower than the reference potential, and the circuit means includes the voltage generation It is preferable that the pulse signal supplied to the means further has a function of controlling the pulse width of the pulse signal supplied to the gate of the lower transistor by the detection signal of the detection circuit to turn off the lower transistor. .

According to such a configuration, since the comparison means using the capacitor and the inverter (for example, the comparison circuit using the coupling capacitor C1 and the inverter 331) is used, the detection suitable for integration and high-speed operation. In addition to configuring the circuit, in addition to turning off the lower transistor at light load, it is possible to stop the current flowing from the intermediate node to the reference potential side when the lower transistor is on at a heavier load Thus, more power consumption can be reduced.

Embodiments of the invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a power supply circuit according to the first embodiment of the present invention. This embodiment shows a configuration of a synchronous rectification type switching regulator using a CMOS integrated circuit as an efficient stabilized DC power supply.

In FIG. 1, the power supply circuit includes a high-order transistor (QP1) and a low-order transistor (QN1), and is a DC-DC conversion circuit that is a synchronous rectification type switching regulator that alternately turns on and off and outputs a DC voltage VOUT. The output voltage of the DC-DC conversion circuit is compared with the reference voltage value of the reference voltage source E to obtain an error signal, and the pulse width of the PWM signal is controlled based on the error signal, whereby the DC A PWM circuit 32 for controlling the output of the DC conversion circuit to be constant, and a PWM signal of the PWM circuit 32 are input and supplied to the upper transistor (QP1) and the lower transistor (QN1) of the DC-DC conversion circuit. When the gate pulses SH and SL are generated and the load is light (for example, when the thinning operation state is set, the lowermost S in FIG. 16). Reference) is configured to have an output driver 31 for controlling so as to stop the driving of the lower transistor (QN1), and. For example, the output driver 31 verifies the pulse width of the low level period of the PWM signal SH, determines that the load is light when the duty ratio of the pulse width is smaller than a predetermined value (reference value), and drives the lower transistor (QN1). Control to stop. The PWM circuit 32 and the output driver 31 constitute PWM circuit means.

The DC-DC conversion circuit includes a terminal 1 to which a direct-current voltage VIN (= power supply voltage VDD, for example, 4 V) as an input voltage is supplied and a terminal 2 to which a reference potential VSS (= ground potential GND, for example, 0 V) is applied. Between the transistors, the upper transistor (QP1) and the lower transistor (QN1) are connected in series with a common drain D. The source S of the upper transistor (QP1) is connected to the terminal 1, and the source S of the lower transistor (QN1) is connected to the terminal 2.

High frequency pulses SH and SL are supplied as PWM signals from the PWM circuit means to the gates of the upper transistor (QP1) and the lower transistor (QN1), and the transistors are alternately turned on and off by the high frequency pulses SH and SL. As a result, an AC voltage VMA is generated at the intermediate node K, which is a connection point between the two transistors.

The gate pulse SL of the lower transistor (QN1) is substantially synchronized with the gate pulse SH of the upper transistor (QP1), but the period during which the gate pulse SL is at the high level is the period during which the gate pulse SH is at the high level. It is formed so as to have a slightly narrower width, and by preventing the PMOS and NMOS from being turned on at the same time, it prevents the through current from flowing from the power supply VIN side to the reference potential VSS side. In addition, a Schottky diode SD is connected between the source and drain of the lower transistor (QN1) to prevent overvoltage and power supply backup to the low side transistor when the low side transistor is off.

Between the intermediate node K where the AC voltage VMA is generated and the terminal 2 to which the reference potential VSS is applied, the rectifying coil L1 and the stabilization capacitor C0 are connected in series, and the output terminal 4 connected to the series connection point. DC voltage VOUT (for example, 1.5 V) smoothed by the stabilization capacitor C0 is output to a load (not shown).

The output DC voltage VOUT is fed back to the negative terminal of the error amplifier 40 via a feedback line, and is compared with the reference voltage value of the reference voltage source E connected to the terminal 5 to which the reference potential VSS is applied.

An error (error) voltage as a comparison result of the error amplifier 40 is supplied to the PWM circuit 32, and the pulse width of the PWM signal generated by the PWM circuit 32 is controlled by the error voltage.

FIG. 2 is a circuit diagram showing a configuration example of the output driver 31.

In FIG. 2, the output driver 31 includes an input terminal 6 to which a PWM signal from the PWM circuit 32 (inverted relationship with the SH signal) is input, a control unit 311, a 2-input NAND gate 312, and a 2-input input. A NAND gate 315, inverters 313, 314, 316, 317, an output terminal 7 for outputting a high frequency pulse SH as a gate signal of the upper transistor (QP1), and a high frequency pulse SL as a gate signal of the lower transistor (QN1) are output. Output terminal 8 to be configured.

The control unit 311 receives / SH obtained by inverting the high frequency pulse SH and the PWM signal from the terminal 6, and the duty ratio of the / SH pulse width (however, since it is inverted, the pulse width of the high level period). Is larger than a predetermined reference value (for example, 20%) or smaller, if it is larger, a high level is output as the determination signal PWM2, and if it is smaller, a low level is output as the determination signal PWM2.

Therefore, if the pulse width (low active) of the gate pulse SH of the upper transistor (QP1) is smaller than the reference value of the duty ratio, the control unit 311 outputs a low level as the determination signal PWM2, and the lower transistor (QN1). Are input to a two-input NAND gate 315 for controlling the driving of the second gate, and the output of the NAND gate 315 becomes a high level. Then, it is inverted by the inverter 316 and becomes a low level, and is output to the SL output terminal 8. As a result, the output terminal 8 of the gate pulse SL is set to the low level during the period in which the duty ratio of the gate pulse SH is smaller than the reference value, and the driving of the lower transistor (QN1) is stopped (off). Will be.

Note that, based on the potential change of the intermediate node K after the driving of the lower transistor (QN1) is stopped, the source (ie, terminal 2 of the reference potential VSS) of the lower transistor (QN1) to the drain (ie, intermediate node K). The current supply is handled by a Schottky diode SD (Shotky Diode).

FIG. 3 shows a configuration example of the control unit 311 for determining the magnitude of the pulse width of the gate pulse SH.

  A circuit 311 shown in FIG. 3 includes an input terminal 9 for inputting a PWM signal from the PWM circuit 32, an input terminal 10 to which a DC voltage VIN (= power supply voltage VDD) is supplied, and an SH from the output driver 31 of FIG. An input terminal 11 for inputting a / SH signal obtained by inverting the signal, an input terminal 12 to which a reference potential VSS is supplied, PMOS (QP2), PMOS (QP3), and PMOS (QP) constituting a constant current circuit (current mirror) PMOS (QP4) as a first constant current source constituting a constant current circuit (current mirror) together with QP2), a constant current source Q0, NMOS (QN2), NMOS (constituting constant current circuit (current mirror)) QN4) (however, the capacity for the same gate voltage is larger in the NMOS (QN4)), the PMOS (QP4) as the first constant current source and the second constant current source. An NMOS (QN3) whose drain and source are connected in series with the NMOS (QN4) as a current source, a resistor R and a capacitor C connected between the drain of the PMOS (QP4) and the VSS line. An integration circuit; a first CMOS inverter formed by a PMOS (QP5) and an NMOS (QN7) connected in series between the VIN line and the VSS line with the output of the integration circuit as an input; and the first CMOS A second CMOS inverter formed of PMOS (QP6) and NMOS (QN8) connected in series between the VIN line and the VSS line with the output of the inverter as an input, the PWM signal from the input terminal 9, and the first 2 and the output of the integration circuit (R, C) of the output (ie, the duty ratio of the SH pulse). A two-input NAND gate 320 for outputting the SH pulse width determination signal PWM2 corresponding to large), and is configured to include an output terminal 13 for outputting the SH pulse width determination signal PWM2, the. The SH pulse width determination signal PWM2 is supplied to one input terminal of the 2-input NAND gate 315 of FIG. 2 for controlling the driving of the lower transistor (QN1).

Regarding the above-mentioned NMOS (QN4), 'the capacity for the same gate voltage is larger in the NMOS (QN4)', for example, the channel width of the NMOS (QN4) is larger than that of the NMOS (QN2), for example. The drain current flowing through the NMOS (QN4) is 5 times larger than the drain current flowing through the NMOS (QN2) even when the same gate voltage is applied to the NMOS (QN2) and NMOS (QN4). This means that it is about twice as large (that is, about 5 times the power supply capacity).

In the configuration of FIG. 3 described above, for example, when the 1 MHz PWM pulse SH is inverted / the high level period of SH exceeds 20% of the duty ratio (that is, when the load is heavy), the NMOS (QN3) is turned off. Is not long enough to charge the integration circuit (R, C), the voltage of the integration circuit (R, C) charged during the off period (that is, the output voltage of the capacitor C) is the second stage. Since the threshold value of the first CMOS inverter (QP5, QN7) cannot be exceeded and remains at the low level, the output of the first CMOS inverter (QP5, QN7) is at the high level, and the second CMOS inverter (QP6) , QN8) becomes a low level, the output PWM2 of the 2-input NAND gate 320 becomes a high level, and the SL output of the output driver 31 of FIG. Transistor (QN1) is driven (ON).

On the other hand, when the high level period of the inversion pulse / SH falls below 20% duty ratio (that is, when the load becomes light), the integration circuit (R, C) is charged during the period when the NMOS (QN3) is turned off. Therefore, the voltage of the integration circuit (R, C) charged during the off period (that is, the output voltage of the capacitor C) is the first CMOS inverter (QP5, QN7) of the next stage. , The output of the first CMOS inverter (QP5, QN7) becomes low level, the output of the second CMOS inverter (QP6, QN8) becomes high level, and two inputs The output PWM2 of the NAND gate 320 is at a low level, the SL output of the output driver 31 in FIG. 2 is at a low level, and the driving of the lower transistor (QN1) in FIG. 1 is stopped (off). It is. Therefore, when the load is reduced and the duty ratio of the pulse width of the PWM pulse SH is less than 20%, the driving of the lower transistor (QN1) is stopped and only the upper transistor (QP1) is driven. Further, when the load becomes heavy and the duty ratio of the pulse width of the PWM pulse SH exceeds 20%, both the lower transistor (QN1) and the upper transistor (QP1) are in a normal driving state.

By the way, in the configuration of the control unit 311 of the output driver 31 as shown in FIG. 3, when the load weight (that is, the load current) changes with a reference value (for example, 20%) of a predetermined duty ratio as a boundary. Depending on the load current, the lower transistor (QN1) is repeatedly turned on and off, so that an oscillation state is reached. Therefore, the output voltage VOUT fluctuates at a frequency of 22 KHz or the like depending on whether the lower transistor (QN1) is driven (that is, a low-frequency ripple having an amplitude of, for example, about 0.1 V is generated in the output voltage VOUT), and the power supply capability changes. . This is because, for example, a portable device such as a personal digital assistant (PDA) generally has a large load fluctuation from a stationary operation (no load) to a maximum operation (maximum load), and may easily oscillate depending on the load current. It means that you can do it.

Next, the configuration of the control unit 311 of the output driver 31 for preventing the above oscillation will be described.

FIG. 4 shows another configuration example of the control unit 311 that determines the magnitude of the pulse width of the gate pulse SH.

  The circuit 311 shown in FIG. 4 is different from the circuit configuration of FIG. 3 in that NMOS (QN2) and NMOS (QN4) constituting a constant current circuit (current mirror) [however, the capability for the same gate voltage is that of NMOS (QN4). This is because the NMOS (QN6) having the same capacity can be connected in parallel to the NMOS (QN4) via the switching NMOS (QN5). That is, when the NMOS (QN5) is turned on, the NMOS (QN6) is connected in parallel with the NMOS (QN4). Regarding the signs (1) and (5) in the figure, when the current amount Ibias of the current source Q0 with respect to the same bias voltage is set to (1), (5) shows the current of Ibias × 5 with respect to the same bias voltage. It means that there is the ability to flow. Therefore, when the NMOS (QN4) and the NMOS (QN6) are connected in parallel, it means that the ability to flow a current of Ibias × 10 with respect to the same bias voltage is generated. Other configurations are the same as those in FIG.

In the circuit of FIG. 4, by adopting a configuration in which the determination of the pulse width of SH is provided with hysteresis, for example, when it is detected that the duty ratio falls below a reference value (for example, 10%), the lower transistor (QN1) is driven. Until the duty ratio reaches 20%, the driving of the lower transistor (QN1) is stopped. When the load becomes heavy and the duty ratio exceeds 20%, the lower transistor (QN1) is stopped. QN1) is driven, and the driving of the lower transistor (QN1) is stopped only when the duty ratio becomes less than 10% when the load fluctuates and becomes light again. As a result, even if the pulse width varies (that is, the load current varies) with respect to one reference value of the duty ratio, the oscillation state described above is repeated in which the lower transistor (QN1) is repeatedly turned on and off. Can be prevented.

The operation of the circuit shown in FIG. 4 will be described with reference to FIG. FIG. 5A shows the duty ratio (low active) of the pulse width in the low level period of the PWM signal SH, and shows an example in which the duty ratio changes in the range of 10 to 20%. FIGS. 5B and 5C show the driving of the lower transistor (QN1) accompanying the change in the duty ratio of the SH pulse when hysteresis is given to the determination of the SH pulse width (in the case of the circuit of FIG. 4). Indicates presence / absence (on or off).

The configuration of FIG. 4 will be described along the passage of time of FIG. For example, when the 1 MHz PWM pulse SH is inverted / the high level period of SH is less than 10% of the duty ratio (that is, when the load is light), the integration time is long because the NMOS (QN3) is turned on for a short time and is turned off. Since the circuit (R, C) is sufficiently charged and the charging voltage becomes a high level exceeding the threshold value of the first CMOS inverter (QP5, QN7) at the next stage, the first CMOS inverter (QP5, QN7) ) Is low level, the output of the second CMOS inverter (QP6, QN8) is high level, the output PWM2 of the 2-input NAND gate 320 is low level, and the SL output of the output driver 31 of FIG. 2 is low level. The driving of the first lower transistor (QN1) is stopped (off).

On the other hand, when the high level period of the inversion pulse / SH is between 10% and 20% exceeding the duty ratio of 10% (that is, when the load is slightly reduced), the period during which the NMOS (QN3) is turned on Is slightly longer, but the capacity of the NMOS (QN4) connected in series to the NMOS (QN3) does not change (that is, the NMOS (QN6) is not connected in parallel at this time), so the integration circuit is in the off period of the NMOS (QN3). The voltage charged to (R, C) remains at the high level, and the driving of the lower transistor (QN1) in FIG. 1 is stopped (off) as in the above state where the duty ratio is less than 10%. To maintain.

When the duty ratio exceeds 20% during the high level period of the inversion pulse / SH (that is, when the load becomes heavy), the off period of the NMOS (QN3), that is, the charging of the integration circuit (R, C). Since the period is shortened and the output voltage of the integrating circuit (R, C) cannot exceed the threshold value of the first CMOS inverter (QP5, QN7) of the next stage and becomes low level, the first CMOS inverter ( The output of QP5, QN7) is high level, the output of the second CMOS inverter (QP6, QN8) is low level, the output PWM2 of the 2-input NAND gate 320 is high level, and the SL output of the output driver 31 of FIG. Thus, the lower transistor (QN1) in FIG. 1 is driven (ON). In this case, since the output of the first CMOS inverter (QP5, QN7) is at a high level, the gate of the NMOS (QN5) is set to a high level and the NMOS (QN5) is turned on. As a result, the NMOS (QN4) is turned on. The NMOS (QN6) is connected in parallel, and the capacity of the NMOS connected in series to the NMOS (QN3) is doubled [compared to the drain current value indicated by (1) such as NMOS (QN2) (5) Therefore, the charging charge of the integrating circuit (R, C) absorbed to the VSS side through the NMOS (QN3) during the ON period of the NMOS (QN3) is doubled. That is, the charging charge of the integrating circuit (R, C) is sufficiently discharged during the ON period of the NMOS (QN3).

As described above, when the NMOS (QN6) is connected in parallel to the NMOS (QN4), the load changes and becomes lighter. When the duty ratio of / SH falls below 20% and becomes 20 to 10%, the NMOS The off period of QN3 [that is, the charging period of the integration circuit (R, C)] is slightly longer and the charge charged in the integration circuit (R, C) increases during the off period, but the on period of the NMOS (QN3) Since the charging charge discharge capability of the integrating circuit (R, C) in FIG. 5 is kept high, the charging voltage of the integrating circuit (R, C) exceeds the threshold value of the first CMOS inverter (QP5, QN7). Can't keep up low level.

When the load is further reduced and the duty ratio of / SH is less than 10%, the NMOS (QN3) is turned off for a long period, so that the voltage charged in the integrating circuit (R, C) is the first stage. Therefore, the output of the first CMOS inverter (QP5, QN7) is low and the output of the second CMOS inverter (QP6, QN8) is high. The output PWM2 of the 2-input NAND gate 320 is at a low level, the SL output of the output driver 31 in FIG. 2 is at a low level, and the driving of the lower transistor (QN1) in FIG. 1 is stopped (off). At this time, since the output of the first CMOS inverter (QP5, QN7) is at a low level, the switching NMOS (QN5) is turned off, and the charge discharge capability of the integrating circuit (R, C) is low [NMOS ( QN2) and the like, and the drain current value indicated by (1) is changed to (5) × 1, that is, 5 times).

According to the first embodiment described above, when the duty ratio of the active pulse input to the gate of the upper transistor (QP1) becomes smaller than a predetermined reference value, the driving of the lower transistor (QN1) is stopped ( By turning off, in the case of a light load, the drive current of the lower transistor does not cause a decrease in efficiency.

Furthermore, by providing the first and second reference values and giving hysteresis characteristics to the drive (on / off) control of the lower transistor (QN1), a ripple (amplitude 0...) Is applied to the output voltage of the DC-DC conversion circuit. It is possible to prevent generation of low-frequency oscillation such as 1 V and 22 KHz. In the case of one reference value, when the load current fluctuates, the lower transistor (QN1) is turned on and off around the reference value due to the fluctuation, and the ripple is output to the output of the DC-DC conversion circuit. It is possible to eliminate the possibility of the occurrence of

FIG. 6 shows the configuration of the power supply circuit according to the second embodiment of the present invention. In the present embodiment, the same parts as those in FIG.

The power supply circuit shown in FIG. 6 is different from the power supply circuit shown in FIG. 1 in that the potential VMA of the intermediate node K is VSS when the lower transistor (QN1) is on during the period in which the upper transistor (QP1) is off. After undershooting to a potential lower than the level, it returns from the undershoot, reaches the VSS level, detects that it has further increased, and has a detection circuit 33 that outputs a detection signal NOFF, and the output driver 31A includes: The PWM signal of the PWM circuit 32 is inputted, and the gate pulses SH and SL to be supplied to the upper transistor (QP1) and the lower transistor (QN1) of the DC-DC conversion circuit are created. During operation, the lowermost stage SH in FIG. 16) stops driving the lower transistor (QN1). Among the PWM signals SH and SL supplied to the DC-DC conversion circuit, the pulse width of the high level period of the PWM signal SL related to on / off of the lower transistor (QN1) is provided. The second function is controlled by the detection signal NOFF, and controls to turn off the lower transistor (QN1) when the lower transistor (QN1) is on during the off period of the upper transistor (QP1). Configured. The PWM circuit 32 and the output driver 31A constitute PWM circuit means.

Specifically, the first function of the output driver 31A is to test the pulse width of the low level period of the PWM signal SH, for example, and the load is light when the duty ratio of the pulse width is smaller than a predetermined value (reference value). And control to stop the driving of the lower transistor (QN1).

The second function of the output driver 31A is as shown in FIGS. 8A to 8C when the lower transistor (QN1) is on during the period in which the upper transistor (QP1) is off. When the intermediate node potential VMA undershoots to a potential lower than the VSS level and then returns from the undershoot to the VSS level and further rises, the ON state of the lower transistor (QN1) is forcibly turned off, This is to prevent the intermediate node potential VMA from becoming higher than the VSS level and causing a current to flow from the intermediate node K side to the VSS side to consume power.

FIG. 7 shows a configuration example of the output driver 31A in FIG. The 2-input NAND gate 315 of the output driver 31 shown in FIG. 2 is a 3-input NAND gate 315a. That is, the NAND gate 315 of FIG. 2 is provided with an input terminal 19 for inputting another detection signal NOFF to form a three-input NAND gate 315a. The control unit 311 is the same as that described in FIG. 3 or FIG. Other configurations are the same as those in FIG.

With the configuration of FIG. 7, the output driver 31A can have the above-described first and second functions.

The second function of the output driver 31A and the detection circuit 33 that generates the detection signal NOFF will be described with reference to FIGS.

FIG. 8 is a timing chart showing changes in the PWM signals SH and SL and the intermediate node potential VMA in FIG. 6, where (a) shows the PWM signal SH, (b) shows the PWM signal SL, and (c) shows the intermediate node potential VMA. Each is shown. FIG. 9 is an enlarged view showing FIG. FIG. 10 is a timing chart showing the relationship between the reference potential VSS and the intermediate node potential VMA and the detection signal NOFF of the detection circuit 33. FIG. 10A shows the reference when the NMOS is on while the PMOS is off. The change state of the intermediate node potential VMA with respect to the potential VSS (when lightly loaded) is shown, and (b) shows the detection signal NOFF generated by the detection circuit 33 based on VMA and VSS.

High frequency pulses SH and SL are supplied as PWM signals from the PWM circuit means to the gates of the upper transistor (QP1) and the lower transistor (QN1), and the MOS transistors are alternately turned on by the high frequency pulses SH and SL. Turned off. As shown in FIG. 8C, during a period in which the upper transistor (QP1) is on and the lower transistor (QN1) is off, a current based on the DC voltage VIN (= VDD) from the power supply causes the coil L1 to be turned on. Since the stabilization capacitor C0 is charged through the intermediate node potential VMA, the intermediate node potential VMA becomes the DC voltage VIN (= VDD). When the upper transistor (QP1) is turned off and the lower transistor (QN1) is turned on, the intermediate node potential VMA is the reference potential. It rises after falling to a level slightly lower than VSS (= GND), crosses the VSS level at point P, further rises linearly and rises to a level higher than VSS (= GND).

The voltage change of VMA in the off period of the upper transistor (QP1) is as shown in FIG. 9, and from the VSS level in the period T2 after the lower transistor (QN1) is turned on in the off period of the upper transistor (QP1). Since the NMOS (QN1) is turned off after undershooting to a low potential and returning to the undershoot, the voltage of the VMA rises rapidly. In the period T1 when the upper transistor (QP1) is on, the intermediate node voltage VMA is kept constant at VIN (= VDD).

As shown in FIGS. 10A and 10B, the detection circuit 33 outputs a high level signal (H) as the detection signal NOFF when the intermediate node potential VMA is lower than the reference potential VSS level in the period T2. When the voltage rises above the VSS level, a low level signal (L) is output.

When the output driver 31A receives the detection signal NOFF in FIG. 10B during the period T2, the output driver 31A drops the pulse width indicated by the two-dot chain line of the pulse SL in FIG. As a result, the pulse width shown by the solid line is changed. As a result, the on period of the lower transistor (QN1) is shortened, but the output voltage VOUT supplied to the load (not shown) is mainly determined by the charging voltage stored in the stabilization capacitor C0 during the on period of the upper transistor (QP1). The on period of the lower transistor (QN1) has little influence. On the contrary, the effect of preventing the power loss caused by the current flowing from the intermediate node K (and hence the stabilization capacitor C0) to the reference potential VSS side during the ON period of the lower transistor (QN1) is greater.

FIG. 11 shows a configuration example of the detection circuit 33. FIG. 11A is a circuit diagram thereof, and FIG. 11B is a diagram showing switching timings of the switches S1 to S3 in FIG. Here, an example using a single-stage inverter (331) is shown.

The detection circuit 33 includes an input terminal 14 for the intermediate node potential VMA, switches S1 and S2, a coupling capacitor C1, an inverter 331, a switch S3, a two-input NAND gate 334, an inverter 335, and an output terminal for the detection signal NOFF. 18. The inverter 331 is driven using the same voltage as the power supply voltage VIN (= VDD) and the reference potential VSS. The switches S1 and S2 are two-input changeover switches having input ends A and B, respectively. The switch S3 is an on / off changeover switch and is connected in parallel between the input and output ends of the inverter 331.

The intermediate node potential VMA is input to the input terminal 14, and is supplied to the input point a of the inverter 331 through the switches S1 and S2 and further through the coupling capacitor C1 in the period T2. At this time, since the switch S3 is open, the signal at the input point a is inverted and input to one input terminal of the NAND gate 334, and the high level indicating the period T2 given to the other input terminal 17 A NAND (NAND) is taken between the level signal and the output signal to the output terminal 18 via the inverter 335. In the period T1, the input terminal of the coupling capacitor C1 is set to the VSS level, and the switch S3 is short-circuited.

Note that the switch S1 sets the output terminal of the switch S1 to VSS so that the power supply voltage VIN does not affect the subsequent stage via the output terminal of the switch S1 when the input voltage VMA becomes VIN (= VDD) in the period T1. It is provided to keep it on the level side.

The NAND gate 334 and the inverter 335 are gates added to further convert the signal obtained by binarizing the change of the analog signal VMA in the period T2 by the inverter 331 into a digital signal.

One of the intermediate node potential VMA input to the terminal 14 and the reference potential VSS applied to the terminals 15 and 16 is input in response to switching of the switches S1 and S2 corresponding to the periods T2 and T1, and the coupling capacitor C1 Will be added to the input terminal.

Therefore, first, during the period T1, VSS is input, and the input / output of the inverter 331 is short-circuited, so the execution level of the input point a of the inverter 331 is within VIN / 2 (= Vref). In this state, as shown in FIG. 12, when the lower transistor (QN1) is turned on at the timing of period T2, VMA undershoots and becomes a voltage slightly lower than VSS. Since this is transmitted to the input point a of the inverter 331 by capacitive coupling by the capacitor C1, the input level a of the inverter 331 at this time becomes an input level lower than the threshold value Vref (= VIN / 2), and the inverter 331 The inverted output is at a high (H) level, and then when VMA is higher than Vref, the inverted output of the inverter 331 is at a low (L) level.

That is, in the period T2, the detection signal NOFF obtained at the output terminal 18 is output as a change from H level to L level in accordance with the change in VMA with respect to the VSS level.

FIG. 13 shows another configuration example of the detection circuit 33. FIG. 13A is a circuit diagram thereof, and FIG. 13B is a diagram showing switching timings of the switches S1 to S4 in FIG. Here, an example using two-stage inverters (331, 332) is shown. Switches S1 and S2 are two-input changeover switches having input terminals A and B, and switches S3 and S4 are on / off changeover switches.

In the example of FIG. 13, a coupling capacitor C2, an inverter 332, and an inverter 333 are further added after the inverter 331 in FIG. 11, and a switch S4 is connected in parallel between the input and output of the inverter 332. . Similarly to the inverter 331, the inverter 332 is driven using the same voltage as the power supply voltage VIN (= VDD) and the reference potential VSS. An inverter 333 connected between the inverter 332 and the NAND gate 334 is inserted to match the signal polarity with the circuit of FIG. Note that the NAND gate 334 and the inverter 335 are added in order to further convert the signal obtained by binarizing the change of the analog signal VMA in the period T2 by the inverters 331 and 332 in the same manner as in FIG. Gate.

Therefore, the circuit of FIG. 13 has a gain obtained by using two stages of inverter configurations, and the operation is the same as that of FIG.

According to the second embodiment described above, in addition to the current consumption reduction (stop of lower transistor driving at light load) in the first embodiment, wasteful power consumption at lower transistor driving is reduced. Therefore, it is possible to further reduce power consumption.

The present invention is not limited to the embodiment described above, and can be implemented by appropriately changing each embodiment without departing from the scope of the present invention.

As described above, according to the power supply circuit of the present invention, when the load is light, the driving of the lower transistors can be stopped to reduce current consumption.

The figure which shows the structure of the power supply circuit of the 1st Embodiment of this invention. FIG. 2 is a circuit diagram illustrating a configuration example of an output driver in FIG. 1. The circuit diagram which shows the structural example of the control part in FIG. The circuit diagram which shows the other structural example of the control part in FIG. FIG. 5 is a diagram for explaining the operation of the circuit of FIG. 4. The figure which shows the structure of the power supply circuit of the 2nd Embodiment of this invention. The figure which shows the structural example of the output driver in FIG. 7 is a timing chart showing changes in the PWM signals SH and SL and the intermediate node potential VMA in FIG. The enlarged view which expands and shows FIG.8 (c). 4 is a timing chart showing a relationship between a reference potential VSS and an intermediate node potential VMA and a detection signal NOFF of the detection circuit. FIG. 7 is a diagram illustrating a configuration example of the detection circuit in FIG. The figure which shows the detection signal NOFF in FIG. FIG. 7 is a diagram illustrating another configuration example of the detection circuit in FIG. 6, and a diagram illustrating a switching timing of switches S <b> 1 to S <b> 4. The figure which shows the structure of the conventional synchronous rectification type | mold switching regulator using a CMOS integrated circuit. 15 is a timing chart showing the relationship between PWM signals SH and SL and the intermediate node potential VMA in the switching regulator circuit of the power supply circuit of FIG. The figure which shows the change of the pulse width of PWM signal SH which arises with the change of load.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Power supply input terminal 2 ... Reference potential input terminal 4 ... Output terminal 31 ... Output driver 32 ... PWM circuit 33 ... Detection circuit 40 ... Error amplifier (error detection means)
QP1 ... PMOS (upper transistor)
QN1 ... NMOS (lower transistor)
L1 ... Rectification coil C0 ... Stabilization capacitance C1, C2 ... Coupling capacitance

Claims (7)

It has an upper transistor and a lower transistor connected in series between the power supply voltage and the reference potential. According to the fluctuation of the load, the drive of the two transistors is turned on / off with a pulse signal and supplied to the load by changing the on period. Voltage generating means for generating a stabilized DC voltage to be
Load level determining means for detecting a load state of the load and determining whether the load is heavy or light with respect to a reference is provided, and when the light load is determined, the driving of the lower transistor is turned off. Circuit means;
A power supply circuit comprising: It has an upper transistor and a lower transistor connected in series between the power supply voltage and the reference potential. According to the fluctuation of the load, the drive of the two transistors is turned on / off with a pulse signal and supplied to the load by changing the on period. Voltage generating means for generating a stabilized DC voltage to be
Error detection means for comparing the output of the voltage generation means with a reference value to obtain an error signal;
The voltage generation unit is controlled based on the error signal, and includes a load state determination unit that detects the magnitude of the load variation and determines whether the load is heavy or light with respect to a reference. Circuit means for turning off the driving of the lower transistor when a light load is determined;
A power supply circuit comprising:   2. The load state determining means detects a length of a pulse width of a pulse signal for turning on driving of the upper transistor with respect to the reference, and determines a light load when a short pulse is detected. Or the power supply circuit of 2. It has an upper transistor and a lower transistor connected in series between the power supply voltage and the reference potential. According to the fluctuation of the load, the drive of the two transistors is turned on / off with a pulse signal and supplied to the load by changing the on period. Voltage generating means for generating a stabilized DC voltage to be
When detecting the magnitude of the fluctuation of the load, a load state for determining whether the load is heavy or light using the first and second criteria (the second criterion is larger than the first criterion) A determination unit that turns off the driving of the lower transistor when the light weight of the load is less than the first reference, and turns off the driving of the lower transistor when the light weight of the load is greater than or equal to the first reference and less than the second reference; In this case, the driving of the lower transistor is kept off, and when the load of the load is equal to or higher than the second reference, the driving of the lower transistor is turned on / off by a pulse signal, and the weight of the load is higher than the first reference. Circuit means for maintaining driving of the lower transistor on and off by a pulse signal when the driving of the lower transistor is less than a reference of 2 and the driving of the lower transistor is turned on and off by a pulse signal;
A power supply circuit comprising: It has an upper transistor and a lower transistor connected in series between the power supply voltage and the reference potential. According to the fluctuation of the load, the drive of the two transistors is turned on / off with a pulse signal and supplied to the load by changing the on period. Voltage generating means for generating a stabilized DC voltage to be
Error detection means for comparing the output of the voltage generation means with a reference value to obtain an error signal;
The voltage generator is controlled based on the error signal. When detecting the magnitude of the fluctuation of the load, the first and second references (the second reference is larger than the first reference) are used. A load state determining means for determining whether the load is heavy or light, and when the load light weight is less than the first reference, the driving of the lower transistor is turned off, and the load light weight is the first If the load of the lower transistor is more than the second reference and the lower transistor is driven off, the lower transistor is kept off. When the load is lighter than the first reference and lower than the second reference and the driving of the lower transistor is turned on / off by the pulse signal, the driving of the lower transistor is turned on / off by the pulse signal. Circuit means to maintain the off,
A power supply circuit comprising:   The load state determination means detects the length of the pulse width of the pulse signal that turns on the driving of the upper transistor with respect to the first and second references, determines the weight of the load according to the length, The driving of the lower transistor is turned off until the light weight of the transistor rises from less than the first reference to less than the second reference. When the load of the load falls below the first reference, the drive of the lower transistor is turned on / off by the pulse signal until the load weight falls from the second reference or higher to the first reference or higher. 6. The power supply circuit according to claim 4, wherein the driving of the lower transistor is turned off. Comparing means using a capacitor and an inverter is provided, and when the lower transistor is turned on during the off period of the upper transistor, the intermediate node potential at the connection point of the upper transistor and the lower transistor is under a level lower than the reference potential. And further comprising a detection circuit that outputs a detection signal indicating that the undershoot returns to the state exceeding the reference potential after shooting.
The circuit means controls the pulse width of the pulse signal supplied to the gate of the lower transistor among the pulse signals supplied to the voltage generating means by the detection signal of the detection circuit, and turns off the lower transistor. The power supply circuit according to any one of claims 1, 2, 4, and 5, further comprising:

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