JP2008172117A - Electro-optical device, electro-optical device substrate, semiconductor element, and electronic apparatus - Google Patents

Abstract

Provided are an electro-optical device, a substrate for an electro-optical device, a semiconductor element, and an electronic apparatus that can suppress the connection resistance between all bump portions and terminal portions and make the connection resistance uniform, thereby reducing conduction defects of semiconductor elements. To do.
An electro-optical device includes an electro-optical device substrate on which a semiconductor element is mounted, the semiconductor element including a plurality of bump portions, the electro-optical device substrate including a plurality of terminal portions, and a plurality of terminal portions. The bump part and the plurality of terminal parts are electrically connected using an anisotropic conductive film containing conductive particles, and the plurality of bump parts and the terminal part are arranged along a predetermined side of the semiconductor element. A bump portion and a terminal portion that form a second row and include a first row closer to the predetermined side and a second row farther from the predetermined side than the first row. Is made smaller than the plane projection areas of the bump portions and the terminal portions constituting the first row.
[Selection] Figure 3

Description

  The present invention relates to an electro-optical device, a substrate for an electro-optical device, a semiconductor element, and an electronic apparatus. In particular, an electro-optical device including an electro-optical device substrate on which a semiconductor element is mounted using an anisotropic conductive film, an electro-optical device substrate used in such an electro-optical device, a semiconductor element, and the like The present invention relates to an electronic apparatus provided with an electro-optical device.

  Conventionally, as one aspect of an electro-optical device, a pair of substrates each having an electrode formed thereon are arranged to face each other, and a voltage applied to a plurality of pixels that are intersection regions of the electrodes is selectively turned on and off. A liquid crystal device that modulates light passing through a liquid crystal material in a pixel region and displays an image such as an image or a character is widely used. In such a liquid crystal device, a voltage is selectively applied to each pixel region by selectively outputting a drive signal to a plurality of data lines and source lines via semiconductor elements.

  This semiconductor element has a plurality of bump portions as terminals on the active surface, and the plurality of bump portions are mounted on the substrate so as to be electrically connected to the terminal portion connected to the wiring on the substrate. Has been. As a method for mounting such a semiconductor element, mounting is performed using an anisotropic conductive film (ACF) in which conductive particles that electrically connect the bump part and the terminal part are mixed in an adhesive that fixes the semiconductor element and the substrate. There is a way. This mounting method uses, for example, a thermocompression bonding apparatus as shown in FIG. 6 to press a semiconductor element with an ACF interposed between the substrate placed on the mounting table and the semiconductor element. The conductive particles are fixed in a state where they are brought into contact with each other while being crushed, and the bump portion and the terminal portion are electrically connected.

  Incidentally, in recent years, in order to improve the image quality of image display, the resolution of liquid crystal devices has been increased, and the number of data lines and source lines has increased. On the other hand, in order to make a semiconductor element inexpensive or to reduce the outer size of an electro-optical device or an electronic device, the outer size of the semiconductor element has been reduced. In such a case, the pitch between adjacent bumps provided in the semiconductor element is electrically connected to the terminals of the respective wirings and the bump portions for outputting signals are arranged in a line. The interval is reduced, and adjacent bumps are easily short-circuited.

Therefore, a display device that uses semiconductor elements with bumps formed in a staggered pattern to prevent contact between the bumps and reduces the outer diameter size of the drive circuit chip to enable a reduction in the size of the display device as a whole is proposed. Has been. More specifically, as shown in FIG. 16, a plurality of pixels arranged in a matrix on the substrate, and a drive circuit chip GDR (semiconductor element) mounted on the substrate for causing the pixels to perform display. The drive circuit chip GDR has a plurality of output terminals OT (bump portions) connected to the output wiring GL formed on the substrate and a plurality of dummy terminals DT arranged adjacent to each other. Disclosed is a display device in which the output terminals OT are formed in a zigzag pattern along the upper side of the drive circuit chip GDR, the clearance between the adjacent output terminals OT is secured, and the contact between the output terminals OT is prevented. (See Patent Document 1).
JP 2003-98973 A (paragraph 0033, FIG. 1)

However, when the bump portions are formed in a staggered manner as in the display device of Patent Document 1, the bump portions are arranged in a plurality of rows along one side of the semiconductor element. Then, when the semiconductor element is pressed when mounting using the ACF, among the bump portions arranged in a plurality of rows along one side, the bump portion on the inner side (the side far from the one side) is strongly pressed while the outer side ( There is a case where the pressing force of the bump portion on the side close to one side becomes small. As a result, the degree of crushing of the conductive particles at the outer bump portion becomes insufficient, and a sufficient contact area between the conductive particles and the bump portion or terminal portion cannot be secured, resulting in increased connection resistance or poor conduction. There was a risk of it occurring.
Although the cause of the variation in the pressing force is not clear, it is presumed that the stretchability during thermocompression bonding due to the difference in material between the substrate and the semiconductor element has an effect.

Accordingly, the inventors of the present invention have made diligent efforts, and among the bump portions and terminal portions arranged in a plurality of rows along a predetermined side of the semiconductor element, the bump portions and terminals on the side where the pressing force when mounting the semiconductor element is reduced The present invention has been completed by finding that such a problem can be solved by relatively increasing the planar projection area of the portion.
That is, the present invention suppresses the connection resistance between all the bump parts and the terminal parts and reduces the connection resistance even in the case of a semiconductor element having a small external size including bump parts arranged in a plurality of rows along a predetermined side. It is an object of the present invention to provide an electro-optical device that can be uniformized and can reduce conduction defects of semiconductor elements. Another object of the present invention is to provide a substrate for an electro-optical device and a semiconductor element used in such an electro-optical device, and an electronic apparatus including such an electro-optical device.

According to the present invention, an electro-optical device includes an electro-optical device substrate on which a semiconductor element is mounted. The semiconductor element includes a plurality of bump portions, and the electro-optical device substrate includes a plurality of terminal portions. The plurality of bump portions and the plurality of terminal portions are electrically connected using an anisotropic conductive film containing conductive particles, and the plurality of bump portions and the terminal portion are arranged along predetermined sides of the semiconductor element, respectively. A plurality of rows, a first row closer to the predetermined side, a second row farther from the predetermined side than the first row, and a bump portion constituting the second row; An electro-optical device in which the planar projection area of the terminal portion is smaller than the planar projection area of the bump portion and the terminal portion constituting the first row is provided, and the above-described problems can be solved.
That is, among the bump portions and terminal portions arranged in a plurality of rows, the planar projection areas of the second bump portions and terminal portions on the side far from the predetermined side are set to the first bump portions and terminal portions on the side close to the side. By making it smaller than the planar projection area, it is possible to prevent the pressing force acting on the first bump portion from being reduced.
Further, since the planar projection areas of the first bump part and the terminal part are larger than the planar projection areas of the second bump part and the terminal part, the continuity interposed between the first bump part and the terminal part. The number of particles can be relatively increased. Therefore, in the first bump portion, even if the pressing force is relatively small and the degree of crushing of the individual conductive particles is small, the contact area as a whole of the first bump portion and the terminal portion can be increased. And increase in connection resistance can be reduced.
As a result, it is possible to provide an electro-optical device in which variation in connection resistance between all bump portions and terminal portions is suppressed and conduction failure of semiconductor elements is reduced.

Further, in configuring the electro-optical device of the present invention, all the bump portions constituting the first row of the plurality of rows and all the bump portions constituting the second row having the planar projection area of the terminal portion, and It is preferable that it is larger than the planar projection area of the terminal portion.
By configuring in this way, it is possible to reduce variation in all connection resistances of the bump portions and the terminal portions arranged in a plurality of rows, and it is possible to reduce the conduction failure of the semiconductor element.

In configuring the electro-optical device of the present invention, the gaps between the plurality of bump portions and the terminal portions adjacent to each other in the direction orthogonal to the extending direction of the predetermined side are adjacent in the direction along the predetermined side. It is preferable that the size of the gap between the plurality of bump portions and the terminal portion is larger.
With this configuration, when a plurality of bump rows and terminal portions are arranged along the long side of the peripheral sides of the rectangular semiconductor element, the semiconductor element is displaced in the rotational direction. Even if it exists, it can prevent that the distance of the terminal part corresponding to the bump part adjacent to a predetermined bump part becomes too small. Therefore, it is possible to reduce the occurrence of a short circuit while making the planar projection areas of the second bump part and the terminal part smaller than the planar projection areas of the first bump part and the terminal part.

In configuring the electro-optical device of the present invention, the length of the bump portion constituting the first row and the direction perpendicular to the extending direction of the predetermined side of the terminal portion constitutes the second row. And it is preferable that it is longer than the length of the direction orthogonal to the extending direction of the predetermined | prescribed edge | side of a terminal part.
With this configuration, the planar projection area of the second bump portion and the terminal portion is relatively reduced while increasing the gap between the bump and the terminal portion adjacent to each other in the direction orthogonal to the extending direction of the predetermined side. can do.

In configuring the electro-optical device of the present invention, it is preferable that the plurality of bump portions and the terminal portions are arranged in a staggered manner.
With this configuration, it is possible to easily route the wiring connected to the terminal portion on the substrate side.

In configuring the electro-optical device according to the present invention, the plurality of bump portions are preferably output-side bump portions.
By configuring in this way, there is a relatively large number compared to the input-side bump portion, and in the output-side bump portion where it is highly necessary to prevent adjacent bump portions from contacting each other, Short circuit can be prevented and conduction failure can be reduced.

Another aspect of the present invention is an electro-optical device including an electro-optical device substrate on which a semiconductor element is mounted. The semiconductor element includes a plurality of bump portions, and the electro-optical device substrate includes a plurality of terminals. A plurality of bump portions and a plurality of terminal portions are electrically connected using an anisotropic conductive film containing conductive particles, and the plurality of bump portions and the terminal portions are disposed on a predetermined side of the semiconductor element. The first bump portion and terminal portion on the side far from the center of gravity of the planar shape of the semiconductor element, and the second bump portion and terminal portion on the side closer to the center of gravity of the planar shape of the semiconductor element than the first bump portion and terminal portion The planar projection areas of the second bump part and the terminal part are larger than the planar projection areas of the first bump part and the terminal part.
That is, the pressing force acting on the first bump portion on the side far from the center of gravity by relatively increasing the planar projection area of the plurality of bump portions and the terminal portion as the distance from the center of gravity of the planar shape increases. Can be reduced. In addition, the number of conductive particles interposed between the first bump portion and the terminal portion can be relatively increased, and an increase in connection resistance between the first bump portion and the terminal portion can be reduced. Accordingly, it is possible to provide an electro-optical device in which variation in connection resistance between all bump portions and terminal portions is suppressed and conduction failure of semiconductor elements is reduced.

Still another embodiment of the present invention is an electro-optical device substrate on which a semiconductor element is mounted using an anisotropic conductive film containing conductive particles, and the electro-optical device substrate is connected to the semiconductor element. A plurality of terminal portions, and the plurality of terminal portions form a plurality of terminal rows respectively arranged along a predetermined side of the semiconductor element to be connected, and the first terminal portion on the side close to the predetermined side and the first terminal portion And a second terminal portion farther from the predetermined side than the first terminal portion, and the planar projection area of the second terminal portion is larger than the planar projection area of the first terminal portion. It is.
That is, by reducing the planar projection area of the second terminal portion on the side far from the predetermined side of the semiconductor element to be mounted smaller than the planar projection area of the first terminal portion on the side close to the side, the semiconductor element It is possible to prevent the pressing force acting on the bump portion corresponding to the first terminal portion from being reduced when mounting. In addition, the number of conductive particles interposed between the first terminal portion and the bump portion of the semiconductor element can be relatively increased, and an increase in connection resistance between the first terminal portion and the bump portion is reduced. Can do. Therefore, it is possible to provide a substrate for an electro-optical device that can suppress variation in connection resistance between all the bump portions and the terminal portions and can reduce the conduction failure of the semiconductor element.

Still another embodiment of the present invention is an electro-optical device substrate on which a semiconductor element is mounted using an anisotropic conductive film containing conductive particles, and the electro-optical device substrate is connected to the semiconductor element. A plurality of terminal portions are provided, and the plurality of terminal portions are arranged on a predetermined side of the semiconductor element to be connected, the first terminal portion on the side farther from the center of gravity of the planar shape of the semiconductor element and the semiconductor than the first terminal portion. An electro-optical device substrate including a second terminal portion closer to the center of gravity of the planar shape of the element, wherein the planar projection area of the second terminal portion is larger than the planar projection area of the first terminal portion.
In other words, the plane projection area of the plurality of terminal portions is relatively increased as the distance from the center of gravity of the planar shape of the semiconductor element to be mounted becomes larger, so that it corresponds to the first terminal portion farther from the center of gravity. It is possible to prevent the pressing force acting on the bump portion to be reduced. Further, the number of conductive particles interposed between the first terminal portion and the bump portion of the semiconductor element can be relatively increased, and an increase in connection resistance between the first terminal portion and the bump portion is reduced. Can do. Accordingly, it is possible to provide an electro-optical device substrate in which variations in connection resistances between all bump portions and terminal portions are suppressed, and conduction defects of semiconductor elements are reduced.

According to still another aspect of the present invention, there is provided a semiconductor element including a plurality of bump portions as terminals and mounted using an anisotropic conductive film, wherein the plurality of bump portions are arranged along a predetermined side. A plurality of bump arrays arranged respectively, and including a first bump portion closer to the predetermined side and a second bump portion farther from the predetermined side than the first bump portion are active. This is a semiconductor element in which the planar projected area of the first bump portion viewed from the surface side is larger than the planar projected area of the second bump portion.
That is, by reducing the planar projection area of the second bump portion on the side far from the predetermined side where the plurality of bump rows are arranged, smaller than the planar projection area of the first bump portion on the side close to the side, the semiconductor It is possible to prevent the pressing force acting on the first bump portion from being reduced when the element is mounted. In addition, the number of conductive particles interposed between the first bump portion and the terminal portion on the substrate can be relatively increased, and an increase in connection resistance between the first bump portion and the terminal portion is reduced. Can do. Therefore, it is possible to provide a semiconductor element that can suppress variation in connection resistance between all bump portions and terminal portions and reduce conduction defects.

Further, another aspect of the present invention is a semiconductor element that includes a plurality of bump portions as terminals and is mounted using an anisotropic conductive film, wherein the plurality of bump portions are on a predetermined side, A first bump portion farther from the center of gravity of the planar shape of the semiconductor element, and a second bump portion closer to the center of gravity of the planar shape of the semiconductor element than the first bump portion, and from the active surface side This is a semiconductor device in which the planar projected area of the first bump portion as viewed is larger than the planar projected area of the second bump portion.
That is, by increasing the planar projected area of the plurality of bump portions relatively as the distance from the center of gravity of the planar shape increases, the first bump portion far from the center of gravity when mounting the semiconductor element is formed. It can prevent that the pressing force which acts is small. In addition, the number of conductive particles interposed between the first bump portion and the terminal portion can be relatively increased, and an increase in connection resistance between the first bump portion and the terminal portion can be reduced. Therefore, it is possible to provide a semiconductor element that can suppress variation in connection resistance between all bump portions and terminal portions and reduce conduction defects.

Still another embodiment of the present invention is an electronic apparatus including any of the electro-optical devices described above.
In other words, since the electro-optical device is provided in which the variation in connection resistance of the plurality of bump portions is suppressed and the occurrence of poor conduction is reduced, an electronic apparatus with few occurrences of malfunction can be obtained.

  In the present specification, the “planar projected area” means a projected area when viewed in a direction orthogonal to the active surface in a semiconductor element, and orthogonal to the substrate surface in an electro-optical device substrate or an electro-optical device. This is a concept that means a projected area when viewed in a direction.

  Hereinafter, exemplary embodiments of the electro-optical device, the substrate for the electro-optical device, the semiconductor element, and the electronic apparatus according to the invention will be described in detail with reference to the drawings. However, this embodiment shows one aspect of the present invention and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

[First Embodiment]
The first embodiment of the present invention is an electro-optical device including an electro-optical device substrate on which a semiconductor element is mounted.
In the electro-optical device according to the present embodiment, the semiconductor element includes a plurality of bump portions, the electro-optical device substrate includes a plurality of terminal portions, and the plurality of bump portions and the plurality of terminal portions are anisotropic including conductive particles. A plurality of bump portions and terminal portions are electrically connected using a conductive film, and each of the plurality of bump portions and the terminal portion forms a plurality of rows arranged along a predetermined side of the semiconductor element, and a first row closer to the predetermined side. And a second row farther from the predetermined side than the first row, and a bump projection and a terminal constituting the first row in terms of a planar projection area of the bump portion and the terminal portion constituting the second row It is characterized by being smaller than the planar projection area of the part.

Hereinafter, a liquid crystal device as an electro-optical device according to the first embodiment of the present invention will be described as an example with reference to FIGS. 1 to 12 as appropriate.
In addition, what attached | subjected the same code | symbol in each figure has shown the same member, and while abbreviate | omitting description suitably, the one part member is abbreviate | omitted suitably in each figure.

1. Overall Structure First, the overall structure of the liquid crystal device 10 according to the first embodiment of the present invention will be specifically described with reference to FIG. Here, FIG. 1 is a schematic perspective view of a liquid crystal device 10 according to the present embodiment. In FIG. 1, the upper surface is an image display surface.

  As shown in FIGS. 1 and 2, the liquid crystal device 10 according to the present embodiment includes a liquid crystal panel in which two substrates 30 and 60 each having electrodes are bonded together with a sealing material and a liquid crystal material is disposed in a cell region. 20 is provided. The lighting device 11 is disposed on the back side of the liquid crystal panel 20. The liquid crystal panel 20 and the illuminating device 11 are accommodated in a frame-shaped housing 1 made of plastic or the like, and are sandwiched and fixed by a metal frame 2 from the outside.

  In addition, the element substrate 60 constituting the liquid crystal panel 20 has a substrate extending portion 60 </ b> T that protrudes outward from the outer shape of the counter substrate 30. A connection terminal (not shown) is formed on the surface of the substrate extension 60T that holds the liquid crystal material, and the semiconductor element 91 and the flexible circuit board 93 are connected to the connection terminal. Yes. A light source 13 is mounted on the flexible circuit board 93, and the illumination device 11 is configured by the light source 13 and the light guide plate 15. The light emitted from the light source 13 is guided by the light guide plate 15 and is incident on the liquid crystal panel 20.

2. Liquid crystal panel As the liquid crystal panel 20, an active matrix type liquid crystal panel having a switching element such as a TFT element (Thin Film Transistor) or a TFD element (Thin Film Diode), or a passive matrix type liquid crystal having no switching element. Panels are typical. Among these, a configuration example of an active matrix type liquid crystal panel including a TFT element will be described.
FIG. 2 is a partial enlarged cross-sectional view of each pixel region of the active matrix type liquid crystal panel 20 having TFT elements. As shown in FIG. 2, the liquid crystal panel 20 includes an element substrate 60 that includes a TFT element as a switching element, and a counter substrate 30 that faces the element substrate 60 and includes a color filter 37. A polarizing plate 50 with a retardation film in which a retardation film 47 and a polarizing plate 49 are laminated is disposed on the outer surface (upper side in FIG. 2) of the counter substrate 30. Similarly, a polarizing plate 90 with a retardation film in which a retardation film 87 and a polarizing plate 89 are laminated is also disposed on the outer surface (lower side in FIG. 2) of the element substrate 60. The above-described lighting device (not shown) is disposed below the element substrate 60.

In the liquid crystal panel 20, the counter substrate 30 includes a color filter 37 composed of a plurality of colored layers 37 r, 37 g, and 37 b having different hues with a substrate 31 such as glass as a base, and a counter substrate 30 formed on the color filter 37. An electrode 33 and an alignment film 45 formed on the counter electrode 33 are provided. A transparent resin layer 41 is provided between the color filter 37 and the counter electrode 33 to optimize the retardation of each of the reflective region and the transmissive region.
Here, the counter electrode 33 is a planar electrode formed on the entire area of the counter substrate 30 with ITO (indium tin oxide) or the like. The color filter 37 includes a plurality of colored layers having hues of R (red), G (green), and B (blue), and pixel regions corresponding to the pixel electrodes 63 on the element substrate 60 facing each other are predetermined. It is provided so as to exhibit light of the hue. A light shielding film 39 is provided corresponding to a region corresponding to the gap between the pixel regions.
The alignment film 85 made of a polyimide-based polymer resin provided on the surface is subjected to a rubbing process as an alignment process.

Further, the element substrate 60 facing the counter substrate 30 is formed on a TFT element 69 as an active element functioning as a switching element, with a substrate 61 such as glass as a base, and a transparent insulating film 81 interposed therebetween. The pixel electrode 63 formed and an alignment film 85 formed on the pixel electrode 63 are provided.
Here, the pixel electrode 63 shown in FIG. 2 is formed as a light reflection film 79 (63a) for performing reflective display in the reflection region, and is formed as a transparent electrode 63b with ITO or the like in the transmission region. ing. The light reflecting film 79 as the pixel electrode 63a is formed of a light reflecting material such as Al (aluminum) or Ag (silver). However, the configuration of the pixel electrode and the light reflection film is not limited to the configuration as shown in FIG. 2, and the entire pixel electrode is formed using ITO or the like, and a reflection film using aluminum or the like as another member. It can also be set as the provided structure.
The alignment film 85 made of a polyimide-based polymer resin provided on the surface is subjected to a rubbing process as an alignment process.

The TFT element 69 includes a gate electrode 71 formed on the element substrate 60, a gate insulating film 72 formed on the entire area of the element substrate 60 on the gate electrode 71, and the gate insulating film 72 interposed therebetween. A semiconductor layer 70 formed above the gate electrode 71, a source electrode 73 formed on one side of the semiconductor layer 70 via a contact electrode 77, and a contact electrode 77 on the other side of the semiconductor layer 70. And a drain electrode 66 formed through the electrode.
The gate electrode 71 extends from the gate bus wiring (not shown), and the source electrode 73 extends from the source bus wiring (not shown). Further, a plurality of gate bus lines extend in the horizontal direction of the element substrate 60 and are formed in parallel in the vertical direction at equal intervals, and the source bus lines cross the gate bus lines with the gate insulating film 72 interposed therebetween. A plurality of lines extending in the vertical direction are formed in parallel in the horizontal direction at equal intervals.
Such a gate bus wiring is connected to a liquid crystal driving IC (not shown) and functions as, for example, a scanning line, while a source bus wiring is connected to another driving IC (not shown), for example, a signal line. Acts as
The pixel electrode 63 is formed in a region excluding a portion corresponding to the TFT element 69 in a rectangular region defined by the gate bus line and the source bus line intersecting each other. An area is configured.

Here, the gate bus wiring and the gate electrode can be formed of chromium, tantalum, or the like, for example. The gate insulating film is formed of, for example, silicon nitride (SiN _x ), silicon oxide (SiO _x ), or the like. Further, the semiconductor layer can be formed of, for example, doped a-Si, polycrystalline silicon, CdSe, or the like. Further, the contact electrode can be formed of, for example, a-Si, and the source electrode and the source bus wiring and the drain electrode integrated therewith can be formed of, for example, titanium, molybdenum, aluminum, or the like.

The organic insulating film 81 is formed over the entire area of the element substrate 60 so as to cover the gate bus lines, the source bus lines, and the TFT elements. However, a contact hole 83 is formed in a portion corresponding to the drain electrode 66 of the organic insulating film 81, and the pixel electrode 63 and the drain electrode 66 of the TFT element 69 are electrically connected at the contact hole 83.
In addition, in the organic insulating film 81, a resin film having a concavo-convex pattern composed of a regular or irregular repetitive pattern of peaks and valleys is formed as a scattering shape in a region corresponding to the reflective region R. Has been. As a result, the light reflection film 79 (63a) laminated on the organic insulating film 81 also has a light reflection pattern composed of an uneven pattern. However, this uneven pattern is not formed in the transmission region T.

In the liquid crystal panel having the above-described structure, external light such as sunlight and indoor illumination light enters the liquid crystal panel 20 from the counter substrate 30 side, and passes through the color filter 37 and the liquid crystal material 21 to reflect light. The film 79 reaches the film 79, is reflected there, passes through the liquid crystal material 21 and the color filter 37 again, and exits from the liquid crystal panel 20 to perform reflection display. On the other hand, the illuminating device is turned on, and light emitted from the illuminating device enters the liquid crystal panel 20, passes through the transparent electrode 63 b, and passes through the color filter 37, the liquid crystal material 21, and the like. Transparent display is performed by exiting 20.
Then, the light emitted from each pixel region is mixed and visually recognized, and various color displays are recognized as a color image as the entire display region.

3. Next, a semiconductor element mounting structure provided on the element substrate 60 constituting the liquid crystal panel 20 will be described in detail. 3 to 5 are diagrams for explaining the mounting structure of the semiconductor element 91. FIG. 3A is a plan view of the semiconductor element 91 as viewed from the side opposite to the active surface side, and FIG. 3B is a plan view of the semiconductor element mounting region 26 of the element substrate 60 as viewed from the mounting surface side. The figure is shown. 4 is an exploded perspective view of the glass substrate 61, the semiconductor element 91, and the anisotropic conductive film (hereinafter referred to as “ACF”) 100. FIG. 5 is a cross-sectional view of the mounting structure of the semiconductor element 91, and shows a cross-sectional view of the XX cross-section in FIG.

  As shown in FIGS. 3A and 4, the semiconductor element 91 includes a plurality of bump portions 96, 97 a, and 98 a that are electrically connected to the terminal portions 16, 17, and 18 on the element substrate 60 side. Yes. Each of the bump portions 96, 97a, 98a includes an output side bump portion 97a, 98a that outputs a signal to the gate bus wiring 65 and the source bus wiring 66, and an input side to which a drive signal from a CPU (not shown) is input. The bump portion 96 is included. The semiconductor element 91 used in the present embodiment is mounted on the glass substrate 61 using the ACF 100, and the conductive particles 102 included in the ACF 100 are crushed by all the bump portions 96, 97a, 98a to contact each other. The heights of all the bump portions 96, 97a, 98a are made equal so that the

  In the case of a conventional semiconductor element, the distance between the adjacent output side bump portions 97a and 98a and the distance between the adjacent input side bump portions 96 are secured about 5 to 7 times the particle diameter of the conductive particles. On the other hand, in the case of a semiconductor element having a reduced outer diameter size, it is about three times the particle size of the conductive particles. This is because, while reducing the outer diameter size of the semiconductor element 91, it is necessary to prevent the conductive particles from continuing to short-circuit adjacent bump portions or terminal portions on the substrate. These bump portions 96, 97a, 98a are configured as rectangular bump portions in which the surface of a metal layer such as Cu is plated with gold.

  On the other hand, as shown in FIG. 3B and FIG. 4, one end side of the gate bus wiring 65 and the source bus wiring 66 in the display area A is extended to the substrate extension 60 </ b> T of the element substrate 60. A wiring terminal portion 14 is formed at an end portion of the gate bus wiring 65 and the like. These wiring terminal portions 14 are electrically connected to the output-side bump portions 97a and 98a of the semiconductor element 91 so that a drive signal from the semiconductor element 91 is output. Further, on the side farther from the display area A than the wiring terminal portion 14, the terminal portion 18 to which the input side bump portion 96 of the semiconductor element 91 is electrically connected and the external to which the flexible circuit board 93 is electrically connected. A connection terminal portion 19 is formed. The terminal portion 18 and the external connection terminal portion 19 are electrically connected by a connection wiring 67.

In the substrate overhanging portion 60T, the gate bus wiring 65, the source bus wiring 66, and the connection wiring 67 are covered with an insulating film 94, and openings 94a are formed at positions corresponding to the respective terminal portions in the insulating film 94. Is formed (see FIG. 5). A conductive film 22 made of corrosion-resistant ITO is formed in the opening 94a of the insulating film 94 so that the metal material constituting the gate bus wiring 65 and the like is not corroded, and each terminal portion 16, 17, 18 is formed. It is configured as.
However, the configuration of the terminal portion is not limited to such an example.

In the mounting structure of the semiconductor element 91 provided in the present embodiment, as shown in FIG. 5, the semiconductor element 91 is mounted on the glass substrate 61 using the ACF 100, and each terminal portion 16 on the glass substrate 61. The bumps 97a of the semiconductor element 91 are electrically connected to each other through conductive particles 102 included in the ACF 100.
As a specific example of the mounting method, the ACF 100 is disposed between the glass substrate 61 and the semiconductor element 91 as shown in FIG. 6 and is included in the ACF 100 by pressing the semiconductor element 91 by the pressing head 111 of the thermocompression bonding apparatus 110. The conductive particles 102 are crushed and the adhesive 101 is solidified in a state where the conductive particles 102 are in contact with both the bump portions 113 and the terminal portions 114. In this way, the conductivity between the bump part 113 and the terminal part 114 is ensured.

Here, as shown in FIG. 3A, the output-side bump portions 97a and 98a of the semiconductor element 91 used in this embodiment are close to the side 91a arranged along the side 91a on the display area A side. The first output side bump row 97 on the side and the second output side bump row 98 far from the side 91a are arranged in a zigzag pattern as a whole. The planar projection area of the second output-side bump portion 98 a constituting the second output-side bump row 98 is equal to the planar projection area of the first output-side bump portion 97 a constituting the first output-side bump row 97. Has been smaller than. In the example of the semiconductor element 91 shown in FIG. 3A, the planar projection area of all the second output side bump portions 98 a constituting the second output side bump row 98 is the same as that of the first output side bump row 97. It is configured to be smaller than the planar projection area of all the first output side bump portions 97a to be configured.
Corresponding to the arrangement of the output-side bump portions 97a and 98a of the semiconductor element 91, the wiring terminal portions 14 on the glass substrate 61 are also arranged in a staggered manner. As for the planar projection area of the wiring terminal portion 14, the planar projection area of the second wiring terminal portion 17 to which the second output-side bump portion 98 a of the semiconductor element 91 is electrically connected is the second projection area of the semiconductor element 91. One output side bump portion 97a is configured to be smaller than the planar projection area of the first wiring terminal portion 16 to which the first wiring terminal portion 16 is electrically connected.

  Since the respective output side bump portions 97a and 98a and the wiring terminal portions 17 and 18 are configured in this way, when the semiconductor element 91 is pressed to be mounted using the ACF 100, the second output side bump portion is formed. The pressing force acting on 98a is reduced. Therefore, the pressing force acting on the first output side bump portion 97a can be relatively increased. Therefore, as in the prior art, the degree of crushing of the conductive particles 102 interposed between the first output-side bump portion 97a on the side close to the predetermined side 91a and the first wiring terminal portion 17 and the side far from the predetermined side 91a The crushing degree of the conductive particles 102 interposed between the second output-side bump portion 98a and the second wiring terminal portion 18 is not significantly different, and variation in connection resistance can be reduced.

  Furthermore, the planar projection area of the first output-side bump portion 97a on the side close to the predetermined side 91a is relatively smaller than the planar projection area of the second output-side bump portion 98a on the side far from the side 91a. Therefore, the number of conductive particles 102 that can exist between the first output-side bump portion 97a and the first wiring terminal portion 17 is determined by the second output-side bump portion 98a and the second wiring terminal portion 18. Can be relatively larger than the number of conductive particles 102 that can exist between the two. Therefore, it is assumed that the first output-side bump portion 97a and the first wiring terminal portion 17 are smaller than the degree of collapse of the conductive particles 102 between the second output-side bump portion 98a and the second wiring terminal portion 18. Even when the degree of crushing of the conductive particles 102 between them is small, the contact area as a whole can be earned, and the increase in connection resistance can be reduced.

  Describing conceptually, as shown in FIG. 7, the degree of collapse of the conductive particles 102b corresponding to the second output-side bump part 98a is greater than the degree of collapse of the conductive particles 102a corresponding to the first output-side bump part 97a. The first output-side bump is large when the contact area of the conductive particles 102b with respect to the second output-side bump portion 98a or the second wiring terminal portion 18 is 2 (relative value) and the connection resistance is 1 (Ω). It is assumed that the contact area of the conductive particles 102a with respect to the portion 97a or the first wiring terminal portion 17 is 1 (relative value) and the connection resistance is 2 (Ω). At this time, although there is a difference in the contact area between the individual conductive particles 102a and 102b and the bump portions 97a and 98a or the wiring terminal portions 17 and 18, the second output-side bump portion 98a and the second wiring terminal portion 18 are different. If the number of conductive particles 102b interposed between the first output side bump portion 97a and the first wiring terminal portion 17 is four, The total contact area is 4 and equal. Therefore, the electrical connection resistance of the first output side bump part 97a and the first wiring terminal part 17 and the electrical connection resistance of the second output side bump part 98a and the second wiring terminal part 18 are as follows. It will be made uniform.

As described above, as an example in which the planar projection area of the second output side bump portion on the side far from the predetermined side is relatively smaller than the planar projection area of the first output side bump portion on the side close to the predetermined side. Examples include those shown in FIGS. 8A to 8C.
FIG. 8A shows the length of the second output side bump portion 98a in the direction along the predetermined side 91a (X direction) and the length of the first output side bump portion 97a in the direction along the X direction. This is an example in which the planar projection area is varied by shortening the length. FIG. 8B shows the length of the second output side bump portion 98a along the direction (Y direction) orthogonal to the X direction as the first output side bump portion 97a in the direction along the Y direction. This is an example in which the planar projection area is made different by making it shorter than the length of. FIG. 8C shows a plan view by making the lengths of both the second output side bump portions 98a along the X direction and the Y direction shorter than the lengths of both the first output side bump portions 97a. This is an example in which the projected areas are different.
Further, although not shown, the first output-side bump portion 97a and the second output-side bump portion 98a can be arranged in a staggered manner with different plane projection areas as described above.

The present invention can be configured in any of these modes, but the position of the bump part and the position of the wiring terminal part are relatively shifted so that the adjacent bump part and the wiring terminal part are short-circuited. As shown in FIG. 8A, it is preferable to shorten the length of the second output-side bump portion 98a in the direction along the Y direction.
More specifically, the alignment performed when mounting the semiconductor element is performed using the alignment mark formed in the mounting region 26 of the glass substrate 61 and the alignment mark formed in the semiconductor element 91 in the XY direction. Alignment is performed. Therefore, as shown in FIG. 9, when the position of the semiconductor element 91 is shifted by θ in the rotation direction, the positional shift in the Y direction is larger than that in the X direction. Therefore, as shown in FIG. 8A, the length of the second output side bump portion 98a in the Y direction is shortened, and the distance (first number) between the first output side bump portion 97a and the second output side bump portion 98a. By securing a large distance between the first output-side bump row 97 and the second output-side bump row 98, it is possible to prevent a short circuit between the bump portion and the wiring terminal portion adjacent in the Y direction.
In addition, since the distance between the first output-side bump portion 97a and the second output-side bump portion 98a is ensured as described above, it is difficult to perform laser cutting when forming the data bus wiring and the source bus wiring. Can also be prevented.

  In the example shown in FIG. 3, the plurality of output-side bump portions 97a and 98a and the plurality of wiring terminal portions 14 are arranged in a staggered manner as a whole. With such an arrangement, it is possible to provide a margin in the wiring design for drawing out the gate bus wiring 65 and the source bus wiring 66 to a predetermined side.

  The output-side bump portions 97a and 98a are arranged in a plurality in this way and have a configuration in which the plane projection areas are different so as to satisfy a predetermined relationship. Since the number of the bumps 97a and 98a on the output side is all connected to different gate bus lines 65 or source bus lines 66, the connection resistance at each connection point is reduced. Because it is necessary to keep. That is, since the plurality of terminal portions 18 to which the plurality of input side bump portions 96 are connected are provided with a plurality of terminal portions having a certain common function, the connection resistance of some of the input side bump portions 96 is reduced. This is because the connection resistance can be easily kept low if a plurality of terminal portions having a certain function are viewed as a whole even if they are lowered. Therefore, it is preferable to change the plane projection area so as to satisfy the predetermined relationship, particularly on the output side bump portions 97a and 98a side.

4). The present invention is not limited to the configuration of the semiconductor element mounting structure described so far, and various modifications can be made.
In the configuration example described above, the planar projection areas of all the second output-side bump portions constituting the second output-side bump row are equal to all the first output-side bump portions constituting the first output-side bump row. Is smaller than the projected area of the first output-side bump portion, in other words, the first projected-side bump portion is partially smaller than the projected area of the first output-side bump portion. The planar projection area of the output-side bump part may be larger than the planar projection area of the second output-side bump part. For example, as shown in FIG. 10, the planar output area of the first output-side bump portion 97 b is set to the second output-side bump portion in a region near the corner portion 91 b of the semiconductor element 91 where the applied pressing force tends to be small. It can be larger than the planar projection area of 98b.

In addition, the above-described configuration example includes a bump portion having a two-row configuration including a first output-side bump row and a second output-side bump row. However, as shown in FIG. The bump portions 97a, 98a, and 99a having a three-row configuration including the bump row 99 may be used. In this case, the second output-side bump portion 98a constituting the second output-side bump row 98 is larger than the plane projection area of the first output-side bump portion 97a constituting the first output-side bump row 97. Further, the planar projection area of the third output-side bump portion 99a constituting the third output-side bump row 99 is smaller than the planar projection area of the second output-side bump portion 98. Is done.
With this configuration, the projected area on the output side bump portions 97a, 98a, and 99a gradually increases as the predetermined side 91a is approached, and variation in connection resistance between each bump portion and the wiring terminal portion is reduced. Can do.

  Furthermore, the configuration example described above is an example of the output-side bump portions 97a and 98a arranged in a plurality of rows along the side 91a on the display area A side in the semiconductor element 91. As shown in FIG. Bump portions 92 are arranged in a plurality of rows on the side 91c side that is continuous from 91a and extends in the vertical direction, and the planar projection area of the second bump portion 92b far from the side 91c is closer to the side 91c. It is also possible to make it smaller than the planar projection area of the first bump portion 92a.

  In addition, the configuration of the semiconductor element mounting structure described so far is related to the connection configuration between the output-side bump portion of the semiconductor element and the wiring terminal portion on the substrate side. Depending on the outer diameter size, even the input-side bump can be configured similarly. In general, the number of input-side bumps is smaller than the number of output-side bumps. For example, in order to reduce the external size of a semiconductor element, the output-side bumps have a three-row configuration and input-side bumps. When the portions are configured in two rows, the gap between the input-side bump portions may be narrowed. Therefore, by applying the present invention, conduction failure can be reduced.

[Second Embodiment]
The second embodiment is a liquid crystal device similar to the first embodiment, and the plurality of bump portions and terminal portions are far from the center of gravity of the planar shape of the semiconductor element on a predetermined side of the semiconductor element. A first bump part and a terminal part on the side, and a second bump part and a terminal part on the side closer to the center of gravity of the planar shape of the semiconductor element than the first bump part and the terminal part, In this liquid crystal device, the planar projection area of the terminal portion is smaller than the planar projection areas of the first bump portion and the terminal portion.
Hereinafter, the description will focus on the points different from the first embodiment, and the description of the points that can be configured in the same manner as the other first embodiments will be omitted.

1. FIG. 13 is a plan view of the semiconductor element 191 and the substrate 161 that constitute the mounting structure of the semiconductor element 191 provided in the liquid crystal device of this embodiment. FIG. 13 corresponds to FIG. 3 in the first embodiment.
As shown in FIG. 13A, the output-side bump portion 196 of the semiconductor element 191 used in the present embodiment is on the side 191 a side near the display area A, on the side far from the center of gravity P of the planar shape of the semiconductor element 191. The first output side bump part 197a and the second output side bump part 198a closer to the center of gravity P of the planar shape of the semiconductor element 191 than the first output side bump part 191a are included. The plane projection area of the second output side bump portion 198a is smaller than the plane projection area of the first output side bump portion 197a. In the example of the semiconductor element 191 shown in FIG. 13A, all the bump portions 197a and 198a on the predetermined side 191a side gradually become closer to the center of gravity P of the planar shape of the semiconductor element 191, and the output side bump portions 197a and 198a. The planar projection area is reduced. In other words, all the output-side bump portions 197a and 198a on the predetermined side 191a side are configured such that the planar projection areas of the output-side bump portions 197a and 198a gradually increase as the distance from the planar center of gravity P of the semiconductor element 191 increases. Has been.

  Further, the wiring terminal portions 116 and 117 on the glass substrate 161 are also gradually wired as they approach the center of gravity P ′ of the mounting region 126 of the semiconductor element 191 corresponding to the output side bump portions 197a and 198a provided in the semiconductor element 191. The planar projected areas of the terminal portions 116 and 117 are reduced, in other words, the projected planar areas of the wiring terminal portions 116 and 117 are gradually increased as the distance from the center of gravity P ′ of the mounting region 126 of the semiconductor element 191 increases. ing.

  The output-side bump portions 197a and 198a and the wiring terminal portions 116 and 117 are configured in this manner, so that when the semiconductor element 191 is pressed to be mounted using an ACF (not shown), the semiconductor element The pressing force acting on the first output-side bump portion 197a located at a position away from the center of gravity P of the plane shape 191 is reduced, and the pressing force acting on the first output-side bump portion 197a is reduced. Can be prevented. Therefore, as in the prior art, the conductive particles (not shown) are crushed between the first output-side bump portion 197a and the first wiring terminal portion 116 on the side far from the center of gravity P of the planar shape of the semiconductor element 191. The degree of crushing of conductive particles (not shown) interposed between the second output side bump portion 198a and the second wiring terminal portion 117 on the side close to the center of gravity P is not significantly different, and the connection resistance is reduced. Variations can be reduced.

  Furthermore, the planar projection area of the first output-side bump part 197a far from the center of gravity P is relatively larger than the planar projection area of the second output-side bump part 198a near the center of gravity P. From the second output side bump portion 198a and the second wiring terminal portion, the number of conductive particles (not shown) that can exist between the first output side bump portion 197a and the first wiring terminal portion 116 is determined. The number can be relatively larger than the number of conductive particles (not shown) that can exist between the first and second layers. For this reason, it is assumed that the first output-side bump portion 197a and the first wiring terminal portion 116 are less than the degree of collapse of the conductive particles between the second output-side bump portion 198a and the second wiring terminal portion 117. Even when the degree of crushing of the conductive particles between them is small, the contact area as a whole can be earned, and the increase in connection resistance can be reduced.

  Thus, the planar projection area of the second output-side bump part 198a on the side close to the center of gravity P of the planar shape is relatively smaller than the planar projection area of the first output-side bump part 197a far from the center of gravity P. There is no particular limitation on the mode to be performed, and a configuration similar to that illustrated in the first embodiment can be employed.

2. Modifications Also in the present embodiment, the present invention is not limited to the configuration of the semiconductor element mounting structure described above, and various modifications can be made.
For example, the above-described configuration example includes a two-row bump section including a first output-side bump row and a second output-side bump row. As shown in FIG. A bump portion having a three-row configuration including the bump row 199 may be used. Also in this case, the planar projected area of the output-side bump portion is gradually increased as the distance from the planar center of gravity P of the semiconductor element 191 increases. As a result, it is possible to reduce variation in connection resistance between each output-side bump portion and the wiring terminal portion.
Similarly to the first embodiment, the present invention can be applied even to input side bumps depending on the number of input side bump portions and the outer diameter size of the semiconductor element.

[Third Embodiment]
As a third embodiment according to the present invention, an electronic apparatus including the liquid crystal device according to the first embodiment or the second embodiment will be specifically described.

FIG. 15 is a schematic configuration diagram showing the overall configuration of the electronic apparatus of the present embodiment. The electronic apparatus includes a liquid crystal panel 20 provided in the liquid crystal device and a control unit 200 for controlling the liquid crystal panel 20. In FIG. 15, the liquid crystal panel 20 is conceptually divided into a panel structure 20a and a drive circuit 20b composed of a semiconductor element (IC) or the like. The control means 200 preferably includes a display information output source 201, a display processing circuit 202, a power supply circuit 203, and a timing generator 204.
The display information output source 201 includes a memory composed of a ROM (Read Only Memory), a RAM (Random Access Memory), etc., a storage unit composed of a magnetic recording disk, an optical recording disk, etc., and a tuning that outputs a digital image signal in a synchronized manner. It is preferable that the display information is supplied to the display processing circuit 202 in the form of an image signal or the like of a predetermined format based on various clock signals generated by the timing generator 204.

The display processing circuit 202 includes various well-known circuits such as a serial-parallel conversion circuit, an amplification / inversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and executes processing of input display information to display the image. Information is preferably supplied to the driving circuit 20b together with the clock signal CLK. Furthermore, the drive circuit 20b preferably includes a first electrode drive circuit, a second electrode drive circuit, and an inspection circuit. Further, the power supply circuit 203 has a function of supplying a predetermined voltage to each of the above-described components.
If the electronic device according to the present embodiment includes a semiconductor element mounting structure in which the planar projection areas of the bump portions are different so as to satisfy a predetermined relationship, an electronic device with less conduction failure of the semiconductor element and can do.

  According to the present invention, it is possible to provide an electro-optical device and an electronic apparatus that have a semiconductor device with few conduction defects by including a semiconductor element mounting structure in which the planar projection areas of the bump portions are different so as to satisfy a predetermined relationship. be able to. Therefore, electro-optical devices and electronic devices such as liquid crystal devices and electroluminescence devices, such as mobile phones and personal computers, liquid crystal televisions, viewfinder type / monitor direct view type video tape recorders, car navigation devices, pagers, Electrophoresis devices, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, electronic devices with touch panels, devices with electron-emitting devices (FED: Field Emission Display and SCEED: Surface-Conduction Electron-Emitter Display) ) And so on.

1 is a schematic perspective view of a liquid crystal device according to a first embodiment. It is a schematic sectional drawing of the pixel area | region part of the liquid crystal device concerning 1st Embodiment. It is a top view of the semiconductor element and element substrate which are used for the liquid crystal device of a 1st embodiment. It is an exploded view for demonstrating the structure of the mounting structure of a semiconductor element. It is sectional drawing for demonstrating the structure of the mounting structure of a semiconductor element. It is a figure for demonstrating the mounting method of the semiconductor element using an anisotropic conductive film. It is a figure for demonstrating the effect | action of this invention. It is a figure which shows the structural example of the 1st and 2nd bump part which varied the planar projection area. It is a figure which shows the state which the position shift of the semiconductor element produced. It is a figure which shows the modification which varied the planar projection area of the one bump part of the 1st bump row | line | column and the 2nd bump row | line | column. It is a figure which shows the modification which applied the mounting structure of the semiconductor element of 1st Embodiment to the semiconductor element provided with the bump part of 3 rows structure. It is a figure which shows the modification which applied this invention in the bump part arranged in multiple rows along the edge | side of the side orthogonal to the edge | side of the display area side. It is a top view of the semiconductor element and element substrate which are used for the liquid crystal device of a 2nd embodiment. It is a figure which shows the modification which applied the mounting structure of the semiconductor element of 2nd Embodiment to the semiconductor element provided with the bump part of 3 rows structure. It is a block diagram which shows schematic structure of the electronic device of 3rd Embodiment. It is a figure which shows the structure of the bump part of the conventional semiconductor element.

Explanation of symbols

10: liquid crystal device (electro-optical device), 11: illumination device, 13: light source, 14: wiring terminal portion, 15: light guide plate, 16: first wiring terminal portion, 17: second wiring terminal portion, 18: Terminal part, 19: External connection terminal part, 20: Liquid crystal panel, 21: Liquid crystal material, 22: Conductive film, 23: Seal material, 26: Semiconductor mounting region, 30: Color filter substrate, 31: Glass substrate, 33: Planar electrode (counter electrode), 37: colored layer, 41: resin layer, 45: alignment film, 60: element substrate (substrate for electro-optical device), 60T: substrate overhanging part, 61: glass substrate, 63: pixel Electrode, 65: Gate bus wiring, 66: Source bus wiring, 67: Connection wiring, 69: TFT element, 75: Alignment film, 91: Semiconductor element, 91a / 91c: Side of semiconductor element, 91b: Corner part, 93: Flexible circuit board, 94: Insulating film 94a: Opening portion, 96: Input side bump portion, 97: First output side bump row, 97a: First output side bump portion, 98: Second output side bump row, 98a: Second output side bump row Part: 99: third output side bump row, 99a: third output side bump part, 100: ACF (anisotropic conductive film), 101: adhesive, 102: conductive particles, 161: substrate, 191: semiconductor Element, 191a / 191c: Side of semiconductor element, 196: Input side bump portion, 197: First output side bump row, 197a: First output side bump portion, 198: Second output side bump row, 198a: 2nd output side bump part, 199: 3rd output side bump row, 199a: 3rd output side bump part

Claims (12)

In an electro-optical device including an electro-optical device substrate on which a semiconductor element is mounted,
The semiconductor element includes a plurality of bump portions, the electro-optical device substrate includes a plurality of terminal portions, and the plurality of bump portions and the plurality of terminal portions use an anisotropic conductive film containing conductive particles. Electrically connected,
The plurality of bump portions and the terminal portion form a plurality of rows respectively arranged along a predetermined side of the semiconductor element, and are closer to the first row and the first row closer to the predetermined side. A second row far from the predetermined side,
An electro-optical device, wherein a planar projection area of a bump portion and a terminal portion constituting the second row is smaller than a planar projection area of a bump portion and a terminal portion constituting the first row.   Of the plurality of rows, the planar projection areas of all the bump portions and terminal portions constituting the first row are larger than the planar projection areas of all the bump portions and terminal portions constituting the second row. The electro-optical device according to claim 1.   The gaps between the plurality of bump portions and terminal portions adjacent to each other in the direction along the predetermined side are adjacent to each other in the direction perpendicular to the extending direction of the predetermined sides. The electro-optical device according to claim 1, wherein the electro-optical device is larger than the size of the electro-optical device.   The length in the direction perpendicular to the extending direction of the predetermined side of the bump part and the terminal part constituting the first row is the extension of the predetermined side of the bump part and the terminal part constituting the second row. The electro-optical device according to claim 1, wherein the electro-optical device is longer than a length in a direction orthogonal to the current direction.   The electro-optical device according to claim 1, wherein the plurality of bump portions and the terminal portions are arranged in a staggered manner.   The electro-optical device according to claim 1, wherein the plurality of bump portions are output-side bump portions. In an electro-optical device including an electro-optical device substrate on which a semiconductor element is mounted,
The semiconductor element includes a plurality of bump portions, the electro-optical device substrate includes a plurality of terminal portions, and the plurality of bump portions and the plurality of terminal portions use an anisotropic conductive film containing conductive particles. Electrically connected,
The plurality of bump portions and terminal portions are arranged on a predetermined side of the semiconductor element, the first bump portion and terminal portion on the side far from the center of gravity of the planar shape of the semiconductor element, and the first bump portion and terminal portion. A second bump part and a terminal part closer to the center of gravity of the planar shape of the semiconductor element than
An electro-optical device, wherein the planar projection areas of the second bump part and the terminal part are smaller than the planar projection areas of the first bump part and the terminal part. In the substrate for an electro-optical device on which a semiconductor element is mounted using an anisotropic conductive film containing conductive particles,
The electro-optical device substrate includes a plurality of terminal portions connected to the semiconductor element,
The plurality of terminal portions form a plurality of terminal rows respectively arranged along a predetermined side of the semiconductor element to be connected, and the first terminal portion and the first terminal portion on the side close to the predetermined side A second terminal portion farther from the predetermined side than the predetermined side,
An electro-optical device substrate, wherein a planar projection area of the second terminal portion is smaller than a planar projection area of the first terminal portion. In the substrate for an electro-optical device on which a semiconductor element is mounted using an anisotropic conductive film containing conductive particles,
The electro-optical device substrate includes a plurality of terminal portions connected to the semiconductor element,
The plurality of terminal portions are arranged on a predetermined side of the semiconductor element to be connected, the first terminal portion on the side farther from the center of gravity of the planar shape of the semiconductor element and the semiconductor element than the first terminal portion. A second terminal portion on the side close to the center of gravity of the planar shape,
An electro-optical device substrate, wherein a planar projection area of the second terminal portion is smaller than a planar projection area of the first terminal portion. In a semiconductor element that includes a plurality of bump portions as terminals and is mounted using an anisotropic conductive film,
The plurality of bump portions form a plurality of bump rows respectively arranged along a predetermined side, and the first bump portion closer to the predetermined side and the predetermined side than the first bump portion. And a second bump portion on the side far from the
A semiconductor element, wherein a planar projection area of the second bump portion viewed from the active surface side is smaller than a planar projection area of the first bump portion. In a semiconductor element that includes a plurality of bump portions as terminals and is mounted using an anisotropic conductive film,
The plurality of bump portions are on a predetermined side, on the side farther from the center of gravity of the planar shape of the semiconductor element, and on the side closer to the center of gravity of the planar shape of the semiconductor element than the first bump portion And a second bump portion of
A semiconductor element, wherein a planar projection area of the second bump portion viewed from the active surface side is smaller than a planar projection area of the first bump portion.   An electronic apparatus comprising the electro-optical device according to claim 1.

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