JP2008166560A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further reduce the scale of a semiconductor device comprising a MOS transistor and a Schottky barrier diode on the same semiconductor substrate as compared with a conventional device.
On a semiconductor substrate, a first conductivity type first well, a second conductivity type second well different from the first conductivity type, and a second conductivity type third well are provided. A first MOS transistor T1 is provided on the second well 4, a second MOS transistor T2 is provided on the first well 3, and a first Schottky barrier diode D1 is provided on the third well 5. A refractory metal silicide film (51-58) is formed on the electrode of each element.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a MOS transistor and a Schottky barrier diode on the same semiconductor substrate and a manufacturing method thereof.

  Schottky barrier diodes, in which a metal layer is provided on a semiconductor substrate and a Schottky junction structure is formed at the contact interface between the metal layer and the semiconductor layer, do not use minority carriers. Has a property of high speed and low forward voltage and low power consumption. For this reason, it is used for standard logic ICs, power supply circuits, and the like.

  As a method of forming such a Schottky barrier diode on the same semiconductor substrate as a MOS transistor, conventionally, after forming a MOS transistor, the interlayer insulating film on a predetermined electrode formation region is etched to form a semiconductor through a contact hole. After exposing the substrate surface and implanting high-concentration impurity ions into the exposed surface, the interlayer insulating film on a predetermined Schottky junction formation region is etched to expose the semiconductor substrate surface through the contact hole, and then A method of forming a Schottky junction at the interface between a semiconductor substrate surface and a metal film in a Schottky junction formation region by depositing a metal film on the substrate is conventionally disclosed (for example, see Patent Document 1). In this case, if the semiconductor substrate is N-type, a Schottky barrier diode is formed in which the metal film side on the Schottky junction formation region is an anode electrode and the metal film on the electrode formation region is a cathode electrode. Become.

  When performing a step of implanting high-concentration impurity ions to form a conductive region for taking out one electrode (a cathode electrode in the above example) of a Schottky barrier diode as in the method described in Patent Document 1, Since an interlayer insulating film is deposited on the Schottky junction formation region for forming the key junction, high concentration impurity ions are not implanted into the region, thereby affecting the characteristics of the Schottky junction. A Schottky barrier diode can be formed without any problem. Further, since the MOS transistor and the Schottky barrier diode are formed over the same substrate, the semiconductor device can be highly integrated.

JP-A-2-125463

  However, in the case of the method described in Patent Document 1, since the impurity ion implantation process and the metal film deposition process for forming the Schottky barrier diode are performed after the contact hole is formed, the element characteristics of the Schottky barrier diode are obtained. In order to fit within the range of the design stage, it is necessary to correctly form contact holes in a predetermined region. For this purpose, it is necessary to form a contact hole having a sufficiently large hole diameter in consideration of errors during the etching process so that the contact hole is correctly formed in the region. However, in order to form a contact hole having a hole diameter as described above, it is necessary to secure a certain distance between elements, which is contrary to the trend of high integration. Become.

  In view of the above problems, the present invention is a semiconductor device including a MOS transistor and a Schottky barrier diode on the same semiconductor substrate, and an object of the present invention is to further reduce the scale of the device as compared with a conventional device. And Another object of the present invention is to provide a manufacturing method for manufacturing such a semiconductor device.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising a MOS transistor and a Schottky barrier diode on a semiconductor substrate, wherein the element isolation insulation is provided on the semiconductor substrate. A first conductivity type first well and a second conductivity type different from the first conductivity type are formed by forming an active region separated by a film and implanting low concentration impurity ions into a predetermined region on the semiconductor substrate. Active regions for forming MOS transistors are formed on the first well and the second well, respectively, and an element region is formed on the third well. A first step of forming two regions of a first diode electrode formation region and a second diode electrode formation region separated by an isolation insulating film; and after the first step, a gate is formed on the semiconductor substrate After the gate electrode film is deposited through the edge film, the first gate electrode serving as the gate electrode of the first MOS transistor is formed on the first well in a predetermined region on the second well by patterning into a predetermined shape. A second step of forming a second gate electrode to be a gate electrode of the second MOS transistor in the predetermined region, and after the second step, with respect to the first well and the second diode electrode formation region, By implanting the second conductivity type high-concentration impurity ions, a second source / drain diffusion region and a diffusion region for a diode electrode, which become a source / drain diffusion region of the second MOS transistor, are formed, and the second well The first conductivity type high-concentration impurity ions are implanted into the first MOS transistor, thereby forming a first source / drain diffusion region of the first MOS transistor. A third step of forming a source / drain diffusion region; and after completion of the third step, at least the first gate is implanted by implanting a rare gas element or an ion composed of the same element as the semiconductor substrate. A fourth step of amorphizing the surface of any one of the electrode, the first source / drain diffusion region, the second gate electrode, the second source / drain diffusion region, and the diode electrode diffusion region; And after the completion of the fourth step, a refractory metal film is deposited on the entire surface of the semiconductor substrate to form a Schottky junction at the interface between the first diode electrode formation region and the refractory metal film, The refractory metal film side of the Schottky junction is used as a first diode electrode, and the first diode electrode formation region side of the Schottky junction and the diffusion region for the diode electrode are used. A fifth step of forming a first Schottky barrier diode using the refractory metal film formed in contact with the second diode electrode forming region to be electrically connected as a second diode electrode; and after the fifth step, By performing annealing treatment, at least one of the first gate electrode, the first source / drain diffusion region, the second gate electrode, the second source / drain diffusion region, and the diffusion region for the diode electrode And a sixth step of removing the unreacted refractory metal film after siliciding the interface between the one region and the refractory metal film.

  According to the first feature of the method of manufacturing a semiconductor device according to the present invention, when manufacturing a semiconductor device including each element of the first MOS transistor, the second MOS transistor, and the first Schottky barrier diode on the same substrate, An interlayer insulating film is formed after the source / drain diffusion region, the diode electrode diffusion region, and the refractory metal silicide film are formed, and it is not necessary to form contact holes for ion implantation and metal film deposition. Therefore, unlike the conventional method, it is not necessary to form a contact hole having a sufficient hole diameter in consideration of an etching error in order to keep the element characteristics within the range of the design stage, so that the distance between the elements can be reduced. . Thereby, the integration degree can be further increased.

  In addition, since a refractory metal silicide film is formed at the interface of the diffusion region or the interface of the gate electrode, the resistance during conduction is reduced. As a result, high integration can be achieved while suppressing an increase in resistance value when forming an electrical connection with the diffusion region or the gate electrode.

  In the fourth step, ions implanted for amorphization are rare gas elements or ions composed of the same element as the semiconductor substrate, and do not exhibit P-type or N-type characteristics. Therefore, even if the ions are implanted into the first diode electrode formation region, the electrical characteristics of the first diode electrode formation region are not affected. For this reason, it does not affect the electrical characteristics of the Schottky junction subsequently formed in the region, in other words, it does not affect the characteristics of the first Schottky barrier diode formed on the same substrate. Integration can be achieved.

  The semiconductor device manufacturing method according to the present invention has a second feature that, in addition to the first feature, the fourth step is a step of performing ion implantation on the entire surface of the semiconductor substrate.

  As described above, the constituent elements of the ions implanted in the fourth step are elements that do not exhibit P-type or N-type characteristics, and thus do not affect the conductivity type of each diffusion region. Therefore, as in the second feature of the method of manufacturing a semiconductor device according to the present invention, even when ion implantation is performed on the entire surface of the substrate, the conductivity type of each diffusion region including the first diode electrode formation region is changed. Since the diffusion region interface or the gate electrode interface can be made amorphous without affecting the electrical characteristics of the first Schottky barrier diode, that is, the number of processes can be reduced. .

  In the semiconductor device manufacturing method according to the present invention, in addition to the first or second feature, the second well and the third well are electrically insulated in the first step. This is the third feature.

  Further, in addition to any one of the first to third features, the method of manufacturing a semiconductor device according to the present invention further includes an edge portion of the first diode electrode formation region in the third step. A fourth feature is that a PN junction is formed in the first diode electrode formation region by implanting the high-concentration impurity ions of the first conductivity type.

  According to the fourth feature of the semiconductor device manufacturing method of the present invention, the semiconductor device is formed in a contact region between the third well and the refractory metal film or the refractory metal silicide film formed on the well 3. A rectifying action in the same direction as the rectifying direction of the Schottky junction can be formed adjacent to the Schottky junction forming portion. Thereby, the rectifying action of the Schottky barrier diode can be complementarily enhanced.

  The semiconductor device according to the present invention includes a first well of a first conductivity type, a second well of a second conductivity type different from the first conductivity type, and a third well of the second conductivity type on a semiconductor substrate. A first diode electrode formation region provided with a well in a state where a surface vicinity region in each well is separated by an element isolation insulating film, and separated by an element isolation insulating film in a surface vicinity region in the third well And a second diode electrode formation region, and a diode electrode diffusion region is formed in the second diode electrode formation region by high-concentration impurity ion implantation of the second conductivity type. A first gate insulating film and a first gate electrode that are sequentially formed in a predetermined region from the bottom, and at least a region of the first conductivity type in a region near the surface in the second well on the outer side in the vicinity of the lower region of the first gate electrode. High concentration A first MOS transistor having a first source / drain diffusion region formed by pure ion implantation; a second gate insulating film formed in a predetermined region on the first well; 2 gate electrodes and a second source / drain diffusion region formed by high concentration impurity ion implantation of the second conductivity type in a region near the surface in the first well at least near the lower region of the first gate electrode A refractory metal film or a refractory metal silicide film formed so as to be in contact with the upper surface of the first diode electrode formation region as a first diode electrode, and the diode electrode A first shot in which a refractory metal film or a refractory metal silicide film formed so as to be in contact with the upper surface of the diffusion region for use is a second diode electrode A barrier diode, and at least any of the first gate electrode, the first source / drain diffusion region, the second gate electrode, the second source / drain diffusion region, and the diode electrode diffusion region A first feature is that a refractory metal silicide film is formed at the interface of the one region.

  According to the first characteristic configuration of the semiconductor device according to the present invention, each element of the first MOS transistor, the second MOS transistor, and the first Schottky barrier diode is provided on the same substrate, and any one of these elements or By providing the refractory metal silicide film on all the electrodes, the resistance in the diffusion region or the gate electrode can be reduced. Therefore, high integration can be achieved while suppressing an increase in resistance value when forming an electrical connection with the diffusion region or the gate electrode.

  In addition to the first characteristic configuration, the semiconductor device according to the present invention has a second characteristic that the second well and the third well are electrically insulated.

  In addition to the first or second characteristic configuration, the semiconductor device according to the present invention may have at least a part of the upper surface of the refractory metal film or the high-temperature metal at the edge portion of the first diode electrode formation region. A third feature is that the first conductive type high-concentration diffusion region is in contact with the melting point metal silicide film, and a PN junction is formed in the first diode electrode formation region.

  According to the third characteristic configuration of the semiconductor device according to the present invention, the shot formed in the contact region between the third well and the refractory metal film or the refractory metal silicide film formed on the third well. A rectifying action in the same direction as the rectifying direction of the key junction can be formed adjacent to the location where the Schottky junction is formed. Thereby, the rectifying action of the Schottky barrier diode can be complementarily enhanced.

  According to the configuration of the present invention, the device scale of a semiconductor device including a MOS transistor and a Schottky barrier diode on the same substrate can be reduced.

  In the following, an embodiment of a semiconductor device according to the present invention (hereinafter referred to as “the present invention apparatus” as appropriate) and a manufacturing method thereof (hereinafter referred to as “the present invention method” as appropriate) will be described with reference to FIG. .

[Description of the device of the present invention]
FIG. 1 is a structural diagram showing a schematic configuration of the apparatus of the present invention, in which FIG. 1 (a) shows a sectional structural view, and FIG. 1 (b) shows a planar structural view. FIG. 1A shows a cross-sectional structure when the device of the present invention is cut along the line XX ′ in FIG. In FIG. 1B, for convenience of explanation, a part of the structure such as an interlayer insulating film is omitted.

  FIG. 1 schematically shows the structure of the apparatus of the present invention, and the scale of the actual structure does not necessarily match the scale of the drawing. The same applies to FIGS. 2 to 12 and FIG. 15 described later.

  As shown in FIG. 1B, the device 1 of the present invention includes a first MOS transistor T1, a second MOS transistor T2, and a first Schottky barrier diode D1 on a semiconductor substrate 2.

  As shown in FIG. 1A, the device 1 of the present invention includes a first well 3 of a first conductivity type, a second well 4 of a second conductivity type different from the first conductivity type on a semiconductor substrate 2, And a third well 5 of the second conductivity type. Each well is separated and formed by an element isolation insulating film 6.

  A first MOS transistor T1 having a first gate insulating film 7, a first gate electrode 8, and first source / drain diffusion regions 32, 33 of the first conductivity type is formed on the second well 4. Then, diffusion regions 17 and 18 having a lower concentration than the first source / drain diffusion regions 32 and 33 are formed at the ends of the first source / drain diffusion regions 32 and 33 on the first gate electrode 8 side. . Hereinafter, the diffusion regions 17, 18, 32, and 33 are collectively referred to as “first source / drain diffusion regions DZ1” as appropriate. A sidewall insulating film 21 is formed on the side wall of the first gate electrode 8.

  Further, a refractory metal silicide film 52 is formed on the first gate electrode 8, and refractory metal silicide films 51 and 53 are formed on the first source / drain diffusion region DZ1, respectively.

  On the first well 3, a second MOS transistor T2 having a second gate insulating film 9, a second gate electrode 11, and second conductivity type second source / drain diffusion regions 23, 24 is formed. Then, diffusion regions 12 and 13 having a concentration lower than that of the second source / drain diffusion regions 23 and 24 are formed at the ends of the second source / drain diffusion regions 23 and 24 on the second gate electrode 11 side. . Hereinafter, the diffusion regions 12, 13, 23, and 24 are collectively referred to as “second source / drain diffusion regions DZ2” as appropriate. A sidewall insulating film 22 is formed on the side wall of the second gate electrode 9.

  Further, a refractory metal silicide film 55 is formed on the second gate electrode 11, and refractory metal silicide films 54 and 56 are formed on the second source / drain diffusion region DZ2.

  On the third well 5, there are a first diode electrode comprising a refractory metal silicide film 57 on a second conductivity type active region constituting the third well 5, and a second conductivity type high concentration diffusion region. A first Schottky barrier diode D1 having a second diode electrode comprising a refractory metal silicide film 58 is formed on the diode electrode diffusion region 25 to be formed. A Schottky junction SJ is formed at the interface between the refractory metal silicide film 57 and the active region of the third well 5, and the refractory metal silicide film 57 side of the Schottky junction SJ is a first diode electrode (anode electrode or cathode electrode). A Schottky barrier diode is configured in which the third well 5 side of the Schottky junction SJ is a second diode electrode different from the first diode electrode (a cathode electrode if the first diode electrode is an anode electrode). Here, the diode electrode diffusion region 25 formed of the diffusion region of the same second conductivity type as the third well 5 is electrically connected to the third well 5 and formed on the diode electrode diffusion region 25. Since the refractory metal silicide film 58 is electrically connected to the diode electrode diffusion region 25, the third well side 5 of the Schottky junction SJ and the refractory metal silicide film 58 are electrically connected. That is, the refractory metal silicide film 58 constitutes the second diode electrode of the Schottky barrier diode. FIG. 1A shows a contact plug 62 for connection to the first diode electrode of the Schottky barrier diode, and a wiring layer 63 electrically connected to the contact plug 62 is an interlayer insulating film. 61 is formed.

  In general, in the case of high integration, there is a problem that resistance during conduction increases due to shortening of the size of the diffusion region or the gate electrode as a result of miniaturization of the element size. According to the configuration of the device 1, a refractory metal silicide film is formed on each electrode of the first MOS transistor T1, the second MOS transistor T2, and the first Schottky barrier diode D1 formed on the same semiconductor substrate 2. Therefore, the resistance in the diffusion region or the gate electrode can be reduced. Therefore, high integration can be achieved while suppressing an increase in resistance value when forming an electrical connection with the diffusion region or the gate electrode.

  In the configuration of FIG. 1, when the first conductivity type is P type and the second conductivity type is N type, the device 1 of the present invention uses the refractory metal silicide film 57 as the anode electrode and the refractory metal silicide film. The first Schottky barrier diode D1 having 58 as a cathode electrode is provided.

  In FIG. 1, two MOS transistors of different conductivity types and a Schottky barrier diode are formed on the same substrate. However, a MOS transistor and a Schottky barrier diode are formed on the same semiconductor substrate. The number of MOS transistors and Schottky barrier diodes formed on the substrate is not limited to this number. Therefore, for example, a second well and a third well of the second conductivity type are formed on the semiconductor substrate (the first well of the first conductivity type is not formed), and the first MOS is formed on the second well. The transistor may comprise a first Schottky barrier diode on the third well.

  1, the first gate electrode 8, the second gate electrode 11, the first source / drain diffusion region DZ1, the second source / drain diffusion region DZ2, the diode electrode diffusion region 25, and the third well 5 are provided. The refractory metal silicide films are formed on the respective surfaces of the first diode electrode constituting region composed of the diffusion regions (refractory metal silicide films 51 to 58). It is not necessary to form the melting point metal silicide film, and a configuration in which the high melting point silicide film is formed in any region may be employed.

[Description of the method of the present invention]
Below, this invention method which manufactures this invention apparatus 1 mentioned above is demonstrated with reference to each figure of FIGS. Each of FIGS. 2 to 12 is a schematic cross-sectional structure diagram in one process when manufacturing the device 1 of the present invention, and FIGS. 13 and 14 are flowcharts showing the manufacturing process of the device 1 of the present invention (paper surface). It is divided into two drawings for convenience.) In addition, each step shown in the following sentence represents one step in the flowcharts in FIGS. 13 and 14.

  First, as shown in FIG. 2, an element isolation insulating film 6 is formed on a semiconductor substrate 2, and low concentration impurity ions are implanted into a predetermined region, so that the first conductivity type (hereinafter referred to as “P type”). ) First well 3, second conductivity type (hereinafter referred to as “N-type”) second well 4, and second conductivity type (N-type) third well 5. Further, the first diode electrode formation region 5a and the second diode electrode formation region 5b separated by the element isolation insulating film 6 are formed on the third well 5 (step # 1).

  Here, when the semiconductor substrate 2 is a P-type substrate, the second well 4 and the third well 5 are formed by implanting N-type impurity ions into the second well region and the third well region, respectively. Good as a thing. In this case, the first well 3 is constituted by the P-type low concentration region constituted by the substrate surface. Alternatively, the first well 3 may be formed by implanting P-type impurity ions, and the second well 4 and the third well 5 may be formed by implanting N-type impurity ions.

  The second well 4 constitutes an active region of the first MOS transistor T1, and the first well 3 constitutes an active region of the second MOS transistor T2. Of the third well 5, the first diode electrode of the first Schottky barrier diode D1 is formed in the first diode electrode formation region 5a, and the first diode electrode of the first Schottky barrier diode D1 is formed in the second diode electrode formation region 5b. Two diode electrodes are then constructed. When the third well 5 is N-type, the first diode electrode constitutes an anode electrode and the second diode electrode constitutes a cathode electrode.

  Next, as shown in FIG. 3, after the surface of the active region of the semiconductor substrate 2 is thermally oxidized to deposit a silicon oxide film, an amorphous or polycrystalline silicon film is deposited and patterned into a predetermined shape. Thus, the first gate insulating film 7 and the first gate electrode 8 are formed on the second well, and the second gate insulating film 9 and the second gate electrode 11 are formed on the first well 3 (step # 2).

  Next, as shown in FIG. 4, in the state where the second well 4 and the first diode electrode formation region 5a are masked by the resist films 15 and 16, respectively, the second conductivity type (N type) intermediate concentration impurity ions (N type) (It is assumed that the concentration is lower than the high-concentration impurity ions implanted in step # 6, which will be described later), and diffusion regions 12 and 13 are formed in the first well 3, and the second diode electrode in the third well 5 is formed. Diffusion regions 14 are respectively formed in the regions 5b (step # 3). Thereafter, the resist films 15 and 16 are peeled off.

  Incidentally, in the ion implantation process of step # 3, the entire third well 5 may be masked by the resist film 16.

  Next, as shown in FIG. 5, in the state where the first well 3 and the third well 5 are masked with the resist film 19, intermediate concentration impurity ions of the first conductivity type (P type) (implanted in step 7 described later). Then, the diffusion regions 17 and 18 are formed in the second well 4 (step # 4). Thereafter, the resist film 19 is peeled off.

  Next, as shown in FIG. 6, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 2 by, for example, a CVD method, and then etched back to thereby etch the sidewall portion of the first gate electrode 8 (and the first gate insulating film 7). Further, by leaving the silicon oxide film only on the side walls of the second gate electrode 11 (and the second gate insulating film 9), the side wall insulating film 21 and the side wall insulating film 22 are formed (step # 5).

  Next, as shown in FIG. 7, in the state where the second well 4 and the first diode electrode formation region 5a are masked by the resist films 27 and 28, respectively, the second conductivity type (N type) high concentration impurity ions (N type) In this case, the second source / drain diffusion regions 23 and 24 are formed in the first well 3 and the second source / drain diffusion regions 23 and 24 in the third well 5. A diode electrode diffusion region 25 is formed in each diode electrode formation region 5b (step # 6). Through this process, the second MOS transistor T2 is formed on the first well 3. In the first well 3, a partial region is masked in the sidewall insulating film 22, so that the step is formed at the end of the source / drain diffusion regions 23 and 24 on the second gate electrode 11 side. The intermediate concentration diffusion regions 12 and 13 implanted in # 3 are formed, and an LDD (Lightly Doped Drain) structure is formed in the region. This has the effect of relaxing the electric field at the boundary between the source / drain diffusion regions 23 and 24 and the channel region sandwiched between these regions.

  Next, after the resist films 27 and 28 are peeled off, as shown in FIG. 8, the first conductivity type (P-type) high resistance is obtained with the first well 3 and the third well 5 masked with the resist film 31. Concentration impurity ions (assuming a higher concentration than the intermediate concentration impurity ions implanted in step # 4) are implanted to form second source / drain diffusion regions 32 and 33 in the second well 4 (step #). 7). Through this process, the first MOS transistor T1 is formed on the second well 4. In the first MOS transistor T1, similarly to the second MOS transistor T2, the intermediate concentration diffusion regions 17 and 18 are formed at the ends of the high concentration source / drain diffusion regions 32 and 33 on the first gate electrode 8 side. Thus, an LDD structure is formed.

  Next, after the resist film 31 is peeled off, an active region exposed as shown in FIG. 9 is implanted by implanting ions composed of a rare gas element or the same element as the constituent element of the semiconductor substrate 2. The surface and the surfaces of the first gate electrode 8 and the second gate electrode 11 are amorphized, and the amorphous layers 41 to 48 are formed (step # 8). This amorphization step is performed in order to facilitate the phase transition of the crystal phase for reducing the resistance value in the subsequent silicide film formation step.

For example, when the dose amount is 5.0 × 10 ¹⁴ ions / cm ² , the ion implantation energy for each implanted ion species is about 10 keV in the case of Ar ions, about 5 keV in the case of Ne ions, and in the case of Xe ions. Ion implantation is performed at about 33 keV, about 56 keV for Rn ions, about 7 keV for Si ions, and about 18 keV for Ge ions. Thereby, the injection range (Rp) can be about 12 nm and the injection distribution (Rp + 3ΔRp) can be about 30 nm. The injection range represents a projection range from the surface of the semiconductor substrate along the incident axis of the injection, and the injection distribution refers to a projected range of a Gaussian distribution in a direction perpendicular to the incident axis. It is assumed to represent the sum of three times the statistical fluctuation projection variance of.

  Since the constituent elements of the ions implanted in step # 8 are elements that do not exhibit P-type or N-type characteristics, they do not affect the conductivity type of each diffusion region. Therefore, even when ion implantation is performed particularly in the first diode electrode formation region 5a, it does not affect the conductivity type in the region, so that it is formed in the region in the subsequent process. It does not affect the electrical characteristics of the Schottky junction. On the other hand, if, for example, ions of an element exhibiting P-type characteristics are implanted to form an amorphous state, it is necessary to mask the first well 3 and the third well 5 in which the N-type diffusion region is formed. If the amorphization is performed by implanting ions of an element exhibiting N-type characteristics, it is necessary to mask the second well 4 in which the P-type diffusion region is formed. That is, when amorphization is performed using ions of an element exhibiting any conductivity type, a resist film forming process for masking a predetermined region and a resist film peeling process are required. In order to amorphize the interface between both the type diffusion region and the N type diffusion region, it is necessary to change the constituent elements of the implanted ions and perform ion implantation in two steps. Therefore, the step of amorphization can be significantly shortened by implanting ions composed of elements that do not exhibit any conductivity type characteristics as in step # 8.

  Next, as shown in FIG. 10, a refractory metal film 40 such as Ti or Co is deposited on the entire surface of the semiconductor substrate 2 (step # 9).

  Next, annealing is performed to silicide the interface between the refractory metal film 40 and the active region or the gate electrode as shown in FIG. 11 (step # 10). Thereby, refractory metal silicide films 51 to 58 are formed at the interface between the refractory metal film 40 and the active region or the gate electrode. As the annealing conditions, for example, when the refractory metal film 40 is Ti, it is about 650 ° C. to 700 ° C. for about 1 minute, and when it is Co, it is 450 ° C. to 530 ° C. Heat treatment may be performed for about 1 minute under temperature conditions.

  Next, as shown in FIG. 12, the unreacted refractory metal film 40 is removed by wet etching (step # 11). Thereafter, the annealing process is performed again to perform the phase transition process of the refractory silicide films 51 to 58 (step # 12). By this treatment, the high melting point silicide films 51 to 58 are phase-transitioned to a low resistance crystal phase. In particular, since amorphization is performed in step # 8, the refractory silicide film is efficiently phase-shifted by the annealing process in step # 12. As conditions for the annealing process in Step # 12, regardless of whether the refractory metal film 40 is Ti or Co, for example, heat treatment is performed for about 30 seconds under a temperature condition of 650 ° C. to 700 ° C. good.

  Thereafter, as shown in FIG. 1, after depositing an interlayer insulating film 61, contact plugs 62 and the like are formed in a predetermined contact plug formation region, and a wiring layer 63 is formed. Thus, the first MOS transistor T1, the second MOS transistor T2, and the first Schottky barrier diode D1 are formed on the same semiconductor substrate 2 in a state where the conduction resistance is reduced.

  According to the above-described method of the present invention, the interlayer insulating film is formed after forming the source / drain diffusion region, the diode electrode diffusion region, and the refractory metal silicide film, and is used for ion implantation and metal film deposition. There is no need to form contact holes. Therefore, unlike the conventional method, it is not necessary to form a contact hole having a sufficient hole diameter in consideration of an etching error in order to keep the element characteristics within the range of the design stage, so that the distance between the elements can be reduced. . Thereby, the integration degree can be further increased.

  In the above-described embodiment, the exposed surfaces of all the diffusion regions on the first well 3, the second well 4, and the third well 5 and the exposed surfaces of the first gate electrode 8 and the second gate electrode 11 are all formed. Although it is assumed that it is amorphized (the amorphous layers 41 to 48 are formed) in the process according to Step # 7, it is not always necessary that all these exposed surfaces be amorphized. Similarly, the entire region at the interface between the exposed surface and the refractory metal film 40 is silicided (the refractory metal silicide films 51 to 58 are formed) by the process according to Step # 10. All of these interfaces need not be silicided. However, in order to increase the effect of reducing the conduction resistance, it is preferable to form a refractory metal silicide film on the entire interface.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> In the embodiment described above, the first diode electrode formation region 5a in the third well in the step of implanting the first conductivity type (P-type) impurity ions of at least one of step # 4 or step # 7. Of these, the first conductivity type impurity ion implantation may be performed also on the edge portion in contact with the element isolation insulating film 6 (see FIG. 15). FIG. 15 is a schematic cross-sectional structure diagram of the device 1 of the present invention according to this process when the first conductivity type (P-type) impurity ions are also implanted into the edge portion in Step # 7. As shown in FIG. 15, instead of the resist film 31 of FIG. 8, by implanting the first conductivity type (P-type) impurity ions in the state where the resist films 31a, 31b, 31c are formed, Along with the drain diffusion regions 32 and 33, a high-concentration diffusion region 71 is formed at the edge portion of the first diode electrode formation region 5a. By configuring in this way, a PN junction in the same direction as the rectification direction of the Schottky junction formed in a later step is formed between the high concentration diffusion region 71 and the third well 5. Can be complementarily increased.

  <2> In the embodiment described above, the first conductivity type is P-type and the second conductivity type is N-type. However, the first conductivity type may be N-type and the second conductivity type may be P-type. In this case, the device 1 of the present invention includes a Schottky barrier diode D1 having a first diode electrode as a cathode electrode and a second diode electrode as an anode electrode on the third well 5.

Structure diagram showing schematic configuration of the device of the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention Flowchart showing a manufacturing process of a semiconductor device according to the present invention. Flowchart showing a manufacturing process of a semiconductor device according to the present invention. Schematic cross-sectional structure diagram in a process of manufacturing a semiconductor device according to the present invention

Explanation of symbols

1: Semiconductor device according to the present invention 2: Semiconductor substrate 3: First well 4: Second well 5: Third well 5a: First diode electrode formation region 5b: Second diode electrode formation region 6: Element isolation insulating film 7 : First gate insulating film 8: First gate electrode 9: Second gate insulating film 11: Second gate electrode 12: Diffusion region 13: Diffusion region 14: Diffusion region 15: Resist film 16: Resist film 17: Diffusion region 18 : Diffusion region 19: Resist film 21: Side wall insulating film 22: Side wall insulating film 23: Second source / drain diffusion region 24: Second source / drain diffusion region 25: Diffusion region for diode electrode 27: Resist film 28: Resist film 32: First source / drain diffusion region 33: First source / drain diffusion region 41: Amorpha Layer 42: amorphous layer 43: amorphous layer 44: amorphous layer 45: amorphous layer 46: amorphous layer 47: amorphous layer 48: amorphous layer 51: refractory metal silicide film 52: refractory metal silicide film 53: refractory metal silicide film 54: refractory metal silicide film 55: refractory metal silicide film 56: refractory metal silicide film 57: refractory metal silicide film 58: refractory metal silicide film 61: interlayer insulating film 62: contact plug 63: wiring layer 71: High concentration diffusion region D1: First Schottky barrier diode DZ1: First source / drain diffusion region DZ2: Second source / drain diffusion region SJ: Schottky junction T1: First MOS transistor T2: Second MOS transistor

Claims (7)

A method for manufacturing a semiconductor device comprising a MOS transistor and a Schottky barrier diode on a semiconductor substrate,
An active region isolated by an element isolation insulating film is formed on the semiconductor substrate, and low-concentration impurity ions are implanted into a predetermined region on the semiconductor substrate, whereby a first well of the first conductivity type, the first conductivity An active region for forming a MOS transistor is formed on each of the first well and the second well by forming a second well of a second conductivity type different from the mold and a third well of the second conductivity type. Forming a first diode electrode formation region and a second diode electrode formation region separated by an element isolation insulating film on the third well;
After completion of the first step, a gate electrode film is deposited on the semiconductor substrate via a gate insulating film, and then patterned into a predetermined shape, whereby a gate electrode of the first MOS transistor is formed in a predetermined region on the second well. A second step of forming a first gate electrode to be a second gate electrode to be a gate electrode of a second MOS transistor in a predetermined region on the first well;
After the second step, the source / drain diffusion region of the second MOS transistor is implanted by implanting high concentration impurity ions of the second conductivity type into the first well and the second diode electrode formation region. Second source / drain diffusion regions and diode electrode diffusion regions are formed, and high concentration impurity ions of the first conductivity type are implanted into the second well, whereby the source / drain regions of the first MOS transistor are implanted. A third step of forming a first source / drain diffusion region to be a drain diffusion region;
After the third step, at least the first gate electrode, the first source / drain diffusion region, and the second source are implanted by implanting ions composed of a rare gas element or the same element as the semiconductor substrate. A fourth step of amorphizing the surface of any one of the gate electrode, the second source / drain diffusion region, and the diffusion region for the diode electrode;
After completion of the fourth step, a refractory metal film is deposited on the entire surface of the semiconductor substrate to form a Schottky junction at the interface between the first diode electrode formation region and the refractory metal film, and The second high-melting point metal film side of the junction is a first diode electrode, and the second diode electrode formation region is electrically connected to the first diode electrode formation region side of the Schottky junction through the diode electrode diffusion region A fifth step of forming a first Schottky barrier diode using the refractory metal film formed in contact with the second diode electrode;
After the fifth step, annealing is performed to at least the first gate electrode, the first source / drain diffusion region, the second gate electrode, the second source / drain diffusion region, and the diode electrode. And a sixth step of removing any unreacted refractory metal film after siliciding the interface between any one of the diffusion regions and the refractory metal film. Device manufacturing method. The fourth step is
2. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed on the entire surface of the semiconductor substrate. In the first step,
The method for manufacturing a semiconductor device according to claim 1, wherein the second well and the third well are electrically insulated. In the third step,
Further, a PN junction is formed in the first diode electrode formation region by implanting high concentration impurity ions of the first conductivity type into an edge portion of the first diode electrode formation region. The method for manufacturing a semiconductor device according to claim 1. On a semiconductor substrate, a first conductivity type first well, a second conductivity type second well different from the first conductivity type, and a second conductivity type third well are formed in a region near the surface in each well. Are separated by an element isolation insulating film, and two regions of a first diode electrode forming region and a second diode electrode forming region separated by an element isolation insulating film are provided in a region near the surface in the third well. A diffusion region for a diode electrode is formed in the second diode electrode formation region by high concentration impurity ion implantation of the second conductivity type;
A first gate insulating film and a first gate electrode which are sequentially formed in a predetermined region on the second well from the bottom; and at least a region in the vicinity of the surface in the second well on the outer side in the vicinity of the lower region of the first gate electrode. A first MOS transistor having a first source / drain diffusion region formed by high-concentration impurity ion implantation of the first conductivity type;
A second gate insulating film and a second gate electrode formed in order from the bottom in a predetermined region on the first well; and at least a region in the vicinity of the surface in the first well on the outer side near the lower region of the first gate electrode A second MOS transistor having a second source / drain diffusion region formed by high concentration impurity ion implantation of the second conductivity type;
The refractory metal film or the refractory metal silicide film formed so as to be in contact with the upper surface of the first diode electrode formation region is used as the first diode electrode, and is formed so as to be in contact with the upper surface of the diffusion region for the diode electrode. A first Schottky barrier diode using a refractory metal film or a refractory metal silicide film as a second diode electrode,
High at the interface of at least one of the first gate electrode, the first source / drain diffusion region, the second gate electrode, the second source / drain diffusion region, and the diode electrode diffusion region. A semiconductor device, wherein a melting point metal silicide film is formed.   The semiconductor device according to claim 5, wherein the second well and the third well are electrically insulated. In the edge portion of the first diode electrode formation region, at least a part of the upper surface has the high-concentration diffusion region of the first conductivity type in contact with the refractory metal film or the refractory metal silicide film,
The semiconductor device according to claim 5, wherein a PN junction is formed in the first diode electrode formation region.

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