JP2001168352A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [PROBLEMS] To form an SDB having excellent withstand voltage by using a metal such as tungsten which can be embedded in a fine contact hole. SOLUTION: An n-type well 4 is formed on a main surface of a semiconductor substrate 1, a MISFET is formed, and silicon oxide films 18 and 19 covering the MISFET are formed. After forming the connection holes 20 to 22 in the silicon oxide film 19 and the like, a p-type impurity is ion-implanted to form a p-type semiconductor region 24 at the bottom of the connection hole 20. Thereafter, a tungsten film 25 is formed by a sputtering method, and a tungsten film 26 is formed by a CVD method. Thereafter, a plug is formed by applying CMP to the tungsten films 26 and 25. As a result, a plug for leading out the source / drain region of the MISFET is formed, and a p-well is formed between the n-type well 4 and the tungsten film 25.
The type semiconductor region 24 is formed, and an SBD (Schottky barrier diode) having excellent withstand voltage is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing technology, and more particularly, to an SBD (Schottky Barrier).
The present invention relates to a technology that is effective when applied to a semiconductor device having a diode.

[0002]

2. Description of the Related Art For example, Japanese Patent Application Laid-Open No. 58-161378 discloses a method of forming a reverse conductivity type (p type) epitaxial layer on a one conductivity type (n ⁺ type) semiconductor substrate and forming a Schottky layer on the epitaxial layer. A technique for forming a metal electrode layer (for example, molybdenum) for forming a junction to obtain a constant voltage diode is disclosed. With this technique, the variation of the punch-through voltage can be reduced, and the punch-through voltage can be set in a wide range from a low voltage to a high voltage.

[0003] For example, Japanese Patent Application Laid-Open No. 4-103170 describes a technique relating to a semiconductor device having a step of simultaneously forming an SBD and its lead electrode. That is, after forming an element isolation region and a polycrystalline silicon film on an n-type semiconductor substrate and patterning the polycrystalline silicon film, a metal film (tungsten film) is selected on an exposed portion of the n-type substrate and on the polycrystalline silicon film. A technique for forming a Schottky junction at a junction between the tungsten film and the n-type substrate is disclosed. According to such a technique, pattern shift between the polycrystalline silicon film and the metal film is prevented, and the <100> plane of the silicon substrate can be used as compared with the SBD using aluminum.

[0004] For example, in Japanese Patent Application Laid-Open No. 3-222362, an insulating film is formed on an n-type silicon substrate, a contact window is formed in the insulating film, and a contact metal layer made of tungsten is formed. Heat treatment,
A semiconductor device in which a Schottky barrier is formed by contact between an n-type silicon substrate at the bottom of a contact window and a contact metal layer (tungsten) is disclosed.

[0005]

However, the present inventors have studied to form an SBD in a highly integrated semiconductor device, and have recognized the following problems.

That is, considering the integration of a semiconductor device, a contact hole is formed in an interlayer insulating film formed after a semiconductor element such as a MISFET is formed on a semiconductor substrate, rather than forming a diode element individually on a semiconductor substrate. Preferably, an SBD is formed by joining the metal formed in the contact hole and the semiconductor substrate to form a diode element. The configuration in this respect is similar to that of the above-mentioned document (Japanese Patent Laid-Open No. 3-222362). With such a configuration, the SBD can be formed in an area (plane area) where the contact hole is formed, and can be advantageously used for integration. In addition, a connection member (plug) for connecting a wiring formed on an insulating film covering the MISFET and the like to a source / drain region (semiconductor substrate) of the MISFET.
In the step of forming (1), a metal terminal which is one terminal of the SBD can be simultaneously formed. As a result, the process can be simplified.

Here, in consideration of the high-frequency characteristics of the SBD, an electron is preferable as a carrier of the SBD. Therefore, an n-type semiconductor region is used for the semiconductor substrate (contact on the semiconductor side). As the metal at the other contact point, a laminated film in which a molybdenum-based material (molybdenum silicide or the like) is laminated with an aluminum-based material (aluminum silicide or the like) is used. The molybdenum-based material is used because the Schottky barrier between the n-type semiconductor region and the n-type semiconductor region cannot be sufficiently increased without using such a material in relation to the work function of the n-type semiconductor region. The reduction in the Schottky barrier causes the reverse breakdown voltage of the SBD to be insufficient, and a desired SBD characteristic cannot be obtained, which causes inconvenience. According to the study of the present inventors, although a predetermined characteristic can be obtained by using a material such as platinum in addition to molybdenum, a Schottky junction with an n-type semiconductor substrate using a metal material used in a semiconductor process such as tungsten or titanium can be obtained. Forming
It has been found that a sufficient barrier potential cannot be obtained and an SBD with a sufficiently high withstand voltage cannot be formed.

On the other hand, for higher integration of semiconductor devices, MI
There is a demand for miniaturizing the size of a plug for connecting a source / drain (semiconductor substrate) of an SFET and a wiring formed thereon. The plug is MISF
A contact hole is formed in an insulating film covering the ET, and a metal material is buried in the contact hole.

However, the above-described laminated film of a molybdenum-based material and an aluminum-based material is not suitable for embedding in a miniaturized contact hole. That is, it has been found that an aluminum-based material does not have good step coverage, and it is difficult to bury a fine (for example, 0.5 μm diameter) contact hole.

[0010] Tungsten has been known as a metal material suitable for filling fine contact holes. However, as described above, it is not possible to form an SBD having excellent withstand voltage with tungsten. Tungsten having excellent embedding properties is formed by a CVD method, and a stacked film of titanium and titanium nitride is used as a barrier film for the purpose of suppressing reactivity with a substrate during the CVD process. Materials and n suitable for barrier film
It is difficult to form an SBD with sufficient characteristics even with a junction with the type semiconductor region.

On the other hand, molybdenum and platinum can be exemplified as materials suitable for forming the SBD. However, these materials are not materials that are conventionally frequently used in a semiconductor process, and use of these materials requires new equipment. It is necessary to develop a new technology that makes full use of these materials. Investment in these facilities and new development factors are factors that increase the cost of products, which is not desirable.

An object of the present invention is to provide a technique capable of forming an SDB having excellent withstand voltage using a metal such as tungsten which can be embedded in a fine contact hole.

Another object of the present invention is to provide a technique capable of forming an SDB having excellent withstand voltage by using a conventionally used material.

Still another object of the present invention is to provide a technique capable of easily forming a semiconductor device having an SDB with excellent withstand voltage without adding a new step to achieve the above-mentioned object. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor device according to the present invention includes an n-type semiconductor region formed on a main surface of a semiconductor substrate, an insulating film formed on the main surface, a first connection hole formed in the insulating film, A semiconductor device having a first conductive member made of a metal or a metal compound formed in a connection hole, wherein the first conductive member and n
A p-type semiconductor region is formed between the p-type semiconductor region and the p-type semiconductor region. According to such a semiconductor device, the first conductive member and n
Since the p-type semiconductor region is formed between the semiconductor device and the p-type semiconductor region, the barrier potential of the SBD (Schottky barrier diode) having the first conductive member as one terminal and the n-type semiconductor region as the other terminal is increased. can do. Thereby, an SBD with a high withstand voltage can be formed. Further, since the first conductive member is formed in the first connection hole (through hole) formed in the insulating film, the planar area required for forming the SBD can be reduced, and high integration can be achieved. it can.

Here, the p-type semiconductor region can be formed at the bottom of the first connection hole in a self-aligned manner with respect to the first connection hole.

The thickness of the p-type semiconductor region is 20-30.
It can be in the nm range.

The first conductive member includes a first conductive film formed in contact with the inner wall of the first connection hole and the p-type semiconductor region, and a second conductive film filling the connection hole. Can be a tungsten film, a titanium film, a tantalum film, a tungsten nitride film, a titanium nitride film, or a tantalum nitride film. Although it is difficult to form an SBD having a sufficient withstand voltage even if these first conductive films are formed directly in contact with the n-type semiconductor region, in the present invention, the p-type semiconductor region is formed as an n-type semiconductor region in contact with the first conductive film. Since it is formed on the type semiconductor region, it is possible to secure a sufficiently high Schottky barrier and increase the breakdown voltage of the SBD. The material of the first conductive film is a material often used in a conventional semiconductor process, and there is no need to introduce a new manufacturing apparatus or develop a new process for implementing the present invention.

The second conductive film can be a tungsten film formed by a CVD method. The material (tungsten) of the second conductive film is also a material often used in the conventional semiconductor process, and there is no need to introduce a new manufacturing apparatus or develop a new process for implementing the present invention.

Further, a barrier film having resistance to an atmosphere for forming tungsten by a CVD method can be formed between the first conductive film and the second conductive film. By forming the barrier film, damage to the substrate and the insulating film due to the atmosphere (for example, a halogen atmosphere such as fluorine) in tungsten CVD can be suppressed. Examples of the barrier film include a titanium nitride film, a tungsten nitride film, and a tungsten film formed by a sputtering method.

In the above-mentioned semiconductor device, the semiconductor device further comprises a MISFET formed on a main surface of the semiconductor substrate;
A second connection hole formed in an insulating film on a semiconductor region functioning as a source / drain of the first and second conductive members made of a metal or a metal compound formed in the second connection hole; The member may be formed simultaneously with the first conductive member. That is, in addition to SBD, MI
It has another element such as an SFET and forms a first conductive member for forming an SBD on an insulating film covering the MISFET and the like, and forms a second conductive member for pulling up a source / drain terminal of the MISFET. It is assumed that the first and second conductive members are formed at the same time.

In such a semiconductor device, the MISFET
Source / drain lifting member (second conductive member) and S
One electrode of the BD can be formed at the same time, and the process can be simplified. In particular, when the semiconductor device becomes highly integrated, the diameter of the second conductive member (diameter of the second connection hole) for raising the source / drain terminals of the MISFET is increased.
Becomes smaller. Therefore, it is necessary to embed the second connection member in a connection hole having a small diameter of, for example, about 0.5 μm. Therefore, it is necessary to select a material having excellent embedding characteristics as the material of the second connection member. In the present invention, as described above, a first conductive film such as a tungsten film, a titanium film, a tantalum film, a tungsten nitride film, a titanium nitride film, or a tantalum nitride film, and a second conductive film such as tungsten formed by a CVD method are used. It is possible to sufficiently satisfy the requirement of the recess embedding property.

The first connection hole and the second connection hole can be formed with the same design opening size. By forming the first and second connection holes with the same opening diameter in this manner, formation (exposure) of a photoresist film for opening the connection holes becomes easy. That is, in order to simultaneously expose photoresist films having different opening diameters, it is difficult to adjust exposure conditions and the like.
If the aperture diameter is uniform, exposure conditions (selection of a modified illumination method of an exposure light source, selection of a resist material, etc.) become easy.

In the above case, the first connection hole and the second connection hole can be opened simultaneously in the same processing step. If the opening diameter of the connection hole is uniform, etching becomes easy and processing can be performed at the same time. That is, since the etching rate in the connection hole depends on the opening diameter, it is necessary to adjust the use of an etching stopper or to optimize the etching conditions in order to simultaneously process the connection holes having different opening diameters. Such adjustments are difficult. However, in the case of the present invention, since the opening diameter is uniform, such an adjustment is not required, and the connection hole opening step can be simplified.

In the above case, a plurality of first connection holes are formed, and the plurality of first conductive members formed in the first connection holes can be connected to each other on the insulating film. Since the diameter of the connection hole is made small in accordance with the lead-out member of the MISFET, a plurality of SBDs can be formed in order to secure a current value necessary for the SBD. In this case, the metal-side terminals (first connection members) of the SBD can be connected to each other by the wiring on the insulating film, and the SBD can be connected in parallel.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of (a)
Forming an element isolation region on the main surface of the semiconductor substrate and forming an n-type semiconductor region in a part of the active region surrounded by the element isolation region; (b) MISFE in the active region
Forming T and forming an insulating film covering the MISFET and the n-type semiconductor region; (c) reaching the first connection hole reaching the n-type semiconductor region and the semiconductor region functioning as the source / drain of the MISFET in the insulating film; Forming a second connection hole, (d) ion-implanting a p-type impurity into the first connection hole, and forming a p-type semiconductor region on the surface of the n-type semiconductor region at the bottom of the first connection hole; (e) A step of depositing a first conductive film on the surface of the semiconductor substrate including the inside of the first and second connection holes; and (f) a step of depositing a second conductive film filling the inside of the first and second connection holes. . According to such a method of manufacturing a semiconductor device, a semiconductor integrated circuit device having the above-described SBD can be formed. Further, since the p-type impurity is ion-implanted by ion implantation after forming the first connection hole in the insulating film, the p-type semiconductor region can be formed in a self-aligned manner with the first connection hole.

The first connection hole and the second connection hole in the step (c) can be formed simultaneously in the same processing step.

The first and second connection holes can be formed with the same opening size.

The first conductive film can be a tungsten film, a titanium film, a tantalum film, a tungsten nitride film, a titanium nitride film, or a tantalum nitride film, and the second conductive film is formed by a CVD method. Tungsten film.

Further, before the step (f), a barrier film having resistance to an atmosphere for forming tungsten by a CVD method can be formed. The barrier film can be a titanium nitride film, a tungsten nitride film, or a tungsten film formed by a sputtering method.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIGS.
3A and 3B are cross-sectional views or plan views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, except for FIG.

First, as shown in FIG. 1, an element isolation region 2, a p-type well 3, and an n-type well 4 are formed on a main surface of a semiconductor substrate 1.

The semiconductor substrate 1 has, for example, a resistivity of several Ωc.
Single crystal silicon into which a p-type impurity has been introduced to an extent of m is used. At the stage of the so-called pre-process, wafer-like single-crystal silicon is used, but after the post-process, the wafer is divided into chips. Hereinafter, in the present specification, a semiconductor substrate includes a wafer-like and a chip-like one. Although a single crystal silicon wafer is illustrated here, a so-called SOI (Silicon On Ins) in which an insulating film is formed on an upper layer of single crystal silicon and an epitaxial growth layer is further formed thereon.
ulator) A substrate may be used. Alternatively, a substrate such as a glass substrate in which a silicon film is formed over an insulating substrate may be used.

The element isolation region 2 is, for example, LOCOS
(Local Oxidation of Silicon) method.
That is, a sacrificial oxide film and a silicon nitride film are formed on the surface of the semiconductor substrate 1, and the silicon nitride film is patterned so as to have an opening in a region where the element isolation region 2 is formed. Next, using a silicon nitride film as a mask, for example, thermal oxidation is performed to form a thick field insulating film in the opening. Thereafter, the silicon nitride film is removed by wet etching using, for example, hot phosphoric acid or the like to form an element isolation region 2 as shown in FIG. here,
Although the LOCOS method is illustrated, a shallow trench isolation structure may be used. That is, a shallow groove is formed in the semiconductor substrate 1 and a silicon oxide film filling the shallow groove is formed by, for example, TEOS.
(TEOS oxide film) formed by CVD (Chemical Vapor Deposition) using (tetraethoxysilane) and ozone (O ³ ) as source gases, and the TEOS oxide film is polished by, eg, CMP (Chemical Mechanical Polishing). The silicon oxide film may be left only in the shallow groove to serve as an element isolation region.

The p-type well 3 and the n-type well 4 are formed by, for example, an ion implantation method. That is, in order to form the p-type well 3, a photoresist film having an opening in a region where a well is to be formed is formed, and for example, boron (B) is ion-implanted using the photoresist film as a mask. In order to form the n-type well 4, a photoresist film having an opening formed in a region where a well is to be formed is formed, and phosphorus (P) is ion-implanted using the photoresist film as a mask. After these ion implantations, the photoresist film is removed, and heat treatment for activating impurities is performed. However, the heat treatment does not need to be performed at this stage, and when the heat treatment can be performed in a subsequent heat step, the heat treatment can also be performed in the subsequent heat step. The heat treatment uses, for example, an RTA (Rapid Thermal Anneal) method. In the following description, steps for implanting impurities may be described, but heat treatment is similarly required to activate impurities in a semiconductor region formed by the ion implantation. These heat treatments can be performed using the RTA method, and the heat treatments may be performed for each ion implantation step, but it is only necessary that the heat treatments be performed at the final stage of the steps, as described above. Therefore, in the following description, the heat treatment step will be omitted.

In FIG. 1 and the following sectional views,
The left side shows the SBD formation region, and the right side shows the MISFET formation region. In the present embodiment, the MISFE
Although T is shown, it goes without saying that a resistance element, a capacitor element, a wiring, and the like may be formed in addition to this. The MISFET formation region is an n-channel MISFET
An nMISFET region in which is formed, and a p-channel MIS
It is divided into pMISFET regions where FETs are formed.
Further, the SBD formation region is divided into a region S where a Schottky barrier is to be formed later and a pull-up region L of a semiconductor-side terminal of the SBD.

Next, as shown in FIG. 2, a gate insulating film 5 and a gate electrode 6 of the MISFET are formed in the active region of the MISFET formation region. Further, an n ⁻ -type semiconductor region 7 and a p ⁻ -type semiconductor region 8 having a low impurity concentration and functioning as a part of a source / drain are formed in the active regions on both sides of the gate electrode 6.

The gate insulating film 5 can be formed by, for example, a thermal CVD method and is a silicon oxide film having a thickness of 7 to several tens nm. It is formed on the entire surface of the semiconductor substrate 1 and is simultaneously patterned by patterning when forming the gate electrode 6 described below.

Gate electrode 6 is made of a polycrystalline silicon film, and for example, an n-type impurity is introduced at a high concentration. Thus, the gate electrode 6 functions as a wiring. The gate electrode 6 is formed by depositing a polycrystalline silicon film on the silicon oxide film serving as the gate insulating film by, for example, a CVD method. Thereafter, the photoresist film is patterned, and dry etching (anisotropic etching) is performed using the photoresist film as a mask. The thickness of the gate electrode 6 is set to several hundred nm.

The n ⁻ type semiconductor region 7 and the p ⁻ type semiconductor region 8 are formed by an ion implantation method. The n ⁻ type semiconductor region 7 is formed by covering the pMISFET region and the region S where the Schottky barrier of the SBD is formed with a photoresist film, and n-type impurities (for example, phosphorus or arsenic (As)) in the presence of the photoresist film. Is formed by ion implantation at a low concentration. At this time, the n ⁻ type semiconductor region 9 is also formed in the region L where the extraction electrode is formed after the SBD formation region. This makes it possible to use a photolithography mask (reticle) for forming an n ⁺ -type semiconductor region, which will be described later, in this step. However, n ^-
For type semiconductor region 9 is the formed region, the n ⁺ -type semiconductor region later is formed, wherein the n ^- -type semiconductor region 9
Need not be formed.

The p ⁻ type semiconductor region 8 is formed by nMISF
The ET region and the SBD formation region are covered with a photoresist film, and p-type impurities (for example, boron) are ion-implanted at a low concentration in the presence of the photoresist film.

In the ion implantation step, the n ⁻ type semiconductor region 7 and the p ⁻ type semiconductor region 8 are formed in self alignment with the gate electrode 6.

In the step of forming the n ⁻ -type semiconductor region 7 and the p ⁻ -type semiconductor region 8, neither the n-type impurity nor the p-type impurity is introduced into the region S of the SBD where the Schottky barrier is formed. . This is because a p-type impurity is introduced into the region S at a film thickness and an impurity concentration suitable for forming a Schottky barrier of the SBD later.

Next, as shown in FIG. 3, an insulating film 10 is formed on the entire surface of the semiconductor substrate 1. The insulating film 10 is, for example, T
An EOS oxide film can be used. The thickness of the insulating film 10 is, for example, 100 to several hundred nm. Insulating film 10
May be replaced with a silicon nitride film.

Next, as shown in FIG. 4, the photoresist film 11 is patterned so as to cover the region S where the Schottky barrier of the SBD is formed.
Anisotropic etching (dry etching) is performed in the presence of 1. Thus, the insulating film 10 in a region other than the region where the photoresist film 11 is formed is removed, and the sidewall spacer 12 is formed on the side wall of the gate electrode 6.

Next, as shown in FIG. 5, the n ⁺ -type semiconductor region 13 having a high impurity concentration and functioning as a part of the source / drain of the MISFET and p ⁺
The n ⁺ type semiconductor region 15 which is to be in contact with the pull-up electrode of the SBD is formed.

The n ⁺ type semiconductor region 13, the p ⁺ type semiconductor region 14 and the n ⁺ type semiconductor region 15 are formed by ion implantation. The formation of the n ⁺ type semiconductor regions 13 and 15 is p
The MISFET region and the region S where the Schottky barrier of the SBD is formed are covered with a photoresist film, and are formed by ion-implanting n-type impurities (for example, phosphorus or arsenic (As)) at a high concentration in the presence of the photoresist film. .

The p ⁺ type semiconductor region 14 is formed by nMIS
The FET region and the SBD formation region are covered with a photoresist film, and p-type impurities (for example, boron) are ion-implanted at a high concentration in the presence of the photoresist film.

In the ion implantation step, the n ⁺ -type semiconductor region 13 and the p ⁺ -type semiconductor region 14 are formed in a self-aligned manner with respect to the gate electrode 6 and the sidewall spacer 12. Through these steps, n ⁻ type semiconductor region 7 and n ⁺ type semiconductor region 13 or p ⁻ type semiconductor region 8
And it consists of p ⁺ -type semiconductor region 14 LDD (Lightly
Doped drain is formed. Further, the n ⁺ -type semiconductor region 15 is formed so as to overlap with the above-mentioned n ⁻ -type semiconductor region 9, and the n ⁻ -type semiconductor region 9 disappears. Since the n ⁺ -type semiconductor region 15 is formed, no Schottky barrier is formed between the semiconductor substrate 1 (n ⁺ -type semiconductor region 15) and the pull-up electrode at the semiconductor-side terminal of the SBD, and the contact resistance can be reduced. . Further, since the n ⁺ type semiconductor region 13 and the n ⁺ type semiconductor region 15 are formed at the same time, the process can be simplified.

In the above-mentioned ion implantation step, no impurity is introduced into the region S where the Schottky barrier of the SBD formation region is formed, both n-type and p-type, as described above.

After that, the photoresist film 11 is removed. At this stage, the insulating film 10 remains in the SBD formation region where the Schottky barrier is formed. By leaving the insulating film 10 in this manner, formation of a silicide layer in a region where a Schottky barrier is formed can be prevented in a salicide step described later.

Next, as shown in FIG. 6, a metal film 16 is formed. The metal film 16 can be formed by, for example, a sputtering method, and uses a material that forms a compound (silicide) with silicon, such as titanium, tungsten, and cobalt.

Next, as shown in FIG.
Then, a heat treatment is performed using, for example, an RTA method to cause a silicide reaction in a region where the silicon and the metal film 16 are in contact with each other, thereby forming a silicide layer 17 in the contact portion. Thereafter, the unreacted metal film 16 is removed by, for example, wet etching.

As described above, the n ⁺ type semiconductor regions 13 and 15 and the p ⁺ type semiconductor region 1 are formed using the so-called salicide method.
A silicide layer 17 is simultaneously formed on the surfaces of the gate electrode 4 and the gate electrode 6. Thereby, the process is shortened to reduce the contact resistance (contact resistance) with the conductive members formed on the n ⁺ -type semiconductor regions 13 and 15 and the p ⁺ -type semiconductor region 14 and to reduce the n ⁺ -type semiconductor region 13 , 15, the p ⁺ type semiconductor region 14 and the gate resistance of the gate electrode 6 can be reduced. In particular, since the gate electrode 6 also functions as a wiring,
The performance of the semiconductor device can be improved by reducing the gate wiring resistance. In addition, the reduction of the contact resistance can also contribute to higher performance of the semiconductor device. In the case of a highly integrated semiconductor device, improvement of the operation speed is a fundamental requirement, and the semiconductor device of this embodiment can provide an excellent method for satisfying such requirement.

Since the region S of the SBD formation region where the Schottky barrier is formed is covered with the insulating film 10, no silicide layer is formed. It is necessary to form a Schottky barrier later in the region S, and not forming a silicide layer in this region is a necessary condition for forming an SBD.

Next, as shown in FIG. 8, a silicon oxide film 18 is formed on the entire surface of the semiconductor substrate 1, and further a silicon oxide film 19 is formed. The surface of the silicon oxide film 19 is planarized using, for example, a CMP method. Silicon oxide film 18
For example, a TEOS oxide film can be used. Although the silicon oxide film 19 may use a TEOS oxide film,
It is preferable to use a silicon oxide film having more excellent step coverage (flatness). For example, SOG (Spin On Glass
) Film, PSG (Phosphor Silicate Glass) film, BP
An SG (Boron Phosphor Silicate Glass) film or the like is used for the silicon oxide film 19. Further, a silicon oxide film having a low dielectric constant (for example, a silicon oxide film to which fluorine is added) can be used as the silicon oxide film 19. This allows
High-speed response performance of the semiconductor device can be improved by reducing stray capacitance between wirings. Also, a silicon oxide film 1 formed by a CMP method
9 In order to recover the damage on the surface, a silicon oxide film (for example, a TEOS oxide film) may be further formed.

Next, as shown in FIG. 9, a photoresist film is patterned on the silicon oxide film 19, and connection holes 20 to 23 are formed in the interlayer insulating film such as the silicon oxide film 19 using the photoresist film as a mask. I do. FIG.
Is a plan view showing a plane pattern at this stage.

The connection hole 20 is opened in the region S where the Schottky barrier of the SBD is formed, and has a relatively large opening diameter. The opening diameter of the connection hole 20 is, for example, several μm. By forming such a large opening diameter, it is possible to increase the area of the Schottky barrier and secure a current value required for the SBD.

The connection hole 21 is formed in the region L where the pull-up electrode of the semiconductor side terminal of the SBD is formed, and is formed with a relatively small opening. The connection hole 22 is opened in the source / drain region of the MISFET, and has a small opening diameter in a highly integrated semiconductor device. The opening diameter is, for example, 0.5 μm. The connection hole 23 is a connection hole for connecting to the gate electrode 6, and has a relatively small opening diameter.

The opening diameter of the connection holes 21 to 23 is
It is preferable that the connection hole opening step is divided into the connection hole 20 and the connection holes 21 to 23 because the connection hole is formed to be smaller than the opening diameter. That is, the connection holes 21 to 23 are opened after the connection hole 20 is opened, or vice versa, and an etching process for opening is performed separately. As described above, since the opening diameter of the connection hole 20 is large, the connection hole 2 is temporarily formed in the same process.
When openings 0 to 23 are formed, the connection holes 20 having a larger opening diameter have a higher etching rate, and the semiconductor substrate 1
(N-type well 4). At this stage, since the openings of the connection holes 21 to 23 have not been completed, over-etching is further performed, and the etching at the bottom of the connection hole 20 becomes excessive, which may cause damage due to the etching. For this reason, it is preferable to optimize the etching conditions in consideration of the etching rate that varies depending on the opening diameter, so that the connection hole opening step performs just etching. Therefore, in the case of the present embodiment in which the opening diameters of the connection holes are largely different, it is preferable to separate the etching steps. However, such separation of the steps is not an essential requirement of the present invention. For example, by forming a thin silicon nitride film on the surface of the semiconductor substrate 1 and using this silicon nitride film as an etching stopper, it is possible to take a measure to absorb a difference in etching rate.
For example, the first etching is performed under the condition that the silicon oxide film is etched but the silicon nitride film is not etched, and then the second etching is performed to etch the silicon nitride film. By such two-stage etching, the silicon nitride film functions as an etching stopper in the first etching, so that sufficient over-etching can be performed even when connection holes having different opening diameters are mixed. In the second etching, since the silicon nitride film is thin, the required amount of over-etching is small even if the opening diameter is different, and the base substrate is not unnecessarily damaged. Thus, the connection hole diameters are different. The connection holes can be simultaneously opened.

Next, as shown in FIG. 11, a p-type impurity (for example, boron difluoride (BF ₂ )) is ion-implanted. This ion implantation is performed on the entire surface of the semiconductor substrate 1 as shown. As a result, the p-type semiconductor region 24 is
Formed at the bottom. The energy of the implanted ions is, for example, 2-3 keV. The implanted ion concentration is low enough to form the p-type semiconductor region 24 by inverting the n-type well 4. For this reason, as shown, p-type ions may be implanted into the connection holes 21 to 23 other than the connection hole 20. A semiconductor region having a high impurity concentration has already been formed at the bottom of these connection holes 21 to 23, and even if a low concentration p-type impurity is implanted, there is no effect. For this reason, in this ion implantation step, there is no need to form a photoresist film by photolithography, and the step can be simplified.

The thickness of the p-type semiconductor region 24 is about 20 to 30
nm. By controlling the thickness and the amount of impurities of the p-type semiconductor region 24, the height (barrier potential) of a Schottky barrier described later can be controlled.

In the present ion implantation step, the connection holes 20
Is formed, the p-type semiconductor region 24 is formed in a self-aligned manner with respect to the connection hole 20. As described later, a metal connection member is formed in the connection hole 20, and the connection member and the p-type semiconductor region 24 are formed.
And a Schottky barrier is formed. Since this connection member is also formed in the connection hole 20, the connection member is formed in a self-aligned manner with respect to the p-type semiconductor region 24. Thus, a semiconductor device having an SBD with high integration can be formed without wasting a wasteful planar area for forming the SBD.

In such a p-type semiconductor region 24, even if the junction metal for forming the Schottky barrier is tungsten as described below, the height of the barrier can be sufficiently increased, and the breakdown voltage can be reduced. An excellent SBD can be formed.

Next, as shown in FIG.
Is formed on the entire surface of the substrate. The tungsten film 25 is formed by a sputtering method.
The tungsten film 25 has connection holes 20 to 2 as shown in FIG.
3 is formed with good step coverage so as to cover the inner surface. This can be realized by forming the tungsten film 25 so thin that the film thickness can be formed with good step coverage. Further, the tungsten film 25 also functions as a blocking layer (barrier layer) when a tungsten film described in the next step is formed by a CVD method. Further, the CV described in the next step
The tungsten film formed by the method D has a disadvantage of poor adhesion, but the tungsten film 25 is formed,
A tungsten film can be formed with good adhesion by the method.

Next, as shown in FIG.
A tungsten film 26 for burying 23 is formed. The tungsten film 26 is formed by a CVD method. As described above, the semiconductor device of the present embodiment is highly integrated, and the opening diameter of the connection hole 22 is as small as 0.5 μm. Even in the case of such a connection hole having a small opening diameter, it is possible to satisfactorily fill the concave portion by using a tungsten film formed by the CVD method. Tungsten has conventionally been known as a material capable of filling such fine connection holes, and is often used in semiconductor processes.
As described above, even when such tungsten is formed on the n-type semiconductor region (n-type well 4), a Schottky barrier having a sufficient height is not formed and an SBD with a low withstand voltage is formed. In the embodiment, since the p-type semiconductor region 24 is formed in a region that is in contact with the tungsten film 25, an SBD having excellent withstand voltage can be formed even if a tungsten film is used. That is, an SBD having excellent withstand voltage can be formed on an n-type substrate using a material which is excellent in micromachining applications such as tungsten and whose applicability has been proven.

This point will be further described with reference to FIG.
FIG. 14A shows a band diagram when a Schottky junction is formed using tungsten on an n-type substrate shown as a comparison, and FIG. 14B shows an n-type substrate according to the present embodiment.
FIG. 4 shows a band diagram when a p-type semiconductor region 24 is formed on a mold substrate (n-type well 4) and a Schottky junction is formed using tungsten.

As shown in FIG. 14A, the barrier potential (Φb1) when the junction between the metal (tungsten film 25) and the semiconductor substrate (n-type well 4) is formed without forming the p-type semiconductor region 24. Although a Schottky junction is formed, the potential Φb1 is small. According to the study of the present inventors, the value of Φb1 is about 0.55 to 0.6 eV. On the other hand, in the present embodiment, as shown in FIG. 14B, the p-type semiconductor region 24 is formed between the metal (tungsten film 25) and the semiconductor substrate (n-type well 4). The height of the Schottky barrier between the metal (tungsten film 25) and the semiconductor substrate (n-type well 4) (barrier potential Φ
b2) is higher than Φb1. According to the study of the present inventors, the value of Φb2 can be set to 0.7 eV or more. Note that the value of Φb2 can be controlled by the amount of ions (the amount of impurities) implanted into the p-type semiconductor region 24 and the depth thereof (the thickness of the p-type semiconductor region 24).

Next, as shown in FIG.
The tungsten films 26 and 25 in regions other than 23 are removed by polishing by, for example, a CMP method. As a result, plugs 27 to 29 as connection members are formed. Plug 27
The (second connection member) is a connection member for drawing out the source / drain of the MISFET, and the plug 28 is a connection member for drawing out the semiconductor-side terminal of the SBD. Also, plug 29
The (first connection member) is also a metal-side terminal of the SBD, and also functions as a connection member that draws out the terminal. As described above, the Schottky barrier is formed at the bottom of the plug 29.

Next, as shown in FIGS. 16 and 17, for example, a tungsten film is deposited on the entire surface of the semiconductor substrate 1,
The wiring 30 is formed by patterning this tungsten film in a predetermined shape. Here, a tungsten film is illustrated, but an aluminum film, a stacked film of a titanium nitride film and aluminum, a copper wiring using a damascene method, or the like may be used.

Thereafter, a wiring in a further upper layer can be formed, but a detailed description thereof will be omitted.

According to the present embodiment, a sufficiently high Schottky barrier (barrier) is formed by using tungsten on n-type well 4 to form p-type semiconductor region 24 in the region where the Schottky barrier of the SBD is formed. Can be formed. Thereby, an SBD with a high withstand voltage using a tungsten material can be formed. Further, since the SBD is formed in the connection hole 20 in a self-alignment manner, it is advantageous for high integration. Further, in the case of a highly integrated semiconductor device, the opening diameter of the connection hole 22 must be reduced to about 0.5 μm. However, since tungsten is used as a material for filling the connection hole 22,
The embedding property of the connection hole can be favorably maintained. In addition, there is no need to use platinum, molybdenum, or the like to manufacture these semiconductor devices, and there is no need to introduce new equipment and consider new process development. Further, the connecting member 29 for forming the Schottky barrier of the SBD and the other connecting members 27 and 28 can be formed at the same time, and the process can be simplified to form a semiconductor device having the SBD.

(Embodiment 2) FIGS. 18 to 23 are sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

The manufacturing method of this embodiment is the same as that of the first embodiment.
Are the same as the steps up to FIG. Therefore, a detailed description thereof will be omitted.

As shown in FIG. 8, each member up to the silicon oxide film 19 is formed in the same manner as described in the first embodiment.
Thereafter, as shown in FIGS. 18 and 19, connection holes 31 to 34 are formed using photolithography. The connection hole 31 is formed in the region S where the Schottky barrier of the SBD is formed.
And a Schottky barrier is formed at the bottom of the connection hole 31 later. The connection hole 32 is formed in the region L where the pull-up electrode of the semiconductor-side terminal of the SBD is formed. The connection hole 33 is opened in the source / drain region of the MISFET, and has a small opening diameter in a highly integrated semiconductor device. The connection hole 34 is a connection hole for connecting to the gate electrode 6, and has a relatively small opening diameter. Here, the connection holes 31 to 34 are processed so as to have substantially the same opening diameter. That is, these opening diameters are, for example, 0.5 μm.

By forming the connection holes 31 to 34 so as to have the same opening diameter, the patterning process of the photoresist film for forming the connection holes and the etching process for processing the connection holes are facilitated. . That is, to form photoresist films having different processing dimensions (patterning dimensions), selection of exposure conditions in an exposure step for photolithography (for example, using a normal illumination method or an annular illumination method in a modified illumination method). Or 4
(E.g., whether to use a point illumination method) becomes difficult. On the other hand, if the processing dimensions are uniform, it is easy to select exposure conditions, that is, it is possible to select exposure conditions suitable for the dimensions, and it is easy to form a photoresist film.

When the processing dimensions of the connection holes 31 to 34 are uniform, the opening diameter of each connection hole is substantially uniform, so that the etching rate of the insulating film such as the silicon oxide film in the connection hole becomes substantially the same. . Therefore, the connection holes are etched at substantially the same speed over the entire surface of the semiconductor substrate 1, and the connection holes can be brought into a just-etched state almost simultaneously.
Thus, over-etching of the connection hole bottom can be suppressed without using a complicated process (for example, a process using a thin silicon nitride film or the like).

Further, since the connection holes 31 to 34 can be simultaneously opened, the steps can be simplified and the manufacturing cost competitiveness of the semiconductor device can be improved.

If the connection hole 31 is formed in the same size as the connection hole 33 or the like, there is a possibility that a sufficient SBD current capacity cannot be secured. For this reason, the number of the connection holes 31 can be increased as much as possible to secure the current capacity required for the SBD, and a plurality of the connection holes 31 can be formed. In FIG. 19, the connection hole 31 is 1
Although six are formed, it is needless to say that the number is not limited to this.

Next, as shown in FIG.
P-type impurities (eg, B
F ₂ ) is ion-implanted. As a result, the p-type semiconductor region 24 is formed at the bottom of the connection hole 31. At this time, there is no effect on the semiconductor region at the bottom of the connection holes 32 to 34 as in the first embodiment.

Next, as shown in FIG.
In the same manner as described above, tungsten films 25 and 26 are formed, and as shown in FIGS. 22 and 23, the tungsten films 25 and 26 are polished and removed by applying a CMP method to form plugs 27 to 29. Further, the wiring 30 is formed as in the first embodiment.

As in the first embodiment, the plug 29 is
D is a metal side terminal. When a plurality of plugs 29 are formed in order to secure a necessary current density, the SBDs are connected by a single wiring 30 as shown in the drawing so that the SBDs are connected in parallel. The other description is the same as in the first embodiment, and will not be repeated.

According to the present embodiment, a plurality of connection holes 31 for forming an SBD are provided, and the dimensions of the connection holes 31 are changed to other connection holes 3.
It is almost the same as 2-34. For this reason, the photolithography and etching steps of the connection hole processing step are facilitated, and the steps can be shortened. The necessary current capacity of the SBD can be realized by forming a plurality of connection holes 31 and a plurality of plugs and connecting them in parallel.

(Embodiment 3) FIGS. 24 to 26 are sectional views showing a method of manufacturing a semiconductor device according to still another embodiment of the present invention in the order of steps.

The method of manufacturing a semiconductor device according to the present embodiment
This is the same as the steps up to FIG. 11 in the first embodiment.

As shown in FIG. 24, the p-type semiconductor region 24
Embodiment 1 after performing ion implantation for forming
Instead of the tungsten film 25, a titanium nitride film 40 is formed. The titanium nitride film 40 can be formed by, for example, a CVD method or a sputtering method.

Thereafter, as shown in FIG. 25, a tungsten film 41 is formed by sputtering, and as shown in FIG. 26, a tungsten film 42 is formed by CVD. Subsequent steps are the same as in the first embodiment.

In this embodiment, the metal (metal compound) in contact with p-type semiconductor region 24 is titanium nitride film 40.
As described above, when a Schottky junction is formed with an n-type substrate (n-type well 4) using titanium nitride as a metal material, a sufficient Schottky barrier height (barrier potential) cannot be obtained. However, in the present embodiment, since the p-type semiconductor region 24 is formed, even when the titanium nitride film 40 is formed, a sufficient barrier potential is obtained as in the case of tungsten in the first embodiment. be able to. Note that the optimum value of the barrier potential may change because the material is replaced with titanium nitride. In such a case, the barrier potential can be optimized by changing the amount of impurities introduced into the p-type semiconductor region 24 or the thickness of the p-type semiconductor region 24.

Note that, instead of the titanium nitride film 40, a titanium (Ti) film, a tantalum (Ta) film, a tungsten nitride (WN) film, or a tantalum nitride (TaN) film can be exemplified. Even when a Schottky barrier is formed using these metals or metal compounds, the amount of impurities to be introduced into the p-type semiconductor region 24 or the p-type semiconductor region 2
Needless to say, the barrier potential can be optimized by changing the thickness of the substrate 4.

The tungsten film 4 formed by the sputtering method
1 prevents the undersubstrate (semiconductor substrate 1) from being corroded by the atmosphere when the tungsten film 42 is deposited by the CVD method. That is, when the tungsten film is formed by the CVD method, the tungsten film is exposed to a halogen atmosphere such as fluorine, so that the tungsten film 41 has a role of a barrier for blocking such a halogen atmosphere.

Therefore, when the metal (metal compound) film forming the Schottky junction has the above-described blocking function of the atmosphere, the tungsten film 41 is not necessary. FIG. 27 is a cross-sectional view showing one example, in which a tungsten film 42 is formed on a titanium nitride film 40 by a direct CVD method. In addition to the titanium nitride film 40, a tungsten nitride film or a tungsten film formed by a sputtering method can be exemplified as a film having such a blocking action.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, it goes without saying that the titanium nitride film 40 and the like described in the third embodiment can be applied to the structure of the connection hole 31 and the like described in the second embodiment.

Further, in the above-described embodiment, a wiring formed by patterning is exemplified as the wiring 30, but it is needless to say that the wiring may be formed by using a so-called damascene method.

In the above embodiment, an n-channel MISFET and a p-channel MISFET are exemplified in addition to the SBD. However, in addition to these MISFETs, an active element such as a bipolar transistor may be formed. , N channel MISFET only, p channel M
Only the ISFET may be formed. In addition, DRA
Memory cells such as M and flash memory may be formed on the same substrate to form a system LSI.

In the above embodiment, the semiconductor device having the SBD has been generally described.
D can be applied to rectification, detection, or electrostatic protection circuits, and the present invention can be applied to a semiconductor device in which these rectification, detection, or electrostatic protection circuits are formed on the same substrate. It is possible. For example, the present invention can be applied to an IC card that can be remotely operated, an IC for a tester, or a read / write IC of a hard disk drive.

[0100]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

By using a metal such as tungsten that can be buried in a fine contact hole, an SDB with excellent withstand voltage can be formed.

An SDB having excellent withstand voltage can be formed by using a conventionally used material.

A semiconductor device having an SDB with excellent withstand voltage can be easily formed without adding a new process.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 3 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 10 is a cross-sectional plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 11 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 12 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 13 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 14 is a band diagram (b) showing a state of a Schottky barrier and a band diagram (a) shown for comparison in one embodiment of the present invention.

FIG. 15 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 16 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 17 is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 18 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

FIG. 19 is a plan view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

FIG. 20 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

FIG. 21 is a sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

FIG. 22 is a cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

FIG. 23 is a plan view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

FIG. 24 is a sectional view illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention in the order of steps.

FIG. 25 is a cross-sectional view showing a method of manufacturing a semiconductor device according to still another embodiment of the present invention in the order of steps.

FIG. 26 is a sectional view illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention in the order of steps.

FIG. 27 is a cross-sectional view showing another example of a method of manufacturing a semiconductor device according to still another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation region 3 p-type well 4 n-type well 5 gate insulating film 6 gate electrode 7 n ^- type semiconductor region 8 p ^- type semiconductor region 9 n ^- type semiconductor region 10 insulating film 11 photoresist film 12 sidewall Spacer 13 n ⁺ type semiconductor region 14 p ⁺ type semiconductor region 15 n ⁺ type semiconductor region 16 metal film 17 silicide layer 18, 19 silicon oxide film 20-23 connection hole 24 p type semiconductor region 25, 26 tungsten film 27-29 plug (Connection member) 30 Wiring 31-34 Connection hole 40 Titanium nitride film 41, 42 Tungsten film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 F term (Reference) 4M104 AA01 AA09 BB14 BB17 BB18 BB20 BB25 BB28 BB30 BB32 BB33 CC01 CC03 DD02 DD07 DD26 DD37 DD43 DD75 DD84 FF13 FF22 FF31 GG03 GG09 GG10 GG14 HH09 HH17 5F033 HH08 HH11 HH19 HH33 JJ18 JJ19 JJ21 JJ32 JJ33 JJ34 KK01 KK25 KK27 KK28 MM01 MM05 NN06 PP04 Q15 RR15Q14 AQ14 RRQA AB01 AC01 AC03 AC05 AC10 BA01 BB06 BB08 BB12 BC06 BE03 BF06 BF07 BG12 CC06 DA25 DA27

Claims (17)

[Claims] 1. An n-type semiconductor region formed on a main surface of a semiconductor substrate, an insulating film formed on the main surface, a first connection hole formed in the insulating film, and the first connection hole. A semiconductor device having a first conductive member made of a metal or a metal compound formed therein, wherein a p-type semiconductor region is formed between the first conductive member and the n-type semiconductor region. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the p-type semiconductor region is formed at a bottom of the first connection hole in a self-aligned manner with respect to the first connection hole. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein said p-type semiconductor region has a thickness in a range of 20 to 30 nm. 4. The semiconductor device according to claim 1, wherein the first conductive member is formed in contact with an inner wall of the first connection hole and the p-type semiconductor region. A first conductive film, and a second conductive film filling the connection hole, wherein the first conductive film is a tungsten film, a titanium film, a tantalum film, a tungsten nitride film, a titanium nitride film, or a tantalum nitride film. A semiconductor device characterized by the above-mentioned. 5. The semiconductor device according to claim 4, wherein said second conductive film is a tungsten film formed by a CVD method. 6. The semiconductor device according to claim 5, wherein a barrier film having resistance to an atmosphere in which tungsten is formed by a CVD method is provided between the first conductive film and the second conductive film. A semiconductor device characterized by being formed. 7. The semiconductor device according to claim 6, wherein the barrier film is a titanium nitride film, a tungsten nitride film,
Alternatively, a semiconductor device is a tungsten film formed by a sputtering method. 8. The semiconductor device according to claim 1, further comprising: a MISFET formed on a main surface of the semiconductor substrate; and a semiconductor region functioning as a source / drain of the MISFET. A second connection hole formed in the insulating film above, and a second conductive member made of a metal or a metal compound formed in the second connection hole; A semiconductor device formed simultaneously with a conductive member. 9. The semiconductor device according to claim 8, wherein the first connection hole and the second connection hole are processed to have the same design opening size. 10. The semiconductor device according to claim 9, wherein said first connection hole and said second connection hole are simultaneously opened in the same processing step. 11. The semiconductor device according to claim 9, wherein a plurality of said first connection holes are formed, and said plurality of first conductive members formed in said first connection holes are formed on said insulating film. A semiconductor device, wherein the semiconductor devices are connected to each other. 12. (a) forming an element isolation region on a main surface of a semiconductor substrate, and forming an n-type semiconductor region in a part of the active region surrounded by the element isolation region; b) forming a MISFET in the active region;
Forming an insulating film covering the SFET and the n-type semiconductor region; (c) forming a first film on the insulating film reaching the n-type semiconductor region;
Forming a connection hole and a second connection hole reaching the semiconductor region functioning as a source / drain of the MISFET; (d) ion-implanting a p-type impurity into the first connection hole, and forming the second connection hole at the bottom of the first connection hole. forming a p-type semiconductor region on the surface of the n-type semiconductor region; (e) depositing a first conductive film on the surface of the semiconductor substrate including the inside of the first and second connection holes; A second filling the inside of the first and second connection holes;
A method for manufacturing a semiconductor device, comprising: depositing a conductive film. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first connection hole and the second connection hole in the step (c) are simultaneously formed in the same processing step. A method for manufacturing a semiconductor device. 14. The method of manufacturing a semiconductor device according to claim 12, wherein the first and second connection holes are formed with the same opening size. 15. The method of manufacturing a semiconductor device according to claim 12, wherein the first conductive film is a tungsten film, a titanium film, a tantalum film, a tungsten nitride film, and a titanium nitride film. Or the tantalum nitride film, and the second conductive film is a tungsten film formed by a CVD method. 16. The method for manufacturing a semiconductor device according to claim 15, wherein before the step (f), a barrier film having resistance to an atmosphere for forming tungsten by a CVD method is formed. Manufacturing method of a semiconductor device. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the barrier film is a titanium nitride film, a tungsten nitride film,
Alternatively, a method for manufacturing a semiconductor device, comprising a tungsten film formed by a sputtering method.