JP2005322730A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of abnormal oxide in a contact region of a gate wiring.
A method of manufacturing a semiconductor device having a field effect transistor, comprising: forming a semiconductor film on a main surface of a semiconductor substrate; and ion-implanting an impurity for reducing a resistance value into the semiconductor film. A step of patterning the semiconductor film to form a wiring including the gate electrode and a contact region, a step of forming a metal / semiconductor reaction layer on the surface of the wiring, and covering the wiring Forming an insulating film on the main surface of the semiconductor substrate, and etching the insulating film to form a connection hole on a contact region of the wiring,
The impurity ion implantation step is performed in a state in which a portion of the semiconductor film to be a contact region of the wiring is covered with a mask.
[Selection] Figure 15

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having a field effect transistor and a technique effective when applied to the manufacturing technique.

  As a field effect transistor mounted on a semiconductor device, for example, an insulated gate field effect transistor called MISFET (Metal Insulator Semiconductor Field Effect Transistor) is known. This MISFET is widely used as a transistor element constituting an integrated circuit because it has a feature of being easily integrated.

  A MISFET generally has a structure including a channel formation region, a gate insulating film, a gate electrode, a source region, a drain region, and the like, regardless of the n-channel conductivity type or the p-channel conductivity type. The gate insulating film is provided in the element formation region of the main surface (element formation surface, circuit formation surface) of the semiconductor substrate, and is formed of, for example, a silicon oxide film. The gate electrode is provided on the element formation region on the main surface of the semiconductor substrate with a gate insulating film interposed, and is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. The channel formation region is provided in a region of the semiconductor substrate facing the gate electrode (a region immediately below the gate electrode). The source region and the drain region are formed of a pair of semiconductor regions (impurity diffusion regions) provided so as to sandwich the channel formation region in the channel length direction of the channel formation region.

  The gate electrode of the MISFET is formed by a part of wiring (hereinafter referred to as gate wiring) extending over the element formation region and the element isolation region on the main surface of the semiconductor substrate. The gate wiring has a gate electrode of the MISFET and a routing portion (wiring portion) connected to the gate electrode, and a contact region for electrical connection with the upper layer wiring is provided in the wiring portion.

  Here, in the MISFET, a gate insulating film made of a silicon oxide film is usually called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A channel formation region refers to a region where a current path (channel) that connects a source region and a drain region is formed. In addition, a current flowing in the thickness direction (depth direction) of the semiconductor substrate is called a vertical type, and a current flowing in the plane direction (surface direction) of the semiconductor substrate is called a horizontal type. In addition, an n-channel conductivity type (or simply n-type) in which an electron channel (conductive path) is formed in a channel formation region between a source region and a drain region, and a p-type in which a hole channel is formed. It is called channel conductivity type (or simply p-type). A type in which drain current flows only when a voltage equal to or higher than a threshold voltage is applied to the gate electrode is called an enhanced type (or E type or normally-off type), and drain current flows even if no voltage is applied to the gate electrode. Is called depletion type (or D type or normally-on type).

  By the way, MISFETs are continually miniaturized along with high integration and multi-function. In order to suppress the occurrence of short channel effects and hot electrons with the miniaturization of MISFETs, in MISFETs with a gate length of 1 [μm] or less (submicron generation), the impurity concentration on the channel formation region side of the drain region is reduced The LDD structure is adopted. Since the LDD structure can reduce the amount of diffusion of the drain region to the channel formation region side and secure the channel length dimension, generation of a short channel effect can be suppressed. In addition, since the gradient of the impurity concentration distribution at the pn junction formed between the drain region and the channel formation region is relaxed and the electric field strength generated in this region can be weakened, the amount of hot carriers generated can be reduced. it can.

  An MISFET having an LDD structure mainly includes a semiconductor region in which a gate electrode is formed on a main surface of a semiconductor substrate with a gate insulating film interposed therebetween, and then impurities are ion-implanted into the main surface of the semiconductor substrate and aligned with the gate electrode. (Extension region) is formed, and then a sidewall spacer is formed on the side wall of the gate electrode, and then a semiconductor region (contact region) aligned with the sidewall spacer is formed by implanting impurities into the main surface of the semiconductor substrate. It is obtained by doing.

  On the other hand, miniaturization of the MISFET leads to an increase in gate resistance due to reduction in the gate length dimension, and an increase in source resistance, drain resistance, and contact resistance due to shallow junction (shallowing) of the source region and drain region. This is a factor that hinders the speeding up of a memory IC (Integrated Circuit), a logic IC, a hybrid IC having a memory function and a logic function, and the like.

  Therefore, a technique for reducing resistance using a refractory metal silicide film is attracting attention in response to miniaturization and speeding up. In particular, the use of a low resistance technique called a salicide (abbreviation of Self-Aligned Silicide) technique is effective in realizing a hybrid IC.

  In addition, as a well-known document relevant to this invention, Unexamined-Japanese-Patent No. 6-204163 (patent document 1) is mention | raise | lifted, for example. This patent document 1 discloses a technique for forming an electrical contact on which a delamination does not occur on a doped polysilicon surface.

JP-A-6-204163

  As a result of studying a semiconductor device having a salicide MISFET, the present inventor has found the following problems.

  The salicide structure MISFET mainly forms a gate insulating film on the main surface of the semiconductor substrate, and then forms, for example, a polysilicon film as a semiconductor film on the main surface of the semiconductor substrate including the gate insulating film, Thereafter, impurities for reducing the resistance value are ion-implanted into the polysilicon film, and then the polysilicon film is patterned to form a gate wiring including a gate electrode and a contact region, and then the main surface of the semiconductor substrate Impurities are ion-implanted to form a pair of semiconductor regions (extension regions) aligned with the gate electrode, and then sidewall spacers are formed on the side walls of the gate wiring including the gate electrode, and then the main surface of the semiconductor substrate is formed. Impurity ions are implanted to form a pair of semiconductor regions (contact regions) aligned with the sidewall spacers on the side walls of the gate electrode. After that, for example, a cobalt (Co) film is formed as a refractory metal film on the main surface of the semiconductor substrate including the semiconductor region (contact region) and the gate wiring, and then the semiconductor region (contact region). The silicon (Si), Si of the gate wiring, and Co of the cobalt film are subjected to heat treatment to form a metal / semiconductor reaction layer on the semiconductor region (contact region) and the gate wiring, for example, cobalt silicide (SiCo). ) Layer and then selectively removing the unreacted cobalt film.

On the other hand, the electrical connection between the gate wiring and the upper layer wiring is performed through a connection hole formed on the contact region of the gate wiring by etching the interlayer insulating film.
In the manufacturing process of a semiconductor device, in order to make a good connection in a connection hole (to reduce contact resistance), a cleaning process is generally performed to remove organic and inorganic contamination after forming the connection hole. Yes. In this cleaning processing, APM cleaning (alkali processing) and HPM cleaning (oxidizing acid processing) are performed.

In the APM cleaning, for example, a cleaning solution of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5 (60 ° C., 120 sec) is used.
In the HPM cleaning, for example, a cleaning solution of HCl: H ₂ O ₂ : H ₂ O = 1: 1: 5 (60 ° C., 120 sec) is used.

  In this cleaning process, the present inventors oxidize the cobalt silicide (CoSi) layer of the gate wiring to generate an abnormal oxide, and due to the influence of the abnormal oxide, a poor conduction between the gate wiring and the upper wiring occurs. I found out.

  According to the inventor's study, the connection failure is caused by the misalignment of the mask when the connection hole is formed, and the connection hole 18b eats away from the gate wiring 10 as shown in FIG. 64 (schematic cross-sectional view). It has been found that this happens when it comes out (when it is out of line with the gate wiring).

  Since the connection hole 18 b is formed by etching the interlayer insulating film 17, when the connection hole 18 b is out of alignment with the gate wiring 10, the side wall spacer 13 is scraped off due to overetching, and the gate wiring 10 poly The silicon film 6 is exposed. Further, when the connection hole 18b is disconnected from the gate wiring 10, the sidewall spacer 13 is removed by APM cleaning, and the polysilicon film 6 of the gate wiring 10 is exposed. The exposure of the polysilicon film 6 of the gate wiring 10 also occurs during over-etching when the sidewall spacer 13 is formed.

When the HPM cleaning is performed with the polysilicon film 6 of the gate wiring 10 exposed, a local battery is formed between the polysilicon film 6 of the gate wiring 10 and the cobalt silicide layer 16a, and the cobalt silicide layer 16a is oxidized. An abnormal oxide 21 is generated. Specifically, as shown in FIG. 65 (schematic perspective view), holes are generated by the reaction between H ₂ O ₂ in the HPM cleaning liquid and Si of the polysilicon film 6, thereby causing the cobalt silicide layer 16 a to have a hole. Co is eluted into the solution, and Si in the cobalt silicide layer 16a grows abnormally as SiO ₂ . Since the APM cleaning liquid is also mixed with H ₂ O _2, there is a possibility that an abnormal oxide may be generated. However, since SiO ₂ is dissolved by NH ₄ OH in the APM cleaning liquid, no abnormal oxide remains.

  The generation of abnormal oxide due to such local cell action causes poor conduction between the gate wiring and the upper wiring and causes a decrease in the manufacturing yield of the semiconductor device, and therefore countermeasures are necessary. In particular, since the width of the gate wiring becomes narrower with the miniaturization of processes and devices, and it is necessary to allow the connection holes to be disconnected from the gate wiring, such a defect may become more apparent in the future. is there.

According to the study by the present inventor, it has been found that the reaction between H ₂ O ₂ in the HPM cleaning solution and Si in the polysilicon film is easier to occur as the impurity concentration in the polysilicon film is higher. This is because holes are more easily tunneled between the polysilicon film / cobalt silicide layer as the impurity concentration in the polysilicon film is higher.

  FIG. 66 is a diagram showing an example of the prior art. In the manufacturing process of a semiconductor device having two-level complementary MOSFETs having different gate breakdown voltages, the types of impurities (ions) implanted into the polysilicon film in the contact region of the gate wiring It is a figure which shows seed | species) and injection amount. As shown in FIG. 66, a very large amount of impurity ions of a total order of 1E16 (1 × 10 16 [atoms / cm 2]) is implanted into the polysilicon film in the contact region of the gate wiring.

  FIG. 67 is a diagram showing an example of the prior art, and shows the relationship between the impurity concentration in the polysilicon film in the contact region of the gate wiring and the contact resistance in a semiconductor device having two-level complementary MOSFETs with different gate breakdown voltages. FIG. As shown in FIG. 67, it can be seen that the drop in resistance increases as the impurity concentration increases.

Therefore, the present inventor made the present invention paying attention to the impurity ion implantation step in the manufacturing process of the MISFET.
An object of the present invention is to provide a technique capable of suppressing generation of abnormal oxide in a contact region of a gate wiring.
Another object of the present invention is to provide a technique capable of improving the manufacturing yield of semiconductor devices.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

In the manufacturing process of MISFET, generally, after forming a gate insulating film,
(A) Impurity ion implantation for reducing the resistance value of a semiconductor film used for forming a gate wiring including a gate electrode and a contact region;
(B) Impurity ion implantation for forming a pair of semiconductor regions (extension regions) aligned with the gate electrode;
(C) Impurity ion implantation for forming a semiconductor region (contact region) aligned with the side wall spacer on the side wall of the gate electrode;
Is implemented.

  In any one of these impurity ion implantations ((A), (B), (C)), impurities are not implanted into the contact region of the gate wiring, and the impurity concentration in the contact region of the gate wiring is reduced. By lowering the value, the above object can be achieved. For example:

(1) A gate wiring including a gate electrode and a contact region is formed by patterning a semiconductor film after ion implantation of an impurity for reducing a resistance value into a semiconductor film (for example, a silicon film). Therefore, in the step (A), impurities are ion-implanted into the semiconductor film in a state where the portion of the semiconductor film that becomes the contact region of the gate wiring is covered with the mask.

(2) A pair of semiconductor regions (extension regions) aligned with the gate electrode are formed by ion-implanting impurities into the main surface of the semiconductor substrate. Therefore, in the step (B), impurities are ion-implanted into the main surface of the semiconductor substrate with the contact region of the gate wiring covered with a mask.

(3) A pair of semiconductor regions (contact regions) aligned with the side wall spacers on the side walls of the gate electrode are formed by ion implantation of impurities into the main surface of the semiconductor substrate. Therefore, in the step (C), impurities are ion-implanted into the main surface of the semiconductor substrate with the contact region of the gate wiring covered with a mask.

  Of the impurity ion implantation steps (A) to (C), it is desirable not to implant impurities into the contact region of the gate wiring in the step having the largest dose.

  Further, in order to suppress an increase in resistance of the semiconductor film in the contact region of the gate wiring, an impurity is ion-implanted in the contact region of the gate wiring in any one of the steps (A) to (C). Is desirable. When the semiconductor film in the contact region of the gate wiring is non-doped (when not on-implanted at all), the contact region has a high resistance, which hinders the speeding up of the circuit. Therefore, it is important to reduce the impurity concentration in the semiconductor film in the contact region while suppressing the increase in resistance of the contact region.

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.
According to the present invention, generation of abnormal oxide in the contact region of the gate wiring can be suppressed.
According to the present invention, it is possible to improve the manufacturing yield of semiconductor devices.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

(Embodiment 1)
In the first embodiment, of the three impurity ion implantations ((A), (B), (C)) performed in the manufacture of the MISFET, the impurity for reducing the resistance of the polysilicon film serving as the gate wiring An example in which ion implantation (A) is controlled to suppress generation of abnormal oxide in the contact region of the gate wiring will be described.

1 to 15 are diagrams related to the semiconductor device according to the first embodiment of the present invention.
FIG. 1 is a schematic plan view showing a schematic configuration of a complementary MISFET mounted on a semiconductor device.
2 is a schematic cross-sectional view showing a schematic configuration of the complementary MISFET of FIG.
3 to 14 are schematic cross-sectional views showing a manufacturing process of a semiconductor device,
FIG. 15 is a schematic plan view showing a mask pattern in the manufacturing process of the semiconductor device.

In FIG.
(A) is sectional drawing which follows the aa line of FIG.
(B) is a sectional view taken along line bb in FIG.
(C) is sectional drawing which follows the cc line of FIG.

3 to 14,
(A) is sectional drawing in the position in alignment with the aa line of FIG.
(B) is a cross-sectional view at a position along the line bb in FIG.
(C) is sectional drawing in the position in alignment with the cc line of FIG.

In FIG.
(A) is a top view which shows the mask pattern (M1) of FIG.
(B) is a plan view showing the mask pattern (M2) of FIG.
(C) is a plan view showing the mask pattern (M3) of FIG. 8,
(D) is a plan view showing the mask pattern (M4) of FIG. 9,
(E) is a plan view showing the mask pattern (M5) of FIG. 11,
(F) is a top view which shows the mask pattern (M6) of FIG.

  As shown in FIGS. 1 and 2 ((a), (b), (c)), the semiconductor device of the first embodiment is a p-type substrate 1 (hereinafter referred to as a silicon substrate) made of, for example, single crystal silicon as a semiconductor substrate. Called).

  The main surface (element formation surface, circuit formation surface) of the silicon substrate 1 has element formation regions (active regions) 1n and 1p partitioned by an element isolation region (inactive region) 2, and the element formation region 1n includes , A p-type well region 4 and an n-type MISFET-Qn (see FIG. 2A) are formed, and an n-type well region 3 and a p-type MISFET-Qp (see FIG. 2B) are formed in the element formation region 1p. Is formed. The n-type and p-type MISFETs (Qn, Qp) are a kind of field effect transistor, and in the first embodiment, a drain type current flows in the plane direction of the silicon substrate 1.

  Although not limited to this, the element isolation region 2 is configured by, for example, a shallow groove isolation (SGI) region. The shallow groove isolation region is formed by forming a shallow groove on the main surface of the silicon substrate 1 and then selectively burying an insulating film (for example, a silicon oxide film) inside the shallow groove.

  The n-type and p-type MISFETs (Qn, Qp) mainly have a channel formation region, a gate insulating film 5, a gate electrode 7, a source region, and a drain region. The gate insulating film 5 is provided in the element forming region (1n, 1p) on the main surface of the silicon substrate 1, and the gate electrode 7 is interposed on the element forming region on the main surface of the silicon substrate 1 with the gate insulating film 5 interposed therebetween. The channel formation region is provided in the surface layer portion of the silicon substrate 1 immediately below the gate electrode 7. The source region and the drain region are provided in the surface layer portion of the silicon substrate 1 so as to sandwich the channel formation region in the channel length (gate length) direction of the channel formation region.

  As shown in FIG. 2A, the source region and the drain region of the n-type MISFET-Qn are a pair of n-type semiconductor regions (impurity diffusion layers) 11 as extension regions and a pair of n-type semiconductors as contact regions. The region (impurity diffusion layer) 14 is included. The n-type semiconductor region 11 is provided in the element formation region 1 n on the main surface of the silicon substrate 1 in alignment with the gate electrode 7. The n-type semiconductor region 14 is provided in the element formation region 1 n on the main surface of the silicon substrate 1 in alignment with the side wall spacer 13 provided on the side wall of the gate electrode 7.

  As shown in FIG. 2B, the source region and drain region of the p-type MISFET-Qp are a pair of p-type semiconductor regions (impurity diffusion layers) 12 as extension regions and a pair of p-type semiconductors as contact regions. The region (impurity diffusion layer) 15 is included. The p-type semiconductor region 12 is provided in the element formation region 1 p on the main surface of the silicon substrate 1 in alignment with the gate electrode 7. The p-type semiconductor region 14 is provided in the element formation region 1 p on the main surface of the silicon substrate 1 in alignment with the side wall spacer 13 provided on the side wall of the gate electrode 7.

  The n-type semiconductor region 14 that is a contact region has a higher impurity concentration than the n-type semiconductor region 11 that is an extension region. The p-type semiconductor region 15 that is the contact region has a higher impurity concentration than the p-type semiconductor region 12 that is the extension region. That is, the n-type and p-type MISFETs (Qn, Qp) of the first embodiment have an LDD structure.

  As shown in FIG. 1, on the main surface of the silicon substrate 1, a gate wiring 10 extending over the element formation region (1n, 1p) and the element isolation region 2 is provided. The gate wiring 10 includes gate electrodes 7 of n-type and p-type MISFETs (Qn, Qp), and routing portions (wiring portions) 8 integrally connected to the gate electrodes 7. Is provided with a contact region 9 for electrical connection with the upper wiring.

  As shown in FIG. 2 ((a), (b)), the surfaces of the semiconductor regions (14, 15) of the n-type and p-type MISFETs (Qn, Qp) are made of metal in order to reduce resistance. For example, a cobalt silicide (CoSi) layer 16b is formed as the semiconductor reaction layer. 2 ((a), (b), (c)), for example, a cobalt silicide (CoSi) layer is formed on the surface of the gate wiring 10 as a metal / semiconductor reaction layer in order to reduce the resistance. 16a is formed. These cobalt silicide layers (16a, 16b) are formed in alignment with the sidewall spacers 13 by, for example, a salicide (Self Aligned Silicide) technique. That is, the n-type and p-type MISFETs (Qn, Qp) of Embodiment 1 have a salicide structure.

  The gate wiring 10 has a multilayer structure having a semiconductor film and a metal / semiconductor reaction layer provided on the semiconductor film. For example, a polysilicon film is used as the semiconductor film, and a cobalt silicide layer 16a is used as the metal / semiconductor reaction layer. The cobalt silicide layer 16a is formed over the gate wiring 10 including the gate electrode 7 and the routing portion 8 of each of the n-type and p-type MISFETs (Qn, Qp).

  As shown in FIG. 2 ((a), (b), (c)), the main surface of the silicon substrate 1 is covered with, for example, silicon oxide so as to cover the n-type and p-type MISFETs (Qn, Qp). An interlayer insulating film 17 made of a film is provided. On the n-type semiconductor region 14 and the p-type semiconductor region 15, as shown in FIGS. 2A and 2B, a connection hole 18 a that reaches the silicide layer 16 b from the surface of the interlayer insulating film 17 is provided. The conductive plug 19 is embedded in the connection hole 18a. The n-type and p-type semiconductor regions (14, 15) are electrically connected to the wiring 20 extending on the interlayer insulating film 17 with the silicide layer 16a and the conductive plug 19 interposed therebetween.

As shown in FIG. 2C, a connection hole 18b reaching the silicide layer 16a from the surface of the interlayer insulating film 17 is provided on the contact region 9 of the gate wiring 10, and a conductive layer is formed in the connection hole 18b. A plug 19 is embedded. The contact region 9 of the gate wiring 10 is electrically connected to the wiring 20 extending on the interlayer insulating film 17 with the conductive plug 19 interposed.
The gate wiring 10 has a portion having a higher impurity concentration than the contact region 9 in the polysilicon film.

Next, the manufacture of the semiconductor device of Embodiment 1 will be described with reference to FIGS.
First, a p-type silicon substrate 1 made of single crystal silicon having a specific resistance of about 10 [Ωcm] is prepared, and thereafter, an element isolation region 2 that partitions the element formation regions 1n and 1p is formed on the main surface of the silicon substrate 1. (See FIGS. 3A, 3B, and 3C). The element isolation region 2 is not limited to this. For example, a shallow groove (for example, a groove having a depth of about 300 [nm]) is formed on the main surface of the silicon substrate 1, and then the main surface of the silicon substrate 1 is formed. An insulating film made of a silicon oxide film is formed by a CVD (Chemical Vapor Deposition) method, and then flattened by a CMP (Chemical Mechanical Polishing) method so that the insulating film remains selectively inside the shallow groove. It is formed by doing.

  Next, a p-type well region 4 is selectively formed in the element formation region 1n on the main surface of the silicon substrate 1, and an n-type well region 3 is selectively formed in the element formation region 1p. Thereafter, as shown in FIG. Then, a gate insulating film 5 made of a silicon oxide film having a thickness of about 2 to 4 [nm] is formed in the element formation regions 1n and 1p on the main surface of the silicon substrate 1, for example.

  Next, as shown in FIG. 4 ((a), (b), (c)), the silicon substrate 1 including the gate insulating film 5 in each of the element formation regions 1n and 1p and the element isolation region 2 is formed. On the main surface, as a semiconductor film used for forming the gate wiring 10, a polysilicon film 6 having a thickness of, for example, about 100 to 300 [nm] is formed by a CVD (Chemical Vapor Deposition) method.

  Next, an impurity for reducing the resistance value is ion-implanted into the polysilicon film 6 (impurity ion implantation (A)). In the first embodiment, this impurity ion implantation is controlled so that impurities are not ion-implanted into the portion of the silicon film 6 that becomes the contact region 9 of the gate wiring 10.

  In this impurity ion implantation, impurity ion implantation for converting the gate electrode 7 of the n-type MISFET-Qn into n-type and impurity ion implantation for converting the gate electrode 7 of the p-type MISFET-Qp into p-type are separately performed. Do. In a CMIS (Complementary Metal Insulator Semiconductor) process after 0.2 [μm], in order to suppress the short channel effect of the p-type MISFET due to miniaturization, the gate electrode of the p-type MISFET is made p-type, and the structure of the p-type MISFET From the buried channel type to the surface channel type.

  Here, impurity ion implantation for making the gate electrode 7 of the n-type MISFET-Qn n-type is called n-type impurity ion implantation, and impurity ions for making the gate electrode 7 of the p-type MISFET-Qp p-type. The implantation is called p-type impurity ion implantation.

The n-type impurity ion implantation is performed as shown in FIGS. 5A, 5B, and 5C in the portion of the polysilicon film 6 that becomes the gate wiring 10 (gate wiring formation region) and FIG. As described above, the etching is performed in a state where the portion on the element formation region 1p (the portion serving as the gate electrode of the p-type MISFET) and the portion serving as the contact region 9 of the gate wiring 10 are selectively covered with the mask M1. In this n-type impurity ion implantation, for example, phosphorus (P) is used as an impurity, acceleration energy is about 20 KeV, and a dose amount is about 6.0E15 (6 × 10 ¹⁵ [atoms / cm ² ]). . As the mask M1, for example, a photoresist mask formed by a photolithography technique is used.

  In this step, of the portion of the polysilicon film 6 to be the gate wiring 10, the portion of the silicon film 6 covered with the mask M1, specifically, the portion to be the gate electrode of the p-type MISFET (on the element formation region 1p) ), A portion of the portion that becomes the routing portion 8 of the gate wiring 10, and a portion that becomes the contact region 9 of the gate wiring 10 are not subjected to impurity ion implantation.

  On the other hand, of the portion of the polysilicon film 6 that becomes the gate wiring 10, the portion that is not covered with the mask M1, specifically, the portion that becomes the gate electrode 7 of the n-type MISFET (the portion on the element formation region 1n), In addition, impurity ions are implanted into a part of the portion that becomes the routing portion 8 of the gate wiring 10.

The p-type impurity ion implantation is shown in FIG. 6 ((a), (b), (c)) and FIG. 15 (b) in the portion (gate wiring formation region) of the polysilicon film 6 to be the gate wiring 10. As described above, the process is performed in a state where the portion on the element formation region 1n (the portion serving as the gate electrode of the n-type MISFET) and the portion serving as the contact region 9 of the gate wiring 10 are selectively covered with the mask M2. In this impurity ion implantation, for example, boron (B) is used as an impurity, and the acceleration energy is about 5 KeV and the dose amount is about 4.0E15 (4 × 10 ¹⁵ [atoms / cm ² ]). As the mask M2, for example, a photoresist mask formed by a photolithography technique is used.

  In this process, the silicon film 6 covered with the mask M2 among the silicon film 6 to be the gate wiring 10, specifically, the part to be the gate electrode of the n-type MISFET (on the element formation region 1n). (Parts), a part of the part that becomes the routing part 8 of the gate wiring 10, and a part that becomes the contact region 9 of the gate wiring 10 are not subjected to ion implantation of impurities.

  On the other hand, of the portion of the polysilicon film 6 that becomes the gate wiring 10, the portion that is not covered with the mask M 2, specifically, the portion that becomes the gate electrode 7 of the p-type MISFET (the portion on the element formation region 1 p), In addition, impurity ions are implanted into a part of the portion that becomes the routing portion 8 of the gate wiring 10.

  In the first embodiment, n-type impurity ion implantation is performed prior to p-type impurity ion implantation. However, n-type impurity ion implantation is performed prior to p-type impurity ion implantation. You may go to

  Next, after removing the mask M2, the polysilicon film 6 is patterned, and as shown in FIGS. 7 (a), (b), and (c), the gate disposed on the element formation region 1n. An electrode 7, a gate electrode 7 disposed on the element formation region 1 p, a routing portion 8 that is integrally connected to the gate electrode 7 and disposed on the element isolation region 2, and is provided in the routing portion 8. A gate wiring 10 having the contact region 9 formed is formed.

  Next, after performing heat treatment for activating impurities in the polysilicon film of the gate wiring 10, as shown in FIGS. 8 (a), (b), (c), and FIG. 15 (c). In addition, while the element formation region 1p on the main surface of the silicon substrate 1 is selectively covered with the mask M3, impurities are ion-implanted into the element formation region 1n on the main surface of the silicon substrate 1 to be aligned with the gate electrode 7. A pair of n-type semiconductor regions (extension regions) 11 are formed (impurity ion implantation (B)). As the mask M3, for example, a photoresist mask formed by a photolithography technique is used. Impurity ion implantation is not limited to this, but is performed, for example, in three steps.

In the first impurity ion implantation, for example, arsenic (As) is used as an impurity, and the acceleration energy is about 3 KeV and the dose is about 1.0E15 (1 × 10 ¹⁵ [atoms / cm ² ]).

In the second impurity ion implantation, for example, boron (B) is used as an impurity, and the acceleration energy is about 20 KeV and the dose is about 1.0E13 (1 × 10 ¹³ [atoms / cm ² ]).

In the third impurity ion implantation, for example, boron (B) is used as an impurity, and the acceleration energy is about 10 KeV and the dose is about 5.6E13 (1 × 10 ¹³ [atoms / cm ² ]).

  In this step, impurities are ion-implanted into the portion of the gate wiring 10 covered with the mask M3, specifically, the gate electrode 7 on the element formation region 1p and a part of the routing portion 8. Absent.

  On the other hand, impurity ion implantation is performed on a portion of the gate wiring 10 that is not covered with the mask M3, specifically, on the gate electrode 7 on the element formation region 1n, a part of the routing portion 8, and the contact region 9. Is done.

  Next, after removing the mask M3, as shown in FIGS. 9 ((a), (b), (c)) and FIG. 15 (d), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M4, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (extension regions) 12 aligned with the gate electrode 7 ( Impurity ion implantation (B)). As the mask M4, for example, a photoresist mask formed by a photolithography technique is used. Impurity ion implantation is not limited to this, but is performed, for example, in three steps.

In the first impurity ion implantation, for example, boron difluoride (BF ₂ ) is used as an impurity, the acceleration energy is about 3 KeV, and the dose amount is about 1.0E15 (1 × 10 ¹⁵ [atoms / cm ² ]). Perform under conditions.

In the second impurity ion implantation, for example, phosphorus (P) is used as an impurity, and the acceleration energy is about 55 KeV and the dose is about 1.0E13 (1 × 10 ¹³ [atoms / cm ² ]).

In the third impurity ion implantation, for example, phosphorus (P) is used as an impurity, and the acceleration energy is about 30 KeV and the dose is about 5.6E13 (1 × 10 ¹³ [atoms / cm ² ]).

  In this step, impurity ions are implanted into the portion of the gate wiring 10 covered with the mask M4, specifically, the gate electrode 7 on the element formation region 1n and a part of the routing portion 8. Absent.

  On the other hand, in the portion of the gate wiring 10 that is not covered with the mask M4, specifically, the gate electrode 7 on the element formation region 1p, a part of the routing portion 8, and the contact region 9, impurity ions are implanted. Is done.

  Next, after removing the mask 4, as shown in FIGS. 10 (a), (b), and (c), sidewall spacers 13 are formed on the side walls of the gate wiring 10 including the gate electrode 7 and the routing portion 8. Form. The sidewall spacer 13 is formed by forming an insulating film made of, for example, a silicon oxide film on the entire main surface of the silicon substrate 1 by a CVD method, and thereafter performing anisotropic etching such as RIE (Reactive Ion Etching) on the insulating film. It is formed by applying. The sidewall spacer 13 is formed in alignment with the gate wiring 10.

  Next, as shown in FIGS. 11 (a), (b), (c)) and FIG. 15 (e), the element formation region 1p on the main surface of the silicon substrate 1 is selectively covered with a mask M5. In this state, impurities are ion-implanted into the element formation region 1n on the main surface of the silicon substrate 1 to form a pair of n-type semiconductor regions (contacts) 14 aligned with the sidewall spacers 13 (impurity ion implantation (C)). . As the mask M5, for example, a photoresist mask formed by a photolithography technique is used. Impurity ion implantation is not limited to this, but is performed, for example, in two steps. In FIG. 15E, the side wall spacers 13 are not shown for easy understanding of the invention.

In the first impurity ion implantation, for example, arsenic (As) is used as an impurity, under conditions of an acceleration energy of about 40 KeV and a dose amount of about 4.0E15 (1 × 10 ¹⁵ [atoms / cm ² ]).

In the second impurity ion implantation, for example, phosphorus (P) is used as an impurity, and the acceleration energy is about 55 KeV and the dose amount is about 2.0E13 (1 × 10 ¹³ [atoms / cm ² ]).

  In this step, impurities are not ion-implanted into the portion of the gate wiring 10 covered with the mask M5, specifically, the gate electrode 7 and part of the routing portion 8 on the element formation region 1p. .

  On the other hand, impurity ion implantation is performed on a portion of the gate wiring 10 that is not covered with the mask M5, specifically, on the gate electrode 7 on the element formation region 1n, a part of the routing portion 8, and the contact region 9. Is done.

  Next, after removing the mask 5, as shown in FIGS. 12 (a), (b), (c)) and FIG. 15 (f), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M6, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (contacts) 15 aligned with the sidewall spacers 13 ( Impurity ion implantation (C)). As the mask M6, for example, a photoresist mask formed by a photolithography technique is used. Impurity ion implantation is not limited to this, but is performed, for example, in two steps. In FIG. 15F, the side wall spacers 13 are not shown for easy understanding of the invention.

In the first impurity ion implantation, for example, boron difluoride (BF ₂ ) is used as an impurity, the acceleration energy is about 25 KeV, and the dose amount is about 2.0E15 (1 × 10 ¹⁵ [atoms / cm ² ]). Perform under conditions.

In the second impurity ion implantation, for example, boron (B) is used as an impurity, and the acceleration energy is about 20 KeV and the dose is about 2.0E13 (1 × 10 ¹³ [atoms / cm ² ]).

  In this step, impurity ions are not implanted into the portion of the gate wiring 10 covered with the mask M6, specifically, the gate electrode 7 on the element formation region 1n and part of the routing portion 8. .

  On the other hand, in the portion of the gate wiring 10 that is not covered with the mask M6, specifically, the gate electrode 7 on the element formation region 1p, a part of the routing portion 8, and the contact region 9, impurity ions are implanted. Is done.

Next, after removing the mask M6, ion implantation is performed in the n-type semiconductor region 11 formation step, the p-type semiconductor region 12 formation step, the n-type semiconductor region 14 formation step, and the p-type semiconductor region 15 formation step. The impurities (P, As, B, BF ₂ ) are activated by heat treatment.

  In the first embodiment, the heat treatment for activating the impurities in the polysilicon film of the gate wiring 10 is performed before the extension forming step. However, the activation of the impurities in the polysilicon film of the gate wiring 10 is performed. May be performed in a heat treatment for activating impurities in the semiconductor region (11, 12, 14, 15).

  Next, as shown in FIG. 13 ((a), (b), (c)), on the surface of the gate wiring 10 including the gate electrode 7 and the routing portion 8, and on the surface of the semiconductor region (14, 15), For example, cobalt silicide layers (16a, 16b) are formed as the metal / semiconductor reaction layers. The cobalt silicide layers (16a, 16b) are formed by removing the natural oxide film and the like to expose the surface of the gate wiring 10 and the surface of the semiconductor region (14, 15), and then the main surfaces of the silicon substrate 1 including these surfaces. A cobalt (Co) film as a refractory metal film is formed on the entire surface by sputtering, and thereafter, Si in the polysilicon film of the gate wiring 10, Si in the semiconductor region (14, 15), and Co in the cobalt film. The film is formed by performing a heat treatment that causes the unreacted cobalt film to be selectively removed. The cobalt silicide layers (16a, 16b) are formed in alignment with the sidewall spacers 13. Through this process, the salicide structure n-type and p-type MISFETs (Qn, Qp) are almost completed.

  Next, an interlayer insulating film 17 made of, for example, a silicon oxide film is formed on the entire surface of the main surface of the silicon substrate 1 including the n-type and p-type MISFETs (Qn, Qp) and the gate wiring 10 by the CVD method. Thereafter, the surface of the interlayer insulating film 17 is planarized by the CMP method.

  Next, the interlayer insulating film 17 is etched, and as shown in FIGS. 14 ((a), (b), (c)), contact holes 18a and contacts for the gate wiring 10 are formed on the semiconductor regions (14, 15). A connection hole 18 b is formed on the region 9. The connection hole 16a reaches the cobalt silicide layer 16b from the surface of the interlayer insulating film 17, and the connection hole 18b reaches the cobalt silicide layer 16a from the surface of the interlayer insulating film 17.

  Next, in order to make a good connection in the connection holes (18a, 18b) (to reduce contact resistance), a cleaning process is performed to remove organic and inorganic contaminants. In this cleaning processing, APM cleaning (alkali processing) and HPM cleaning (oxidizing acid processing) are performed.

In the APM cleaning, for example, a cleaning solution of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5 (60 ° C., 120 sec) is used.
In the HPM cleaning, for example, a cleaning solution of HCl: H ₂ O ₂ : H ₂ O = 1: 1: 5 (60 ° C., 120 sec) is used.

  Next, a conductive plug 19 is formed by embedding a conductive material such as a metal in the connection holes (18 a, 18 b), and then a wiring 20 is formed on the interlayer insulating film 17. By this step, the structure shown in FIG. 2 is obtained.

  By the way, the connection holes (18a, 18b) are formed by forming a photosensitive resist film on the interlayer insulating film 17, and then positioning a photomask (reticle) having a pattern for forming the connection holes, and thereafter performing an exposure process. The pattern of the photomask is transferred to the photosensitive resist film, and then a development process and a cleaning / drying process are performed to form a mask (etching mask) made of a photosensitive resist film on the interlayer insulating film 17. Then, since the interlayer insulating film exposed from the etching mask is formed by etching, as shown in FIG. 64, the connection hole 18b protrudes from the gate wiring due to misalignment of the photomask (gate wiring). May be formed in an off-centered state.

  In the case where such disconnection occurs, the side wall spacer 13 is removed by over-etching when forming the connection hole, and the polysilicon film 6 of the gate wiring 10 is exposed in the connection hole 18b. Further, when such misalignment occurs, the sidewall spacer 13 is scraped by APM cleaning after forming the connection hole, and the polysilicon film 6 of the gate wiring 10 is exposed in the connection hole 18b. The exposure of the polysilicon film 6 of the gate wiring 10 also occurs during over-etching when the sidewall spacer 13 is formed.

  When HPM cleaning is performed in the connection hole 18b with the polysilicon film 6 of the gate wiring 10 exposed, as described above, a local battery is formed between the polysilicon film of the gate wiring 10 and the cobalt silicide layer 16a. The cobalt silicide layer 16a is oxidized to generate an abnormal oxide. This abnormal oxide is more easily generated as the impurity concentration in the polysilicon film of the gate wiring 10 is higher. Therefore, in order to suppress the generation of the abnormal oxide, the abnormal oxide in the contact region 9 of the gate wiring 10 It is effective to reduce the impurity concentration.

  In the first embodiment, an impurity ion implantation step (see FIGS. 5 and 15A) for converting the gate electrode 7 of the n-type MISFET-Qn into the n-type, and the gate electrode 7 of the p-type MISFET-Qp are made p In a step of implanting impurity ions for making a mold (see FIGS. 6 and 15B), a portion of the silicon film 6 that becomes the contact region 9 of the gate wiring 10 is covered with a mask (M1, M2). Since impurities are ion-implanted into the silicon film 6, the contact region of the gate wiring 10 is compared with the case where the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 is not covered with the mask (M1, M2). 9 can reduce the impurity concentration in the polysilicon film.

In this way, by performing impurity ion implantation in a state where the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 is covered with the mask (M1, M2), the polysilicon film in the contact region 9 of the gate wiring 10 is obtained. The impurity concentration inside can be lowered. That is, the routing portion 8 which is a part of the gate wiring 10 is formed such that the impurity concentration of the polysilicon film in the contact region 9 in which the connection hole 18b is formed is different from the impurity concentration in other regions. The impurity concentration of the polysilicon film in the region 9 is lower than the impurity concentration in other regions. For this reason, it is possible to suppress the generation of abnormal oxide generated in the contact region 9 of the gate wiring 10 due to the local battery action.
In addition, by suppressing the generation of abnormal oxide, poor conduction between the gate wiring 10 and the upper wiring 20 can be suppressed, so that the manufacturing yield of the semiconductor device can be improved.

  In the manufacturing process of the complementary MISFET, generally, when an impurity for ion-implanting a portion of the polysilicon film 6 that becomes the gate electrode 7 of the n-type MISFET-Qn is ion-implanted, the gate of the p-type MISFET-Qp When the portion of the polysilicon film 6 that becomes the electrode 7 is covered with the mask M1, and the impurity for making the portion of the polysilicon film 6 that becomes the gate electrode 7 of the p-type MISFET-Qp into the p-type is ion-implanted, n A portion of the polysilicon film 6 that becomes the gate electrode 7 of the type MISFET-Qn is covered with a mask M2. In the first embodiment, the polysilicon film 6 that becomes the gate electrode 7 of the p-type MISFET-Qp is ion-implanted when the impurity for converting the polysilicon film 6 that becomes the gate electrode 7 of the n-type MISFET-Qn into the n-type is ion-implanted. And the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 are covered with the same mask M1, and the portion of the polysilicon film 6 that becomes the gate electrode 7 of the p-type MISFET-Qp is made p-type. When the impurity ions are implanted, the portion of the polysilicon film 6 that becomes the gate electrode 7 of the n-type MISFET-Qn and the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 are covered with the same mask M2. Yes.

  By performing impurity ion implantation in this way, it is not necessary to newly form a mask that covers the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10, so that abnormal oxidation can be performed without increasing the manufacturing cost. The production of objects can be suppressed, and the manufacturing yield of semiconductor devices can be improved.

  In order to realize high integration and low cost of a semiconductor device, how to reduce the number of photomasks (reticles) is an important issue. This is because the reduction in the number of photomasks not only reduces the production cost of the photomask itself, but also a series of processes of applying, exposing, developing, cleaning and drying the photoresist for forming a photoresist pattern using the photomask. This is because the process cost of the semiconductor device can be significantly reduced. In addition, it is possible to further reduce the rate of occurrence of defects due to foreign matter, and to improve the yield and reliability of the semiconductor device.

  If no impurity ions are implanted into the polysilicon film in the contact region 9 of the gate wiring 10, the contact region 9 becomes high resistance. In contrast, in the first embodiment, in the impurity ion implantation (B) in FIGS. 15C and 15D and in the impurity ion implantation (C) in FIGS. Since impurities are ion-implanted into the polysilicon film, the impurity concentration in the polysilicon film in the contact region 9 is lowered while suppressing the increase in resistance of the contact region 9.

  Further, a cobalt silicide layer is formed over the entire polysilicon film 6 in order to suppress an increase in resistance accompanying the miniaturization of the gate wiring 10. Therefore, the impurity concentration in the polysilicon film in the contact region 9 is lowered while suppressing the increase in resistance of the entire gate wiring 10.

  In the first embodiment, the contact region of the gate wiring 10 in both the n-type impurity ion implantation shown in FIGS. 5 and 15A and the p-type impurity ion implantation shown in FIGS. 6 and 15B. The example in which the portion of the polysilicon film 6 to be 9 is covered with the mask (M1, M2) has been described. However, in any one of the impurity ion implantations, the portion of the polysilicon film 6 to be the contact region 9 of the gate wiring 10 is masked. You may make it cover with (M1, M2).

  In consideration of misalignment of the photomask in the process of forming the connection hole 18b, it is desirable that the contact region 9 of the gate wiring 10 be larger than the plane area of the connection hole 18b.

  Incidentally, as shown in FIGS. 15A and 15B, the polysilicon film 6 is divided into an n-type region and a p-type region by n-type and p-type impurity ion implantation (A). . At the boundary between the n-type region and the p-type region (dotted line portion in FIG. 15C), both the n-type region and the p-type region are present due to mutual diffusion. Become.

  In the first embodiment, the gate wiring 10 is formed so as to avoid the contact region 9 from the boundary between the n-type region and the p-type region of the polysilicon film 6. Therefore, as in the first embodiment, it is possible to form the polysilicon in the contact region 9 only by forming the gate wiring 10 so that the contact region 9 is not located at the boundary between the n-type region and the p-type region of the polysilicon film 6. The impurity concentration in the silicon film can be lowered.

(Embodiment 2)
In the second embodiment, of the three ion implantations ((A), (B), (C)) performed in the manufacture of the MISFET, impurities for forming a pair of extension regions that are a source region and a drain region An example in which ion implantation (B) is controlled to suppress generation of abnormal oxide in the contact region of the gate wiring will be described.

16 to 22 are diagrams related to the semiconductor device according to the second embodiment of the present invention.
16 to 21 are schematic cross-sectional views showing the manufacturing process of the semiconductor device,
FIG. 22 is a schematic plan view showing a mask pattern in the manufacturing process of the semiconductor device.

16 to 21,
(A) is sectional drawing in the position in alignment with the aa line of FIG.
(B) is a cross-sectional view at a position along the line bb in FIG.
(C) is sectional drawing in the position in alignment with the cc line of FIG.

In FIG.
(A) is a top view which shows the mask pattern (M1) of FIG.
(B) is a plan view showing the mask pattern (M2) of FIG.
(C) is a plan view showing the mask pattern (M3) of FIG.
(D) is a plan view showing the mask pattern (M4) of FIG.
(E) is a plan view showing the mask pattern (M5) of FIG. 20,
(F) is a top view which shows the mask pattern (M6) of FIG.

  First, after the polysilicon film 6 is formed by performing the same process as in the first embodiment, impurities for reducing the resistance value are ion-implanted into the polysilicon film 6 (impurity ion implantation (A)). In this impurity ion implantation, as in the first embodiment, n-type impurity ion implantation and p-type impurity ion implantation are performed separately.

  The n-type impurity ion implantation is shown in FIGS. 16 (a), (b), (c) and FIG. 22 (a) in the portion of the polysilicon film 6 (gate wiring formation region) to be the gate wiring 10. As described above, the etching is performed in a state where the portion on the element formation region 1p (the portion serving as the gate electrode of the p-type MISFET) and the portion serving as the contact region 9 of the gate wiring 10 are selectively covered with the mask M1. The impurity type and introduction condition, and the pattern of the mask M1 are the same as those in the first embodiment (see FIG. 15A).

  The p-type impurity ion implantation is shown in FIG. 17 ((a), (b), (c)) and FIG. 22 (b) in the portion of the polysilicon film 6 (gate wiring formation region) that becomes the gate wiring 10. As described above, the process is performed in a state where the part on the element formation region 1n (the part that becomes the gate electrode of the n-type MISFET) is selectively covered with the mask M2. The impurity type and introduction conditions are the same as those in the first embodiment, but the pattern of the mask M2 is different from that in the first embodiment (see FIG. 15B).

  In this step, the portion of the polysilicon film that becomes the contact region 9 of the gate wiring 10 is not covered with the mask M2 unlike the first embodiment, and therefore, in this second embodiment, impurities are also ionized in this portion. Injected.

  Next, after removing the mask M2, the polysilicon film 6 is patterned to form the gate wiring 10, and then a heat treatment for activating impurities in the polysilicon film of the gate wiring 10 is performed. 18 ((a), (b), (c)) and FIG. 22 (c), the element formation region 1p on the main surface of the silicon substrate 1 and the contact region 9 of the gate wiring 10 are masked with a mask M3. Then, impurities are ion-implanted into the element formation region 1n on the main surface of the silicon substrate 1 to form a pair of n-type semiconductor regions (extension regions) 11 aligned with the gate electrode 7 (impurities). Ion implantation (B)). The type of impurities and the introduction conditions are the same as those in the first embodiment, but the pattern of the mask M3 is different from that in the first embodiment (see FIG. 15C).

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M3 unlike the first embodiment, in this second embodiment, impurity ions are implanted into the contact region 9 of the gate wiring 10. Is not done.

  Next, after removing the mask M3, as shown in FIG. 19 ((a), (b), (c)) and FIG. 22 (d), an element formation region 1n on the main surface of the silicon substrate 1, and In a state where the contact region 9 of the gate wiring 10 is selectively covered with the mask M4, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1, and a pair of p-type semiconductor regions aligned with the gate electrode 7 (Extension region) 12 is formed (impurity ion implantation (B)). The type of impurities and the introduction conditions are the same as in the first embodiment, but the pattern of the mask M4 is different from that in the first embodiment (see FIG. 15D).

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M4 unlike the first embodiment, in this second embodiment, impurity ion implantation is performed in the contact region 9 of the gate wiring 10. Is not done.

  Next, after removing the mask 4, side wall spacers 13 are formed on the side walls of the gate wiring 10 in the same manner as in the first embodiment, and then, FIG. 20 ((a), (b), (c)), As shown in FIG. 22E, impurities are ion-implanted into the element formation region 1n on the main surface of the silicon substrate 1 in a state where the element formation region 1p on the main surface of the silicon substrate 1 is selectively covered with a mask M5. Then, a pair of n-type semiconductor regions (contacts) 14 aligned with the sidewall spacers 13 are formed (impurity ion implantation (C)). The impurity type and introduction conditions, and the pattern of the mask M5 are the same as those in the first embodiment (see FIG. 15E). In FIG. 22 (e), the illustration of the sidewall spacers 13 is omitted for easy understanding of the invention.

  Next, after removing the mask 5, as shown in FIGS. 21 (a), (b), (c)) and FIG. 22 (f), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M6, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (contacts) 15 aligned with the sidewall spacers 13 ( Impurity ion implantation (C)). The impurity type and introduction conditions, and the pattern of the mask 6 are the same as those in the first embodiment (see FIG. 15F). In FIG. 22F, the side wall spacers 13 are not shown for easy understanding of the invention.

  Thereafter, n-type and p-type MISFETs are formed by performing the same process as in the first embodiment, and then the same process as in the first embodiment is performed to obtain the structure shown in FIG.

  In the second embodiment, in an impurity ion implantation step (see FIGS. 18 and 22C) for forming a pair of n-type semiconductor regions (extension regions) 11 that are a source region and a drain region of an n-type MISFET. Impurities are ion-implanted into the element formation region 1n with the contact region 9 of the gate wiring 10 covered with the mask M3, and a pair of p-type semiconductor regions (extension regions) 12 serving as a source region and a drain region of the p-type MISFET-Qp. In the impurity ion implantation step for forming (see FIGS. 19 and 22D), impurities are ion-implanted into the element formation region 1n with the contact region 9 of the gate wiring 10 covered with the mask M4. Therefore, compared with the case where the contact region 9 of the gate wiring 10 is not covered with the mask (M3, M4), the gate It is possible to lower the impurity concentration in the polysilicon film in the contact area 9 line 10. That is, the routing portion 8 which is a part of the gate wiring 10 is formed such that the impurity concentration of the polysilicon film in the contact region 9 in which the connection hole 18b is formed is different from the impurity concentration in other regions. The impurity concentration of the polysilicon film in the region 9 is lower than the impurity concentration in other regions.

  Further, in impurity ion implantation for forming a pair of n-type semiconductor regions (extension regions) 11 which are a source region and a drain region of the n-type MISFET, the element formation region 1p and the contact region 9 of the gate wiring 10 are masked in the same mask. In the impurity ion implantation for forming a pair of p-type semiconductor regions (extension regions) 12 which are covered with M3 and form the source region and the drain region of the p-type MISFET, the element formation region 1n and the contact region 9 of the gate wiring 10 are the same. Therefore, it is not necessary to newly form a mask that covers the contact region 9 of the gate wiring 10.

  Therefore, also in the second embodiment, the generation of abnormal oxides can be suppressed as in the first embodiment, and the manufacturing yield of the semiconductor device can be improved. Furthermore, these effects can be obtained without increasing the manufacturing cost.

  In the second embodiment, the impurity ions are implanted into the polysilicon film in the contact region 9 in the impurity ion implantation (A) in FIG. 22B and the impurity ion implantation (C) in FIGS. 22E and 22F. Therefore, the impurity concentration in the polysilicon film in the contact region 9 is lowered while suppressing the increase in resistance of the contact region 9.

  In the second embodiment, impurity ion implantation (see FIGS. 18 and 22C) for forming the n-type semiconductor region (extension region) 11 and the p-type semiconductor region (extension region) 12 are formed. In both of the impurity ion implantations (see FIGS. 19 and 22D), the example in which the contact region 9 of the gate wiring 10 is covered with the mask (M3, M4) has been described. The contact region 9 of the gate wiring 10 may be covered with a mask (M3, M4).

(Embodiment 3)
In the third embodiment, of the three ion implantations ((A), (B), (C)) included in the MISFET manufacturing process, impurities for forming a pair of contact regions that are a source region and a drain region An example in which ion implantation (C) is controlled to suppress generation of abnormal oxide in the contact region of the gate wiring will be described.

23 to 29 are diagrams related to the semiconductor device according to the third embodiment of the present invention.
23 to 28 are schematic cross-sectional views showing a manufacturing process of a semiconductor device,
FIG. 29 is a schematic plan view showing a mask pattern in a manufacturing process of a semiconductor device.

In FIGS. 23 to 28,
(A) is sectional drawing in the position in alignment with the aa line of FIG.
(B) is a cross-sectional view at a position along the line bb in FIG.
(C) is sectional drawing in the position in alignment with the cc line of FIG.

In FIG. 29,
(A) is a top view which shows the mask pattern (M1) of FIG.
(B) is a plan view showing the mask pattern (M2) of FIG.
(C) is a plan view showing the mask pattern (M3) of FIG.
(D) is a plan view showing the mask pattern (M4) of FIG.
(E) is a plan view showing the mask pattern (M5) of FIG. 27;
(F) is a top view which shows the mask pattern (M6) of FIG.

  First, after the polysilicon film 6 is formed by performing the same process as in the first embodiment, impurities for reducing the resistance value are ion-implanted into the polysilicon film 6 (impurity ion implantation (A)). In this impurity ion implantation, as in the first embodiment, n-type impurity ion implantation and p-type impurity ion implantation are performed separately.

  The n-type impurity ion implantation is shown in FIGS. 23 (a), (b), (c), and FIG. As described above, the etching is performed in a state where the portion on the element formation region 1p (the portion serving as the gate electrode of the p-type MISFET) and the portion serving as the contact region 9 of the gate wiring 10 are selectively covered with the mask M1. The impurity type and introduction condition, and the pattern of the mask M1 are the same as those in the first embodiment (see FIG. 15A).

  The p-type impurity ion implantation is shown in FIG. 24 ((a), (b), (c)) and FIG. 29 (b) in the portion (gate wiring formation region) of the polysilicon film 6 to be the gate wiring 10. As described above, the process is performed in a state where the part on the element formation region 1n (the part that becomes the gate electrode of the n-type MISFET) is selectively covered with the mask M2. The impurity type and introduction conditions are the same as those in the first embodiment, but the pattern of the mask M2 is different from that in the first embodiment (see FIG. 15B).

  In this step, since the polysilicon film portion that becomes the contact region 9 of the gate wiring 10 is not covered with the mask M2 unlike the first embodiment, impurities are also ionized in this portion in the third embodiment. Injected.

  Next, after removing the mask M2, the polysilicon film 6 is patterned to form the gate wiring 10, and then a heat treatment for activating impurities in the polysilicon film of the gate wiring 10 is performed. As shown in FIGS. 25 (a), (b), (c)) and FIG. 29 (c), the element formation region 1p on the main surface of the silicon substrate 1 is selectively covered with a mask M3. Impurities are ion-implanted into the element formation region 1n on the main surface of the silicon substrate 1 to form a pair of n-type semiconductor regions (extension regions) 11 aligned with the gate electrode 7 (impurity ion implantation (B)). The impurity type and introduction conditions, and the pattern of the mask M3 are the same as those in the first embodiment (see FIG. 15C).

  Next, after removing the mask M3, as shown in FIGS. 26 (a), (b), (c)) and FIG. 29 (d), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M4, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (extension regions) 12 aligned with the gate electrode 7 ( Impurity ion implantation (B)). The impurity type and introduction condition, and the pattern of the mask M4 are the same as those in the first embodiment (see FIG. 15D).

  Next, after removing the mask 4, side wall spacers 13 are formed on the side walls of the gate wiring 10 in the same manner as in the first embodiment, and then, FIG. 27 ((a), (b), (c)), 29E, the element formation region 1p on the main surface of the silicon substrate 1 and the contact region 9 of the gate wiring 10 are selectively covered with a mask M5, and the main surface of the silicon substrate 1 is covered. Impurities are ion-implanted into the element formation region 1n to form a pair of n-type semiconductor regions (contacts) 14 aligned with the sidewall spacers 13 (impurity ion implantation (C)). The types of impurities and the introduction conditions are the same as those in the first embodiment, but the pattern of the mask M5 is different from that in the first embodiment (see FIG. 15E). In FIG. 29 (e), the side wall spacers 13 are not shown for easy understanding of the invention.

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M5 unlike the first embodiment, in this third embodiment, impurity ions are implanted into the contact region 9 of the gate wiring 10. Is not done.

  Next, after removing the mask 5, as shown in FIGS. 28 (a), (b), (c)) and FIG. 29 (f), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M6, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (contacts) 15 aligned with the sidewall spacers 13 ( Impurity ion implantation (C)). The impurity type and introduction conditions are the same as those in the first embodiment, but the pattern of the mask M6 is different from that in the first embodiment (see FIG. 15F). In FIG. 29 (f), the illustration of the sidewall spacers 13 is omitted for easy understanding of the invention.

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M6 unlike the first embodiment, in this third embodiment, impurity ions are implanted into the contact region 9 of the gate wiring 10. Is not done.

  Thereafter, n-type and p-type MISFETs are formed by performing the same process as in the first embodiment, and then the same process as in the first embodiment is performed to obtain the structure shown in FIG.

  In the third embodiment, in impurity ion implantation (see FIGS. 27 and 29E) for forming a pair of n-type semiconductor regions (contact regions) 14 which are a source region and a drain region of an n-type MISFET, Impurities are ion-implanted into the element formation region 1n with the contact region 9 of the wiring 10 covered with the mask M5, and a pair of p-type semiconductor regions (contact regions) 15 which are a source region and a drain region of the p-type MISFET-Qp are formed. In the impurity ion implantation step for forming (see FIGS. 28 and 29F), impurities are ion-implanted into the element formation region 1p with the contact region 9 of the gate wiring 10 covered with the mask M6. Compared with the case where the contact region 9 of the gate wiring 10 is not covered with a mask (M5, M6), the contour of the gate wiring 10 It is possible to lower the impurity concentration in the polysilicon film in the preparative region 9. That is, the routing portion 8 which is a part of the gate wiring 10 is formed such that the impurity concentration of the polysilicon film in the contact region 9 in which the connection hole 18b is formed is different from the impurity concentration in other regions. The impurity concentration of the polysilicon film in the region 9 is lower than the impurity concentration in other regions.

  In the impurity ion implantation for forming a pair of n-type semiconductor regions (contact regions) 14 which are the source region and the drain region of the n-type MISFET, the element formation region 1p and the contact region 9 of the gate wiring 10 are masked in the same mask. In the impurity ion implantation for forming a pair of p-type semiconductor regions (contact regions) 15 which are covered with M5 and are a source region and a drain region of the p-type MISFET, the element formation region 1n and the contact region 9 of the gate wiring 10 are the same. Therefore, it is not necessary to newly form a mask that covers the contact region 9 of the gate wiring 10.

  Therefore, in the third embodiment, as in the first embodiment, the generation of abnormal oxides can be suppressed, and the manufacturing yield of semiconductor devices can be improved. Furthermore, these effects can be obtained without increasing the manufacturing cost.

  In the third embodiment, impurities are implanted into the polysilicon film in the contact region 9 in the impurity ion implantation (A) in FIG. 29B and the impurity ion implantation (B) in FIGS. 29C and 29D. Therefore, the impurity concentration in the polysilicon film in the contact region 9 is lowered while suppressing the increase in resistance of the contact region 9.

  In the third embodiment, impurity ion implantation (see FIGS. 27 and 29C) for forming the n-type semiconductor region (contact region) 14 and the p-type semiconductor region (contact region) 15 are formed. In both of the impurity ion implantations (see FIGS. 28 and 29D), the example in which the contact region 9 of the gate wiring 10 is covered with the masks (M5, M6) has been described. The contact region 9 of the gate wiring 10 may be covered with a mask (M5, M6).

  In the first to third embodiments, the impurity ion implantation (A) for reducing the resistance value of the polysilicon film and the impurity ion implantation for forming a pair of semiconductor regions (extension regions) aligned with the gate electrode. (B) In any one of the impurity ion implantations (C) for forming a pair of semiconductor regions (contact regions) aligned with the side wall spacers on the side walls of the gate electrode, Impurities are not ion-implanted into the contact region 9, but in any two of these impurity ion implantations ((A), (B), (C)), the contact region 9 of the gate wiring 10 is formed in the contact region 9. Impurities may not be ion-implanted.

  In the first to third embodiments, the present invention is applied to a semiconductor device having a complementary MISFET. However, the present invention is a semiconductor having one of an n-type MISFET and a p-type MISFET. It can also be applied to devices. However, in this case, it is necessary to newly add a mask for covering the contact region of the gate wiring.

  In the first to third embodiments, the gate wiring 10 having two gate electrodes has been described. However, the present invention can also be applied to a gate wiring having one gate electrode, and a DRAM (Dynamic Random Access Memory). Or a gate wiring having a plurality of gate electrodes, such as a word line of a flash memory or the like.

(Embodiment 4)
In the fourth embodiment, among the n-type and p-type MISFETs, three impurity ion implantations ((A), (B), (C)) for forming the n-type MISFET are controlled to control the gate. An example of suppressing the generation of abnormal oxide in the contact region of the wiring will be described.

30 to 36 are diagrams related to the semiconductor device according to the fourth embodiment of the present invention.
30 to 35 are schematic cross-sectional views showing the manufacturing steps of the semiconductor device,
FIG. 36 is a schematic plan view showing a mask pattern in the manufacturing process of the semiconductor device.

30 to 35,
(A) is sectional drawing in the position in alignment with the aa line of FIG.
(B) is a cross-sectional view at a position along the line bb in FIG.
(C) is sectional drawing in the position in alignment with the cc line of FIG.

In FIG. 36,
(A) is a top view which shows the mask pattern (M1) of FIG.
(B) is a plan view showing the mask pattern (M2) of FIG. 31;
(C) is a plan view showing the mask pattern (M3) of FIG. 32;
(D) is a plan view showing the mask pattern (M4) of FIG.
(E) is a plan view showing the mask pattern (M5) of FIG. 34;
FIG. 36F is a plan view showing the mask pattern (M6) in FIG.

  First, after the polysilicon film 6 is formed by performing the same process as in the first embodiment, impurities for reducing the resistance value are ion-implanted into the polysilicon film 6 (impurity ion implantation (A)). In this impurity ion implantation, as in the first embodiment, n-type impurity ion implantation and p-type impurity ion implantation are performed separately.

  The n-type impurity ion implantation is shown in FIG. 30 ((a), (b), (c)) and FIG. As described above, the etching is performed in a state where the portion on the element formation region 1p (the portion serving as the gate electrode of the p-type MISFET) and the portion serving as the contact region 9 of the gate wiring 10 are selectively covered with the mask M1. The impurity type and introduction condition, and the pattern of the mask M1 are the same as those in the first embodiment (see FIG. 15A).

  The p-type impurity ion implantation is shown in FIG. 31 ((a), (b), (c)) and FIG. 36 (b) in the portion of the polysilicon film 6 (gate wiring formation region) that becomes the gate wiring 10. As described above, the process is performed in a state where the part on the element formation region 1n (the part that becomes the gate electrode of the n-type MISFET) is selectively covered with the mask M2. The impurity type and introduction conditions are the same as those in the first embodiment, but the pattern of the mask M2 is different from that in the first embodiment (see FIG. 15B).

  In this step, the portion of the polysilicon film that becomes the contact region 9 of the gate wiring 10 is not covered with the mask M2 unlike the first embodiment, and therefore, in this second embodiment, impurities are also ionized in this portion. Injected.

  Next, after removing the mask M2, the polysilicon film 6 is patterned to form the gate wiring 10, and then a heat treatment for activating impurities in the polysilicon film of the gate wiring 10 is performed. 32 ((a), (b), (c)) and FIG. 36 (c), the element formation region 1p on the main surface of the silicon substrate 1 and the contact region 9 of the gate wiring 10 are masked with a mask M3. Then, impurities are ion-implanted into the element formation region 1n on the main surface of the silicon substrate 1 to form a pair of n-type semiconductor regions (extension regions) 11 aligned with the gate electrode 7 (impurities). Ion implantation (B)). The type of impurities and the introduction conditions are the same as those in the first embodiment, but the pattern of the mask M3 is different from that in the first embodiment (see FIG. 15C).

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M3 unlike the first embodiment, impurity ion implantation is performed on the contact region 9 of the gate wiring 10 in the fourth embodiment. Is not done.

  Next, after removing the mask M3, as shown in FIGS. 33 (a), (b), (c)) and FIG. 36 (d), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M4, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (extension regions) 12 aligned with the gate electrode 7 ( Impurity ion implantation (B)). The impurity type and introduction condition, and the pattern of the mask M4 are the same as those in the first embodiment (see FIG. 15D).

  Next, after removing the mask 4, side wall spacers 13 are formed on the side walls of the gate wiring 10 in the same manner as in the first embodiment, and thereafter, FIG. 34 ((a), (b), (c)), 36E, the element formation region 1p on the main surface of the silicon substrate 1 and the contact region 9 of the gate wiring 10 are selectively covered with a mask M5, and the main surface of the silicon substrate 1 is covered. Impurities are ion-implanted into the element formation region 1n to form a pair of n-type semiconductor regions (contacts) 14 aligned with the sidewall spacers 13 (impurity ion implantation (C)). The type of impurities and the introduction conditions are the same as those in the first embodiment, but the pattern of the mask M5 is different from that in the first embodiment (see FIG. 15E). In FIG. 36 (e), the side wall spacers 13 are not shown in order to facilitate understanding of the invention.

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M5 unlike the first embodiment, in the fourth embodiment, impurity ion implantation is performed in the contact region 9 of the gate wiring 10. Is not done.

  Next, after removing the mask 5, as shown in FIGS. 35 (a), (b), (c)) and FIG. 36 (f), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M6, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (contact regions) 15 aligned with the sidewall spacers 13. (Impurity ion implantation (C)). The impurity type and introduction conditions, and the pattern of the mask 6 are the same as those in the first embodiment (see FIG. 15F). In FIG. 36 (f), the illustration of the sidewall spacers 13 is omitted for easy understanding of the invention.

  Thereafter, n-type and p-type MISFETs are formed by performing the same process as in the first embodiment, and then the same process as in the first embodiment is performed to obtain the structure shown in FIG.

  In the fourth embodiment, three impurity ion implantations ((A), (B), (C)) for forming an n-type MISFET, specifically, the gate electrode 7 of the n-type MISFET-Qn is replaced with an n-type. In the impurity ion implantation for forming the impurity (see FIG. 36A), impurities are ion-implanted into the polysilicon film 6 with the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 covered with the mask 1. Impurity ion implantation (see FIG. 36C) for forming a pair of n-type semiconductor regions (extension regions) 11 which are a source region and a drain region of the n-type MISFET-Qn, and a source of the n-type MISFET-Qn In impurity ion implantation (see FIG. 36E) for forming a pair of n-type semiconductor regions 14 which are regions and drain regions, contact of the gate wiring 10 Since the impurity is ion-implanted into the element formation region 1n in a state where the region 9 is covered with the mask (M3, M5), the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 and the gate wiring 10 Compared with the case where the contact region 9 is not covered with the mask (M1, M3, M5), the impurity concentration in the polysilicon film in the contact region 9 of the gate wiring 10 can be lowered. That is, in the third embodiment, the contact region 9 in which the connection hole 18b is formed in the routing portion 8 that is a part of the gate wiring 10 has a structure having only n-type impurities. In the present embodiment, an example of the n-type MISFET-Qn is shown. However, in the case of the p-type MISFET-Qp, the contact region 9 in which the connection hole 18b is formed has a structure having only an n-type impurity. Similar effects can be obtained.

  That is, the routing portion 8 which is a part of the gate wiring 10 is formed such that the impurity concentration of the polysilicon film in the contact region 9 in which the connection hole 18b is formed is different from the impurity concentration in other regions. The impurity concentration of the polysilicon film in the region 9 is lower than the impurity concentration in other regions.

  Further, in impurity ion implantation for making the gate electrode 7 of the n-type MISFET-Qn n-type, a portion of the polysilicon film 6 that becomes the gate electrode 7 of the p-type MISFET (polysilicon film 6 on the element formation region 1p) In order to form a pair of n-type semiconductor regions (extension regions) 11 which are the source region and the drain region of the n-type MISFET, covering the portion of the polysilicon film 6 which becomes the contact region 9 of the gate wiring 10 with the same mask M1. In the impurity ion implantation, the element formation region 1p and the contact region 9 of the gate wiring 10 are covered with the same mask M3 to form a pair of n-type semiconductor regions (contact regions) 14 which are a source region and a drain region of the n-type MISFET. In the impurity ion implantation, the element formation region 1p and the gate wiring 10 are connected. Since the gate region 9 is covered with the same mask M5, it is necessary to newly form a mask that covers the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 and a mask that covers the contact region 9 of the gate wiring 10. There is no.

  Therefore, also in the fourth embodiment, as in the first embodiment, the generation of abnormal oxides can be suppressed, and the manufacturing yield of semiconductor devices can be improved. Furthermore, these effects can be obtained without increasing the manufacturing cost.

  In the fourth embodiment, in the impurity ion implantation (A) in FIG. 36B, the impurity ion implantation (B) in FIG. 36D, and the impurity ion implantation (C) in FIG. Since the impurities are ion-implanted into the polysilicon film, the impurity concentration in the polysilicon film in the contact region 9 is lowered while suppressing the increase in resistance of the contact region 9.

  In the fourth embodiment, an example of controlling three impurity ion implantations ((A), (B), (C)) for forming an n-type MISFET-Qn (FIGS. 36A and 36C). (See (e)), the same effect can be obtained even when three impurity ion implantations for forming the p-type MISFET-Qp are controlled.

(Embodiment 5)
In the fifth embodiment, among the three ion implantations ((A), (B), (C)) included in the MISFET manufacturing process, the source region and the drain are impurities implanted into the contact region of the gate wiring. Impurity ion implantation (B) for forming a pair of extension regions which are regions, and impurity ion implantation (C) for forming a pair of contact regions which are a source region and a drain region are controlled, and gate wiring An example of suppressing the formation of abnormal oxide in the contact region will be described.

37 to 43 are diagrams related to the semiconductor device according to the fifth embodiment of the present invention.
37 to 42 are schematic cross-sectional views showing the manufacturing steps of the semiconductor device,
FIG. 43 is a schematic plan view showing a mask pattern in the manufacturing process of the semiconductor device.

In FIGS. 37 to 42,
(A) is sectional drawing in the position in alignment with the aa line of FIG.
(B) is a cross-sectional view at a position along the line bb in FIG.
(C) is sectional drawing in the position in alignment with the cc line of FIG.

In FIG.
(A) is a top view which shows the mask pattern (M1) of FIG.
(B) is a plan view showing the mask pattern (M2) of FIG. 38;
(C) is a plan view showing the mask pattern (M3) of FIG. 39;
(D) is a plan view showing the mask pattern (M4) of FIG.
(E) is a plan view showing the mask pattern (M5) of FIG. 41;
(F) is a top view which shows the mask pattern (M6) of FIG.

  First, after the polysilicon film 6 is formed by performing the same process as in the first embodiment, impurities for reducing the resistance value are ion-implanted into the polysilicon film 6 (impurity ion implantation (A)). In this impurity ion implantation, as in the first embodiment, n-type impurity ion implantation and p-type impurity ion implantation are performed separately.

  The n-type impurity ion implantation is shown in FIGS. 37 (a), (b), (c) and FIG. 43 (a) in the portion of the polysilicon film 6 (gate wiring formation region) to be the gate wiring 10. As described above, the etching is performed in a state where the portion on the element formation region 1p (the portion serving as the gate electrode of the p-type MISFET) and the portion serving as the contact region 9 of the gate wiring 10 are selectively covered with the mask M1. The impurity type and introduction condition, and the pattern of the mask M1 are the same as those in the first embodiment (see FIG. 15A).

  The p-type impurity ion implantation is shown in FIGS. 38 ((a), (b), (c)) and FIG. 43 (b) in the portion of the polysilicon film 6 (gate wiring formation region) to be the gate wiring 10. As described above, the process is performed in a state where the part on the element formation region 1n (the part that becomes the gate electrode of the n-type MISFET) is selectively covered with the mask M2. The impurity type and introduction conditions are the same as those in the first embodiment, but the pattern of the mask M2 is different from that in the first embodiment (see FIG. 15B).

  In this step, the portion of the polysilicon film that becomes the contact region 9 of the gate wiring 10 is not covered with the mask M2 unlike the first embodiment, and in this fifth embodiment, impurities are also ionized in this portion. Injected.

  Next, after removing the mask M2, the polysilicon film 6 is patterned to form the gate wiring 10, and then a heat treatment for activating impurities in the polysilicon film of the gate wiring 10 is performed. 39 ((a), (b), (c)) and FIG. 43 (c), the element formation region 1p on the main surface of the silicon substrate 1 and the contact region 9 of the gate wiring 10 are masked with a mask M3. Then, impurities are ion-implanted into the element formation region 1n on the main surface of the silicon substrate 1 to form a pair of n-type semiconductor regions (extension regions) 11 aligned with the gate electrode 7 (impurities). Ion implantation (B)). The type of impurities and the introduction conditions are the same as those in the first embodiment, but the pattern of the mask M3 is different from that in the first embodiment (see FIG. 15C).

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M3 unlike the first embodiment, impurity ion implantation is performed on the contact region 9 of the gate wiring 10 in the fifth embodiment. Is not done.

  Next, after removing the mask M3, as shown in FIGS. 40 (a), (b), (c)) and FIG. 36 (d), the element formation region 1n on the main surface of the silicon substrate 1 is masked. While selectively covered with M4, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1 to form a pair of p-type semiconductor regions (extension regions) 12 aligned with the gate electrode 7 ( Impurity ion implantation (B)). The type of impurities and the introduction conditions are the same as in the first embodiment, but the pattern of the mask M4 is different from that in the first embodiment (see FIG. 15D).

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M4 unlike the first embodiment, in the fifth embodiment, impurity ion implantation is performed in the contact region 9 of the gate wiring 10. Is not done.

  Next, after removing the mask 4, side wall spacers 13 are formed on the side walls of the gate wiring 10 in the same manner as in the first embodiment, and then, FIG. 41 ((a), (b), (c)), 43E, the element formation region 1p on the main surface of the silicon substrate 1 and the contact region 9 of the gate wiring 10 are selectively covered with a mask M5, and the main surface of the silicon substrate 1 is covered. Impurities are ion-implanted into the element formation region 1n to form a pair of n-type semiconductor regions (contacts) 14 aligned with the sidewall spacers 13 (impurity ion implantation (C)). The type of impurities and the introduction conditions are the same as those in the first embodiment, but the pattern of the mask M5 is different from that in the first embodiment (see FIG. 15E). In FIG. 41 (e), the side wall spacers 13 are not shown for easy understanding of the invention.

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask M5 unlike the first embodiment, in this fifth embodiment, impurity ion implantation is performed in the contact region 9 of the gate wiring 10. Is not done.

  Next, after removing the mask 5, as shown in FIGS. 42 (a), (b), (c)) and FIG. 43 (f), an element formation region 1n on the main surface of the silicon substrate 1, and In a state where the contact region 9 of the gate wiring 10 is selectively covered with a mask M6, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1, and a pair of p-type semiconductors aligned with the side wall spacers 13 are aligned. Region (contact region) 15 is formed (impurity ion implantation (C)). The types of impurities and the introduction conditions are the same as those in the first embodiment, but the pattern of the mask 6 is different from that in the first embodiment (see FIG. 15F). In FIG. 41 (f), the side wall spacers 13 are not shown for easy understanding of the invention.

  In this step, since the contact region 9 of the gate wiring 10 is covered with the mask 6 unlike the first embodiment, in the fifth embodiment, impurity ion implantation is performed in the contact region 9 of the gate wiring 10. Is not done.

Thereafter, n-type and p-type MISFETs are formed by performing the same process as in the first embodiment, and then the same process as in the first embodiment is performed to obtain the structure shown in FIG.
In the fifth embodiment, since the contact region 9 is covered with the masks M3 to M6 in the impurity ion implantation (B) and (C), the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 and the gate Compared with the case where the contact region 9 of the wiring 10 is not covered with a mask (M1, M3, M4, M5, M6), the impurity concentration in the polysilicon film in the contact region 9 of the gate wiring 10 can be lowered.

  That is, the routing portion 8 which is a part of the gate wiring 10 is formed such that the impurity concentration of the polysilicon film in the contact region 9 in which the connection hole 18b is formed is different from the impurity concentration in other regions. The impurity concentration of the polysilicon film in the region 9 is lower than the impurity concentration in other regions.

Further, in impurity ion implantation for making the gate electrode 7 of the n-type MISFET-Qn n-type, a portion of the polysilicon film 6 that becomes the gate electrode 7 of the p-type MISFET (polysilicon film 6 on the element formation region 1p) And the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 is covered with the same mask M1,
In impurity ion implantation for forming a pair of n-type semiconductor regions (extension regions) 11 which are a source region and a drain region of an n-type MISFET, the element formation region 1p and the contact region 9 of the gate wiring 10 are formed with the same mask M3. Covering,
In impurity ion implantation for forming a pair of p-type semiconductor regions (extension regions) 12 which are a source region and a drain region of a p-type MISFET, the element formation region 1n and the contact region 9 of the gate wiring 10 are covered with the same mask M4. Covering,
In impurity ion implantation for forming a pair of n-type semiconductor regions (contact regions) 14 which are a source region and a drain region of an n-type MISFET, the element formation region 1p and the contact region 9 of the gate wiring 10 are formed with the same mask M5. Covering,
In impurity ion implantation for forming a pair of p-type semiconductor regions (contact regions) 15 which are a source region and a drain region of a p-type MISFET, the element formation region 1n and the contact region 9 of the gate wiring 10 are formed with the same mask M6. Therefore, it is not necessary to newly form a mask that covers the portion of the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 and a mask that covers the contact region 9 of the gate wiring 10.

  Accordingly, also in the fifth embodiment, as in the first embodiment, the generation of abnormal oxides can be suppressed, and the manufacturing yield of the semiconductor device can be improved. Furthermore, these effects can be obtained without increasing the manufacturing cost.

  In the fifth embodiment, in the impurity ion implantation (A) in FIG. 43B, impurities are ion-implanted into the portion of the polysilicon film 6 that becomes the contact region 9, so that the increase in resistance of the contact region 9 is suppressed. However, the impurity concentration in the polysilicon film in the contact region 9 is lowered.

  In the fifth embodiment, the example (see FIG. 43) in which only the impurity for converting the gate electrode of the p-type MISFET into the p-type is described as the impurity introduced into the contact region 9 of the gate wiring 10 has been described. The same effect can be obtained even when the gate electrode 7 of the n-type MISFET-Qn is made only of impurities for making it n-type.

(Embodiment 6)
In the sixth embodiment, in the two-level complementary MISFET having different gate breakdown voltages, the second-level complementary MISFET is formed in the contact region of the gate wiring including the gate electrode of the first-level complementary MISFET. Impurity ion implantation for forming the first level complementary MISFET is not performed in the contact region of the gate wiring including the gate electrode of the second level complementary MISFET. An example of suppressing the generation of abnormal oxide in the contact region of each gate wiring will be described.
An example in which the present invention is applied to a semiconductor device having the above will be described.

44 to 62 are diagrams related to the semiconductor device according to the sixth embodiment of the present invention.
FIG. 44 is a schematic plan view showing a schematic configuration of a semiconductor device;
FIG. 45 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device;
46 to 55 are schematic cross-sectional views showing a manufacturing process of a semiconductor device,
FIG. 56 is a schematic plan view showing the mask pattern (M1) of FIG.
FIG. 57 is a schematic plan view showing the mask pattern (M2) of FIG.
58 is a schematic plan view showing the mask pattern (M3) of FIG.
59 is a schematic plan view showing the mask pattern (M4) of FIG.
FIG. 60 is a schematic plan view showing the mask pattern (M5) of FIG.
61 is a schematic plan view showing the mask pattern (M6) of FIG.
62 is a schematic plan view showing the mask pattern (M7) of FIG.
FIG. 63 is a schematic plan view showing the mask pattern (M8) of FIG.

In FIG. 45,
(A) is sectional drawing which follows the aa line of FIG.
(B) is a sectional view taken along line bb in FIG.
(C) is a sectional view taken along line cc of FIG.
(D) is sectional drawing which follows the aa line | wire of FIG.
(E) is sectional drawing which follows the bb line of FIG.
(F) is sectional drawing which follows the cc line of FIG.

46 to 55,
(A) is sectional drawing in the position in alignment with the aa line of FIG.
(B) is a sectional view at a position along the line bb in FIG.
(C) is a cross-sectional view at a position along the line cc of FIG.
(D) is sectional drawing in the position in alignment with the dd line | wire of FIG.
(E) is a cross-sectional view at a position along the line ee in FIG.
(F) is sectional drawing in the position which follows the ff line | wire of FIG.

  As shown in FIGS. 44 and 45 ((a) to (f)), in the semiconductor device of the sixth embodiment, a p-type substrate 1 (hereinafter referred to as a silicon substrate) made of, for example, single crystal silicon is used as a semiconductor substrate. Consists of the subject.

  The main surface (element formation surface, circuit formation surface) of the silicon substrate 1 has element formation regions (active regions) 1n, 1p, 1n1 and 1p1 partitioned by an element isolation region (inactive region) 2. In the region 1n, a p-type well region 4 and an n-type MISFET-Qn (see FIG. 45A) are formed. In the element formation region 1p, an n-type well region 3 and a p-type MISFET-Qp (see FIG. b)) is formed. In the element formation region 1n1, a p-type well region 4 and an n-type MISFET-Qn1 (see FIG. 45D) are formed. In the element formation region 1p1, the n-type well region 3 is formed. And p-type MISFET-Qp1 (refer FIG.45 (e)) is formed.

  The n-type and p-type MISFETs (Qn, Qp) and the n-type and p-type MISFETs (Qn1, Qp2) have different gate breakdown voltages. The n-type and p-type MISFETs (Qn, Qp) are low breakdown voltage MISFETs driven by a power supply voltage of, for example, 1.8 [V] or 3.3 [V]. The n-type and p-type MISFETs (Qn1, Qp1) Is a high voltage MISFET driven by a power supply voltage of 10 to 12 [V]. Note that the n-type and p-type MISFETs (Qn, Qp) and the gate wiring 10 are the same as those in the first embodiment, and a part of the description in the sixth embodiment is omitted.

  The n-type and p-type MISFETs (Qn1, Qp1) mainly have a channel formation region, a gate insulating film 25, a gate electrode 27, a source region, and a drain region. The gate insulating film 25 is provided in the element forming region (1n1, 1p1) on the main surface of the silicon substrate 1, and the gate electrode 27 is interposed on the element forming region on the main surface of the silicon substrate 1 with the gate insulating film 25 interposed therebetween. The channel formation region is provided in the surface layer portion of the silicon substrate 1 immediately below the gate electrode 27. The source region and the drain region are provided in the surface layer portion of the silicon substrate 1 so as to sandwich the channel formation region in the channel length (gate length) direction of the channel formation region. The gate insulating film 25 of the n-type and p-type MISFET (Qn1, Qp1) is thicker than the gate insulating film 5 of the n-type and p-type MISFET (Qn, Qp).

  As shown in FIG. 45D, the source region and the drain region of the n-type MISFET-Qn1 have a pair of n-type semiconductor regions 31 that are extension regions and a pair of n-type semiconductor regions 34 that are contact regions. It has become. The n-type semiconductor region 31 is provided in the element formation region 1 n 1 on the main surface of the silicon substrate 1 in alignment with the gate electrode 27. The n-type semiconductor region 34 is provided in the element formation region 1 n 1 on the main surface of the silicon substrate 1 in alignment with the side wall spacer 13 provided on the side wall of the gate electrode 27.

  As shown in FIG. 45E, the source region and the drain region of the p-type MISFET-Qp1 have a pair of p-type semiconductor regions 32 that are extension regions and a pair of p-type semiconductor regions 35 that are contact regions. It has become. The p-type semiconductor region 32 is provided in the element formation region 1 p 1 on the main surface of the silicon substrate 1 in alignment with the gate electrode 27. The p-type semiconductor region 35 is provided in the element formation region 1 p 1 on the main surface of the silicon substrate 1 in alignment with the side wall spacer 13 provided on the side wall of the gate electrode 27.

  The n-type semiconductor region 34 that is a contact region has a higher impurity concentration than the n-type semiconductor region 31 that is an extension region. The p-type semiconductor region 35 that is a contact region has a higher impurity concentration than the p-type semiconductor region 32 that is an extension region. That is, the n-type and p-type MISFETs (Qn1, Qp2) of Embodiment 6 have an LDD structure.

  As shown in FIG. 44, on the main surface of the silicon substrate 1, a gate wiring 30 extending over the element formation region (1 n 1, 1 p 1) and the element isolation region 2 is provided. Similarly to the gate wiring 10, the gate wiring 30 includes each gate electrode 27 of the n-type and p-type MISFETs (Qn 1, Qp 1) and a lead portion (wiring portion) 28 that is integrally connected to the gate electrode 27. The lead-out portion 28 is provided with a contact region 29 for electrical connection with the upper layer wiring.

  As shown in FIGS. 45 (d) and 45 (e), the surfaces of the semiconductor regions (34, 35) of the n-type and p-type MISFETs (Qn1, Qp1) are made of metal in order to reduce resistance. For example, a cobalt silicide (CoSi) layer 16b is formed as the semiconductor reaction layer. 45 ((d), (e), (f)), for example, a cobalt silicide (CoSi) layer is formed on the surface of the gate wiring 30 as a metal / semiconductor reaction layer in order to reduce the resistance. 16a is formed. These cobalt silicide layers (16a, 16b) are formed in alignment with the sidewall spacers 13 by, for example, a salicide (Self Aligned Silicide) technique. That is, the n-type and p-type MISFETs (Qn1, Qp1) of Embodiment 6 have a salicide structure.

  The gate wiring 30 has a multilayer structure having a semiconductor film and a metal / semiconductor reaction layer provided on the semiconductor film. For example, a polysilicon film is used as the semiconductor film, and a cobalt silicide layer 16a is used as the metal / semiconductor reaction layer. The cobalt silicide layer 16a is formed over the gate wirings 30 including the respective gate electrodes 27 and routing portions 28 of the n-type and p-type MISFETs (Qn1, Qp1).

  45 ((a) to (f)), the main surface of the silicon substrate 1 is covered with n-type and p-type MISFETs (Qn, Qp, Qn1, Qp1), for example, silicon oxide. An interlayer insulating film 17 made of a film is provided. On the n-type semiconductor region 34 and the p-type semiconductor region 35, as shown in FIG. 45 ((d), (e)), a connection hole 18a that reaches the silicide layer 16b from the surface of the interlayer insulating film 17 is provided. The conductive plug 19 is embedded in the connection hole 18a. The n-type and p-type semiconductor regions (34, 35) are electrically connected to the wiring 20 extending on the interlayer insulating film 17 with the silicide layer 16a and the conductive plug 19 interposed therebetween.

A contact hole 18b reaching the silicide layer 16a from the surface of the interlayer insulating film 17 is provided on the contact region 29 of the gate wiring 30 as shown in FIG. 45 (f). A plug 19 is embedded. The contact region 2 of the gate wiring 30 is electrically connected to the wiring 20 extending on the interlayer insulating film 17 with the conductive plug 19 interposed.
The gate wiring 30 has a portion having a higher impurity concentration than the contact region 9 in the polysilicon film.

Next, the manufacture of the semiconductor device of Embodiment 6 will be described with reference to FIGS.
First, a p-type silicon substrate 1 made of single crystal silicon having a specific resistance of about 10 [Ωcm] is prepared, and then element formation regions (1n, 1p, 1n1, 1p1) are partitioned on the main surface of the silicon substrate 1. An element isolation region 2 is formed (see FIG. 46).

  Next, the p-type well region 4 is selectively formed in the element forming regions 1n and 1n1 on the main surface of the silicon substrate 1, and the n-type well region 3 is selectively formed in the element forming regions 1p and 1p1, and then, as shown in FIG. The gate insulating film 25 made of a silicon oxide film having a thickness of, for example, about 15 to 20 [nm] is formed in the element formation region (1n, 1p, 1n1, 1p1) on the main surface of the silicon substrate 1 by performing a thermal oxidation process. To do.

  Next, the gate insulating film 25 in the element formation regions 1n and 1p is selectively removed, and then a thermal oxidation process is performed, so that the element formation regions ((a) and (b)) are formed as shown in FIGS. 1n, 1p), for example, a gate insulating film 5 made of a silicon oxide film having a thickness of about 2 to 4 [nm] is formed.

  Next, on the main surface of the silicon substrate 1 including the gate insulating films (5, 25) of the element formation regions (1n, 1p, 1n1, 1p1) and the element isolation region 2, gate wirings (10, As a semiconductor film used for forming 30), for example, a polysilicon film 6 having a thickness of about 100 to 300 [nm] is formed by a CVD (Chemical Vapor Deposition) method.

  Next, an impurity for reducing the resistance value is ion-implanted into the polysilicon film 6 (impurity ion implantation (A)). In this impurity ion implantation, as in the first embodiment, n-type impurity ion implantation and p-type impurity ion implantation are performed separately.

  As shown in FIGS. 48 (a) to 48 (f) and FIG. 56, the n-type impurity ion implantation is performed in the portion of the polysilicon film 6 (gate wiring formation region) that becomes the gate wiring (10, 30). The portion on the element formation region (1p, 1p1) (the portion that becomes the gate electrode of the p-type MISFET) and the portion that becomes the contact region (9, 29) of the gate wiring (10, 30) are selectively covered with the mask M1. In the state. Impurity types and introduction conditions are the same as in the first embodiment.

  In this step, of the portion of the polysilicon film 6 that becomes the gate wiring (10, 30), the portion of the silicon film 6 covered with the mask M1, specifically, the gate electrode of the p-type MISFET (Qp, Qp1). (7, 27) part (the part on the element formation regions 1p and 1p1), part of the part that becomes the routing part (8, 28) of the gate wiring (10, 30), and the gate wiring (10, 30) Impurity ion implantation is not performed in the portion to be the contact region (9, 29).

  On the other hand, the portion of the polysilicon film 6 that becomes the gate wiring (10, 30) is not covered with the mask M1, specifically, the gate electrode (7, 27) of the n-type MISFET (Qn, Qn1). Impurity ion implantation is performed in the part to be (the part on the element formation regions 1n and 1n1) and the part to be the routing part (8, 28) of the gate wiring (10, 30).

  As shown in FIGS. 49 (a) to (f) and FIG. 57, the p-type impurity ion implantation is performed in the portion of the polysilicon film 6 (gate wiring formation region) that becomes the gate wiring (10, 30). This is performed in a state where the element formation regions 1n and 1n1 (the portion that becomes the gate electrode of the n-type MISFET) are selectively covered with the mask M2. Impurity types and introduction conditions are the same as in the first embodiment.

  In this process, the silicon film 6 covered with the mask M2 among the silicon film 6 to be the gate wiring (10, 30), specifically, the gate electrode (n-type MISFET (Qn, Qn1)) 7, 27) (parts on the element formation regions 1 n and 1 n 1) and part of the part to be the routing parts (8, 28) of the gate wiring (10, 30) are subjected to impurity ion implantation. I will not.

  On the other hand, the portion of the polysilicon film 6 that becomes the gate wiring (10, 30) is not covered with the mask M2, specifically, the gate electrode (7, 27) of the p-type MISFET (Qp, Qp1). (Parts on the element formation regions 1p and 1p1), part of the part that becomes the routing part (8, 28) of the gate wiring (10, 30), and contact region (9 of the gate wiring (10, 30)) , 29), impurity ion implantation is performed.

  Next, after removing the mask M2, the polysilicon film 6 is patterned to form gate wirings 10 and 30 having a pattern shown in FIG.

  Next, after performing heat treatment for activating the impurities in the polysilicon film of the gate wiring 10, as shown in FIGS. 50 (a) to (f) and FIG. With the mask M3 selectively covering the entire surface of the element formation region (1p, 1n1, 1p1) and the contact region 29 with the mask M3, impurities are introduced into the element formation region 1n on the main surface of the silicon substrate 1. Ion implantation is performed to form a pair of n-type semiconductor regions (extension regions) 11 aligned with the gate electrode 7 (impurity ion implantation (B)). Impurity types and introduction conditions are the same as in the first embodiment.

  In this step, impurities are ion-implanted into the portion of the gate wiring 10 covered with the mask M3, specifically, the gate electrode 7 on the element formation region 1p and a part of the routing portion 8. Absent. On the other hand, impurity ion implantation is performed on a portion of the gate wiring 10 that is not covered with the mask M3, specifically, on the gate electrode 7 on the element formation region 1n, a part of the routing portion 8, and the contact region 9. Is done.

  In this step, since the entire gate wiring 30 is covered with the mask M3, the gate wiring 30 including the contact region 29 is not subjected to impurity ion implantation.

  Next, after removing the mask M3, as shown in FIG. 51 ((a) to (f)) and FIG. 59, the element formation region (1n, 1n1, 1p1) and the contact on the main surface of the silicon substrate 1 are contacted. In a state where the entire gate wiring 30 including the region 29 is selectively covered with the mask M4, impurities are ion-implanted into the element formation region 1p on the main surface of the silicon substrate 1, and a pair of p-types aligned with the gate electrode 7 is obtained. A semiconductor region (extension region) 12 is formed (impurity ion implantation (B)). Impurity types and introduction conditions are the same as in the first embodiment.

  In this step, impurity ions are implanted into the portion of the gate wiring 10 covered with the mask M4, specifically, the gate electrode 7 on the element formation region 1n and a part of the routing portion 8. Absent. On the other hand, in the portion of the gate wiring 10 that is not covered with the mask M4, specifically, the gate electrode 7 on the element formation region 1p, a part of the routing portion 8, and the contact region 9, impurity ions are implanted. Is done.

  In this step, since the entire gate wiring 30 is covered with the mask M4, impurity ion implantation is not performed on the gate wiring 30 including the contact region 29.

  Next, after removing the mask M4, as shown in FIG. 52 ((a) to (f)) and FIG. 60, the element formation regions (1n, 1p, 1p1) on the main surface of the silicon substrate 1 and contacts In a state where the entire gate wiring 10 including the region 9 is selectively covered with the mask M5, an impurity is ion-implanted into the element forming region 1n1 on the main surface of the silicon substrate 1, and a pair of n-type aligned with the gate electrode 27 is obtained. A semiconductor region (extension region) 31 is formed (impurity ion implantation (B)). Impurity ion implantation is not limited to this, but is performed, for example, in three steps.

In the first impurity ion implantation, for example, arsenic (As) is used as an impurity, and the acceleration energy is about 6 KeV and the dose is about 2.0E15 (2 × 10 ¹⁵ [atoms / cm ² ]).

In the second impurity ion implantation, for example, boron (B) is used as an impurity, and the acceleration energy is about 20 KeV, and the dose is about 6.0E12 (1 × 10 ¹² [atoms / cm ² ]).

In the third impurity ion implantation, for example, boron (B) is used as an impurity, and the acceleration energy is about 10 KeV and the dose is about 4.0E13 (1 × 10 ¹³ [atoms / cm ² ]).

  In this step, impurity ions are implanted into the portion of the gate wiring 30 covered with the mask M5, specifically, the gate electrode 27 on the element formation region 1p1 and a part of the routing portion 28. Absent. On the other hand, in the portion of the gate wiring 30 that is not covered with the mask M5, specifically, the gate electrode 27 on the element formation region 1n1, the portion of the routing portion 28, and the contact region 29, impurity ions are implanted. Is done.

  In this step, since the entire gate wiring 10 is covered with the mask M5, the gate wiring 10 including the contact region 9 is not subjected to impurity ion implantation.

  Next, after removing the mask M5, as shown in FIGS. 53 ((a) to (f)) and FIG. 61, element formation regions (1n, 1p, 1n1) and contacts on the main surface of the silicon substrate 1 are contacted. In a state where the entire gate wiring 10 including the region 9 is selectively covered with the mask M 6, impurities are ion-implanted into the element forming region 1 p 1 on the main surface of the silicon substrate 1 to match the gate electrode 27. A semiconductor region (extension region) 32 is formed (impurity ion implantation (B)). Impurity ion implantation is not limited to this, but is performed, for example, in three steps.

In the first impurity ion implantation, for example, boron difluoride (BF ₂ ) is used as an impurity, the acceleration energy is about 3 KeV, and the dose amount is about 1.0E15 (1 × 10 ¹⁵ [atoms / cm ² ]). Perform under conditions.

In the second impurity ion implantation, for example, phosphorus (P) is used as an impurity, and the acceleration energy is about 55 KeV, and the dose is about 8.0E12 (8 × 10 ¹² [atoms / cm ² ]).

In the third impurity ion implantation, for example, phosphorus (P) is used as an impurity, under the conditions of an acceleration energy of about 30 KeV and a dose amount of about 4.0E13 (1 × 10 ¹³ [atoms / cm ² ]).

  In this step, impurity ions are implanted into the portion of the gate wiring 30 covered with the mask M6, specifically, the gate electrode 27 on the element formation region 1n1 and part of the routing portion 28. Absent. On the other hand, impurity ions are implanted into a portion of the gate wiring 30 that is not covered with the mask M6, specifically, the gate electrode 27 on the element formation region 1p1, a part of the routing portion 28, and the contact region 29. Is done.

  In this step, since the entire gate wiring 10 is covered with the mask M6, the gate wiring 10 including the contact region 9 is not subjected to impurity ion implantation.

  Next, after removing the mask M 6, the side walls of the gate wiring 10 including the gate electrode 7 and the routing portion 8 and the gate wiring 30 including the gate electrode 27 and the routing portion 28 are formed in the same manner as in the first embodiment. Sidewall spacers 13 are formed on the side walls.

  Next, as shown in FIGS. 54 (a) to (f) and FIG. 62, the element formation region (1p, 1p1) on the main surface of the silicon substrate 1 is selectively covered with a mask M7. Impurities are ion-implanted into the element formation regions 1n and 1n1 on the main surface of the silicon substrate 1, and a pair of n-type semiconductor regions (contact regions) 14 aligned with the sidewall spacers 13 and a pair of alignment aligned with the sidewall spacers 13 are provided. An n-type semiconductor region (contact region) 34 is formed (impurity ion implantation (C)). Impurity types and introduction conditions are the same as in the first embodiment. In FIG. 62, the side wall spacers 13 are not shown for easy understanding of the invention.

  In this step, the portion of the gate wiring (10, 30) covered with the mask M7, specifically, the gate electrode (7, 27) on the element formation region (1p, 1p1), the routing portion (8, 28) is not subjected to impurity ion implantation. On the other hand, a portion of the gate wiring (10, 30) that is not covered with the mask M7, specifically, the gate electrode (7, 27) on the element formation region (1n, 1n1), the routing portion (8, 28). ) And the contact regions (9, 29) are subjected to impurity ion implantation.

  Next, after removing the mask M7, as shown in FIG. 55 ((a) to (f)) and FIG. 63, the element formation region (1n, 1n1) on the main surface of the silicon substrate 1 is selected by the mask M8. In a state of being covered, impurities are ion-implanted into the element formation regions 1p and 1p1 on the main surface of the silicon substrate 1, and a pair of n-type semiconductor regions (contact regions) 15 aligned with the sidewall spacers 13, and sidewalls A pair of n-type semiconductor regions (contact regions) 35 aligned with the spacers 13 are formed (impurity ion implantation (C)). Impurity types and introduction conditions are the same as in the first embodiment. In FIG. 63, the side wall spacers 13 are not shown for easy understanding of the invention.

  In this step, the portion of the gate wiring (10, 30) covered with the mask M8, specifically, the gate electrode (7, 27) on the element formation region (1n, 1n1), the routing portion (8, 28) is not subjected to impurity ion implantation. On the other hand, a portion of the gate wiring (10, 30) that is not covered with the mask M8, specifically, the gate electrode (7, 27) on the element formation region (1p, 1p1), the routing portion (8, 28). ) And the contact regions (9, 29) are subjected to impurity ion implantation.

  Next, the mask M8 is removed, and then heat treatment for activating each impurity in the semiconductor region (11, 12, 14, 15, 31, 32, 34, 35) is performed.

  Next, a cobalt silicide layer (16a, 16b), an interlayer insulating film 17, a connection hole (18a, 18b), a conductive plug 19, and a wiring 20 are formed by the same method as in the first embodiment. As a result, the structure shown in FIG. 45 is obtained.

  In the first embodiment, in the impurity ion implantation (see FIG. 58) for forming a pair of semiconductor regions (extension regions) 11 which are a source region and a drain region of a low breakdown voltage n-type MISFET Qn, a high breakdown voltage MISFET (Qn1 , Qp1) with the mask M3 covering the contact region 29 of the gate wiring 30 on the side, impurities are ion-implanted into the element formation region 1n, and a pair of semiconductor regions which are a source region and a drain region of the low breakdown voltage p-type MISFET Qn In the impurity ion implantation for forming the (extension region) 12 (see FIG. 59), in the state where the contact region 29 of the gate wiring 30 on the high breakdown voltage MISFET (Qn1, Qp1) side is covered with the mask M4, Impurities are ion-implanted into 1p, and a high breakdown voltage n-type MISFET Qn1 saw In impurity ion implantation (see FIG. 60) for forming a pair of semiconductor regions (extension regions) 31 which are regions and drain regions, the contact region 9 of the gate wiring 10 on the low breakdown voltage MISFET (Qn, Qp) side is masked. Impurities are ion-implanted into the element formation region 1n1 in the state covered with M5 to form a pair of semiconductor regions (extension regions) 32 that are a source region and a drain region of the high breakdown voltage p-type MISFET Qp1 ( In FIG. 61), since the impurity region is ion-implanted into the element formation region 1p1 while the contact region 9 of the gate wiring 10 on the low breakdown voltage MISFET (Qn, Qp) side is covered with the mask M6, the gate wiring 10 The contact region 9 of the gate wiring 30 is not covered with the mask (M3, M4). The transfected region 29 as compared with the case of not covered with the mask (M5, M6), the impurity concentration of the polysilicon film in each of the contact region of the gate wirings 10 and 30 (9, 29) can respectively be lowered.

Further, in the impurity ion implantation for forming the pair of n-type semiconductor regions (extension regions) 11, the element formation regions (1p, 1n1, 1p1) and the contact regions 29 of the gate wiring 30 are covered with the same mask M3.
In impurity ion implantation for forming a pair of p-type semiconductor regions (extension regions) 12, the element formation regions (1n, 1n1, 1p1) and the contact regions 29 of the gate wiring 30 are covered with the same mask M4.
In impurity ion implantation for forming a pair of n-type semiconductor regions (extension regions) 31, the element formation region (1n, 1p, 1p1) and the contact region 9 of the gate wiring 10 are covered with the same mask M5.
In the impurity ion implantation for forming the pair of p-type semiconductor regions (extension regions) 32, the element formation region (1n, 1p, 1n1) and the contact region 9 of the gate wiring 10 are covered with the same mask M6. There is no need to newly form a mask covering the contact regions (9, 29) of the gate wirings 10 and 30.

  Therefore, also in the sixth embodiment, the generation of abnormal oxides can be suppressed as in the first embodiment, and the manufacturing yield of the semiconductor device can be improved. Furthermore, these effects can be obtained without increasing the manufacturing cost.

  In the sixth embodiment, in the impurity ion implantation (A) in FIG. 57, the polysilicon film 6 that becomes the contact region 9 of the gate wiring 10 and the polysilicon film 6 that becomes the contact region 29 of the gate wiring 30 are formed. Impurities are ion-implanted, and impurity ions are implanted into the contact region 9 of the gate wiring 10 in the impurity ion implantation (B) in FIGS. 58 and 59, and in the impurity ion implantation (B) in FIGS. Since impurities are ion-implanted into 30 contact regions 29, the impurity concentration in the polysilicon film in the contact region 9 is lowered while suppressing the increase in resistance of the contact region 9.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

  For example, Embodiments 1, 2, 3, 4 and 5 can be implemented in combination, and the respective effects can be obtained. Further, when forming a two-level complementary MISFET as in the sixth embodiment, it is of course possible to combine the sixth embodiment with the first, second, third, fourth and fifth embodiments.

  For example, in the first to sixth embodiments described above, the example in which the polysilicon film is used as the semiconductor film of the gate wiring has been described. However, the present invention uses a single crystal silicon film or an amorphous silicon film as the semiconductor film. The present invention can also be applied to the case of using other semiconductor films. However, in consideration of conductivity, difficulty of film formation, reliability, difference in linear expansion coefficient from the silicon substrate, etc., a polysilicon film is desirable.

  In the first to sixth embodiments described above, the example in which the cobalt silicide layer is used as the metal / semiconductor compound layer of the gate wiring has been described. However, the present invention relates to a tungsten silicide (WSi) layer, a titanium silicide (TiSi), The present invention is also applicable when other metal / semiconductor compound layers such as a nickel silicide (NiSi) layer are used. In particular, CoSi is widely used in deep submicron devices because the resistance rise in narrow wiring is small.

  In the first to sixth embodiments, the example in which the contact region of the gate wiring and the upper wiring 20 are electrically connected via the conductive plug 19 embedded in the connection hole 18b has been described. The present invention can also be applied to a case where a part of the wiring 20 is embedded in the connection hole 18b and the contact region of the gate wiring and the upper wiring 20 are electrically connected.

1 is a schematic plan view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention, where (a) is a cross-sectional view taken along line aa in FIG. 1 and (b) is taken along line bb in FIG. Sectional drawing which follows, (c) is sectional drawing which follows the cc line of FIG. It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 4 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 5 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 4; FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 9; FIG. 11 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; 12 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. FIG. 13 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 12; FIG. 14 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 6 is a schematic plan view showing a mask pattern in the manufacture of the semiconductor device according to the first embodiment of the present invention, (a) is a plan view showing the mask pattern (M1) of FIG. 5, and (b) is a mask of FIG. (C) is a plan view showing the mask pattern (M3) of FIG. 8, (d) is a plan view showing the mask pattern (M4) of FIG. 9, and (e) is a plan view showing the pattern (M2). The top view which shows a mask pattern (M5), (f) is a top view which shows the mask pattern (M6) of FIG. It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 17 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 20; FIG. 17 is a schematic plan view showing a mask pattern in manufacturing a semiconductor device according to Embodiment 2 of the present invention, (a) is a plan view showing a mask pattern (M1) of FIG. 16, and (b) is a mask of FIG. (C) is a plan view showing the mask pattern (M3) of FIG. 18, (d) is a plan view showing the mask pattern (M4) of FIG. 19, and (e) is a plan view showing the pattern (M2). FIG. 22F is a plan view showing the mask pattern (M5), and FIG. 22F is a plan view showing the mask pattern (M6) of FIG. It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 3 of this invention. FIG. 24 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 23; FIG. 25 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 27; FIG. 24 is a schematic plan view showing a mask pattern in the manufacture of a semiconductor device according to Embodiment 3 of the present invention, (a) is a plan view showing a mask pattern (M1) of FIG. 23, and (b) is a mask of FIG. (C) is a plan view showing the mask pattern (M3) of FIG. 25, (d) is a plan view showing the mask pattern (M4) of FIG. 26, and (e) is a plan view showing the pattern (M2). FIG. 29 is a plan view showing the mask pattern (M5), and (f) is a plan view showing the mask pattern (M6) of FIG. It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 4 of this invention. FIG. 31 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 30; FIG. 32 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 31; FIG. 33 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 32; FIG. 34 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 33; FIG. 35 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 34. FIG. 31 is a schematic cross-sectional view showing a mask pattern in the manufacture of a semiconductor device according to Embodiment 4 of the present invention, (a) is a plan view showing a mask pattern (M1) of FIG. 30, and (b) is a mask of FIG. A plan view showing the pattern (M2), (c) a plan view showing the mask pattern (M3) of FIG. 32, (d) a plan view showing the mask pattern (M4) of FIG. 33, and (e) of FIG. FIG. 36 is a plan view showing a mask pattern (M5), and (f) is a plan view showing the mask pattern (M6) of FIG. It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 5 of this invention. FIG. 38 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 37; FIG. 39 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 38; FIG. 40 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 39; FIG. 41 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 40; FIG. 42 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 41; FIG. 38 is a schematic cross-sectional view showing a mask pattern in the manufacture of a semiconductor device according to Embodiment 5 of the present invention, (a) is a plan view showing a mask pattern (M1) of FIG. 37, and (b) is a mask of FIG. (C) is a plan view showing the mask pattern (M3) of FIG. 39, (d) is a plan view showing the mask pattern (M4) of FIG. 40, and (e) is a plan view showing the pattern (M2). FIG. 44 is a plan view showing the mask pattern (M5), and FIG. 42 (f) is a plan view showing the mask pattern (M6) of FIG. It is a typical top view which shows schematic structure of the semiconductor device which is Embodiment 6 of this invention. It is typical sectional drawing which shows schematic structure of the semiconductor device which is Embodiment 6 of this invention, (a) is sectional drawing which follows the aa line of FIG. 44, (b) is the bb line of FIG. (C) is a sectional view taken along line cc in FIG. 44, (d) is a sectional view taken along line dd in FIG. 44, and (e) is a sectional view taken along line ee in FIG. FIG. 4F is a sectional view taken along line ff in FIG. It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 6 of this invention. FIG. 47 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 46; FIG. 48 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 47; FIG. 49 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 48; FIG. 50 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 49; FIG. 51 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 50; FIG. 52 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 51; FIG. 53 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 52; FIG. 54 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 53; FIG. 55 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 54; FIG. 49 is a schematic plan view showing a mask pattern (M1) of FIG. 48. FIG. 50 is a schematic plan view showing a mask pattern (M2) of FIG. 49. FIG. 51 is a schematic plan view showing a mask pattern (M3) of FIG. 50. FIG. 52 is a schematic plan view showing a mask pattern (M4) of FIG. 51. FIG. 53 is a schematic plan view showing a mask pattern (M5) of FIG. 52. FIG. 54 is a schematic plan view showing a mask pattern (M6) of FIG. 53. FIG. 55 is a schematic plan view showing a mask pattern (M7) of FIG. 54. FIG. 56 is a schematic plan view showing a mask pattern (M8) of FIG. 55. It is a figure for demonstrating the conventional problem, and is typical sectional drawing in the contact area | region of gate wiring. It is a figure for demonstrating the conventional problem, and is a typical perspective view in the contact area | region of gate wiring. It is a figure which shows an example of the prior art, and shows the kind and implantation amount of the impurity implanted into the polysilicon film in the contact region of the gate wiring in the manufacturing process of the semiconductor device having two-level complementary MOSFETs having different gate breakdown voltages. FIG. It is a figure which shows a prior art example, and is a figure which shows the relationship between the impurity concentration in the polysilicon film in the contact area | region of a gate wiring, and contact resistance in the semiconductor device which has a two-level complementary MOSFET from which gate breakdown voltage differs.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 1n, 1n1, 1p, 1p1 ... Element formation region (active region), 2 ... Element isolation region (inactive region), 3 ... n-type well region, 4 ... p-type well region,
DESCRIPTION OF SYMBOLS 5 ... Gate insulating film, 6 ... Polysilicon film, 7 ... Gate electrode, 8 ... Leading part (wiring part), 9 ... Contact region, 10 ... Gate wiring,
11, 14... N-type semiconductor region, 12, 15... P-type semiconductor region,
16a, 16b ... silicide layer, 17 ... interlayer insulating film, 18a, 18b ... connection hole, 19 ... conductive plug, 20 ... wiring, 21 ... abnormal oxide,
25... Gate insulating film, 27... Gate electrode, 28... Routing portion (wiring portion), 29.
31, 34... N-type semiconductor region, 32, 35... P-type semiconductor region,
M1-M8 ... Mask, Qn, Qp, Qn1, Qp1 ... MISFET

Claims (41)

A method of manufacturing a semiconductor device having a field effect transistor,
Forming a semiconductor film on the main surface of the semiconductor substrate;
A step of ion-implanting impurities for reducing the resistance value into the semiconductor film;
Patterning the semiconductor film to form a wiring including a gate electrode and a contact region;
Forming a metal / semiconductor reaction layer on the surface of the wiring;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the wiring;
Etching the insulating film to form a connection hole on the contact region of the wiring,
The method of manufacturing a semiconductor device, wherein the impurity ion implantation step is performed in a state where a portion of the semiconductor film to be a contact region of the wiring is covered with a mask. In the manufacturing method of the semiconductor device according to claim 1,
A step of ion-implanting impurities into the main surface of the semiconductor substrate to form a semiconductor region aligned with the gate electrode;
Forming a sidewall spacer on the side wall of the gate electrode;
And a step of forming a semiconductor region aligned with the sidewall spacer by ion-implanting impurities into the main surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 1,
A step of forming a conductive plug in the connection hole;
And a step of forming an upper layer wiring extending on the insulating film and electrically connected to the conductive plug. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. A method of manufacturing a semiconductor device having a field effect transistor,
Forming a semiconductor film on the main surface of the semiconductor substrate;
Patterning the semiconductor film to form a wiring including the gate electrode and a contact region;
A step of forming a semiconductor region aligned with the gate electrode by ion-implanting impurities into the main surface of the semiconductor substrate with the contact region of the wiring covered with a mask;
Forming a metal / semiconductor reaction layer on the surface of the wiring;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the wiring;
And a step of etching the insulating film to form a connection hole on the contact region of the wiring. In the manufacturing method of the semiconductor device according to claim 5,
A step of ion-implanting impurities for reducing the resistance value into the semiconductor film;
Forming a sidewall spacer on the side wall of the gate electrode;
And a step of forming a semiconductor region aligned with the sidewall spacer by ion-implanting impurities into the main surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 5,
A step of forming a conductive plug in the connection hole;
And a step of forming an upper layer wiring extending on the insulating film and electrically connected to the conductive plug. In the manufacturing method of the semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. A method of manufacturing a semiconductor device having a field effect transistor,
Forming a semiconductor film on the main surface of the semiconductor substrate;
Patterning the semiconductor film to form a wiring including the gate electrode and a contact region;
Forming a sidewall spacer on the side wall of the gate electrode;
Forming a semiconductor region aligned with the sidewall spacer by ion-implanting impurities into the main surface of the semiconductor substrate with the contact region of the wiring covered with a mask;
Forming a metal / semiconductor reaction layer on the surface of the wiring;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the wiring;
And a step of etching the insulating film to form a connection hole on the contact region of the wiring. In the manufacturing method of the semiconductor device according to claim 9,
A step of ion-implanting impurities for reducing the resistance value into the semiconductor film;
And a step of forming a semiconductor region aligned with the gate electrode by ion-implanting impurities into the main surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 9,
A step of forming a conductive plug in the connection hole;
And a step of forming an upper layer wiring extending on the insulating film and electrically connected to the conductive plug. In the manufacturing method of the semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. A field effect transistor having a gate electrode formed on a main surface of a semiconductor substrate;
A wiring including the gate electrode and the contact region, and a metal / semiconductor reaction layer provided on the semiconductor film;
An insulating film provided on the main surface of the semiconductor substrate so as to cover the wiring;
A connection hole formed in the insulating film corresponding to the contact region of the wiring,
The semiconductor device, wherein the wiring has a portion having an impurity concentration higher than that of the contact region. The semiconductor device according to claim 13,
The semiconductor device further comprises an upper layer wiring disposed on the insulating film and electrically connected to the wiring through the connection hole. The semiconductor device according to claim 13,
And a conductive plug embedded in the connection hole, and an upper-layer wiring disposed on the insulating film and electrically connected to the wiring through the conductive plug. Semiconductor device. The semiconductor device according to claim 13,
The field effect transistor is
A gate insulating film formed on the main surface of the semiconductor substrate;
A first semiconductor region formed in alignment with the gate electrode on the main surface of the semiconductor substrate;
A side wall spacer provided on a side wall of the gate electrode;
And a second semiconductor region formed in alignment with the sidewall spacer on a main surface of the semiconductor substrate. The semiconductor device according to claim 13,
The semiconductor device, wherein the semiconductor film is a silicon film. A first conductivity type field effect transistor in which a first gate electrode is provided on a first element formation region of a main surface of a semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a second conductivity type field effect transistor having a second gate electrode provided on a second element formation region of a main surface of the semiconductor substrate,
Forming a semiconductor film on a main surface of the semiconductor substrate including on the first and second element formation regions;
A step of ion-implanting impurities for reducing the resistance value into the semiconductor film;
Patterning the semiconductor film to form a wiring including the first gate electrode, the second gate electrode, and a contact region;
Forming a metal / semiconductor reaction layer on the surface of the wiring;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the wiring;
Etching the insulating film to form a connection hole on the contact region of the wiring,
The method of manufacturing a semiconductor device, wherein the impurity ion implantation step is performed in a state where a portion of the semiconductor film to be a contact region of the wiring is covered with a mask. In the manufacturing method of the semiconductor device according to claim 18,
The impurity ion implantation step includes
Impurities in the portion of the semiconductor film to be the first gate electrode in a state where the portion of the semiconductor film to be the second gate electrode and the portion of the semiconductor film to be the contact region of the wiring are covered with a mask A first step of ion-implanting
And a second step of ion-implanting impurities into the portion of the semiconductor film to be the second gate electrode in a state where the portion of the semiconductor film to be the first gate electrode is covered with a mask. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 18,
The impurity ion implantation step includes
Impurities in the portion of the semiconductor film to be the first gate electrode in a state where the portion of the semiconductor film to be the second gate electrode and the portion of the semiconductor film to be the contact region of the wiring are covered with a mask A first step of ion-implanting
Impurities in the portion of the semiconductor film to be the second gate electrode in a state where the portion of the semiconductor film to be the first gate electrode and the portion of the semiconductor film to be the contact region of the wiring are covered with a mask And a second step of ion-implanting the semiconductor device. In the manufacturing method of the semiconductor device according to claim 18,
A step of ion-implanting impurities into the first element formation region to form a semiconductor region aligned with the first gate electrode;
Impurity implantation into the second element formation region to form a semiconductor region aligned with the second gate electrode;
Forming a sidewall spacer on each side wall of the first and second gate electrodes;
Implanting impurities into the first element formation region to form a semiconductor region aligned with a sidewall spacer on the side wall of the first gate electrode;
And a step of forming a semiconductor region aligned with a side wall spacer on a side wall of the second gate electrode by ion-implanting impurities into the second element formation region. In the manufacturing method of the semiconductor device according to claim 18,
A step of forming a conductive plug in the connection hole;
And a step of forming an upper layer wiring extending on the insulating film and electrically connected to the conductive plug. In the manufacturing method of the semiconductor device according to claim 18,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. A first conductivity type field effect transistor in which a first gate electrode is provided on a first element formation region of a main surface of a semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a second conductivity type field effect transistor having a second gate electrode provided on a second element formation region of a main surface of the semiconductor substrate,
Forming a semiconductor film on a main surface of the semiconductor substrate including on the first and second element formation regions;
Patterning the semiconductor film to form a wiring including the first gate electrode, the second gate electrode, and a contact region;
Ion-implanting impurities into the first element formation region to form a semiconductor region aligned with the first gate electrode;
Impurity implantation into the second element formation region to form a semiconductor region aligned with the second gate electrode;
Forming a metal / semiconductor reaction layer on the surface of the wiring;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the wiring;
Etching the insulating film to form a connection hole on the contact region of the wiring,
Impurity ion implantation into the first element formation region is performed in a state where the second element formation region and the contact region of the wiring are covered with a mask. In the manufacturing method of the semiconductor device according to claim 24,
Impurity ion implantation into the second element formation region is performed in a state where the first element formation region and the contact region of the wiring are covered with a mask. In the manufacturing method of the semiconductor device according to claim 24,
Furthermore, a step of introducing an impurity for reducing the resistance value into the semiconductor film;
Forming a sidewall spacer on each side wall of the first and second gate electrodes;
Ion implantation of impurities into the first element formation region to form a semiconductor region aligned with a sidewall spacer on the side wall of the first gate electrode;
And a step of forming a semiconductor region aligned with a side wall spacer on a side wall of the second gate electrode by ion-implanting impurities into the second element formation region. In the manufacturing method of the semiconductor device according to claim 24,
A step of forming a conductive plug in the connection hole;
And a step of forming an upper layer wiring extending on the insulating film and electrically connected to the conductive plug. In the manufacturing method of the semiconductor device according to claim 24,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. A first conductivity type field effect transistor in which a first gate electrode is provided on a first element formation region of a main surface of a semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a second conductivity type field effect transistor having a second gate electrode provided on a second element formation region of a main surface of the semiconductor substrate,
Forming a semiconductor film on a main surface of the semiconductor substrate including on the first and second element formation regions;
Patterning the semiconductor film to form a wiring including the first gate electrode, the second gate electrode, and a contact region;
Forming a sidewall spacer on each side wall of the first and second gate electrodes;
Ion implantation of impurities into the first element formation region to form a semiconductor region aligned with a sidewall spacer on the side wall of the first gate electrode;
Impurity implantation into the second element formation region to form a semiconductor region aligned with a sidewall spacer on the side wall of the second gate electrode;
Forming a metal / semiconductor reaction layer on the surface of the wiring;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the wiring;
Forming a connection hole in the insulating film corresponding to the contact region of the wiring,
Impurity ion implantation into the first element formation region is performed in a state where the second element formation region and the contact region of the wiring are covered with a mask. The method of manufacturing a semiconductor device according to claim 29,
Impurity ion implantation into the second element formation region is performed in a state where the first element formation region and the contact region of the wiring are covered with a mask. The method of manufacturing a semiconductor device according to claim 29,
Furthermore, a step of introducing an impurity for reducing the resistance value into the semiconductor film;
Ion-implanting impurities into the first element formation region to form a semiconductor region aligned with the first gate electrode;
And a step of forming a semiconductor region aligned with the second gate electrode by implanting impurities into the second element formation region. The method of manufacturing a semiconductor device according to claim 29,
A step of forming a conductive plug in the connection hole;
And a step of forming an upper layer wiring extending on the insulating film and electrically connected to the conductive plug. The method of manufacturing a semiconductor device according to claim 29,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. A first conductivity type field effect transistor in which a first gate electrode is provided on a first element formation region of a main surface of a semiconductor substrate;
A second conductivity type field effect transistor in which a second gate electrode is provided on a second element formation region of the main surface of the semiconductor substrate;
A wiring including the first gate electrode, the second gate electrode, and a contact region, wherein a metal / semiconductor reaction layer is formed on the semiconductor film;
An insulating film formed on the main surface of the semiconductor substrate so as to cover the wiring;
A connection hole formed in the insulating film corresponding to the contact region of the wiring,
The semiconductor device, wherein the wiring has a portion having an impurity concentration higher than that of the contact region. The semiconductor device according to claim 34, wherein
The semiconductor device, wherein the semiconductor film is a silicon film. A first conductivity type field effect transistor in which a first gate electrode is provided on a first element formation region of a main surface of a semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a second conductivity type field effect transistor having a second gate electrode provided on a second element formation region of a main surface of the semiconductor substrate,
Forming a semiconductor film on a main surface of the semiconductor substrate including on the first and second element formation regions;
A step of ion-implanting impurities into the semiconductor film;
Patterning the semiconductor film to form a wiring including the first gate electrode, the second gate electrode, and a contact region;
Ion-implanting a first impurity into the first element formation region to form a semiconductor region aligned with the first gate electrode;
Ion-implanting a second impurity into the second element formation region to form a semiconductor region aligned with the second gate electrode;
Forming a sidewall spacer on each side wall of the first and second gate electrodes;
Ion-implanting a third impurity into the first element formation region to form a semiconductor region aligned with a sidewall spacer on the sidewall of the first gate electrode;
Ion-implanting a fourth impurity into the second element formation region to form a semiconductor region aligned with a sidewall spacer on the sidewall of the second gate electrode;
Forming a metal / semiconductor reaction layer on the surface of the wiring;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the wiring;
Etching the insulating film to form a connection hole on the contact region of the wiring,
In the step of implanting impurity ions into the conductive film, the portion of the semiconductor film to be the second gate electrode and the portion of the semiconductor film to be the contact region of the wiring are covered with a mask. Including a step of ion-implanting impurities into a portion of the semiconductor film to be a gate electrode,
The method of manufacturing a semiconductor device, wherein the first and third impurity ion implantations are performed in a state where the second element formation region and the contact region of the wiring are covered with a mask. In the manufacturing method of the semiconductor device according to claim 36,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. A first conductivity type field effect transistor in which a first gate electrode is provided on a first element formation region of a main surface of a semiconductor substrate with a first gate insulating film interposed therebetween;
A second conductivity type field effect transistor in which a second gate electrode is provided on a second element formation region of the main surface of the semiconductor substrate with a second gate insulating film interposed therebetween;
A first conductivity type electric field in which a third gate electrode is provided on a third element formation region on the main surface of the semiconductor substrate with a third gate insulating film thicker than the first gate insulating film interposed therebetween An effect transistor;
A second conductivity type electric field in which a fourth gate electrode is provided on a fourth element formation region of the main surface of the semiconductor substrate with a fourth gate insulating film thicker than the second gate insulating film interposed therebetween A method of manufacturing a semiconductor device having an effect transistor,
Forming a semiconductor film on a main surface of the semiconductor substrate including on the first, second, third and fourth element formation regions;
Patterning the semiconductor film to form a first wiring including the first gate electrode, the second gate electrode, and a contact region; the third gate electrode; the fourth gate electrode; Forming a second wiring including a contact region;
Impurities are ion-implanted into the first element formation region in a state where the second to fourth element formation regions and the contact region of the second wiring are covered with a mask. Forming a matched semiconductor region;
An impurity is introduced into the second element formation region in a state where the first, third, and fourth element formation regions and the contact region of the second wiring are covered with a mask, and the second gate is formed. Forming a semiconductor region aligned with the electrode;
The third gate electrode is formed by introducing an impurity into the third element formation region in a state where the first, second and fourth element formation regions and the contact region of the first wiring are covered with a mask. Forming a semiconductor region matched to
Impurities are ion-implanted into the fourth element formation region with the first, second, and third element formation regions and the contact region of the first wiring covered with a mask. Forming a semiconductor region aligned with the gate electrode;
Forming a metal / semiconductor reaction layer on the surface of each of the first and second wirings;
Forming an insulating film on the main surface of the semiconductor substrate so as to cover the first and second wirings;
Etching the insulating film to form a connection hole on each contact region of the first and second wirings. 40. The method of manufacturing a semiconductor device according to claim 38,
Furthermore, the semiconductor film has a step of ion-implanting impurities for reducing the resistance value,
The impurity ion implantation step includes
A portion of the semiconductor film serving as the first gate electrode; a portion of the semiconductor film serving as the third gate electrode; a portion of the semiconductor film serving as a contact region of the first wiring; and the second wiring. In a state where the portion of the semiconductor film to be the contact region is covered with a mask, impurities are ionized into the portion of the semiconductor film to be the second gate electrode and the portion of the semiconductor film to be the fourth gate electrode A first step of injecting;
A portion of the semiconductor film to be the second gate electrode in a state where the portion of the semiconductor film to be the first gate electrode and a portion of the semiconductor film to be the third gate electrode are covered with a mask; And a second step of ion-implanting impurities into the portion of the semiconductor film to be the fourth gate electrode. 40. The method of manufacturing a semiconductor device according to claim 38,
A step of forming a side wall spacer on each side wall of the first to fourth gate electrodes;
Impurities are ion-implanted into the first and third element formation regions in a state where the second and fourth element formation regions are covered with a mask to form sidewall spacers on the sidewalls of the first gate electrode. Forming aligned semiconductor regions and semiconductor regions aligned with sidewall spacers on the sidewalls of the third gate electrode;
Impurities are ion-implanted into the second and fourth element formation regions in a state where the first and third element formation regions are covered with a mask to form sidewall spacers on the sidewalls of the second gate electrode. Forming a matched semiconductor region and a semiconductor region matched with a sidewall spacer on a side wall of the fourth gate electrode. 40. The method of manufacturing a semiconductor device according to claim 38,
The method of manufacturing a semiconductor device, wherein the semiconductor film is a silicon film.

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