JP2008084999A - Multilayer printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that when a printed wiring board is designed, the mounting positions and the mounting number of chip capacitors are set in a portion where a plane resonance frequency in simulation does not coincide with an integral multiple of the operating frequency of the circuit and design is carried out, but when verification is carried out as to an actually manufactured prototype, the value computed in the simulation has a minute error, so that the mounting positions etc. of the chip capacitors need be redesigned. <P>SOLUTION: This multilayer printed wiring board has at least one layer of each of the power supply layer, the ground layer, and the circuit pattern layer. At least one pair of mutually parallel electrically conductive strip-like patterns is formed on the circuit pattern layer, coating layers having a predetermined width and a predetermined spacing are formed in the longitudinal direction of the one pair of the electrically conductive strip-like patterns and thereon respectively so that a plurality of chip components can be mounted in parallel, and a power supply plane and a ground plane are connected thereto respectively, so that the fine adjustment of the L component of the chip capacitor can be carried out and the plane resonance frequency can be changed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer printed wiring board.

Conventionally, EMI (Electro-Magnetic) of equipment
As a simple method for countermeasures against interference (interference), it is common to surround the printed circuit board with a grounded enclosure. In addition, in order to suppress electromagnetic radiation itself, it is also attempted not to radiate harmonics from a signal line that acts as a harmonic antenna.

  One cause of electromagnetic radiation is the phenomenon that the power plane resonates with high frequency noise. As a countermeasure against electromagnetic radiation, the power plane and ground plane (hereinafter referred to as GND plane) on the printed circuit board are connected via a chip capacitor, and the plane resonance frequency does not match the integer multiple of the circuit operating frequency (clock). In general, a countermeasure for disposing chip capacitors on a printed circuit board is generally known.

  Also, when an integrated circuit (IC) disposed on a printed circuit board performs a large processing at a certain moment, if the current from the current supply part (where the power supply is connected) is used, the impedance of the circuit pattern Therefore, there is a method in which a capacitor is arranged near the IC and used as a battery because the current cannot be supplied in time.

  This method also has an effect as an EMI countermeasure, and the noise of the IC can be suppressed by bypassing the noise from the IC ground (hereinafter referred to as GND) to the power source or returning the noise from the power source to the GND. .

As described above, in recent printed wiring boards, various EMI countermeasures are mounted on devices and the like.
JP-A-5-291818 JP-A-6-203102 JP-A-8-222916

  In recent years, due to environmental considerations, it is possible to reduce costs and reduce product failures by reducing the number of parts arranged on the printed wiring board, rather than resource-saving design / recycle design, reduce design, and reuse design. Therefore, the above-mentioned EMI countermeasures have become popular.

  In addition to the above-mentioned EMI countermeasure activities, the design that can handle various types of printed wiring boards is also flourishing, and the circuit pattern of the printed wiring boards remains unchanged, and semiconductor components such as ICs to be placed are replaced with high-precision ones. As a result, design changes to print wiring boards with higher functionality and higher accuracy than before have become mainstream.

  However, the plane resonance frequency on the printed wiring board changes each time the number and type of semiconductor components such as ICs arranged on the printed wiring board and the place where the printed wiring board is attached to the housing change. It is necessary to change the mounting position or number of chip capacitors again so that they do not coincide with an integer multiple.

  This is because when the plane resonance frequency and an integer multiple of the circuit operating frequency coincide with each other, the circuit operating frequency resonates with the peak value of the plane resonance frequency, which in turn causes EMI.

  For this reason, when designing a printed wiring board, it is also possible to design a printed wiring board by setting the mounting position or number of chip capacitors where the plane resonance frequency does not match an integer multiple of the circuit operating frequency by simulation. ing.

  However, if a printed wiring board is confirmed with a prototype that is actually manufactured, an error may occur slightly from the calculated value calculated by simulation. At this time, it is necessary to redesign the mounting position or number of chip capacitors. Become.

  Such redesign (changing the mounting position or the number of mounted chip capacitors on the substrate once mounted) causes a great labor cost and mold cost.

  The present invention has been made in view of such problems, and when the plane resonance frequency on the printed wiring board changes, the mounting position or the number of mounted chip capacitors on the board is large. An object of the present invention is to provide an inexpensive and simplified multilayer printed wiring board that can reduce the change and finely adjust the plane resonance frequency.

  The multilayer printed wiring board according to claim 1 is a circuit pattern layer comprising a power source layer comprising a power plane connected to a power source, a ground layer comprising a ground plane connected to ground, and a circuit pattern for mounting an electronic component. In the multilayer printed wiring board having at least one layer each, a pair or a plurality of pairs of conductive strip patterns parallel to each other are formed on the circuit pattern layer, and semiconductor chip components are arranged in parallel on each pair of conductive strip patterns. A plurality of coating layers having a predetermined width are formed at predetermined intervals in the longitudinal direction of the pair of conductive strip patterns so that a plurality of the conductive strip patterns can be mounted. One of the pair of conductive strip patterns is a power plane and the pair of conductive strip patterns. Since the other side of the pattern is connected to the ground plane, this structure allows the chip capacitor to Since fine adjustment of the value series inductance (L component) is possible, it is possible to easily change the plane resonant frequency.

  The multilayer printed wiring board according to claim 2 is characterized in that, in claim 1, the length in the longitudinal direction of the pair of conductive strip patterns is 5 mm or less. Can be played.

The multilayer printed wiring board according to claim 3 is the method according to claim 1 or 2,
Since the width of the conductive belt-like pattern is 1.6 mm + fillet or less, the same effects as in the first to second aspects can be obtained.

  Since the multilayer printed wiring board according to the present invention can finely adjust the equivalent series inductance (L component) of the chip capacitor, it is possible to easily change the plane resonance frequency, and versatility with EMI countermeasures taken. It is possible to provide a multi-layer printed wiring board having a high height.

  The present invention will be described in detail with reference to FIGS.

  1 to 7 show an embodiment of a multilayer printed wiring board according to the present invention.

  In this embodiment, a four-layer printed wiring board will be described as a multilayer printed wiring board. The multilayer printed wiring board exemplified here is of a non-penetrating VIA type.

  FIG. 1 is a schematic cross-sectional view showing the structure of a multilayer printed wiring board according to the present invention.

  First, as shown in FIG. 1, two double-sided (two-layer) printed wiring boards 1 and 2 are prepared, and after the second layer 4 and the third layer 5 are etched to form a solid pattern, Through holes 7 and 8 are formed between the first layer 3 and the second layer 4 and between the third layer 5 and the fourth layer 6 to electrically connect the layers. (This through hole is provided in several places.) Since the first layer 3 serves as a circuit component mounting surface, the first layer 3 and the second layer 4 are connected to the through hole 7 between them (the formation of a multilayer printed circuit board). The pattern density on the other circuit component mounting surface can be made relatively large by connecting via via holes). The first layer 3 and the fourth layer 6 are provided with circuit components such as the semiconductor component 9 and a circuit pattern which is a pattern thereof.

  The second layer 4 (power supply layer) is a power plane composed of a solid pattern connected to the power source, and the third layer 5 (ground layer) is a GND plane composed of a solid pattern connected to the ground. The GND plane also functions as a shield pattern.

  Next, as shown in FIG. 2, a base material (hereinafter referred to as “prepreg”) containing an epoxy resin or the like is disposed between the double-sided printed wiring boards 1 and 2. Then, after laminating each, by applying temperature under pressure, the double-sided printed wiring boards 1 and 2 are bonded (adhered) by the prepreg 10, and a single four-layer printed wiring as shown in FIG. A substrate 11 is formed.

  In this state, the through hole 12 penetrating the first layer 3 to the fourth layer 6 is formed to form one four-layer printed wiring board 13 as shown in FIG.

  Next, the conductive strip pattern formed on the circuit pattern of the multilayer printed wiring board will be described.

  FIG. 5 is a diagram showing a conductive strip pattern formed on a circuit pattern in a multilayer printed wiring board.

  The conductive strip pattern 14 is mainly mounted with a chip capacitor, and a plurality of chip capacitors 18 can be mounted in parallel with each pair of conductive strip patterns in the longitudinal direction of the pair of conductive strip patterns. The resist layer and / or silk that is the clothing layer 15 is formed at a predetermined interval.

  The conductive strip pattern 14 is formed with a pair of conductive strip patterns connected to the electrode of the chip capacitor, and is conductively connected to the power plane and the GND plane through through holes 17 (via holes).

  The chip capacitor 18 used here is of a type called 1608 series, and the exposed rectangular pad 16 which is a part of the conductive strip pattern is formed in accordance with a size capable of mounting this type. Incidentally, in the case of the 1608 series which is the chip capacitor 18, as shown in FIG. 6, it is desirable that the rectangular pad 16 has a width of 0.8 mm or less and a width of 1.6 mm or less and a fillet or less. A fillet is the shape of a solder pile when soldered to a component lead and a land or pad.

  The length of the conductive strip pattern is preferably 5 mm in the longitudinal direction, and the conductive strip pattern is divided into two by a resist and / or silk that is the clothing layer 15.

  The conductive belt-like pattern is divided by resist and / or silk that is the clothing layer 15 to provide two rectangular pads 14 for mounting the chip capacitor. Actually, the chip capacitor is provided only in one of the two locations. Will be implemented.

  For example, when designing a multilayer printed wiring board, the mounting position or the number of mounted chip capacitors 18 is determined by simulation so that the plane resonance frequency and the circuit operating frequency do not coincide with an integer multiple. In the case of confirmation, there is a slight error from the calculated value calculated by the simulation, and there is a case where the respective frequencies coincide with each other. At this time, as shown in FIG. 7, the mounting position of the chip capacitor 18 of the conductive strip pattern 14 is mounted at the position of the rectangular pad 16 in the direction away from the through-hole 17 portion, so that the equivalent series inductance ( L component) increases. As a result, the plane resonance frequency can be varied, so that the plane resonance frequency and the operating frequency of the circuit do not coincide with an integral multiple.

  Then, the operating frequency of the circuit resonates with a low portion that is not the peak value of the plane resonance frequency, and as a result, generation of electromagnetic radiation can be suppressed.

  By forming the conductive strip pattern as described above, the plane resonance frequency can be finely adjusted, so that the plane resonance frequency can be easily changed. Can be easily changed without incurring significant labor and mold costs, and electromagnetic radiation can be suppressed.

  The above-described embodiments are illustrated for explanation, and the present invention is not limited thereto, and those skilled in the art will recognize from the claims, the detailed description of the invention, and the description of the drawings. Modifications and additions are possible without departing from the technical idea of the present invention.

  For example, in the multilayer printed wiring board of the present invention, the multilayer printed wiring board exemplified in the embodiment is a non-penetrating VIA type, but may be a generally used penetrating VIA type.

  Further, in the multilayer printed wiring board of the present invention, four layers have been exemplified, but a multilayer board generally adopted conventionally such as eight layers, sixteen layers, thirty-two layers, etc. may be used.

  Moreover, although the electroconductive strip | belt-shaped pattern of the Example description illustrated that it was a 2 division | segmentation shape with the resist and / or silk which are a clothing layer in the longitudinal direction, as shown in FIG. By providing a plurality of exposed rectangular pads, the plane resonance frequency can be further finely adjusted. Any number of divisions can be made as long as they can be divided according to the shape of the chip capacitor.

  From the above, the pad shape dimensions of the rectangular pad on which the chip capacitor having the conductive band pattern is mounted preferably have a width of 0.8 mm or less, a width of 1.6 mm + a fillet or less, and the conductor pattern has a total length of 5 mm in the longitudinal direction. Although exemplified as desirable, it may be handled by changing the pattern size so that chip parts can be mounted, and by dividing the conductive strip pattern in the longitudinal direction, it is divided into more places, The plane resonance frequency can be further finely adjusted.

  In addition, the size of the rectangular pad on which the chip capacitor having the conductive strip pattern described in the embodiment is mounted is illustrated so that the 1608 series can be mounted. However, the pattern size may be changed so that the chip component can be mounted. It doesn't matter.

  A plurality of conductive strip patterns described in the embodiments may be arranged on the substrate.

  In addition, the resist and / or silk that is a coating layer having a predetermined width in the longitudinal direction of the conductive belt-like pattern described in the examples may be the same as the resist and silk of the substrate.

Schematic sectional view showing the structure of a multilayer printed wiring board (Example 1) Schematic sectional view showing the structure of a multilayer printed wiring board (Example 1) Schematic sectional view showing the structure of a multilayer printed wiring board (Example 1) Schematic sectional view showing the structure of a multilayer printed wiring board (Example 1) It is a top view showing the conductive strip pattern concerning the present invention. Example 1 It is a top view showing the conductive strip pattern concerning the present invention. Example 1 It is a top view showing the conductive strip pattern concerning the present invention. Example 1 It is the top view which used the rectangular pad of the electroconductive strip | belt-shaped pattern which concerns on this invention in multiple places.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Double-sided printed wiring board 2 Double-sided printed wiring board 3 1st layer 4 2nd layer 5 3rd layer 6 4th layer 7 Through hole 8 Through hole 9 Semiconductor component 10 Prepreg 11 4th layer printed wiring board 12 Through hole 13 4 layer printing Wiring board 14 Conductive belt-like pattern 15 for chip parts Clothing layer 16 Rectangular pad 17 Through hole 18 Chip capacitor

Claims (3)

In a multilayer printed wiring board having at least one circuit pattern layer consisting of a power supply layer connected to a power supply, a ground layer consisting of a ground plane connected to earth, and a circuit pattern for mounting electronic components,
In the circuit pattern layer, a pair or a plurality of conductive strip patterns parallel to each other are formed,
Each pair of conductive strip patterns is formed with a predetermined width of clothing layers at predetermined intervals in the longitudinal direction of the pair of conductive strip patterns so that a plurality of chip parts can be mounted in parallel.
One of the pair of conductive strip patterns is connected to a power plane, and the other of the pair of conductive strip patterns is connected to a ground plane. In claim 1,
The multilayer printed wiring board, wherein the pair of conductive strip patterns has a length in the longitudinal direction of 5 mm or less In claim 1 or claim 2,
The width of the conductive belt-like pattern is 1.6 mm + fillet or less, and the multilayer printed wiring board is characterized in that