JP2007005694A - Multilayer capacitor - Google Patents

Abstract

The present invention provides a multilayer capacitor capable of smoothing a peak of series resonance and reducing deterioration of impedance characteristics of a decoupling circuit.
A multilayer capacitor of the present invention is configured such that a multilayer body that is formed by laminating a plurality of dielectric layers and a dielectric layer is disposed inside the multilayer body. A plurality of first inner electrodes 3 and second inner electrodes 4 arranged alternately, and a plurality of first inner electrodes 3 and a plurality of second inner electrodes 4 drawn out from the first inner electrode 3 and the second inner electrode 4 to the side surface of the laminate 1 at a plurality of locations. 1st drawer part 5 and 2nd drawer part 6 of the above, the 1st drawer part 5 and the 2nd drawer part which are formed in the lamination direction on the side of layered product 1, and are located up and down in the lamination direction 6 includes a plurality of first terminal electrodes 7 and second terminal electrodes 8 that electrically connect each other, and at least one of the first lead portion 5 and the second lead portion 6 has a conductor material. Blank portions 5a, 6a not to be provided are provided on the inner side in the drawing direction.
[Selection] Figure 2

Description

  The present invention relates to a multilayer capacitor suitably used for a decoupling circuit for supplying power to an IC.

  Conventionally, a multilayer capacitor has been suitably used in a decoupling circuit connected in parallel between an IC and a power source. Such a multilayer capacitor can be used to power an IC during a power shortage state immediately after switching in switching in the IC. Supply.

  As a conventional multilayer capacitor, a plurality of first internal electrodes and second internal electrodes alternately arranged so as to be opposed to each other with a dielectric layer sandwiched inside a multilayer body formed by laminating a plurality of dielectric layers A plurality of first lead portions and second lead portions are led out from the electrodes to the side surface of the laminate at a plurality of locations, respectively, and the first lead portions and the second lead portions positioned vertically in the stacking direction are electrically connected to each other. It is known that the first terminal electrode and the second terminal electrode are formed on the side surface of the laminated body in the lamination direction while being connected to each other. (For example, see Patent Document 1).

In the conventional multilayer capacitor, since the equivalent series inductance is reduced by forming a plurality of lead portions drawn from the internal electrodes and shortening the path of the flowing current, the minimum peak of impedance formed by the series resonance is on the high frequency side. Formed. A capacitor having a functional band near the peak of the series resonance formed in this way is, for example, a high frequency side in a decoupling circuit configured to reduce impedance in a wide band by combining a plurality of capacitors having different functional band frequencies. It is used as a capacitor corresponding to the functional band.
Special table 2002-508114 gazette

  However, the above-described conventional multilayer capacitor has a steep peak of series resonance in the functional band, and if this steepness is high, it is in parallel with a capacitor having a functional band corresponding to a close frequency band. The maximum peak of impedance formed by resonance becomes steep. For this reason, the decoupling circuit configured using the conventional multilayer capacitor has a problem that a frequency band in which the impedance is larger than the standard value is generated in part. In other words, even if the conventional multilayer capacitor has a low-impedance functional band on the high frequency side, the impedance characteristics of the decoupling circuit can be reduced to a certain frequency when the peak of the resonance point is sharply formed. There was a problem that it was greatly degraded in the band.

  The present invention has been devised in view of the problems in the conventional multilayer capacitor as described above, and its purpose is to reduce the degradation of the impedance characteristics of the decoupling circuit by smoothing the series resonance peak. An object of the present invention is to provide a multilayer capacitor.

  The multilayer capacitor of the present invention includes a multilayer body formed by laminating a plurality of dielectric layers, and a plurality of first internal parts arranged alternately so as to face each other with the dielectric layer sandwiched between the multilayer bodies. An electrode and a second internal electrode, and a plurality of first and second lead portions drawn from the first internal electrode and the second internal electrode to the side surface of the laminate at a plurality of locations, respectively. And a plurality of first terminals that are formed on the side surface of the laminate in the laminating direction and electrically connect the first lead portions and the second lead portions that are positioned above and below in the stack direction. In the multilayer capacitor including the electrode and the second terminal electrode, at least one of the first lead portion and the second lead portion has a blank portion in which no conductor material exists provided in the lead direction. It is a characteristic

  In the multilayer capacitor of the present invention, in the above configuration, the multilayer body has a rectangular parallelepiped shape, and the first internal electrode and the second internal electrode that are opposed to each other with the dielectric layer interposed therebetween. Of the first terminal electrode and the second terminal electrode to which the lead portion and the second lead portion are connected are adjacent to each other on the same side surface of the laminate or the adjacent side surface. It is characterized by being.

  The multilayer capacitor of the present invention is characterized in that, in the above configuration, the blank portion is provided in a central region in the drawing direction of the drawing portion.

  The multilayer capacitor of the present invention is characterized in that, in the above configuration, a plurality of the blank portions are provided in the lead-out portion.

  In the multilayer capacitor of the present invention, the first terminal electrodes and the second terminal electrodes are alternately arranged on the side surfaces of the multilayer body in the above configuration.

  According to the multilayer capacitor of the present invention, at least one of the plurality of first lead portions and second lead portions drawn from the first internal electrode and the second internal electrode to the side surface of the multilayer body at a plurality of locations, respectively. Since the blank portion in which no conductor material exists is provided inside the lead-out direction, the DC resistance value of the first lead-out portion and the second lead-out portion increases when used as a capacitor constituting the decoupling circuit. By doing so, the peak of the series resonance becomes gentler with the minimum value rising, and the peak of the parallel resonance with other capacitors does not become steep, so it is possible to reduce the deterioration of the impedance characteristics of the decoupling circuit. .

  According to the multilayer capacitor of the present invention, the first lead portion and the second lead portion drawn from the first internal electrode and the second internal electrode facing each other across the dielectric layer are connected. When adjacent ones of the terminal electrode and the second terminal electrode are arranged on the same side surface of the laminate or adjacent side surfaces, the current flowing between the adjacent terminal electrodes is the shortest distance. Since it concentrates on the peripheral part of the internal electrode, the current flowing in the lead part is also concentrated in the outer region, and an increase in inductance can be effectively suppressed when a blank part in which no conductor material is present is provided.

  Further, according to the multilayer capacitor of the present invention, when the blank portion is provided in the central region in the lead-out direction of the lead-out portion, the balance of the current density in both the outer regions of the lead-out portion where the current is concentrated is improved. As a result, an increase in inductance can be effectively suppressed.

  Further, according to the multilayer capacitor of the present invention, when a plurality of blank portions are provided in the lead portion, the joint portions of the dielectric layers facing each other across the lead portion are dispersed. Since the stress applied at this time is dispersed and the occurrence of delamination between the dielectric layers can be suppressed, the reliability of the multilayer capacitor can be increased.

  According to the multilayer capacitor of the present invention, when the first terminal electrodes and the second terminal electrodes are alternately arranged on the side surfaces of the multilayer body, the adjacent first terminal electrodes and second terminal electrodes are arranged. Since the directions of the respective currents are reversed, the magnetic fluxes generated by the currents cancel each other and the inductance is greatly reduced.

  Hereinafter, the multilayer capacitor of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is an external perspective view showing an example of an embodiment of the multilayer capacitor of the present invention, FIG. 2 is a partially exploded perspective view of the multilayer capacitor of FIG. 1, and FIGS. FIG. 2 is a plan view of a dielectric layer in which a first internal electrode and a dielectric layer in which a second internal electrode are formed of the multilayer capacitor of FIG. 1 are viewed from above. A multilayer capacitor 10 of the present invention shown in these drawings includes a multilayer body 1, a plurality of first internal electrodes 3 and a second internal electrode 4, a plurality of first terminal electrodes 7 and a second terminal electrode 8. .

  The laminated body 1 is a substantially rectangular parallelepiped dielectric formed by laminating, for example, 70 to 600 layers of a plurality of rectangular dielectric layers 2a and 2b. FIG. 2 shows an example in which the number of stacked dielectric layers 2a and 2b is omitted in order to simplify and explain the present embodiment.

  The dielectric layers 2a and 2b are formed to a thickness of 1 μm to 3 μm per layer by a dielectric material mainly composed of, for example, barium titanate, calcium titanate, strontium titanate or the like.

  A plurality of first internal electrodes 3 and a plurality of second internal electrodes 4 are alternately arranged inside the multilayer body 1 so as to face each other with the dielectric layer 2b interposed therebetween, and a capacitance is formed in the opposing region. Has been. The dielectric layer 2b functions as an effective layer for forming a capacitance, and the dielectric layer 2a not sandwiched between the internal electrodes 3 and 4 is disposed on the main surface side of the multilayer body 1 as a protective layer.

The internal electrodes 3 and 4 are formed with a thickness of, for example, 0.5 μm to 2 μm, for example, with a conductive material mainly composed of metal such as nickel, copper, nickel-copper, silver-palladium. Further, since the outer peripheries of the internal electrodes 3 and 4 are separated from the side surface of the multilayer body 1, the opposing area of the internal electrodes 3 and 4 is, for example, when the area of each dielectric layer ² b is 2.3 mm ^2. 1.7 mm ² to ² mm ² .

  In addition, the first internal electrode 3 and the second internal electrode 4 are respectively connected to the multilayer body 1 via the first lead portion 5 and the second lead portion 6 that are drawn to the side surface of the multilayer body 1 at a plurality of locations. Are electrically connected to the plurality of first terminal electrodes 7 and the second terminal electrodes 8.

  The first terminal electrode 7 and the second terminal electrode 8 are formed on the side surface of the multilayer body 1 to have a thickness of, for example, 2 μm to 70 μm in the stacking direction, and are located at the top and bottom of the stacking direction. 7 and the 2nd drawer | drawing-out part 8 are electrically connected, respectively.

  Further, the terminal electrodes 7 and 8 are formed to a thickness of, for example, 0.5 μm to 2 μm, for example, with a conductor material mainly composed of a metal such as nickel, copper, silver, or palladium. The surface of the terminal electrodes 7 and 8 is preferably formed with a conductive material such as tin, solder or gold for the purpose of improving the connection with the wiring of the external wiring board.

  In the multilayer capacitor 10 configured in this way, when a predetermined voltage is applied between the first terminal electrode 7 and the second terminal electrode 8, the first internal electrode 3 and the second internal electrode 4. A capacitance corresponding to the dielectric constant, thickness, opposing area and number of layers of the dielectric layer 2b positioned between the two is formed.

  In the multilayer capacitor 10 of the present invention, when the dielectric layer 2b is made of a dielectric material mainly composed of barium titanate, an appropriate organic solvent, glass frit, organic binder, etc. are added to the barium titanate powder.・ Mixed into a mud-like shape, and formed a plurality of ceramic green sheets of a predetermined shape and thickness by the doctor blade method, etc., and one main surface of each ceramic green sheet, for example, nickel powder A process of printing and applying a conductive paste obtained by adding and mixing an appropriate organic solvent, glass frit, organic binder, etc. in a predetermined pattern by screen printing, etc., and laminating a predetermined number of the obtained ceramic green sheets A laminated sheet consisting of a plurality of ceramic green sheets is formed by pressure bonding, and these are stacked individually. A step of cutting and separating into individual laminates corresponding to the capacitors, a step of firing the individual laminates at a temperature of, for example, 1100 ° C. to 1400 ° C. to obtain the laminate 1, and a side surface of the laminate 1 And forming the terminal electrodes 7 and 8 by printing, coating, and baking the conductor paste in a strip shape in the laminating direction by a screen printing method or the like. The coating on the terminal electrodes 7 and 8 is formed by, for example, electroless plating. In the firing step of this manufacturing method, the ceramic green sheet and the conductive paste are formed into the dielectric layer 2 and the internal electrodes 3 and 4 by firing. In addition, the shrinkage rate accompanying baking of the ceramic green sheet used in this manufacturing method is set to about 10% to 20%, for example. Further, the dielectric material contained in the ceramic green sheet may be added and mixed in the conductor paste.

  In the multilayer capacitor 10 manufactured in this way, the path of the flowing current is shortened by forming a plurality of lead portions 5 and 6 drawn from the internal electrodes 3 and 4, so that the equivalent series inductance is reduced and the series resonance is caused. Since the peak at which the formed impedance is minimized is formed on the high frequency side, for example, in a decoupling circuit configured to reduce the impedance in a wide band by combining a plurality of capacitors having different functional band frequencies, the high frequency side It is used as a capacitor corresponding to the functional band.

  In the multilayer capacitor 10 of the present invention, the plurality of first lead portions 5 and the second lead portions 5 that are drawn from the first internal electrode 3 and the second internal electrode 4 to the side surface of the multilayer body 1 at a plurality of locations, respectively. Since at least one of the lead-out portions 6 is provided with the blank portions 5a, 6a in which no conductor material exists inside the lead-out direction, the first lead-out portion 5 and the second lead-out portion 5 are used when used as a capacitor constituting a decoupling circuit. As the DC resistance value of the lead-out portion 6 increases, the minimum value of the series resonance peak increases and the parallel resonance peak with other capacitors does not become sharp, so the impedance of the decoupling circuit It becomes possible to reduce the deterioration of characteristics.

  The first terminal electrode to which the first lead portion 5 and the second lead portion 6 that are drawn from the first internal electrode 3 and the second internal electrode 4 that are opposed to each other with the dielectric layer 2 interposed therebetween is connected. 7 and the second terminal electrode 8 that are adjacent to each other are disposed on the same side surface of the laminated body 1 or on the adjacent side surface, so that the current flowing between the adjacent terminal electrodes 7 and 8 is the shortest. Since the current concentrates on the peripheral edge portion of the internal electrodes 3 and 4 which are distances, the current flowing through the lead portions 5 and 6 is also concentrated on the outer region, and the inductance when the blank portions 5a and 6a having no conductor material are provided. Can be effectively suppressed.

  Further, since the blank portion is provided in the central region in the pull-out direction of the lead-out portion, the balance of the current density in both the outer regions of the lead-out portions 5 and 6 where the current is concentrated is improved. Current is not concentrated on one side of the outer region, and as a result, an increase in inductance can be effectively suppressed. In this case, in particular, it is important that the blank portions 5a and 6a are provided on a line g connecting the centers in the width direction with respect to the drawing direction of each drawing portion.

  In addition, although the method of narrowing the width | variety with respect to the drawer | drawing-out direction can also be considered for the purpose of raising the direct current resistance value of the drawer | drawing-out parts 5 and 6, in this case, two electric currents which flow outside the drawer | drawing-out parts 5 and 6 approach. Therefore, since the directions of the magnetic fluxes generated by the current are the same, there is a problem that they repel each other and the equivalent series inductance increases, so that it cannot be adopted.

  In the multilayer capacitor of the present invention, since the first terminal electrodes 7 and the second terminal electrodes 8 are alternately arranged on the side surfaces of the multilayer body 1, the adjacent first terminal electrodes 7 and the second terminal electrodes 8. Since the current directions of the terminal electrodes 8 are opposite to each other, the magnetic fluxes generated by the currents cancel each other and the inductance is greatly reduced.

  Note that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made without departing from the scope of the present invention.

  For example, in the example of the embodiment described above, the terminal electrodes 7 and 8 are formed by baking the applied conductor paste, but other than this, for example, the terminal electrodes 7 and 8 can be formed by electroless plating. In addition, when this method is used, there is an advantage that it can be formed accurately with respect to the portion exposed on the side surface.

  In the example of the embodiment described above, the blank portions 5a and 6a occupy 100% on the line g connecting the centers in the width direction with respect to the drawing direction of the drawing portions 5 and 6, but FIG. 3B, the dielectric layer 2b on which the first internal electrode 3 and the second internal electrode 4 of the same multilayer capacitor as in FIGS. 3A and 3B are formed are moved upward. As shown in the plan view seen from above, the effect of the present invention is sufficiently exerted by occupying 80% or more on the line g connecting the centers in the width direction. Further, the shape of the blank portions 5a and 6a is not limited to the rectangular shape and the elliptical shape, and other irregular shapes may be adopted. The width direction preferably accounts for 50% or more.

  Further, in the example of the embodiment described above, the blank portions 5a and 6a are formed only at one place for each of the leading portions 5 and 6, but FIG. 3 (a) is shown in FIGS. As shown in the plan view of the dielectric layer 2b formed with the first internal electrode 3 and the dielectric layer 2b formed with the second internal electrode 4 of the same multilayer capacitor as in FIG. A plurality of blank portions 5a and 6a may be provided for each of the drawing portions 5 and 6. In the case of such a configuration, since the joint portions of the dielectric layers 2b facing each other with the lead portions 5 and 6 interposed therebetween are dispersed, the stress applied during thermal expansion or thermal shrinkage is dispersed. Thus, the reliability of the multilayer capacitor can be increased.

  As the multilayer capacitor 10 of the present invention, the dielectric layer 2 is made of a dielectric material mainly composed of barium titanate, and the multilayer body 1 having a length of 2.0 mm, a width of 1.2 mm, and a height of 0.85 mm is formed. The first terminal electrode 7 and the second terminal electrode 7 are formed by forming the first inner electrode 3 and the second inner electrode 4 alternately by 50 layers each using nickel as a material and baking copper on the side surface. A device in which the terminal electrode 8 was formed was manufactured. Each of the lead portions 3 and 4 has a shape of 160 μm in the lead-out direction, a width of 100 μm with respect to the lead-out direction, and a blank portion 5a, 6a having no conductor in the central region in the lead-out direction with a width of 70 μm over the entire region in the lead-out direction. Four internal electrodes 3 and 4 were formed.

  FIG. 6A is a diagram showing impedance characteristics in a decoupling circuit using the multilayer capacitor 10 of this example. In the figure, the horizontal axis indicates the frequency, and the vertical axis indicates the impedance. The impedance was measured in the frequency band of 1 MHz to 1 GHz. The characteristic curve x in the figure shows the impedance characteristic of the multilayer capacitor 10 of this example, the characteristic curve y shows the impedance characteristic of the low frequency side capacitor used in the decoupling circuit, and the characteristic curve z shows the multilayer capacitor of this example. 10 shows the impedance characteristics of a decoupling circuit consisting of 10 and a low-frequency capacitor. FIG. 6B is a diagram showing impedance characteristics in a decoupling circuit using a conventional multilayer capacitor in which a blank portion in which no conductor material exists is provided in the lead-out portion of the multilayer capacitor of this example. q represents the impedance characteristic of the conventional multilayer capacitor, and the characteristic curve r represents the impedance characteristic of the decoupling circuit composed of the conventional multilayer capacitor and the low frequency side capacitor.

  As can be seen from the results shown in FIGS. 6A and 6B, the impedance characteristic of the multilayer capacitor 10 of this example has a series resonance peak that is gentler than that of the conventional multilayer capacitor. In addition, the impedance characteristic in the decoupling circuit using this also shows that the parallel resonance peak formed by two capacitors is gently formed compared to the one using the conventional multilayer capacitor, and the peak is lower than 60 mΩ, Impedance can be lowered in a wide frequency band.

It is an external appearance perspective view which shows an example of embodiment of the multilayer capacitor of this invention. FIG. 2 is an exploded perspective view of the multilayer capacitor shown in FIG. 1. (A) And (b) is the top view which looked at the dielectric material layer in which the 1st internal electrode of the multilayer capacitor of FIG. 1 was formed, and the dielectric material layer in which the 2nd internal electrode was formed, respectively from the upper direction. (A) And (b) is the top view seen from the upper side which shows the other example of embodiment of the multilayer capacitor of this invention. (A) And (b) is the top view seen from the upper side which shows the further another example of embodiment of the multilayer capacitor of this invention. (A) The diagram which shows the impedance characteristic of the multilayer capacitor of this invention and the decoupling circuit which uses this, (b) is the diagram which shows the impedance characteristic of the conventional multilayer capacitor and the decoupling circuit which uses this.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Laminated body 2a ... Dielectric layer (protective layer)
2b Dielectric layer (effective layer)
DESCRIPTION OF SYMBOLS 3 ... 1st internal electrode 4 ... 2nd internal electrode 5 ... 1st extraction part 5a ... Blank part in which the conductor material in 1st extraction part does not exist 6 ... 2nd Lead portion 6a ... Blank portion where no conductor material exists in the second lead portion 7 ... First terminal electrode 8 ... Second terminal electrode
10 ... Multilayer capacitor

Claims (5)

A laminate formed by laminating a plurality of dielectric layers;
A plurality of first internal electrodes and second internal electrodes alternately disposed so as to be opposed to each other with the dielectric layer in between within the laminated body;
A plurality of first lead portions and second lead portions drawn from the first internal electrode and the second internal electrode to the side surface of the multilayer body at a plurality of positions, respectively;
A plurality of first terminal electrodes formed on the side surface of the laminate in the laminating direction and electrically connecting the first lead portions and the second lead portions positioned above and below the stack direction, respectively. And a multilayer capacitor comprising a second terminal electrode,
A multilayer capacitor in which at least one of the first lead portion and the second lead portion is provided with a blank portion in which no conductive material is present inside the lead direction.   The laminated body has a rectangular parallelepiped shape, and the first lead portion and the second lead portion drawn from the first internal electrode and the second internal electrode facing each other with the dielectric layer interposed therebetween are connected to each other. 2. The adjacent one of the first terminal electrode and the second terminal electrode that are adjacent to each other is disposed on the same side surface of the stacked body or on an adjacent side surface. Multilayer capacitor.   The multilayer capacitor according to claim 1, wherein the blank portion is provided in a central region in a drawing direction of the drawing portion.   The multilayer capacitor according to claim 1, wherein a plurality of the blank portions are provided in the lead-out portion.   2. The multilayer capacitor according to claim 1, wherein the first terminal electrodes and the second terminal electrodes are alternately arranged on a side surface of the multilayer body.

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