JP2010199269A - Capacitor and condenser module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor suitable for a decoupling circuit with low ESL and high ESR.
SOLUTION: A plurality of first internal electrodes and a plurality of second internal electrodes are alternately arranged inside a rectangular parallelepiped laminated body with a dielectric layer interposed therebetween, and the first internal electrode and the second internal electrode are arranged. Each of the electrodes is disposed in the inner edge of the laminate and is connected to the first external electrode or the second external electrode. The strip-shaped connection is formed from the end of the lead-out portion to the center of the dielectric layer. And a main capacitance part formed at a certain distance between the lead-out part and the connection part, and connected to the connection part at the center part of the dielectric layer, the connection part of the first internal electrode, The capacitor is opposed to the connection portion of the second internal electrode. Since the connection portion is formed on the first internal electrode and the second internal electrode, the current path becomes long, and the connection portions are arranged to face each other, so that a multilayer capacitor having low ESL and high ESR is obtained. Can do.
[Selection] Figure 2

Description

  The present invention relates to a multilayer capacitor used in an electronic circuit, and more particularly to a multilayer capacitor suitably used as a capacitor used in a decoupling circuit used for an IC chip operating at a high frequency.

  Conventionally, it has been necessary to connect a decoupling circuit between the IC chip and the power source to prevent intrusion of power source noise from the power source to the IC chip.

  The decoupling circuit is a circuit that removes fluctuations in current by flowing noise to the ground in a wide frequency band from a low frequency to a high frequency. Such a function can be obtained by using a capacitor having a characteristic of low impedance to ground in a wide frequency band. A decoupling circuit having such a function connects a plurality of capacitors having different self-resonance frequencies in parallel, and the frequency band in which the impedance near the self-resonance frequency of each capacitor is the lowest is a low frequency in a wide frequency band of interest. It is configured by arranging so as to be continuous from the side to the high frequency side. And as a capacitor | condenser employ | adopted corresponding to the high frequency side of a decoupling circuit, a multilayer capacitor is used suitably, for example.

  As a multilayer capacitor conventionally used for a decoupling circuit, for example, a rectangular parallelepiped laminate formed by laminating a plurality of rectangular dielectric layers, and a capacitor is formed by sandwiching the dielectric layers inside the laminate. A plurality of first internal electrodes and second internal electrodes arranged alternately so that the portions face each other, and formed on one end surface and the other end surface of the multilayer body in the stacking direction, respectively. A multilayer capacitor including a first external electrode and a second external electrode that electrically connect each other or each of the second internal electrodes is known (see, for example, Patent Document 1).

JP 2004-296940 A

  The conventional multilayer capacitor shortens the current path in order to reduce the equivalent series inductance (ESL), so the equivalent series resistance (ESR) is also low. Such a multilayer capacitor has a steep impedance characteristic that the impedance is extremely low near the self-resonance frequency and the impedance is extremely high near the anti-resonance frequency. When a plurality of such multilayer capacitors are used in the decoupling circuit, the impedance becomes extremely high at the anti-resonance frequency. As a result, in such a frequency band, there is a problem that noise cannot flow to the ground near the anti-resonance frequency.

  In order to solve this problem, it is necessary to obtain a flat impedance characteristic by reducing the level difference between the resonance frequency and the anti-resonance frequency in the portion where the impedance characteristic is combined. For this purpose, the ESR of the capacitor is increased. Measures were taken.

  On the other hand, ESL is a value that determines the self-resonance frequency, and as the ESL increases, the self-resonance frequency decreases. Further, it does not function as a capacitor in a frequency range higher than the self-resonant frequency. Therefore, by reducing the ESL value, the self-resonance frequency can be increased, and it is necessary to lower the ESL in order to function as a capacitor up to a higher frequency range.

  For this reason, the capacitor used in the decoupling circuit must be kept so that the ESR does not become too low. However, if the current path is lengthened to increase the ESR, there is a problem that the ESL becomes high. For example, in the conventional multilayer capacitor described above, if the distance between the first external electrode and the second external electrode is increased and the path of the current flowing through the first internal electrode and the second internal electrode is increased, the ESR is increased. However, there was a problem that the ESL was high.

  The present invention has been devised in view of the problems in the conventional multilayer capacitor as described above, and an object thereof is to provide a multilayer capacitor having a low ESL and a high ESR.

  The capacitor of the present invention is formed in a laminated body formed by laminating a plurality of rectangular dielectric layers, and is formed on a pair of opposed outer surfaces of the laminated body alternately with the dielectric layer interposed therebetween. A first internal electrode electrically connected to one external electrode and a second internal electrode electrically connected to a second external electrode formed on a pair of opposing outer surfaces different from the pair of outer surfaces Each of which is a plurality of capacitors facing each other, wherein each of the first internal electrode and the second internal electrode is disposed at an inner edge of the multilayer body, and the first external electrode or the second external electrode The connected strip-shaped lead-out portion, the strip-shaped connection portion formed from the end of the lead-out portion to the center portion of the dielectric layer, and the connection portion at the center portion of the dielectric layer, and the lead-out portion And constant between the connecting part And a main capacitor portion formed at a distance, and a connecting portion of the second internal electrode and the connecting portion of the first internal electrode is characterized in that it is opposed.

  In the capacitor module of the present invention, a plurality of the capacitors are arranged in a plane, and a plurality of first terminal electrodes and second terminal electrodes made of an annular metal are arranged in a plane between the capacitors. The first derivation portions are electrically connected to each other by the first terminal electrode, and the second derivation portions are electrically connected to each other by the second terminal electrode.

  According to the capacitor of the present invention, since the above configuration is provided, if a current enters from the first external electrode, the current passes through the strip-shaped lead-out portion and the strip-shaped connection portion of the first internal electrode, and the first It flows to the center of the internal electrode, and further flows from the center of the second internal electrode through the dielectric layer to the second external electrode through the strip-shaped connection portion and strip-shaped lead-out portion of the second internal electrode. The above-described current path is long because the band-like connection portion is formed on the first internal electrode and the second internal electrode. Moreover, since the connection part is formed in strip | belt shape, the cross-sectional area is small. Therefore, the capacitor according to the present invention can increase the ESR by forming the band-shaped connecting portion in the first internal electrode and the second internal electrode. Further, the band-shaped connecting portion of the first internal electrode and the band-shaped connecting portion of the second internal electrode are opposed to each other through the dielectric layer, and are overlapped with each other in the stacking direction. Since the direction of the current flowing through the band-shaped connection portion and the direction of the current flowing through the band-shaped connection portion of the second internal electrode are reversed, the inductance generated at the connection portion of the first internal electrode and the second internal electrode Since the inductance generated at the connection portion cancels out, an increase in ESL can be suppressed. Therefore, it is possible to provide a multilayer capacitor having a low ESL and a high ESR by increasing the ESR without increasing the ESL. By using a plurality of such capacitors, the impedance at the anti-resonance frequency formed by capacitors with close self-resonance frequencies can be kept low while keeping the overall impedance low, making it easy to flow noise to the ground. can do.

  According to the capacitor module of the present invention, a plurality of the above capacitors are arranged in a plane, and a plurality of first terminal electrodes and second terminal electrodes made of a ring metal are arranged in a plane between the capacitors. When the first external electrodes are electrically connected by the first terminal electrodes and the second external electrodes are electrically connected by the second terminal electrodes, the IC chip decoupling circuit is used. Since the solder bump for the power terminal of the IC chip can be disposed inside the annular first terminal electrode and the second terminal electrode, the capacitor constituting the capacitor module is used as a part of the decoupling circuit. As a result, the wiring length becomes the shortest and the ESL can be reduced, and the effective frequency region can be shifted to the high frequency side. Further, since it can be mounted under the IC chip, the entire mounting area can be reduced.

  Since the small capacitors that fit between the solder bumps for the power supply terminals of the IC chip are connected by the first terminal electrode and the second terminal electrode made of an annular metal and integrated in a plane, the capacitor module is connected to the power supply terminal. Even if the solder bumps are made as thin as possible, bending stress due to impact during the transportation in the manufacturing process or mounting after the manufacturing is relieved by the bending of the metal part, so it is easy for the bending force A certain strength that does not break can be obtained.

(A) is an external appearance perspective view which shows an example of embodiment of the capacitor | condenser of this invention, (b) is the sectional view on the AA line of the capacitor | condenser of (a). (A) is a plan view of the dielectric layer 7 on which the first internal electrode 5 of the capacitor shown in FIG. 1 is formed as viewed from above, and (b) is the formation of the second internal electrode 6 of the capacitor shown in FIG. It is the top view which looked at the made dielectric material layer 7 from upper direction. (A) is another example of the top view which looked at the dielectric layer 7 in which the 1st internal electrode 5 of the capacitor | condenser shown in FIG. 1 was formed from upper direction, (b) is the 2nd inside of the capacitor | condenser shown in FIG. It is another example of the top view which looked at the dielectric material layer 7 in which the electrode 6 was formed from upper direction. (A) is the external appearance perspective view which shows the example of embodiment of the capacitor module of this invention, (b) is the top view which looked at the example of embodiment of the capacitor module of this invention from the upper direction. FIG. 5 is an enlarged view of the first terminal electrode 21 or the second terminal electrode 22 shown in FIG. 4. (A) is sectional drawing before mounting of the example of embodiment of the capacitor module of this invention, (b) is sectional drawing at the time of mounting of the example of embodiment of the capacitor module of this invention. It is a diagram which shows the impedance characteristic of a decoupling circuit.

  Hereinafter, the capacitor and the capacitor module of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1A is an external perspective view showing an example of an embodiment of the capacitor of the present invention, and FIG. 1B is a cross-sectional view taken along line AA of the capacitor 1 shown in FIG. 2 (a) and 2 (b) show the dielectric layer 7 formed with the first internal electrode 5 and the dielectric layer 7 formed with the second internal electrode 6 of the capacitor 1 shown in FIG. FIG. FIG. 3A is a plan view showing another example of the embodiment of the first internal electrode 5, and FIG. 3B is a plan view showing another example of the embodiment of the second internal electrode 6. is there. In FIG. 3, the same parts as those in FIG. FIG. 4A is an external perspective view showing an example of the embodiment of the capacitor module of the present invention, and FIG. 4B is a plan view of the example of the embodiment of the capacitor module of the present invention as viewed from above. is there. FIG. 5 is an enlarged view of the first terminal electrode 21 or the second terminal electrode 22 shown in FIG. 6A is a cross-sectional view before mounting the example of the capacitor module according to the embodiment of the present invention, and FIG. 6B is a cross-sectional view when mounting the example of the capacitor module according to the embodiment of the present invention. is there. In these figures, 1 is a capacitor, 2 is a first external electrode, 3 is a second external electrode, 4 is a laminate, 5 is a first internal electrode, 6 is a second internal electrode, 7 is a dielectric layer, and 10 is a dielectric layer. Capacitor module, 11 is a first derivation unit, 12 is a second derivation unit, 13 is a first connection unit, 14 is a second connection unit, 15 is a first main capacitance unit, 16 is a second main capacitance unit, and 21 is a first 1 terminal electrode, 22 is a 2nd terminal electrode, 23 is a through-hole, 24 is an IC chip, 25 is a solder bump for power terminals, and 26 is a mounting substrate.

  Capacitors 1 shown in FIGS. 1A and 1B are alternately arranged in a multilayer body 4 formed by laminating a plurality of dielectric layers 7 so as to face each other with the dielectric layer 7 interposed therebetween. In addition, a plurality of first internal electrodes 5 and second internal electrodes 6 are formed.

  Further, the first external electrode 2 is formed on a pair of opposing side surfaces of the four side surfaces of the rectangular parallelepiped capacitor 1, and the second external electrode 3 is formed on a pair of side surfaces where the first external electrode 2 is not formed. ing.

  The stacked body 4 is formed by stacking, for example, 50 to 1000 layers of a plurality of rectangular dielectric layers 7. In FIG. 1B, the number of stacked layers 4 is not shown in order to simplify the description.

  The dielectric layer 7 has a thickness of 1 μm to 5 μm per layer and is formed in a square shape when viewed from above. As a material for forming the dielectric layer 7, for example, a dielectric material mainly composed of ceramics having a relatively high relative dielectric constant such as barium titanate, calcium titanate, strontium titanate, or the like is used.

  The first external electrode 2 is formed by connecting a plurality of first internal electrodes 5, and the second external electrode 3 is formed by being connected in the stacking direction by connecting a plurality of second internal electrodes 6. . As the material of the first external electrode 2 and the second external electrode 3, for example, a conductor material mainly composed of a metal such as nickel, copper, silver, or palladium is used, and the laminated body 1 has a thickness of 2 μm to 20 μm. It is attached. The external electrode connected to such an internal electrode is electrically connected to an external electric circuit, whereby a current flows in the capacitor.

  The first internal electrode 5 and the second internal electrode 6 shown in FIGS. 2A and 2B have dielectric edges other than the first lead-out portion 11 and the second lead-out portion 12 in order to maintain insulation from the outside. It is located slightly inside the periphery of the body layer 7 and is formed to a thickness of 0.5 μm to 2 μm. As the material, for example, a conductor material containing a metal such as nickel, copper, nickel-copper, silver-palladium as a main component is used.

  The first internal electrode 5 shown in FIG. 2A is formed along the pair of opposing sides of the dielectric layer 7 at the inner edge between the dielectric layers 7 of the multilayer body 4, A strip-shaped first lead portion 11 electrically connected to the electrode 2, a strip-shaped first connection portion 13 formed from both ends of the first lead portion 11 to the center of the dielectric layer 7, In addition to being connected to the first connecting portion 13 in the central portion, a main capacity portion 15 formed with a certain distance between the first lead-out portion 11 and the first connecting portion 13 is provided.

  The second internal electrode 6 shown in FIG. 2B is formed along a pair of opposing sides of the dielectric layer 7 at the inner edge between the dielectric layers 7 of the multilayer body 4, and the second external electrode 3. A strip-shaped second lead-out portion 12 electrically connected to the strip, a strip-shaped second connection portion 14 formed from the end of the second lead-out portion 12 to the central portion of the dielectric layer 7, and the central portion of the dielectric layer 7 And the main connection portion 15 formed at a certain distance between the second lead-out portion 12 and the second connection portion 14.

  The first internal electrode 5 is electrically connected to the first external electrode 2 formed on a pair of opposed outer surfaces of the multilayer body 4 by the first lead-out portion 11, and the second internal electrode 6 is connected to the first external electrode. The second external electrode 3 formed on a pair of opposing outer surfaces different from the outer surface on which the electrode 2 is formed is electrically connected to the second lead-out portion 12.

  The widths of the first lead-out part 11 and the second lead-out part 12 are 20 μm to 40 μm, the widths of the first connection part 13 and the second connection part 14 are 20 μm to 40 μm, and the first lead-out part 11 and the first connection part 13 The interval between the main capacitor portion 15 and the interval between the second lead-out portion 12 and the second connecting portion 14 and the main capacitor portion 15 are 20 μm to 40 μm.

  The capacitor generally obtains a capacitance between the opposed internal electrodes. In the capacitor 1 of this example, the first main capacitance portion 15 of the first internal electrode 5 and the second internal electrode are mainly used. Capacitance can be obtained in a region facing the sixth second main capacitor portion 16.

  The first lead-out part 11 is a part for leading the first internal electrode 5 to the side surface of the multilayer body 4, and is a part for connecting to the first external electrode 2. The second lead-out part 12 is a part for leading the second internal electrode 6 to the side surface of the multilayer body 4 and is a part for connecting to the second external electrode 3.

  In such a capacitor 1 of this example, if current flows from the first external electrode 2, the current passes through the first lead-out portion 11 and the strip-shaped first connection portion 13 of the first internal electrode 5, and the first 1 flows to the center of the internal electrode 5 and further passes through the dielectric layer 7 from the center of the second internal electrode 6 through the second connection portion 14 and the second lead-out portion 12 of the second internal electrode 6 to the second external portion. It flows to the electrode 3. The above-described current path is long because the band-like first connection portion 13 and second connection portion 14 are formed in the middle. Moreover, since the 1st connection part 13 and the 2nd connection part 14 are formed in strip | belt shape, the cross-sectional area is small. Therefore, by forming the first connection portion 13 and the second connection portion 14, the capacitor 1 of this example can increase the ESR. Further, in the capacitor 1 of this example, the strip-shaped first connection portion 13 of the first internal electrode 5 and the strip-shaped second connection portion 14 of the second internal electrode 6 are opposed to each other with the dielectric layer 7 interposed therebetween. And the direction of the current flowing through the band-shaped first connection portion 13 of the first internal electrode 5 and the direction of the current flowing through the band-shaped second connection portion 14 of the second internal electrode 6. Is reversed, the inductance generated at the first connecting portion 13 and the inductance generated at the second connecting portion 14 cancel each other, so that an increase in ESL can be suppressed. Therefore, a multilayer capacitor having a low ESL and a high ESR can be obtained by increasing the ESR to a desired value without increasing the ESL. By using a plurality of capacitors 1 of this example, the impedance at the anti-resonance frequency formed by capacitors having close self-resonance frequencies can be kept low while keeping the overall impedance low, so noise can be reduced. It can be made easy to flow to the ground.

  The capacitor 1 shown in FIGS. 1A and 1B, FIGS. 2A and 2B, and FIGS. 4A and 4B is manufactured by, for example, the following method.

  If the dielectric layer 7 is made of a dielectric material mainly composed of barium titanate, an appropriate organic solvent, glass frit, organic binder, etc. are added to and mixed with the barium titanate powder to produce a slurry ceramic. The ceramic slurry is formed to a predetermined thickness by a doctor blade method or the like, and a ceramic green sheet is produced.

  Next, the ceramic green sheet is divided into a plurality of predetermined shapes, and for example, an appropriate organic solvent, glass frit, organic binder or the like is added to and mixed with one main surface of each ceramic green sheet. The conductor paste is printed and applied in a predetermined pattern by a screen printing method or the like.

  By laminating a predetermined number of the obtained ceramic green sheets and press-bonding, a laminated sheet composed of a plurality of ceramic green sheets is formed, and this is cut and separated into individual green laminated bodies corresponding to individual capacitors 1 To do.

  By firing this cut and separated individual green laminate at a temperature of 1100 ° C. to 1400 ° C., for example, a laminate 4 in which a plurality of dielectric layers 7 are laminated can be obtained.

  In the example shown in FIGS. 3A and 3B, the first internal electrode 5 is a belt-like first connection portion 13 formed from one end of the belt-like first lead-out portion 11 to the central portion of the dielectric layer 7. And a main capacitor portion 15, and the second internal electrode 6 is a strip-shaped second connection portion 14 formed from one end of the strip-shaped second lead-out portion 12 to the central portion of the dielectric layer 7, The main capacity unit 15 is provided.

  In the capacitor using the internal electrode of the example shown in FIGS. 3A and 3B, one end of the two ends of the first derivation unit 11 and the first connection unit 13 are connected, and the second derivation is performed. Since one end of the two ends of the portion 12 and the second connection portion 14 are connected, the first connection portion 13 and the second connection are compared with the case where the connection portion is formed from both ends of the lead-out portion. By reducing the number of the portions 14, it is possible to easily narrow the width and further reduce the cross-sectional area of the current path, which is effective for further increasing the ESR.

  The capacitor module 10 shown in FIGS. 4A and 4B is configured by a plurality of capacitors 1, a plurality of first terminal electrodes 21 and a plurality of second terminal electrodes 22.

  In the capacitor module 10 of this example, when arranged in a plane, a plurality of capacitors 1 and a plurality of first terminal electrodes 21 are alternately arranged in contact with each other in the front-rear direction or the left-right direction. A plurality of second terminal electrodes 22 and a plurality of capacitors 1 are alternately disposed in contact with each other in the direction of a pair of surfaces where the first terminal electrodes 21 are not disposed. In addition, one, two, or four external electrodes of the capacitor 1 are disposed in contact with each first terminal electrode 21, and one, two, or four external electrodes are disposed on each second terminal electrode 22. The external electrodes of the capacitor 1 are arranged in contact with each other. The plurality of first terminal electrodes 21 and the plurality of second terminal electrodes 22 used here are metals formed in an annular shape.

  In the capacitor module 10 of this example, a conductive paste in which a conductive powder mainly composed of a metal such as copper is dispersed in a vehicle is applied to the four side surfaces of the multilayer body 4 of the rectangular parallelepiped capacitor 1. The first external electrode 2 and the second external electrode 3 formed by baking are formed, and the first external electrode 2 is formed on each of the pair of side surfaces where the first lead-out portion 11 of the first internal electrode 5 is formed. Then, the second external electrode 3 is formed on each of the other pair of opposite side surfaces that are connected to the first derivation unit 11 and formed with the second derivation unit 12 of the second internal electrode 6, and the second derivation unit 12. Is connected to. In the capacitor module 10 of this example, the first terminal electrode 21 shown in FIGS. 4A and 4B is electrically connected to the first lead-out portion 11 of the first internal electrode 5 through the first external electrode 2. Since the second terminal electrode 22 is electrically connected to the second lead-out portion 12 of the second internal electrode 6 through the second external electrode 3, the capacitor 1, the first connection portion 13, and the second The connection with the connection portion 14 is via the first external electrode 2 or the second external electrode 3 baked on the laminate 4. Therefore, the connection between the capacitor 1 and the first terminal electrode 21 and the second terminal electrode 22 is strong.

  Next, FIG. 5 is an enlarged view of the first terminal electrode 21 or the second terminal electrode 22 shown in FIG. The first terminal electrode 21 and the second terminal electrode 22 have through-holes 23 having an inner diameter enough to allow solder bumps to be disposed therein, and are formed of a conductive material mainly composed of a metal such as nickel or copper. Is.

  The first terminal electrode 21 and the second terminal electrode 22 shown in FIG. 5 are made of, for example, a metal tube having a thickness of 0.1 mm and an inner diameter of 0.7 mm made of a conductive material mainly composed of a metal such as nickel or copper. It is formed by cutting to a length of mm.

  Further, the through holes 23 of the first terminal electrode 21 and the second terminal electrode 22 are opened in the same direction as the main surface of the capacitor 1.

  In the capacitor module 10 configured as described above, when a predetermined voltage is applied between the first terminal electrode 21 and the second terminal electrode 22, the capacitor module 10 is interposed between the first internal electrode 5 and the second internal electrode 6. Charges corresponding to the capacitance set by the dielectric constant, thickness, opposing area and number of layers of the dielectric layer 7 located in the are accumulated.

  The capacitor module 10 described above is preferably used in a decoupling circuit as a decoupling capacitor. The decoupling circuit is connected to a power supply circuit that supplies power to an IC chip such as a microprocessing unit (MPU). By bringing the reactance between the power supply line and the ground close to 0, an alternating current component is caused to flow to the ground. It plays the role of removing noise and radiated electromagnetic noise (EMI noise).

  Next, FIG. 6A is a sectional view before the capacitor module 10 of the first example of the embodiment of the present invention is connected to the IC chip, and FIG. 6B is a diagram of the embodiment of the present invention. It is sectional drawing when the capacitor module 10 of a 1st example is connected with IC chip. Note that the capacitor module 10 shown in FIGS. 6A and 6B shows a cross section of the capacitor 1 and the first terminal electrode 21 in an array.

  In this case, the capacitor module 10 is transported by, for example, using a mounting device by lifting a suction nozzle against the upper side of the capacitor 1 and placing it on the mounting substrate 26. Thereafter, the IC chip 24 is placed on the mounting substrate 26 so that the power terminal solder bumps 25 are disposed in the through holes 23 of the first terminal electrode 21, and reflow soldering is performed. The power terminal solder bump 25 is melted and adhered to the inner wall of the through hole 23 of the first terminal electrode 21, and the mounting substrate 26 and the power terminal solder bump 25 of the IC chip 24 are connected. Although not shown, the second terminal electrode 22 is connected in the same procedure as that for the first terminal electrode 21.

  In the capacitor module 10 of this example, when the capacitor 1 and the first terminal electrode 21 and the second terminal electrode 22 are arranged in a plane, they are arranged alternately in the front-rear direction and the left-right direction. Since the capacitors 1 are arranged so as to be continuous in an oblique direction and the capacitors 1 can be mounted between the terminal electrodes of the IC chip 24 with high density, the capacitor module is arranged in a space that is not normally used between the terminal electrodes of the IC chip 24. Can be used effectively.

  Further, in the conventional decoupling circuit, there is an inductance in the wiring connecting the capacitor module and the power supply terminal of the IC chip, and since this inductance component increases in proportion to the wiring length, the wiring is shortened. There is a need for such a structure.

  In this regard, according to the capacitor module 10 of the first example of the embodiment of the present invention, the power terminal solder bumps 25 of the IC chip 24 are formed inside the annular first terminal electrode 21 and second terminal electrode 22. Since the capacitor 1 constituting the capacitor module 10 is arranged between the power terminal solder bumps 25 of the IC chip 24 as a part of the decoupling circuit, the wiring length is minimized, and the low ESL is achieved. Can be achieved.

  Since the small capacitors 1 placed between the power terminal solder bumps 25 of the IC chip 24 are connected by the first terminal electrode 21 and the second terminal electrode 22 made of an annular metal and integrated in a plane, Even if the capacitor 1 is made as thin as the height of the solder bumps 25 for the power supply terminals, the bending stress due to the shock during transportation in the manufacturing process and mounting after manufacturing is alleviated by bending of the metal part. It is possible to obtain a certain strength that does not easily break against force.

  Further, when the first lead-out portion 11 is formed on a pair of opposite side surfaces of the capacitor 1 and the second lead-out portion 12 is formed on another pair of opposite side surfaces different from the pair of side surfaces, a plurality of first leads The terminal electrode 21 and the plurality of second terminal electrodes 22 are alternately arranged in a plane in the vertical and horizontal directions, and the capacitor 1 is arranged at a position surrounded by the first terminal electrode 21 and the second terminal electrode 22 adjacent to each other at the shortest distance. As a result, the distance between the first terminal electrode 21 and the second terminal electrode 22 can be made narrower than that of one capacitor 1, so that the arrangement density of the power terminal solder bumps 25 can be reduced. It can be suitably used for a decoupling circuit.

  The capacitor module 10 shown in FIG. 4A is manufactured by integrating the capacitor 1 shown in FIG. 1 with the first terminal electrode 21 and the second terminal electrode 22 shown in FIG. 5 by the following method, for example. Is done.

  First, an insulator jig is prepared in which a protrusion with a diameter of 0.5 mm, for example, is formed in the same arrangement size as the arrangement of the solder bumps 25 for the power supply terminal of the IC chip 24. The same number of first terminal electrodes 21 and second terminal electrodes 22 as the solder bumps 25 for terminals are inserted and arranged, and the capacitor 1 is arranged between the first terminal electrodes 21 and the second terminal electrodes 22, and all of them. Is immersed in the plating solution, the first terminal electrode 21 is provided in the first lead-out portion 11 of the first internal electrode 5 of the capacitor 1, and the second terminal electrode 22 is provided in the second lead-out portion 12 of the second internal electrode 6 of the capacitor 1. The capacitor module 10 is manufactured by bonding and integrating them with a plating film. As a metal component used for the plating solution, for example, copper, nickel or the like is used.

  Also, in the conventional capacitor module, when the specification change of the number of solder bumps for power supply terminals of the IC chip to be used occurs, it takes time to change the design and manufacture of the capacitor module, and it is not possible to respond quickly to customer requirements However, according to the capacitor module 10 of the present invention, the number of solder bumps 25 for the power supply terminals of the IC chip 24 can be individually specified by combining the capacitor 1 with the first terminal electrode 21 and the second terminal electrode 22. Because it can respond, it can respond quickly to changes in customer specifications.

  The present invention is not limited to the embodiments described above, and various changes and improvements can be made without departing from the scope of the present invention.

  For example, in the example of the embodiment described above, the dielectric layer 7 forming the capacitor 1 has a rectangular shape as viewed from above, but the dielectric layer 7 has rounded corners of the square shape. It is also possible to use a banded one. When the corner of the dielectric layer 7 is rounded, chipping and cracking at the corner can be prevented.

  In the example of the above-described embodiment, the first terminal electrode 21 and the second terminal electrode 22 of the capacitor module 10 are made of metal formed in an annular shape with no corners. It is also possible to use a prismatic metal having a shape in which a through hole is provided between main surfaces as the first terminal electrode and the second terminal electrode. In this case, since the outer peripheral surfaces of the first terminal electrode and the second terminal electrode are formed of a plurality of planes, the capacitor 1 can be easily joined to the first terminal electrode and the second terminal electrode.

  Examples of the capacitor module of the present invention will be described.

  Here, the laminated body 4 is made of a ferroelectric ceramic mainly composed of barium titanate, and 50 dielectric layers 7 having a thickness of 3 μm are laminated, and the thickness is made of a conductive material mainly composed of nickel. The first internal electrodes 5 and the second internal electrodes 6 of 3 μm are alternately arranged so as to face each other with the dielectric layer 7 of the multilayer body 4 interposed therebetween. The first lead-out portion 11 of the first internal electrode 5 is a capacitor Formed on one pair of opposing side surfaces, the second lead-out portion 12 of the second internal electrode 6 is formed on another pair of opposing side surfaces different from the pair of side surfaces on which the first lead-out portion 11 is formed, The external electrodes 5 and 6 mainly composed of copper are baked on the side surface so as to be connected to the first lead-out portion 11 or the second lead-out portion 12 on each side surface, and both the vertical and horizontal outer dimensions are 1.0 mm and the thickness is 0.5. Four rectangular parallelepiped capacitors 1 were manufactured.

  The first internal electrode 5 is formed along a pair of opposing sides of the dielectric 7 of the multilayer body 4, is electrically connected to the first external electrode 2, and has a strip-shaped first lead-out portion 11 having a width of 30 μm. And a strip-shaped first connecting portion 13 having a width of 30 μm and connected to the first connecting portion 13 at the central portion of the dielectric layer 7. In addition, a main capacitor portion 15 formed with a distance of 30 μm between the first lead-out portion 11 and the first connection portion 13 is provided.

  The second internal electrode 6 is formed along a pair of opposing sides of the dielectric layer 7 of the multilayer body 4, is electrically connected to the second external electrode 3, and has a width of 30 μm. The lead-out part 12 is formed from the end of the second lead-out part 12 to the central part of the dielectric layer 7 and has a band-shaped second connection part 14 having a width of 30 μm, and the second connection part at the central part of the dielectric layer 7 14 and a main capacitor portion 15 formed at a distance of 30 μm between the second lead-out portion 12 and the second connection portion 14.

  The first terminal electrode 21 and the second terminal electrode 22 connected to the capacitor 1 are formed by cutting a cylindrical metal having a thickness of 0.1 mm and an inner diameter of 0.7 mm into a length of 0.5 mm, which is mainly composed of nickel. It was manufactured by doing.

  Next, the capacitor 1 is placed on the protruding portion of the insulator jig in which the protruding portion having a diameter of 0.5 mm is formed at the position corresponding to the solder bump 25 for the power supply terminal of the IC chip 24, and the first terminal electrode 21 and the second terminal. The electrodes 22 were arranged so as to fit. The plurality of first terminal electrodes 21 and second terminal electrodes 22 arranged between the capacitors 1 were arranged so as to be connected to the same external electrode of the capacitor 1. Then, the capacitor 1, the first terminal electrode 21 and the second terminal electrode 22 arranged in the insulator jig are immersed in a plating tank filled with an electroless plating solution using copper as a metal component, and the first external The electrode 2 and the first terminal electrode 21, and the second external electrode 3 and the second terminal electrode 22 are bonded to each other by applying electroless plating to the first internal electrode of the capacitor 1 by the formed plating film. The first lead-out part 11 and the first terminal electrode 21 are electrically connected to each other, and the second lead-out part 12 and the second terminal electrode 22 of the second internal electrode 6 of the capacitor 1 are electrically connected to each other. A capacitor module 10 was manufactured.

  As a test for evaluating the capacitor module 10 of the present invention manufactured by the above method, the IC chip 24 is mounted on the mounting substrate 26 by lifting the capacitor 1 by placing the suction nozzle on the upper side of the capacitor 1 and solder bumps for the power supply terminals. 25 is placed in the through hole 23 of the first terminal electrode 21 and the second terminal electrode 22 of the capacitor module 10, and reflow soldering is performed to melt the power terminal solder bump 25. The solder is adhered to the inner walls of the through holes 23 of the first terminal electrode 21 and the second terminal electrode 22, and the power terminal solder bumps 25 of the IC chip 24 are connected to the mounting substrate 26, thereby realizing an embodiment of the present invention. The capacitor module 10 was mounted on the mounting board 26. As a result, no damage such as chipping or cracking occurred in the capacitor module 10 during transportation or mounting during mounting.

  Further, as a comparative example, the first internal electrode and the second internal electrode with the same material and the same size as the capacitor 1 of the conventional capacitor module, that is, the capacitor module 10 of the embodiment, are sandwiched between the dielectric layers of the laminate. The first lead-out portion of the first internal electrode is formed on a pair of opposing side surfaces of the capacitor, and the second lead-out portion of the second internal electrode is formed as the first lead-out portion. In order to maintain insulation from the outside formed on a pair of opposing side surfaces different from the pair of side surfaces, the peripheral edge excluding the first lead portion of the first internal electrode and the second lead portion of the second internal electrode The external electrode mainly composed of copper is formed on the side surface so that the outer periphery is located slightly inside the peripheral edge of the dielectric layer 9 and is connected to the first lead-out portion or the second lead-out portion on each side surface. After baking, the vertical and horizontal external dimensions are both Four rectangular parallelepiped capacitors having a thickness of 1.0 mm and a thickness of 0.5 mm are manufactured, the first lead-out portion of the first internal electrode of the capacitor and the first terminal electrode are electrically connected, and the second internal electrode of the capacitor The capacitor module was manufactured by electrically connecting the second lead-out part and the second terminal electrode.

  FIG. 7 shows the results of measuring impedance characteristics of the capacitor module 10 which is an example of the present invention and the capacitor module of the comparative example. FIG. 7 is a diagram showing the impedance characteristics of the decoupling circuit, where the horizontal axis indicates frequency (unit: MHz) and the vertical axis indicates signal attenuation (unit: dB). Here, the impedance was measured in a frequency band of 1 to 10000 [MHz]. 7 indicates the attenuation characteristic of the decoupling circuit using the capacitor module 10 according to the embodiment of the present invention, and the dotted characteristic curve B in FIG. 7 indicates the conventional capacitor module of the comparative example. The attenuation characteristic of the decoupling circuit used is shown.

  As shown in FIG. 7, the decoupling circuit using the capacitor module 10 of the present invention as an embodiment does not have an extremely low impedance portion and has a flat portion where the characteristic curve is minimized. On the higher frequency side than the frequency at which the attenuation amount of the module is the maximum value, the measurement result of the capacitor module 10 of the present invention has a portion with a higher attenuation amount and a lower impedance.

  From the above results, according to the capacitor 1 of the present invention, the current path inside the capacitor 1 is long, and the current flows in the first connection portion 13 and the second connection portion 14 in opposite directions. As a result, the ESR of the decoupling circuit can be increased and the ESL can be prevented. As a result, there is no portion where the impedance is extremely low, and there is a flat portion where the characteristic curve is minimized. It could be confirmed. Further, since the bending stress due to the impact during transportation during the mounting is relieved by the bending of the first terminal electrode 21 and the second terminal electrode 22 which are metal parts, the bending stress is not easily destroyed by the bending force. It was also confirmed that the strength could be obtained.

DESCRIPTION OF SYMBOLS 1,100 ... Capacitor 2 ... 1st external electrode 3 ... 2nd external electrode 4 ... Laminated body 5 ... 1st internal electrode 6 ... 2nd internal electrode 7 ... Dielectric Body layer
10 ... Capacitor module
11 ... 1st deriving part
12 ... 2nd derivation part
13 ... 1st connection part
14 ... 2nd connection part
15 ... 1st main capacity section
16 ... Second main capacity section
21 ... 1st terminal electrode
22 ... Second terminal electrode
23 ... Through hole
24 ・ ・ ・ IC chip
25 ... Solder bumps for power terminals
26 ・ ・ ・ Mounting board

Claims (2)

Electrically connected to the first external electrodes formed on a pair of opposed outer surfaces of the multilayer body alternately inside the multilayer body formed by laminating a plurality of rectangular dielectric layers with the dielectric layer interposed therebetween A plurality of second internal electrodes electrically connected to the first internal electrodes connected to the second external electrodes formed on a pair of opposite external surfaces different from the pair of external surfaces. A placed capacitor,
The first internal electrode and the second internal electrode are disposed at the inner edge of the laminate and connected to the first external electrode or the second external electrode, respectively, and from the end of the lead The strip-shaped connection portion formed over the center portion of the dielectric layer and the connection portion at the center portion of the dielectric layer are connected to the connection portion, and a certain distance is provided between the lead-out portion and the connection portion. A capacitor having a formed main capacitance portion, wherein the connection portion of the first internal electrode and the connection portion of the second internal electrode are opposed to each other.   A plurality of capacitors according to claim 1 are arranged in a plane, and a plurality of first terminal electrodes and second terminal electrodes made of an annular metal are arranged in a plane between the capacitors, and the first A capacitor module, wherein the first lead portions are electrically connected to each other by a terminal electrode, and the second lead portions are electrically connected to each other by the second terminal electrode.

Images