JP2009054974A - Multilayer capacitor and capacitor mounting board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer capacitor which can be made high in equivalent series resistance (ESR) without varying equivalent series inductance (ESL) so much, and a capacitor mounting substrate. <P>SOLUTION: Insulating layers 11 and 12 are formed on surfaces of terminal electrodes 7 and 8 respectively to cover exposed surface center portions of first and second lead-out portions 5 and 6 disposed one over the other in a laminating direction (x) with the terminal electrodes 7 and 8 interposed therebetween, so when a plurality of such multilayer capacitors 10 are mounted on a surface of a substrate 13 by using a solder, a current path becomes two narrow paths between the first lead-out portion 5 and second lead-out portion 6, and an electrode pattern 15 of the substrate 13 and can be made long in length by varying the thickness (t) of the insulating layers 11 and 12 and then increasing the height of the solder, and the equivalent series resistance (ESR) can be made high without varying the equivalent series inductance (ESL) so much. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer capacitor and a capacitor mounting board, and more particularly to a multilayer capacitor and a capacitor mounting board that are suitably used in a decoupling circuit for supplying power to an IC.

  Conventionally, a multilayer capacitor has been suitably used in a decoupling circuit connected in parallel between an IC and a power source. Such a multilayer capacitor can be used to power an IC during a power shortage state immediately after switching in switching in the IC. Supply.

  As a conventional multilayer capacitor, a plurality of first internal electrodes and second internal electrodes alternately arranged so as to be opposed to each other with a dielectric layer sandwiched inside a multilayer body formed by laminating a plurality of dielectric layers A plurality of first lead portions and second lead portions are led out from the electrodes to the side surface of the laminate at a plurality of locations, respectively, and the first lead portions and the second lead portions positioned vertically in the stacking direction are electrically connected to each other. It is known that the first terminal electrode and the second terminal electrode are formed on the side surface of the laminate in the lamination direction while being connected in a connected manner (see, for example, Patent Document 1).

In the above conventional multilayer capacitor, the equivalent series inductance is reduced by forming a plurality of lead portions drawn from the internal electrode and shortening the path of the flowing current. Therefore, the minimum peak of impedance formed by series resonance is on the high frequency side. Formed. A capacitor having a functional band near the peak of the series resonance formed in this way is, for example, a high frequency side in a decoupling circuit configured such that a plurality of capacitors having different functional band frequencies are combined to reduce impedance in a wide band. It is used as a capacitor corresponding to the functional band.
Special table 2002-508114 gazette

  However, the above-described conventional multilayer capacitor has a steep peak of series resonance in the functional band, and if this steepness is high, it is in parallel with a capacitor having a functional band corresponding to a close frequency band. The maximum peak of impedance formed by resonance becomes steep. For this reason, the decoupling circuit configured using the conventional multilayer capacitor has a problem that a frequency band in which the impedance is larger than the standard value is generated in part. In other words, even if the conventional multilayer capacitor has a low-impedance functional band on the high frequency side, the impedance characteristics of the decoupling circuit can be reduced to a certain frequency when the peak of the resonance point is sharply formed. There was a problem that it was greatly degraded in the band.

  Therefore, in recent years, as a multilayer capacitor, it is required to increase the equivalent series resistance (ESR) without changing the equivalent series inductance (ESL), but there is still a problem that the impedance is low.

  An object of the present invention is to provide a multilayer capacitor and a capacitor mounting board that can increase the equivalent series resistance (ESR) without significantly changing the equivalent series inductance (ESL).

The multilayer capacitor of the present invention includes a multilayer body formed by laminating a plurality of dielectric layers,
A plurality of first internal electrodes and second internal electrodes alternately arranged so as to face each other across the dielectric layer in the laminated body;
A first lead portion and a second lead portion each drawn from the first internal electrode and the second internal electrode to one side surface of the laminate,
A first terminal electrode and a second terminal electrode, which are formed on a side surface of the stacked body in the stacking direction and electrically connect the first lead-out portions and the second lead-out portions positioned above and below in the stacking direction, respectively. In a multilayer capacitor comprising two terminal electrodes,
On the surface of the first terminal electrode and the surface of the second terminal electrode, the first lead portion positioned above and below in the stacking direction via the first terminal electrode and the second terminal electrode. An insulating layer is formed so as to cover the exposed surface central portion and the exposed surface central portion of the second lead portion.

The multilayer capacitor of the present invention includes a multilayer body formed by laminating a plurality of dielectric layers,
A plurality of first internal electrodes and second internal electrodes alternately disposed so as to be opposed to each other with the dielectric layer in between within the laminated body;
A first lead portion and a second lead portion drawn from the first internal electrode and the second internal electrode to the side surface on one side of the laminate, respectively;
A first terminal electrode formed on a side surface of the stacked body in the stacking direction and electrically connecting the first lead portions and the second lead portions positioned vertically in the stack direction; In a multilayer capacitor comprising two terminal electrodes,
An insulating layer is formed on the side surface of the laminated body so as to cover the exposed surface central portion of the first lead portion and the exposed surface central portion of the second lead portion positioned above and below in the stacking direction, respectively. The first terminal electrode and the second terminal electrode are respectively formed on both sides of the insulating layer.

  In such a multilayer capacitor, there is an insulating layer so as to cover the exposed surface central portion of the first lead portion and the exposed surface central portion of the second lead portion positioned above and below in the stacking direction. The first terminal electrode or the second terminal electrode exists on both sides of the substrate, and when a plurality of such multilayer capacitors are mounted on the surface of the substrate using solder, the insulating layer of the multilayer capacitor is The first terminal electrode and the second terminal electrode, which are in contact with the center portion of each electrode pattern formed on the surface and located on both sides of the insulating layer, and the respective electrode patterns are joined by solder, Between the lead part, the second lead part, and each electrode pattern of the substrate, the current path becomes two narrow paths, and the solder path is lengthened by changing the thickness of the insulating layer to Can be lengthened, equivalent Column inductance (ESL) without much change, it is possible to increase the equivalent series resistance (ESR).

  As a result, the peak of the series resonance of the multilayer capacitor becomes gentle as the minimum value rises, and when the decoupling circuit is configured so that the impedance is lowered in a wide band by combining a plurality of capacitors having different functional bands, the present invention Since the peak of parallel resonance between the multilayer capacitor and the capacitor in the adjacent functional band does not become steep, it is possible to reduce the deterioration of the impedance characteristics of the decoupling circuit.

  The equivalent series inductance (ESL) is joined by solder, and the current path between the first lead part, the second lead part, and the electrode pattern of the substrate becomes two narrow paths by the insulating layer. Will not increase. This is because the equivalent series inductance (ESL) does not depend on the cross-sectional area of the current path but depends on the width of the current path including the insulating layer.

  In the multilayer capacitor of the present invention, the gap between the multilayer capacitor and the substrate can be adjusted by changing the thickness of the insulating layer. For example, the gap between the multilayer capacitor and the substrate can be adjusted by increasing the thickness of the insulating layer. The insulation reliability between the multilayer capacitor and the substrate can be improved, and the long-term connection reliability of the solder connection portion (longer life of the solder in an environmental test such as a temperature cycle test) can be improved.

  Furthermore, in the multilayer capacitor of the present invention, the gap between the multilayer capacitor and the substrate can be made constant when the multilayer capacitor is placed on the substrate by making the thickness of the insulating layer constant, and when the solder is soldered. It is possible to prevent the multilayer capacitor from being inclined and mounted.

  The capacitor mounting board of the present invention is a capacitor mounting board in which a plurality of the above multilayer capacitors are mounted on the surface of the substrate, and the insulating layer of the multilayer capacitor is formed at the center of the electrode pattern formed on the surface of the substrate. The first terminal electrode and the second terminal electrode, which are in contact with each other and located on both sides of the insulating layer, and the corresponding electrode pattern are joined by solder.

  In such a capacitor mounting board, as described above, the current path becomes two narrow paths between the first lead part, the second lead part, and each electrode pattern of the board, and the insulating layer By changing the thickness, the solder height can be lengthened and the current path can be lengthened, and the equivalent series resistance (ESR) can be increased without changing the equivalent series inductance (ESL) so much. As a result, the minimum value of the series resonance peak of the multilayer capacitor becomes gentle, the peak of parallel resonance with other capacitors becomes gentle, and deterioration of the impedance characteristics of the decoupling circuit can be reduced.

  According to the multilayer capacitor and the capacitor mounting substrate of the present invention, when a plurality of multilayer capacitors are mounted on the substrate surface using solder, the insulating layer of the multilayer capacitor contacts the center portion of the electrode pattern formed on the substrate surface. The first terminal electrode and the second terminal electrode, which are in contact with each other and are located on both sides of the insulating layer, and each electrode pattern are joined by solder, and the first lead portion, the second lead portion, and each electrode of the substrate Between the pattern, the current path becomes two narrow paths, and by changing the thickness of the insulating layer, the solder height can be increased and the current path can be lengthened, so that the equivalent series inductance (ESL) The equivalent series resistance (ESR) can be increased without being changed.

  As a result, the peak of the series resonance of the multilayer capacitor becomes gentler as the minimum value rises, and the peak of the parallel resonance with other capacitors does not become steep, so it is possible to reduce the degradation of the impedance characteristics of the decoupling circuit. It becomes possible.

  Hereinafter, the multilayer capacitor of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a cross-sectional view showing one embodiment of the multilayer capacitor of the present invention. A multilayer capacitor 10 of the present invention includes a multilayer body 1, and includes a plurality of first internal electrodes 3 and a plurality of second internal electrodes. 4, a first terminal electrode 7 and a second terminal electrode 8 are provided.

  The laminated body 1 is a substantially rectangular parallelepiped dielectric block formed by laminating a plurality of rectangular dielectric layers 2a and 2b, for example, 70 to 600 layers. The dielectric layers 2a and 2b are formed to a thickness of 1 μm to 3 μm per layer by a dielectric material mainly composed of, for example, barium titanate, calcium titanate, strontium titanate or the like. A plurality of first internal electrodes 3 and a plurality of second internal electrodes 4 are alternately arranged in the laminated body 1 so as to face each other with the dielectric layer 2b interposed therebetween, and capacitance is generated in the facing region. To do.

  In other words, in the multilayer body 1, the dielectric layers and the internal electrodes are alternately stacked, and the first internal electrode 3 and the second internal electrode 4 are formed on the upper and lower surfaces of the dielectric layer 2b. This generates a capacitance.

  The dielectric layer 2b functions as an effective layer for forming capacitance, and the dielectric layer 2a not sandwiched between the internal electrodes 3 and 4 is a protective layer on the main surface side (up and down in the stacking direction) of the stack 1 respectively. Has been placed.

The internal electrodes 3 and 4 are formed to a thickness of, for example, 0.5 μm to 2 μm, for example, from a conductive material mainly composed of a metal such as nickel, copper, nickel-copper, silver-palladium. Further, since the outer peripheries of the internal electrodes 3 and 4 are separated from the side surface of the multilayer body 1, the opposing area of the internal electrodes 3 and 4 is, for example, when the area of each dielectric layer 2b is 2.3 mm ^2. For example, it is set to 1.7 mm ² to ² mm ² .

  In addition, the first internal electrode 3 and the second internal electrode 4 are respectively connected to the multilayer body 1 via the first lead portion 5 and the second lead portion 6 that are drawn to one side surface of the multilayer body 1. Are electrically connected to the plurality of first terminal electrodes 7 and the second terminal electrodes 8 on one side surface thereof. The first lead portion 5 and the second lead portion 6 are made of the same material as the internal electrodes 3 and 4.

  The first terminal electrode 7 and the second terminal electrode 8 are formed on the side surface of the multilayer body 1 with a thickness of, for example, 2 μm to 70 μm in the stacking direction x, and are located at the top and bottom of the stacking direction. The exposed surfaces of the part 5 and the exposed surfaces of the second lead-out part 6 are electrically connected to each other. In FIG. 1B, only a part of the dielectric layers 2a and 2b is indicated by a one-dot chain line, and only a part of the exposed surface of the lead portions 5 and 6 is indicated by a broken line.

  Moreover, the terminal electrodes 7 and 8 are formed, for example by the conductor material which has metals, such as nickel, copper, silver, and palladium, in the thickness of 0.5 micrometer-2 micrometers, for example. In addition, it is preferable to form a film on the surface of the terminal electrodes 7 and 8 with a conductive material such as tin, solder, or gold for the purpose of improving the connection with the wiring of the external wiring board.

  In the multilayer capacitor 10 configured as described above, when a predetermined voltage is applied between the first terminal electrode 7 and the second terminal electrode 8, the first internal electrode 3 and the second internal electrode 4. A capacitance corresponding to the dielectric constant, thickness, opposing area and number of layers of the dielectric layer 2b positioned between the two is formed.

  In the multilayer capacitor of the present invention, the first insulating layer 11 and the second insulating layer 12 are formed in the stacking direction x at the center of the surface of the first terminal electrode 7 and the second terminal electrode 8. The insulating layers 11, 12 are provided on the exposed surface central portion of the first lead portion 5 and the second lead portion 6 located above and below the stacking direction x via the first terminal electrode 7 and the second terminal electrode 8. It is formed so as to cover the central part of the exposed surface.

  In other words, the end surfaces of the lead portions 5 and 6 are exposed on one side surface of the multilayer body 1, and the terminal electrodes 7 and 8 are connected to the side surface of the multilayer body 1 so as to connect the exposed end surfaces (exposed surfaces). Insulating layers 11 and 12 extend in the laminating direction x on the surfaces of the terminal electrodes 7 and 8, respectively, and are perpendicular to the laminating direction x of the insulating layers 11 and 12 (the insulating layers 11 and 12 Terminal electrodes 7 and 8 are exposed on both sides.

  The insulating layer 11 is made of, for example, a heat-resistant resin such as an epoxy resin and does not melt when soldered to the substrate as will be described later. The thickness t of the insulating layers 11 and 12 is set to a thickness that can improve the insulation reliability between the multilayer capacitor and the substrate or the long-term connection reliability of the solder connection portion. The thickness t is approximately the solder height.

  In the multilayer capacitor 10 of the present invention, when the dielectric layer 2b is made of a dielectric material mainly composed of barium titanate, an appropriate organic solvent, glass frit, organic binder, or the like is added to the barium titanate powder.・ Mixed into a mud-like shape, and formed a plurality of ceramic green sheets of a predetermined shape and thickness by the doctor blade method, etc., and one main surface of each ceramic green sheet, for example, nickel powder A process of printing and applying a conductive paste obtained by adding and mixing an appropriate organic solvent, glass frit, organic binder, etc. in a predetermined pattern by screen printing, etc., and laminating a predetermined number of the obtained ceramic green sheets By laminating, a laminated sheet consisting of a plurality of ceramic green sheets is formed. A step of cutting and separating into individual laminates corresponding to the layer capacitors, a step of firing the individual laminates at a temperature of, for example, 1100 ° C. to 1400 ° C., and obtaining the laminate 1; It is manufactured using a manufacturing method including a step of forming the terminal electrodes 7 and 8 by printing, applying and baking the conductor paste on the side surface in a strip shape in the laminating direction by a screen printing method or the like.

  Then, a heat-resistant resin is applied on the terminal electrodes 7 and 8 with a predetermined thickness to form the insulating layer 11. The heat resistant resin coating method for forming the insulating layer 11 is performed by screen printing, for example. Screen printing can be performed before cutting and separating into individual laminates.

  The coating on the terminal electrodes 7 and 8 is formed by, for example, electroless plating. In the firing step of this manufacturing method, the ceramic green sheet and the conductive paste become the dielectric layer 2 and the internal electrodes 3 and 4 by firing, respectively. In addition, the shrinkage rate accompanying baking of the ceramic green sheet used in this manufacturing method is set to about 10% to 20%, for example. Further, the dielectric material contained in the ceramic green sheet may be added and mixed in the conductor paste.

  The multilayer capacitor 10 manufactured in this way is formed on the surface of the first terminal electrode 7 and the second terminal electrode 8 and in the stacking direction x via the first terminal electrode 7 and the second terminal electrode 8. Since the insulating layers 11 and 12 are formed so as to span the exposed surface central portion of the first lead portion 5 and the exposed portion central portion of the second lead portion 6 positioned above and below, such a multilayer capacitor 10 is formed. Is mounted on the surface of the substrate 13 using solder, the insulating layers 11 and 12 of the multilayer capacitor 10 are in contact with the center portion of the electrode pattern 15 formed on the surface of the substrate 13, and the insulating layer 11, The first terminal electrode 7 and the second terminal electrode 8 of the multilayer capacitor 10 formed on both sides of the electrode 12 and the electrode pattern 15 are joined by the solder 17, and the first lead portion 5 and the second lead portion 6. And the electrode pattern of the substrate 13 15, the current path becomes two narrow paths, and by changing the thickness t of the insulating layers 11 and 12, the solder height can be increased and the current path can be lengthened, and the equivalent series inductance ( The equivalent series resistance (ESR) can be increased without significantly changing the ESL).

  As a result, the peak of the series resonance of the multilayer capacitor becomes gentle as the minimum value rises, and when the decoupling circuit is configured so that the impedance is lowered in a wide band by combining a plurality of capacitors having different functional bands, the present invention Since the peak of parallel resonance between the multilayer capacitor and the capacitor in the adjacent functional band does not become steep, it is possible to reduce the deterioration of the impedance characteristics of the decoupling circuit.

  That is, as shown in FIG. 3B, when the impedance characteristic of a capacitor having a functional band on the low frequency side is y and the impedance characteristic of a capacitor having a functional band on the high frequency side is q as shown in FIG. The impedance of the constructed decoupling circuit is a solid line, and the impedance is high at the peak r of the parallel resonance between the two capacitors. On the other hand, as shown in FIG. 3A, when the multilayer capacitor of the present invention is used as a capacitor having a functional band on the high frequency side, the impedance characteristic is x. Since the ESR is increased, the impedance value at a frequency at which the impedance is minimized is increased. The peak z of parallel resonance with the capacitor having the functional band on the low frequency side having the impedance characteristic x is suppressed to a low level.

  In the multilayer capacitor of the present invention, the gap L between the multilayer capacitor 10 and the substrate 13 can be adjusted by changing the thickness t of the insulating layers 11 and 12, for example, the thickness t of the insulating layers 11 and 12 is increased. As a result, the gap L between the multilayer capacitor 10 and the substrate 13 can be increased, the insulation reliability between the multilayer capacitor 10 and the substrate 13 can be improved, and the long-term connection reliability of the solder connection portion can be improved.

  Furthermore, in the multilayer capacitor of the present invention, the thickness t of the insulating layers 11 and 12 is made constant so that the gap L between the multilayer capacitor 10 and the substrate 13 is made constant when the multilayer capacitor 10 is arranged on the substrate 13. It is possible to prevent the multilayer capacitor 10 when soldered from being mounted inclined with respect to the substrate 13.

  FIG. 2 shows a capacitor mounting board of the present invention. In FIG. 2, a plurality of the multilayer capacitors 10 shown in FIG. In FIG. 2, only the mounting structure of one multilayer capacitor is shown.

  The insulating layers 11 and 12 of the multilayer capacitor 10 are in contact with the central portion of the electrode pattern 15 formed on the surface of the resin substrate 13, for example, and the first of the multilayer capacitor 10 located on both sides of the insulating layer 11. The terminal electrode 7 and the second terminal electrode 8 and the electrode pattern 15 are joined by solder 17.

  In such a capacitor-mounted board, as described above, the current path becomes two narrow paths between the first lead part 5, the second lead part 6, and the electrode pattern 15 of the board 13, and By changing the thickness of the insulating layer 11, the solder height can be lengthened and the current path can be lengthened, and the equivalent series resistance (ESR) can be increased without changing the equivalent series inductance (ESL) so much. As a result, the peak value of the series resonance of the multilayer capacitor 10 becomes gentle as the minimum value increases, the peak of parallel resonance with other capacitors becomes gentle, and the deterioration of the impedance characteristics of the decoupling circuit can be reduced. .

  Note that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made without departing from the scope of the present invention.

  For example, in the example of the embodiment described above, the insulating layer 11 is formed on the surface of the terminal electrodes 7 and 8, but as shown in FIG. 4, the exposed surface of the first lead portion 5 positioned above and below in the stacking direction. An insulating layer 11 is formed so as to span the central portion and the exposed surface central portion of the second lead portion 6, and the first terminal electrodes 7 a and 7 b and the second terminal electrodes 8 a and 8 b 11 on both sides.

  Even with such a multilayer capacitor, the same effect as described above can be obtained. As the insulating layer 11 in this case, not only a heat resistant resin but also an inorganic material can be used.

  Furthermore, as shown in FIG. 5, the present invention can be applied to a case where a plurality of lead portions are provided in one internal electrode.

  In order to show the effect of the multilayer capacitor 10 of the present invention, a numerical simulation using a PEEC (Partial Element Equivalent Circuit) method was performed. In accordance with the shape of FIG. 1, internal electrodes 3 and 4 having a length of 1.68 mm, a width of 0.53 mm, a thickness of 1 μm, and a sheet resistance of 100 mΩ / □ are alternately arranged at intervals of 2 μm inside a dielectric material having a dielectric constant of 4000. ESR and ESL were calculated when 50 layers were stacked.

  The lead-out portions 5 and 6 drawn from each internal electrode to the side surface on one side of the laminate were 100 μm in the lead-out direction, 400 μm wide in the lead-out direction, 1 μm thick, and a sheet resistance of 100 mΩ / □. The insulating layer 11, which is a feature of the present invention, was provided at the center of the exposed surface of the lead portion with a thickness t of 100 μm, a width of 200 μm, and a length in the stacking direction of 150 μm.

  When the multilayer capacitor was mounted on the substrate, the solder connection portion (solder 17 in FIG. 2) was connected at two locations with a width of 100 μm, a height of 100 μm, and a length in the stacking direction of 150 μm. For comparison, a conventional capacitor having no insulating layer 11 of the present invention, a solder connection portion having a width of 400 μm, a thickness of 50 μm, and a length in the stacking direction of 150 μm was also calculated.

  As a result of comparing ESR and ESL between the conventional capacitor and the capacitor of the present invention, the ESR of the multilayer capacitor of the present invention is 1.5 times larger than that of the conventional capacitor, and the ESL is only slightly increased to 1.15 times. Met.

BRIEF DESCRIPTION OF THE DRAWINGS An example of embodiment of the multilayer capacitor of this invention is shown, (a) is sectional drawing, (b) is a side view. It is sectional drawing of a part of capacitor | condenser mounting board | substrate. (A) The diagram which shows the impedance characteristic of the multilayer capacitor of this invention and the decoupling circuit which uses this, (b) is the diagram which shows the impedance characteristic of the conventional multilayer capacitor and the decoupling circuit which uses this. The other form of the multilayer capacitor which formed the insulating layer directly on the one side surface of a laminated body is shown, (a) is sectional drawing, (b) is a side view. It is sectional drawing which shows the multilayer capacitor which formed the several extraction part in one internal electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Laminated body 2a ... Dielectric layer (protective layer)
2b Dielectric layer (effective layer)
DESCRIPTION OF SYMBOLS 3 ... 1st internal electrode 4 ... 2nd internal electrode 5 ... 1st extraction part 6 ... 2nd extraction part 7, 7a, 7b ... 1st terminal electrode 8 8a, 8b ... second terminal electrode 10 ... multilayer capacitor 11,12 ... insulating layer 13 ... substrate 15 ... electrode pattern 17 ... solder

Claims (3)

A laminate formed by laminating a plurality of dielectric layers;
A plurality of first internal electrodes and second internal electrodes alternately disposed so as to be opposed to each other with the dielectric layer in between within the laminated body;
A first lead portion and a second lead portion drawn from the first internal electrode and the second internal electrode to the side surface on one side of the laminate, respectively;
A first terminal electrode formed on a side surface of the stacked body in the stacking direction and electrically connecting the first lead portions and the second lead portions positioned vertically in the stack direction; In a multilayer capacitor comprising two terminal electrodes,
On the surface of the first terminal electrode and the surface of the second terminal electrode, the first lead portion located above and below in the stacking direction via the first terminal electrode and the second terminal electrode. A multilayer capacitor comprising an insulating layer formed so as to cover an exposed surface central portion and an exposed surface central portion of the second lead portion. A laminate formed by laminating a plurality of dielectric layers;
A plurality of first internal electrodes and second internal electrodes alternately disposed so as to be opposed to each other with the dielectric layer in between within the laminated body;
A first lead portion and a second lead portion drawn from the first internal electrode and the second internal electrode to the side surface on one side of the laminate, respectively;
A first terminal electrode formed on a side surface of the stacked body in the stacking direction and electrically connecting the first lead portions and the second lead portions positioned vertically in the stack direction; In a multilayer capacitor comprising two terminal electrodes,
An insulating layer is formed on the side surface of the laminated body so as to cover the exposed surface central portion of the first lead portion and the exposed surface central portion of the second lead portion positioned above and below in the stacking direction, respectively. The multilayer capacitor is characterized in that the first terminal electrode and the second terminal electrode are respectively formed on both sides of the insulating layer.   3. A capacitor mounting substrate comprising a plurality of the multilayer capacitors according to claim 1 mounted on the surface of the substrate, wherein an insulating layer of the multilayer capacitor is in contact with a central portion of the electrode pattern formed on the surface of the substrate. And a first terminal electrode and a second terminal electrode located on both sides of the insulating layer, and the corresponding electrode pattern are joined by solder.

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