JP2008021935A - Electronic device and manufacturing method thereof - Google Patents

Abstract

Two or more different regions are defined on the substrate, and silicon is formed in spite of using a second insulating film made of a high-k insulating material when forming an insulating film for each region. An extremely reliable electronic device is realized without impairing the function of the first insulating film such as an oxide film.
A silicon nitride film is formed on a silicon oxide film serving as a gate insulating film in an I / O film forming region, and in this state, a high-layer serving as a gate insulating film in a low leak film forming region is formed. A k insulating material, here, an HfSiO film 7 is formed. Here, the silicon oxide film 4 and the HfSiO film 7 are laminated via the silicon nitride film 5.
[Selection] Figure 4

Description

  The present invention relates to an electronic device and a method for manufacturing the same, and mainly targets a transistor that is a semiconductor element as the electronic device.

As an electronic device, one of semiconductor elements used in a semiconductor integrated circuit is a MOS field effect transistor (MOSFET).
In a semiconductor device including a semiconductor integrated circuit, performance required for an element such as a MOSFET differs depending on the application.

For example, since a high voltage is applied to a MOSFET used for an input / output (I / O) portion, a gate insulating film that is thick to some extent is required in consideration of ensuring sufficient reliability.
A MOSFET used in a low leak portion is conventionally used as a gate insulating film in order to reduce the leakage current while suppressing the equivalent SiO ₂ equivalent film thickness (CET) in order to reduce power consumption. The use of a material having a higher dielectric constant than a silicon oxide film (also referred to as a high-k material) is being studied.
In the MOSFET used for the logic portion, the gate insulating film is being made thinner for high-speed operation.

In general, when forming gate insulating films of different thicknesses and materials in one semiconductor device, the following procedure is performed.
First, a first gate insulating film is formed on a silicon substrate. Next, a resist pattern is formed only in a region where a transistor is to be formed using the first gate insulating film, and the first gate insulating film is dry-etched using this resist pattern as a mask, so that only the region where the first transistor is formed is formed. Then, the first gate insulating film is left, and the first gate insulating film in the other part is removed. Then, after removing the resist pattern, a second gate insulating film made of a material having a film thickness different from that of the first gate insulating film is formed again on the silicon substrate. By repeating this, a plurality of gate insulating films having different thicknesses and materials are formed in one semiconductor device (see, for example, Patent Document 1). The same applies to the case where a high dielectric constant (High-k) insulating film is used for a part of the gate insulating film, for example, the second gate insulating film (see, for example, Patent Document 2).

JP 2000-349287 A JP 2005-51178 A

  However, using the above-described method, a plurality of types of gate insulating films (for example, a thick silicon oxide film for I / O transistors, a high-k insulating film for low-leakage transistors, and a thin silicon oxide film for logic transistors) When forming three or more types of gate insulating films, a laminated structure of a thick silicon oxide film and a high-k film is formed during the formation.

  The high-k insulating material contains metal elements such as Hf, Si, and Al. When creating various types of gate insulating films, if a high-k insulating film is stacked on the silicon oxide film, the metal elements of the high-k insulating film diffuse into the silicon oxide film and serve as the gate insulating film for the silicon oxide film. There is a problem that the function of is impaired. Further, when the high-k insulating film on the silicon oxide film is removed by etching, for example, wet etching, the silicon oxide film is damaged by the etching solution for the high-k insulating film. Due to this damage, the thick silicon oxide film cannot function sufficiently as a gate insulating film of the I / O transistor, and reliability cannot be ensured.

  The present invention has been made to solve the above-described problem, and two or more different regions are defined on the substrate. When an insulating film is separately formed for each region, a high-k insulating material is used. An object of the present invention is to provide a highly reliable electronic device and a method for manufacturing the same without impairing the function of the first insulating film, which is a silicon oxide film, in spite of using the second insulating film. .

  The electronic device according to the present invention includes a substrate in which at least a first region and a second region are defined, a first insulating film formed only in the first region, and a first insulating film. Is made of an insulating material having a high dielectric constant, and includes a second insulating film formed only in the second region, and is etched more than the second insulating film so as to cover the first insulating film. An upper insulating film made of an insulating material having a low speed is formed.

  The method for manufacturing an electronic device according to the present invention includes a step of forming a first insulating film over the entire surface above the substrate, a step of forming an upper insulating film over the entire surface so as to cover the first insulating film, Etching the laminated film composed of the first insulating film and the upper insulating film, leaving the laminated film only in the first region of the substrate, and over the entire surface above the substrate including the upper insulating film, Forming a second insulating film made of an insulating material having a dielectric constant higher than that of the first insulating film; etching the second insulating film; and applying the second insulating film to the second of the substrate The upper insulating film is made of an insulating material having an etching rate lower than that of the second insulating film, and the first insulating film is etched in the first processing step. In the region, the upper insulating film is etched. Used as chromatography, removing the second insulating film on the upper insulating film.

  According to the present invention, two or more different regions are defined on the substrate, and the second insulating film made of the high-k insulating material is used when the insulating film is separately formed for each region. Therefore, an extremely reliable electronic device can be realized without impairing the function of the first insulating film such as a silicon oxide film.

-Basic outline of the present invention-
Two or more different regions are defined on the substrate, and an insulating film such as a first gate insulating film made of silicon oxide and a second gate insulating film made of a high-k insulating material are provided for each region. In the case of separate production, it is inevitable that the first gate insulating film and the second gate insulating film are partially laminated in the course of the manufacturing process.

  In the present invention, it is anticipated that the above laminated state will occur, and in etching the second insulating film, an upper insulating film made of an insulating material having an etching rate lower than that of the second insulating film is formed on the first insulating film. Form. Then, after patterning the upper insulating film and the first insulating film, a second insulating film is formed over the entire surface. At this time, the second insulating film is overlapped with the first insulating film, but both are stacked through the upper insulating film. Therefore, the metal element in the second insulating film made of the high-k insulating material is blocked by the upper insulating film, and the diffusion of the metal element into the first insulating film is suppressed.

  Further, in this case, when the second insulating film on the first insulating film is removed by etching in the patterning of the second insulating film, the upper insulating film functions as an etching stopper. Therefore, the first insulating film is protected from etching by the upper insulating film, and damage due to the etching is suppressed.

-Preferred embodiments to which the present invention is applied-
In this embodiment, a semiconductor device including various MOSFETs is taken as an example, and the configuration thereof will be described together with a manufacturing method.

(First embodiment)
1 to 9 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps.

First, as shown in FIG. 1, element isolation is performed on the silicon substrate 1 by, for example, an STI (Shallow Trench Isolation) method. Thereafter, a silicon oxide film 4 is formed.
Specifically, first, the isolation groove 2 is formed in the element isolation region of the silicon substrate 1. An insulating film, here a silicon oxide film, is deposited to fill the isolation trench 2 by, for example, a CVD method. For example, the surface of the silicon substrate 1 is used as a polishing stopper to form silicon by a chemical mechanical polishing (CMP) method. Polish the oxide film. As described above, the STI element isolation structure 3 formed by filling the isolation trench 2 with silicon oxide is formed.

  In the present embodiment, by forming each STI element isolation structure 3, an active region (hereinafter referred to as “I / O film formation region”) in which a MOSFET of an input / output (I / O) portion is formed on the silicon substrate 1. ), An active region in which a logic portion MOSFET is formed (hereinafter referred to as “logic film forming region”), and an active region in which a low leakage portion MOSFET is formed (hereinafter referred to as “low leakage film”). Defined as “formation regions”).

  Next, a first insulating film, here silicon oxide, is formed to a thickness of, for example, about 2 nm to 10 nm by, for example, a thermal oxidation method on the entire surface including each active region of the silicon substrate 1, and a thick silicon oxide film 4 is formed. Form. For example, a silicon oxynitride film may be formed as the first insulating film instead of the silicon oxide film.

Subsequently, as shown in FIG. 2, a silicon nitride film 5 is formed.
Specifically, an upper insulating film, here silicon nitride, is deposited to a thickness of, for example, about 0.5 nm to 2 nm by, for example, a CVD method so as to cover the silicon oxide film 4 to form a silicon nitride film 5. . The upper insulating film has a lower etching rate than the second insulating film in the etching of the second insulating film described later, in other words, functions as an etching stopper for the second insulating film. As the upper insulating film, for example, an AlN film or an Al ₂ O ₃ film may be formed instead of the silicon nitride film.

Subsequently, as shown in FIG. 3, the silicon nitride film 5 and the silicon oxide film 4 are patterned.
Specifically, a resist is applied to the entire surface of the silicon nitride film 5 and processed by lithography to form a resist pattern 6 that covers only the I / O film forming region of the silicon substrate 1. Then, the silicon nitride film 5 and the silicon oxide film 4 are dry-etched using the resist pattern 6 as a mask to leave a laminated film of the silicon oxide film 4 and the silicon nitride film 5 only in the I / O film formation region.

Subsequently, as shown in FIG. 4, an HfSiO film 7 is formed.
Specifically, the resist pattern 6 is first removed by ashing or the like.
Next, on the entire surface of the silicon substrate 1 including the silicon nitride film 5, a second insulating film, here, HfSiO, which is a high-k insulating material, is deposited to a film thickness of, for example, about 2 nm to 5 nm by, for example, CVD. A film 7 is formed. As the second insulating film, an HfSiON film may be formed instead of the HfSiO film. Further, as the second insulating film, an oxide film or oxynitride film containing at least one of Hf, Si, Ga, Al, La, Zr, Y, Bi, and Ba instead of the HfSiO film (however, It is also preferable to form (except for the HfSiO film and the HfSiON film).

  When the HfSiO film 7 is formed, the HfSiO film 7 is overlapped with the silicon oxide film 4, but both are stacked through the silicon nitride film 5, which is an upper insulating film. Therefore, the metal elements Hf and Si in the HfSiO film 7 are blocked by the silicon nitride film 5 and the diffusion of Hf and Si into the silicon oxide film 4 is suppressed.

Subsequently, as shown in FIG. 5, the HfSiO film 7 is patterned.
Specifically, a resist is applied to the entire surface of the HfSiO film 7 and processed by lithography to form a resist pattern 8 that covers only the low leakage film forming region of the silicon substrate 1. Then, the HfSiO film 7 is etched using the resist pattern 8 as a mask. Since the HfSiO film 7 is an amorphous film here, the silicon substrate 1 is wet-etched using, for example, hydrofluoric acid (HF) as an etchant. By this wet etching, the HfSiO film 7 exposed in the I / O film formation region and the logic formation region is selectively removed, and the HfSiO film 7 remains only in the low leak film formation region protected by the resist pattern 8. To do.

  In this wet etching, when the HfSiO film 7 on the silicon oxide film 4 is removed by etching, the silicon nitride film 5 functions as an etching stopper. Therefore, the silicon oxide film 4 is protected from the etching solution by the silicon nitride film 5, and damage due to the etching is suppressed. This situation is the same even when the second insulating film made of, for example, a high-k insulating material is not an amorphous film and dry etching is performed instead of the wet etching.

  Here, when the HfSiO film 7 is formed, a base film (not shown) such as a silicon oxide film may be formed first, and then the HfSiO film 7 may be formed on the base film. In this case, when the HfSiO film 7 is patterned, the base film is processed together with the HfSiO film 7, and the base film is left only under the HfSiO film 7 on the low leak film formation region.

Subsequently, as shown in FIG. 6, a silicon oxide film 9 is formed.
Specifically, the resist pattern 8 is first removed by ashing or the like.
Next, as the third insulating film, the surface of the silicon substrate 1 is oxidized by, for example, a thermal oxidation method. At this time, since the portion of the silicon substrate 1 whose surface is exposed is only the logic film formation region, a thin silicon oxide film 9 having a thickness of, for example, about 1 nm to 2 nm is formed only in the logic film formation region. . As the third insulating film, a thin silicon oxynitride film may be formed by, for example, thermal oxynitridation instead of the silicon oxide film.

Subsequently, as shown in FIG. 7, gate electrodes 11, 12, 13 and an LDD region 14 are sequentially formed.
Specifically, first, a conductive film, here a polycrystalline silicon film (not shown), is formed on the entire surface of the silicon substrate including the I / O film formation region, the low leak film formation region, and the logic film formation region. For example, it deposits by CVD method. Then, the polycrystalline silicon film is patterned into an electrode shape by lithography and dry etching, the gate electrode 11 is formed on the silicon nitride film 5 in the I / O film forming region, and the HfSiO film 7 is formed in the low leak film forming region. The gate electrode 12 is patterned, and the gate electrode 13 is patterned on the silicon oxide film 9 in the logic film formation region.

Next, using the gate electrodes 11, 12, and 13 as a mask, the surface layer of the silicon substrate 1 under the silicon oxide film 4 in the I / O film formation region and the silicon substrate 1 under the HfSiO film 7 in the low leakage film formation region Impurities are ion-implanted into the surface layer of the silicon substrate 1 under the silicon oxide film 9 in the surface layer and logic film formation region. Here, for example, arsenic (As), which is an n-type impurity, is ion-implanted under the conditions of a dose amount of 1 × 10 ¹³ / cm ² and an acceleration energy of 10 keV to form the LDD region 14.

Subsequently, as shown in FIG. 8, sidewall insulating films 15, source / drain regions 16, and silicide layers 17 are sequentially formed.
Specifically, first, an insulating film is formed on the entire surface of the silicon substrate including the I / O film formation region, the low leakage film formation region, and the logic film formation region so as to cover the gate electrodes 11, 12, and 13. Here, a silicon oxide film (not shown) is deposited by, for example, a CVD method. Then, using the gate electrodes 11, 12, and 13 as a mask, the entire surface of the silicon oxide film is subjected to anisotropic dry etching (etch back). By this etch back, the side wall insulating film 15 is formed leaving the silicon oxide film only on the side surfaces of the gate electrodes 11, 12, and 13. Further, following the formation of the sidewall insulating film 15, the silicon nitride film 5, the silicon oxide film 4, the HfSiO film 7, and the silicon oxide film 9 are formed using the gate electrodes 11, 12, 13 and the sidewall insulating film 15 as a mask. Dry etching is performed to form gate insulating films 34, 35, and 36.

  In this embodiment, the gate insulating film 34 is patterned in a state where the silicon nitride film 5 as the upper insulating film is laminated on the silicon oxide film 4 in the I / O film forming region. Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, the gate insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film. High gate insulation film is realized.

Next, using the gate electrodes 11, 12, 13 and the sidewall insulating film 15 as a mask, the gate insulation in the surface layer of the silicon substrate 1 below the gate insulating film 34 in the I / O film forming region and in the low leak film forming region. Impurities are implanted into the surface layer of the silicon substrate 1 below the film 35 and the surface layer of the silicon substrate 1 below the gate insulating film 36 in the logic film formation region. Here, for example, phosphorus (P), which is an n-type impurity, is ion-implanted under the conditions of, for example, a dose amount of 5 × 10 ¹³ / cm ² and an acceleration energy of 15 keV so as to have a higher impurity concentration than the LDD region 14. A source / drain region 16 is formed so as to overlap with a part of 14.

Next, a metal capable of forming silicide on the entire surface of the silicon substrate 1 including the I / O film formation region, the low leak film formation region, and the logic film formation region, here, for example, W is formed by sputtering or the like. After the deposition, heat treatment is performed. By this heat treatment, W and Si undergo a silicide reaction, and a silicide layer 17 of WSi ₂ is formed on the gate electrodes 11, 12, and 13 and on each source / drain region 14. Thus, by forming a silicide structure (here, a salicide structure), the resistance of the gate electrode and the source / drain regions can be reduced.

  In the present embodiment, the LDD region 14 and the source / drain region 16 are formed by the same ion implantation in each of the I / O film forming region, the low leakage film forming region, and the logic film forming region. Of course, in order to introduce impurities suitable for each formation region, of course, ions are implanted with impurities, dose amount and acceleration energy suitable for each formation region to form LDD regions and source / drain regions. Anyway.

  In this case, a portion other than the formation region for ion implantation is covered with a resist mask, and predetermined ion implantation is performed. As described above, the formation of the resist mask, the ion implantation, and the removal of the resist mask are appropriately repeated for each of the I / O film formation region, the low-leakage film formation region, and the logic film formation region. Then, an LDD region and a source / drain region suitable for each forming region are formed.

  Further, in the present embodiment, the case where n-type impurities are ion-implanted into each of the I / O film formation region, the low leak film formation region, and the logic film formation region is exemplified. It is also possible to change n-type and p-type MOSFETs by changing the order and ion implantation conditions, and separately implanting n-type and p-type impurities in the same silicon substrate 1.

Subsequently, as shown in FIG. 9, the interlayer insulating film 18, the contact plug 21, and the wiring 22 are sequentially formed.
Specifically, first, an insulating film is formed so that the gate electrodes 11, 12, and 13 are embedded on the entire surface of the silicon substrate 1 including the I / O film forming region, the low leak film forming region, and the logic film forming region. Here, a silicon oxide film is deposited by, for example, the CVD method, and the interlayer insulating film 18 is formed.

  Next, a portion corresponding to the source / drain region 16 of the interlayer insulating film 18 is patterned to form a contact hole 19 exposing a part of the surface of the silicide layer 17 on the source / drain region 16. Then, after depositing a conductive material, in this case W, so as to fill the contact hole 19, the surface of the interlayer insulating film 18 is polished as a stopper to polish the W by CMP to form a contact plug 21 that fills the contact hole 19 with W. To do.

  Next, a metal material, in this case, Al (or Al alloy) is deposited on the entire surface of the interlayer insulating film 18 and patterned so that the wiring is electrically connected to the source / drain region 16 through the contact plug 21. 22 is formed.

  Thereafter, through a patterning process for connecting the gate electrodes 11, 12, and 13, and further forming processes such as interlayer insulating films and wirings, the I / O transistor 31 is formed in the I / O film forming region, and the low leakage film The low leakage transistor 32 is formed in the formation region, and the logic transistor 33 is formed in the logic film formation region, thereby completing the semiconductor device of this embodiment.

  As described above, according to the present embodiment, two or more different types, here, three types of formation regions are defined on the silicon substrate 1, and the gate insulating films 34, 35, 36 are defined for each formation region. However, even if the second insulating film (HfSiO film 7) made of a high-k insulating material is used, the function of the first insulating film (silicon oxide film 4) is not impaired and the reliability is extremely high. High MOSFET can be realized.

(Second Embodiment)
This embodiment discloses a semiconductor device including various MOSFETs as in the first embodiment, but differs in that the gate insulating film of the I / O transistor is different.
10 to 14 are schematic cross-sectional views sequentially showing main processes of the semiconductor device manufacturing method according to the second embodiment.

First, similarly to the first embodiment, the respective steps of FIGS. 1 to 5 are performed.
Subsequently, after the resist pattern 8 is removed by ashing or the like, the silicon nitride film 5 is removed as shown in FIG.
Specifically, the silicon substrate 1 is wet-etched using phosphoric acid as an etchant, for example. By this wet etching, the silicon nitride film 5 stacked on the silicon oxide film 4 in the I / O film formation region is selectively removed.

Subsequently, as shown in FIG. 11, a silicon oxide film 9 is formed.
Specifically, as the third insulating film, the surface of the silicon substrate 1 is oxidized by, for example, a thermal oxidation method. At this time, since the portion of the silicon substrate 1 whose surface is exposed is only the logic film formation region, a thin silicon oxide film 9 having a thickness of, for example, about 1 to 2 nm is formed only in the logic film formation region. Is done. As the third insulating film, a thin silicon oxynitride film may be formed by, for example, thermal oxynitridation instead of the silicon oxide film.

Subsequently, as shown in FIG. 12, gate electrodes 11, 12, 13 and an LDD region 14 are sequentially formed.
Specifically, first, a conductive film, here a polycrystalline silicon film (not shown), is formed on the entire surface of the silicon substrate including the I / O film formation region, the low leak film formation region, and the logic film formation region. For example, it deposits by CVD method. Then, the polycrystalline silicon film is patterned into an electrode shape by lithography and dry etching, the gate electrode 11 is formed on the silicon oxide film 4 in the I / O film forming region, and the HfSiO film 7 is formed in the low leak film forming region. The gate electrode 12 is patterned, and the gate electrode 13 is patterned on the silicon oxide film 9 in the logic film formation region.

Next, using the gate electrodes 11, 12, and 13 as a mask, the surface layer of the silicon substrate 1 under the silicon oxide film 4 in the I / O film formation region and the silicon substrate 1 under the HfSiO film 7 in the low leakage film formation region Impurities are ion-implanted into the surface layer of the silicon substrate 1 under the silicon oxide film 9 in the surface layer and logic film formation region. Here, for example, arsenic (As), which is an n-type impurity, is ion-implanted under the conditions of a dose amount of 1 × 10 ¹³ / cm ² and an acceleration energy of 10 keV to form the LDD region 14.

Subsequently, as shown in FIG. 13, a sidewall insulating film 15, a source / drain region 16, and a silicide layer 17 are sequentially formed.
Specifically, first, an insulating film is formed on the entire surface of the silicon substrate including the I / O film formation region, the low leakage film formation region, and the logic film formation region so as to cover the gate electrodes 11, 12, and 13. Here, a silicon oxide film (not shown) is deposited by, for example, a CVD method. Then, using the gate electrodes 11, 12, and 13 as a mask, the entire surface of the silicon oxide film is subjected to anisotropic dry etching (etch back). By this etch back, the side wall insulating film 15 is formed leaving the silicon oxide film only on the side surfaces of the gate electrodes 11, 12, and 13. Further, following the formation of the sidewall insulating film 15, the silicon oxide film 4, the HfSiO film 7, and the silicon oxide film 9 are dry-etched using the gate electrodes 11, 12, 13 and the sidewall insulating film 15 as a mask, and the gate is formed. Insulating films 41, 35, and 36 are formed.

  In the present embodiment, in the I / O film formation region, the silicon oxide film existing in the I / O film formation region in a state where the silicon nitride film 5 as the upper insulating film formed on the silicon oxide film 4 is removed. By patterning 4, the gate insulating film 41 is patterned. Since the gate insulating film 41 has a single-layer structure of only the relatively thick silicon oxide film 4, the film formation can be performed precisely, and there is no influence of the above-described Hf and Si diffusion, wet etching, or the like. A highly functional gate insulating film is realized.

Next, using the gate electrodes 11, 12 and 13 and the sidewall insulating film 15 as a mask, the gate insulation in the surface layer of the silicon substrate 1 under the gate insulating film 41 in the I / O film forming region and in the low leakage film forming region. Impurities are implanted into the surface layer of the silicon substrate 1 below the film 35 and the surface layer of the silicon substrate 1 below the gate insulating film 36 in the logic film formation region. Here, for example, phosphorus (P), which is an n-type impurity, is ion-implanted under a condition of a dose amount of 5 × 10 ¹³ / cm ² and an acceleration energy of 15 keV so as to have a higher impurity concentration than that of the LDD region 14. A source / drain region 16 is formed so as to overlap with a part of 14.

Next, a metal capable of forming silicide on the entire surface of the silicon substrate 1 including the I / O film formation region, the low leak film formation region, and the logic film formation region, here, for example, W is formed by sputtering or the like. After the deposition, heat treatment is performed. By this heat treatment, W and Si undergo a silicide reaction, and a silicide layer 17 of WSi ₂ is formed on the gate electrodes 11, 12, and 13 and on each source / drain region 14. Thus, by forming a silicide structure (here, a salicide structure), the resistance of the gate electrode and the source / drain regions can be reduced.

  In the present embodiment, the LDD region 14 and the source / drain region 16 are formed by the same ion implantation in each of the I / O film forming region, the low leakage film forming region, and the logic film forming region. However, of course, in order to introduce impurities suitable for each formation region, ions are implanted with an impurity, dose amount and acceleration energy suitable for each formation region to form LDD regions and source / drain regions. Anyway. In this case, a portion excluding a formation region for ion implantation is covered with a resist mask, and ion implantation is performed.

  Further, in the present embodiment, the case where n-type impurities are ion-implanted into each of the I / O film formation region, the low leak film formation region, and the logic film formation region is exemplified. It is also possible to change n-type and p-type MOSFETs by changing the order and ion implantation conditions, and separately implanting n-type and p-type impurities in the same silicon substrate 1.

Subsequently, as shown in FIG. 14, an interlayer insulating film 18, contact plugs 21, and wirings 22 are sequentially formed.
Specifically, first, an insulating film is formed so that the gate electrodes 11, 12, and 13 are embedded on the entire surface of the silicon substrate 1 including the I / O film forming region, the low leak film forming region, and the logic film forming region. Here, a silicon oxide film is deposited by, for example, the CVD method, and the interlayer insulating film 18 is formed.

  Next, a portion corresponding to the source / drain region 16 of the interlayer insulating film 18 is patterned to form a contact hole 19 exposing a part of the surface of the silicide layer 17 on the source / drain region 16. Then, after depositing a conductive material, in this case, W, so as to fill the contact hole 19, the surface of the interlayer insulating film 18 is used as a stopper to polish W by CMP to form a contact plug 21 that fills the contact hole 19 with W. To do.

  Next, a metal material, in this case, Al (or Al alloy) is deposited on the entire surface of the interlayer insulating film 18 and patterned so that the wiring is electrically connected to the source / drain region 16 through the contact plug 21. 22 is formed.

  Thereafter, through a patterning process for connecting the gate electrodes 11, 12, and 13, and further forming processes such as interlayer insulating films and wirings, the I / O transistor 31 is formed in the I / O film forming region, and the low leakage film The low leakage transistor 32 is formed in the formation region, and the logic transistor 33 is formed in the logic film formation region, thereby completing the semiconductor device of this embodiment.

  As described above, according to the present embodiment, two or more different types of formation regions, here, three types of formation regions are defined on the silicon substrate 1, and the gate insulating films 41, 35, and 36 are defined for each formation region. However, even if the second insulating film (HfSiO film 7) made of a high-k insulating material is used, the function of the first insulating film (silicon oxide film 4) is not impaired, and the reliability is extremely high. High MOSFET can be realized.

In the first and second embodiments, the case where the silicon oxide film 4 (or silicon oxynitride film) is formed as the first insulating film has been exemplified. However, the present invention is also applied to the following cases, for example. Can do. For example, a silicon nitride film is used as the first insulating film, and an AlN film or an Al ₂ O ₃ film having an etching rate lower than that of the silicon nitride film is formed as an upper insulating film when the second insulating film is etched. In this case, as the second insulating film, an oxide film or oxynitride film containing at least one of Hf, Si, Ga, Al, La, Zr, Y, Bi, and Ba is formed as a material. Is preferred.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Supplementary note 1) a substrate in which at least a first region and a second region are defined;
A first insulating film formed only in the first region;
A second insulating film made of an insulating material having a dielectric constant higher than that of the first insulating film and formed only in the second region,
An electronic device, wherein an upper insulating film made of an insulating material having an etching rate lower than that of the second insulating film is formed so as to cover the first insulating film.

(Supplementary note 2) The electronic device according to supplementary note 1, wherein the upper insulating film is one selected from a silicon nitride film, an AlN film, and an Al ₂ O ₃ film.

  (Supplementary note 3) The electronic device according to Supplementary note 1 or 2, wherein the first insulating film is a silicon oxide film or a silicon oxynitride film.

  (Supplementary Note 4) The second insulating film is an oxide film or an oxynitride film containing at least one of Hf, Si, Ga, Al, La, Zr, Y, Bi, and Ba. The electronic device according to any one of appendices 1 to 3.

(Supplementary Note 5) The stacked film of the first insulating film and the upper insulating film is a gate insulating film of the first transistor formed in the first region,
The electronic device according to any one of appendices 1 to 4, wherein the second insulating film is a gate insulating film of a second transistor formed in the second region.

(Additional remark 6) The said board | substrate is further demarcating 3rd area | region,
The electronic device according to any one of appendices 1 to 5, further including a third insulating film that is formed only in the third region and is thinner than the first insulating film.

  (Supplementary note 7) The electronic device according to supplementary note 6, wherein the third insulating film is a gate insulating film of a third transistor formed in the third region.

(Appendix 8) Forming a first insulating film on the entire surface above the substrate;
Forming an upper insulating film over the entire surface so as to cover the first insulating film;
Etching the laminated film composed of the first insulating film and the upper insulating film, and leaving the laminated film only in the first region of the substrate;
Forming a second insulating film made of an insulating material having a dielectric constant higher than that of the first insulating film on the entire upper surface of the substrate including the upper insulating film;
Etching the second insulating film, leaving the second insulating film only in the second region of the substrate, and
The upper insulating film is made of an insulating material having an etching rate lower than that of the second insulating film,
In the step of etching the second insulating film, in the first region, the upper insulating film is used as an etching stopper, and the second insulating film on the upper insulating film is removed. Electronic device manufacturing method.

(Supplementary Note 9) The upper layer insulating film, a silicon nitride film, a method for fabricating an electronic device according to note 8, characterized in that the one kind selected from the AlN film and the Al ₂ O ₃ film.

  (Additional remark 10) The said 1st insulating film is a silicon oxide film or a silicon oxynitride film, The manufacturing method of the electronic device of Additional remark 8 or 9 characterized by the above-mentioned.

  (Appendix 11) The second insulating film is an oxide film or an oxynitride film containing at least one of Hf, Si, Ga, Al, La, Zr, Y, Bi, and Ba. The manufacturing method of the electronic device of any one of Additional remarks 8-10.

(Supplementary Note 12) The laminated film of the first insulating film and the upper insulating film is a gate insulating film of the first transistor formed in the first region,
The method of manufacturing an electronic device according to any one of appendices 8 to 11, wherein the second insulating film is a gate insulating film of a second transistor formed in the second region.

  (Supplementary note 13) According to any one of supplementary notes 8 to 11, wherein the upper insulating film on the first insulating film is removed after the step of etching the second insulating film. Electronic device manufacturing method.

(Supplementary Note 14) The first insulating film is a gate insulating film of a first transistor formed in the first region,
14. The method of manufacturing an electronic device according to appendix 13, wherein the second insulating film is a gate insulating film of a second transistor formed in the second region.

  (Supplementary Note 15) After the step of etching the second insulating film, the method further includes a step of forming a third insulating film thinner than the first insulating film only in the third region of the substrate. 15. The method for manufacturing an electronic device according to any one of appendices 8 to 14, characterized by:

  (Supplementary note 16) The method for manufacturing an electronic device according to supplementary note 15, wherein the third insulating film is a gate insulating film of a third transistor formed in the third region.

It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by 1st Embodiment in order of a process. FIG. 2 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps following FIG. 1. FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in order of processes following FIG. 2. FIG. 4 is a schematic cross-sectional view subsequent to FIG. 3, illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4, illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps, following FIG. 5. FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 7. FIG. 9 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes subsequent to FIG. 8. It is a schematic sectional drawing which shows the main process of the manufacturing method of the semiconductor device by 2nd Embodiment in order. FIG. 11 is a schematic cross-sectional view sequentially illustrating main steps of the method for manufacturing the semiconductor device according to the second embodiment, following FIG. 10. FIG. 12 is a schematic cross-sectional view sequentially illustrating main steps of the method for manufacturing the semiconductor device according to the second embodiment, following FIG. 11. FIG. 13 is a schematic cross-sectional view sequentially illustrating main steps of the method for manufacturing the semiconductor device according to the second embodiment, following FIG. 12. FIG. 14 is a schematic cross-sectional view sequentially illustrating main steps of the method for manufacturing the semiconductor device according to the second embodiment, following FIG. 13.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Separation groove 3 STI element isolation structure 4, 9 Silicon oxide film 5 Silicon nitride film 6, 8 Resist pattern 7 HfSiO film 11, 12, 13 Gate electrode 14 LDD region 15 Side wall insulating film 16 Source / drain region 17 Silicide layer 18 Interlayer insulating film 19 Contact hole 21 Contact plug 22 Wiring 31 I / O transistor 32 Low leak transistor 33 Logic transistors 34, 35, 36, 41 Gate insulating film

Claims (5)

A substrate in which at least a first region and a second region are defined;
A first insulating film formed only in the first region;
A second insulating film made of an insulating material having a dielectric constant higher than that of the first insulating film and formed only in the second region,
An electronic device, wherein an upper insulating film made of an insulating material having an etching rate lower than that of the second insulating film is formed so as to cover the first insulating film. The laminated film of the first insulating film and the upper insulating film is a gate insulating film of the first transistor formed in the first region,
The electronic device according to claim 1, wherein the second insulating film is a gate insulating film of a second transistor formed in the second region. A third region is further defined in the substrate,
The electronic device according to claim 1, further comprising a third insulating film that is formed only in the third region and is thinner than the first insulating film. Forming a first insulating film on the entire surface above the substrate;
Forming an upper insulating film over the entire surface so as to cover the first insulating film;
Etching the laminated film composed of the first insulating film and the upper insulating film, and leaving the laminated film only in the first region of the substrate;
Forming a second insulating film made of an insulating material having a dielectric constant higher than that of the first insulating film on the entire upper surface of the substrate including the upper insulating film;
Etching the second insulating film, leaving the second insulating film only in the second region of the substrate, and
The upper insulating film is made of an insulating material having an etching rate lower than that of the second insulating film,
In the step of etching the second insulating film, in the first region, the upper insulating film is used as an etching stopper, and the second insulating film on the upper insulating film is removed. Electronic device manufacturing method.   5. The method of manufacturing an electronic device according to claim 4, wherein the upper insulating film on the first insulating film is removed after the step of etching the second insulating film. 6.

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