JP2006112934A - Semiconductor integrated circuit inspection apparatus and inspection method - Google Patents

Abstract

An object of the present invention is to reduce the inspection time of a semiconductor integrated circuit (DUT) to be inspected and perform high-quality inspection at high speed.
An output signal of a DUT 1-1, 1-2 is converted into a DC signal proportional to the amplitude of an AC signal in an RMS / DC converter 3 arranged near a buffer 2 without amplitude loss due to wiring capacitance or the like. To do. The output data is fetched from the A / D converter 11 into the memory 12 in the inspection apparatus body 18 via the high-speed switch 4-1 for DUT1-1, the high-speed switch 4-2 for DUT1-2, and the high-speed switch 4 for DUT selection. . Further, the start and end of loading into the memory 12 and the control of each high-speed switch are collectively performed, and each output signal of the RMS / DC converter 3 is switched at a high speed to continuously record a plurality of DC signals in the memory 12. The data fetched into the memory 12 is obtained by measuring the DC signal of each input / output signal at the target point by the level measuring unit 14 and converting it into an amplitude by the amplitude converting unit 15. The determination unit 16 collates and determines good / bad.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit (hereinafter referred to as IC) inspection apparatus and inspection method.

  The IC is inspected for electrical characteristics before shipment. Although this inspection depends on the scale of the IC, a series of various inspection items are performed in which a rated voltage waveform is applied to the input terminal of the IC over several hundred items and the output voltage waveform obtained from the output terminal is measured. If even one item fails, the IC is determined to be defective and is not shipped. Further, in an IC which is an integrated circuit, a plurality of inputs / outputs are often provided in one IC. In addition, in order to improve inspection efficiency, a simultaneous measurement technique in which input voltage waveforms are simultaneously applied to a plurality of ICs for measurement may be used.

  FIG. 6 shows a configuration diagram of a conventional IC inspection apparatus. FIG. 6 shows an example in which two DUTs are shown as ICs to be inspected (hereinafter referred to as DUTs) 1-1 and 1-2, and two ICs are simultaneously measured to improve inspection efficiency. Each DUT has a plurality of input terminals (IN1 to 3) and a plurality of output terminals (OUT1 to 3). Each input terminal is coupled so that signals can be input simultaneously, and is connected to the termination resistor 5.

  This terminating resistor 5 is used for matching with the signal source output resistor 9 of the signal source 8 included in the inspection apparatus body 18 and uses a value of 50 ohms. Since the six input terminals are coupled to simultaneously input signals to each input terminal, the influence of matching by the input resistance and the termination resistance 5 of the input terminal of each DUT cannot be ignored. As a result, the input signal slightly changes every time the IC is exchanged.

  On the other hand, for each output terminal, one output is selected via the buffer 2 connected to each output terminal, the output switching relay 19 and the DUT switching relay 20 and connected to the inspection apparatus main body 18. Further, by disposing the buffer 2 as close as possible to the output terminal of each DUT, it is possible to reduce the loss due to the wiring capacitance even with a high-frequency signal and to make a structure that can be efficiently connected to the inspection apparatus main body 18. By connecting to the A / D converter 11 in the inspection apparatus body 18 via the coaxial cables 6 and 7, signals can be transmitted efficiently. Further, the test board 17 has SW1 to SW6 as output switching relays 19 for switching signals and input signals from the output terminals of the respective DUTs, and SW7 as DUT switching relays 20.

  The purpose of providing a path through which the input signal to each DUT can be measured is to solve the above-mentioned problem that the input signal slightly changes every time the IC is replaced, and the loss of the buffer 2, each switching relay, A / D This is because the amplitude gain of the DUT is accurately measured without being affected by the accuracy of the converter 11.

  The A / D converter 11 in the inspection apparatus body 18 is connected to the memory 12 and can take in A / D conversion data output from the A / D converter 11. Further, the content of the data fetched into the memory 12 can be obtained by numerical calculation of FFT (Fast Fourier Transform) processing such as average value and amplitude value and RMS (square mean square) processing by the DSP arithmetic processing unit 13, and as a result Is checked against the standard by the determination unit 16 to determine the non-defective product / defective product.

  Next, the operation of the conventional IC inspection apparatus shown in FIG. 6 will be described with reference to the flowchart of FIG. First, signals are simultaneously input to the input terminals of the respective DUTs (Step 1). A signal output via the buffer 2 provided for each output is selected by the output switching relay 19 as OUT1 of the DUT 1-1 (Step 2). Wait until the relay switching is completed (switching on / off of the normal reed relay takes 1 to 3 ms, so take “wait” of 3 to 5 ms for accurate measurement) (Step 3). When the conversion data from the A / D converter 11 is started to be taken into the memory 12 and the point amount necessary for the calculation is reached, the taking of the conversion data from the A / D converter 11 into the memory 12 is stopped (Step 4). Using the data fetched into the memory 12, the DSP arithmetic processing unit 13 such as FFT processing and RMS processing performs arithmetic (Step 5). The calculation result is checked against the standard and determined (Step 6). Thereafter, the processing of step 2 to step 6 is repeatedly performed on all the outputs of each DUT (OUT1 to OUT3 of DUT1-1 and OUT1 to OUT3 of DUT1-2) and the input signals to each DUT, and the total number of processes Is 41 steps.

Next, FIG. 8 shows a specific example of the operation in the flowchart of FIG. 7 as time on the horizontal axis. The passage of time and signal waveform, the timing of loading into the memory, the input signal measurement section (A), the OUT1 measurement section (B), the OUT2 measurement section (C), and the OUT3 measurement section (D) are also shown.
Japanese Patent Laid-Open No. 9-26468

  However, in the prior art, each output of each DUT is switched in order, and after a “wait” necessary for switching the relay is set, a memory flow and numerical calculation are performed each time, and a processing flow is performed. For this reason, even when measuring an early response signal in which the output signal of the IC can ignore the response time, the “wait” time for switching the relay takes longer, resulting in an increase in the inspection time. In addition, the output waveform is A / D converted for each output, fetched into a memory, and subjected to FFT processing, RMS processing, etc., and a plurality of calculations are performed, so there is a problem that it takes much time.

  The present invention is directed to solving the above-described problems of the prior art, and a semiconductor integrated circuit inspection apparatus that performs high-speed and high-quality inspection by reducing the inspection time of a semiconductor integrated circuit (DUT) to be inspected, and The purpose is to provide an inspection method.

  In order to achieve the above object, a semiconductor integrated circuit inspection apparatus according to the present invention is a semiconductor integrated circuit inspection apparatus for simultaneously inspecting a plurality of semiconductor integrated circuits to be inspected having a plurality of input / output terminals. Means for simultaneously inputting input signals to a plurality of input terminals of the integrated circuit, and means for outputting a DC signal proportional to the amplitude of each AC signal from the input signal and the output signals of the plurality of output terminals of the semiconductor integrated circuit to be tested, Each DC signal is switched at high speed to measure amplitude.

  In addition, it has a timing control unit that controls the start and stop of A / D conversion data fetching into the memory and the high-speed switch that switches the DC signal. From the input signal and the output signals of the plurality of output terminals of the semiconductor integrated circuit to be tested The output of each DC signal proportional to the amplitude of each AC signal is continuously taken into a memory by a timing control unit.

  The semiconductor integrated circuit inspection method is a semiconductor integrated circuit inspection method for simultaneously inspecting a plurality of semiconductor integrated circuits to be inspected having a plurality of input / output terminals, and simultaneously inputting input signals to a plurality of input terminals of the semiconductor integrated circuit to be inspected. And a step of measuring the amplitude by switching each DC signal output in proportion to the amplitude of each AC signal from the input signal and the output signals of the plurality of output terminals of the semiconductor integrated circuit to be inspected. And

  Furthermore, it has a step of controlling the timing of starting and stopping the taking in of A / D conversion data into the memory and the control of the high-speed switch for switching the DC signal, and the input signal and the plurality of output terminals of the semiconductor integrated circuit to be inspected. It is characterized in that the output of each DC signal proportional to the amplitude of each AC signal is continuously taken into the memory from the output signal by the step of controlling the timing.

  According to the inspection apparatus and method having the above-described configuration, a DC signal proportional to the AC signal amplitude is output, and the timing for controlling the high-speed selection of the DC signal and the start and end of loading of A / D conversion data into the memory is performed. And a plurality of signal waveforms are continuously recorded in the memory, thereby shortening the inspection time of the semiconductor integrated circuit to be inspected and performing high-quality inspection at high speed.

  According to the present invention, even in the case of a high-frequency signal, loss due to wiring capacitance or the like is greatly reduced, and the calculation processing work is reduced because the signal is converted to a DC signal proportional to the AC signal amplitude on the test board. The recording capacity can be reduced. In addition, the timing control unit comprehensively controls the start and end of A / D conversion data import into the memory and the high-speed switch that switches the DC signal, and the DC signal is switched at high speed to continuously connect multiple signal waveforms. It can be recorded in memory, eliminates the need for conventional “wait” time for relay switching, enables high-speed and high-quality inspection with reduced inspection time, and is extremely large when applied to mass-production inspection that inspects a large amount of ICs. There is an effect that a profit can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an IC inspection apparatus according to Embodiment 1 of the present invention. Here, components corresponding to the components described in FIG. 6 showing the conventional example and having substantially the same functions are denoted by the same reference numerals.

  In FIG. 1, two DUTs are shown as ICs to be inspected (DUTs) 1-1 and 1-2, and a case where two DUTs are measured simultaneously is shown as an example in order to improve inspection efficiency. Each DUT has a plurality of input terminals (IN1 to 3) and a plurality of output terminals (OUT1 to 3). Each input terminal is coupled so that signals can be input simultaneously, and is connected to the termination resistor 5.

  The terminating resistor 5 is used for matching with the signal source output resistor 9 of the signal source 8 included in the inspection apparatus body, and uses a value of 50 ohms. Since the six input terminals are coupled to simultaneously input signals to each input terminal, the influence of matching due to the input resistance and termination resistance 5 of the input terminal of each DUT cannot be ignored. As a result, the input signal slightly changes every time the IC is exchanged.

  On the other hand, each output terminal includes a buffer 2 connected to each output terminal, an RMS / DC converter 3 that converts an AC signal into a DC signal, a high-speed switch 4-1 for DUT1-1 and a high-speed switch 4-2 for DUT1-2, One output is selected via the DUT selection high-speed switch 4 and connected to the inspection apparatus body 18. The RMS / DC converter 3 for converting an AC signal into a DC signal uses a conversion device using semiconductor technology, and is converted into a DC signal proportional to the amplitude of the AC signal.

  Further, by arranging the RMS / DC converter 3 near the buffer 2, it is converted into a DC signal without any loss of amplitude due to wiring capacitance or the like. Each high-speed switch uses an electronic switch using semiconductor technology. Further, there is an object of efficiently transmitting signals by connecting the test board 17 to the A / D converter 11 in the inspection apparatus main body 18 through the coaxial cables 6 and 7. The DUT 1-1 high-speed switch 4-1 and the DUT 1-2 high-speed switch 4-2 are used not only for switching the output of the DUT but also for selecting an input signal.

  The purpose of providing a path through which the input signal to each DUT can be measured is to solve the problem that the input signal changes slightly each time the IC is replaced, and the buffer 2, the loss of each high-speed switch, the A / D converter 11 This is because the amplitude gain of the DUT is accurately measured without being affected by the accuracy. The reason why each DUT has an input signal measurement path is that it is possible to accurately measure the input signal by arranging it close to each DUT, and to eliminate the influence of the loss difference of the DUT selection high-speed switch 4. is there. Each high-speed switch can accurately control the on / off timing on the time axis by the timing control unit 10 in the inspection apparatus main body 18.

  The A / D converter 11 in the inspection apparatus main body 18 is connected to the memory 12 and can take in the data output from the A / D converter 11. Furthermore, the content of the data captured in the memory 12 can be measured by measuring the level of the DC signal corresponding to each input / output signal at each target point by the level measuring unit 14 and converting it into an amplitude by the amplitude converting unit 15. The result is checked against the standard by the determination unit 16 to determine the non-defective product / defective product.

  Next, the operation of the IC inspection apparatus according to the first embodiment shown in FIG. 1 will be described with reference to the flowchart of FIG. First, signals are simultaneously input to the input terminals of the respective DUTs (Step 101). Each of the signals is converted into a DC signal proportional to the amplitude by the RMS / DC converter 3 through the buffer 2 connected to each output terminal (Step 102). The import of the conversion data from the A / D converter 11 to the memory 12 is started (Step 103). A DC signal converted by each RMS / DC converter 3 is continuously switched by a high-speed switch, and a plurality of waveforms are recorded in the memory 12 (Step 104). The import of the conversion data from the A / D converter 11 to the memory 12 is stopped (Step 105). The DC level corresponding to each output terminal is measured from the contents of the memory 12 at the target point (Step 106). An operation for converting the amplitude of the DC level corresponding to each output is performed (Step 107). The calculation result is checked against the standard to make a determination (Step 108).

  Next, waveforms at each point in the operation of the flowchart of FIG. 2 are shown in FIGS. 3 (a), (b), (c), and (d). 3, the four types of waveforms (a) to (d) are the AC signal of the input signal (a) of the buffer 2 at the output terminal portion of each DUT at the measurement point J shown in FIG. 1, and the measurement points shown in FIG. The output signal (b) of the K buffer 2, the output signal (c) of the RMS / DC converter 3 at the measurement point L shown in FIG. 1, and the A / D converter input signal (d) at the measurement point M shown in FIG. . In addition, memory fetch timing and DC level measurement points (P1) to (P8) are also shown.

  Next, the difference between the first embodiment and the prior art will be described. In the conventional case, each output of each DUT is switched in order, waiting for the time required for switching the relay, and taking the memory for each output and performing DSP arithmetic processing, so the relay switching “wait” Time and time required for DSP calculation processing are required, and much inspection time is required.

  In the case of the first embodiment, first, each output signal and input signal of each DUT is converted from an AC signal to a DC signal on the test board 17, so that there is no need for amplitude calculation by the conventional DSP calculation processing unit 13. . Also, the amount of conversion data from the A / D converter 11 taken into the memory 12 can be taken in small because the DC level is only measured at the target point. Furthermore, even in the case of a high-frequency signal, since the AC signal is converted into a DC signal near each input / output terminal, loss due to wiring capacitance or the like can be greatly reduced, and high-accuracy gain measurement can be performed.

  Next, the timing control unit 10 of the inspection device collectively controls the start and end of the conversion data from the A / D converter 11 to the memory 12 and the high-speed switch, and controls each RMS / DC converter 3. Since the DC signal output is switched at a high speed and a plurality of signal waveforms are continuously recorded in the memory 12, the “wait” time required for switching the conventional relay is unnecessary, and the inspection time can be shortened. Therefore, high-speed and high-quality inspection can be provided.

  FIG. 4 is a block diagram showing an IC inspection apparatus according to Embodiment 2 of the present invention. In FIG. 4, the difference from the first embodiment described above is an example in which the number of DUTs is three or more. However, the basic operational effects are the same as those of the first embodiment, and the inspection time can be shortened and high-quality inspection can be performed at high speed.

  FIG. 5 is a block diagram showing an IC inspection apparatus according to Embodiment 3 of the present invention. In FIG. 5, the difference from the first embodiment described above is an example in which the number of DUTs is one and there are three or more input / output terminals. As a result, there is no DUT selection high-speed switch 4 for switching the DUT. However, in the case of the third embodiment, the basic operational effects are the same as those of the first embodiment, and the inspection time can be shortened and high-quality inspection can be performed at high speed.

  The inspection apparatus and inspection method for a semiconductor integrated circuit according to the present invention greatly reduces the loss of wiring capacitance and the like even for a high-frequency signal, and converts it into a DC signal proportional to the AC signal amplitude on the test board, thereby reducing arithmetic processing. Furthermore, the recording capacity to the memory can be reduced, and the timing control unit comprehensively controls the start and end of the A / D conversion data to the memory and the high-speed switch for switching the DC signal. , DC signals can be switched at high speed, and multiple signal waveforms can be recorded continuously in memory, eliminating the “wait” time of conventional relay switching, reducing inspection time, enabling high-speed and high-quality inspection, It is useful as an inspection apparatus and method in an inspection semiconductor integrated circuit.

The block diagram which shows the inspection apparatus of IC in Embodiment 1 of this invention Flowchart showing the operation of the IC inspection apparatus according to the first embodiment. The figure which shows the signal waveform (a) of the measurement point J in this Embodiment 1, the signal waveform (b) of the measurement point K, the signal waveform (c) of the measurement point L, and the signal waveform (d) of the measurement point M The block diagram which shows the test | inspection apparatus of IC in Embodiment 2 of this invention The block diagram which shows the inspection apparatus of IC in Embodiment 3 of this invention Configuration diagram showing a conventional IC inspection device Flow chart showing operation of conventional IC inspection apparatus The figure which shows concrete operation in the conventional IC inspection device

Explanation of symbols

1 DUT (Semiconductor Integrated Circuit)
2 Buffer 3 RMS / DC converter 4 DUT selection high-speed switch 5 Terminating resistors 6 and 7 Coaxial cable 8 Signal source 9 Signal source output resistor 10 Timing control unit 11 A / D converter 12 Memory 13 and 13 ′ DSP arithmetic processing unit 14 Level Measurement unit 15 Amplitude conversion unit 16 Determination unit 17 Test board 18 Inspection device body 19 Output switching relay 20 DUT switching relay

Claims (4)

  In a semiconductor integrated circuit inspection apparatus for simultaneously inspecting a plurality of semiconductor integrated circuits to be inspected having a plurality of input / output terminals, means for simultaneously inputting input signals to a plurality of input terminals of the semiconductor integrated circuit to be inspected, and the input signals Means for outputting a DC signal proportional to the amplitude of each AC signal from the output signals of the plurality of output terminals of the semiconductor integrated circuit to be inspected, and switching the DC signals at high speed to measure the amplitude. Integrated circuit inspection equipment.   A timing control unit is provided for controlling the start and stop of taking A / D conversion data into the memory and the high-speed switch for switching the DC signal. From the input signal and the output signals of the plurality of output terminals of the semiconductor integrated circuit to be inspected 2. The semiconductor integrated circuit inspection apparatus according to claim 1, wherein the output of each DC signal proportional to the amplitude of each AC signal is continuously taken into the memory by the timing control unit.   In a semiconductor integrated circuit inspection method for simultaneously inspecting a plurality of semiconductor integrated circuits to be inspected having a plurality of input / output terminals, a step of simultaneously inputting input signals to a plurality of input terminals of the semiconductor integrated circuit to be inspected, and the input signals And a step of measuring the amplitude by switching at high speed each DC signal output in proportion to the amplitude of each AC signal from the output signals of the plurality of output terminals of the semiconductor integrated circuit to be inspected. Method.   A step of controlling the start and stop of taking A / D conversion data into the memory and the control of the high-speed switch for switching the DC signal, and the step of controlling the input signal and the plurality of output terminals of the semiconductor integrated circuit to be inspected. 4. The method for inspecting a semiconductor integrated circuit according to claim 3, wherein the output of each DC signal proportional to each AC signal amplitude from the output signal is continuously taken into the memory by the step of controlling the timing.

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