JP2008186829A - Tool for inspecting wafer, and measurement method using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a normal operation test needs to be executed to inspect a wafer for shipping to a client in a wafer state and two kinds of wafer inspection tools must be prepared for testing input/output compression and normal operation although efficiency in wafer inspection is improved and costs are reduced by the wafer inspection as the input/output compression test. <P>SOLUTION: The wafer inspection tool can be connected to a plurality of semiconductor devices to be tested by branching an input/output signal line from a testing device (tester) and connecting it to a plurality of probes, thus achieving the input/output compression test and a normal operation test by a single wafer inspection tool. In the case of the input/output compression test, a plurality of semiconductor devices to be tested is measured simultaneously. In the case of the normal operation test, the semiconductor devices to be tested can be measured simultaneously or individually. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to measurement of a semiconductor device, and more particularly to a wafer inspection tool capable of efficiently performing wafer inspection for testing a semiconductor device in a wafer state and a measurement method using the tool.

  A semiconductor device is manufactured through many manufacturing processes and shipped to a customer. As a pre-process (diffusion process) of the semiconductor device, a film formation process, a photolithography process, and an impurity diffusion process are repeatedly performed on the semiconductor substrate. Through these many steps, a wafer on which a plurality of semiconductor devices are formed is completed. The completed wafer is subjected to a wafer inspection process for confirming the operation of the formed semiconductor device, and the quality is determined. Wafer inspection is performed by probing a probe of an inspection jig on a pad of a semiconductor device. Further, as a post-process (assembly process), the wafer is diced and separated into individual semiconductor devices. After that, it goes through a packaging process and an assembly inspection process, and is shipped as a product enclosed in a plastic resin or the like.

  As described above, the semiconductor device is subjected to wafer inspection in a wafer state and assembly inspection after assembling the package. Due to the large scale and high integration of semiconductor devices, these inspection times are very long. Therefore, a plurality of semiconductor devices are inspected simultaneously, the inspection time per semiconductor device is shortened, and the inspection cost is reduced. For example, when the number of simultaneous measurements is 2, the inspection cost can be reduced to half, and when it is 8, the inspection cost can be reduced to 1/8.

  In a semiconductor device having a large number of input / output terminals, the number of simultaneous measurements is limited by the number of input / output signal lines of a test device (tester). In wafer inspection, inspection of some input / output terminals is further omitted for efficiency, and a simplified input / output compression test is performed. Since some input / output terminals are not inspected, the number of simultaneous measurements can be increased. In this way, the input / output compression test is used to improve wafer inspection efficiency and reduce costs. In the inspection after the package is assembled, a normal operation test for inspecting all the input / output terminals is performed. In this way, the wafer inspection in the middle of the process is a simple inspection, but in the assembly inspection before shipment, the normal operation test for all the input / output terminals is performed, so that the shipping quality level of the semiconductor device is ensured. .

  Recently, however, there are cases where a semiconductor device is assembled as a SIP (System In Package) or the like on the customer side for further miniaturization of electronic equipment. In this case, the semiconductor device in a wafer state is shipped to the customer. In this case, the input / output compression test alone is not sufficient, and it is necessary to add a normal operation test in the wafer state. For this reason, it is necessary to prepare a wafer inspection jig for a normal operation test and to perform the wafer inspection as a normal operation test. Therefore, there arises a problem that a wafer inspection jig for at least an input / output compression test and a normal operation test must be prepared for wafer inspection.

  There are the following documents as prior patent documents related to a method for measuring a semiconductor device. In Patent Document 1 (Japanese Patent Laid-Open No. 7-98357), the input signal levels of half of the semiconductor devices that are simultaneously measured are inverted, thereby reducing noise between the input and output terminals and stabilizing the power supply line. In Patent Document 2 (Japanese Patent Laid-Open No. 63-191976), the measurement order is freely set by switching the terminals connected to the measurement circuit with the bits of the register. In Patent Document 3 (Japanese Patent Laid-Open No. 59-35442), in wafer inspection, it is determined whether simultaneous measurement is performed based on a determination signal indicating whether the probe is on the wafer. However, these prior documents do not describe anything related to the above-described problems of the present invention and the techniques for solving the problems.

JP-A-7-98357 JP-A-63-191976 JP 59-35442 A

  As described above, the wafer inspection is an input / output compression test to improve the efficiency of wafer inspection and reduce costs. However, when a wafer is shipped to a customer, it is necessary to perform a normal operation test as a wafer inspection. Therefore, there is a problem that it is necessary to prepare respective wafer inspection jigs for the input / output compression test and the normal operation test. An object of the present invention is to provide a wafer inspection jig capable of performing both an input / output compression test and a normal operation test, and a measuring method thereof.

  In order to solve the above-described problems, the present application basically employs the techniques described below. Needless to say, application techniques that can be variously changed without departing from the technical scope of the present invention are also included in the present application.

  The jig for wafer inspection of the present invention includes a wiring and a probe for connecting a signal from a test apparatus (tester) to a pad of a semiconductor device under test, and branches an input / output signal from the test apparatus, An input / output branch wiring connected to each input / output probe for a plurality of semiconductor devices under test is provided.

  The jig for wafer inspection according to the present invention further includes a selection signal wiring for connecting a selection signal for selecting any one of a plurality of semiconductor devices to be tested, and a selection signal probe.

  The input / output branch wiring of the jig for wafer inspection according to the present invention includes an input / output probe used for an input / output compression test of one semiconductor device under test and an input / output of a semiconductor device under test other than the semiconductor device under test. It is characterized by connecting an input / output probe not used for the compression test.

  The branch wiring of the jig for wafer inspection according to the present invention is characterized by connecting the same input / output probes of a plurality of semiconductor devices under test.

  The measuring method of the present invention is a measuring method using the above-described jig for wafer inspection, and in a normal operation test for inspecting all inputs and outputs of the semiconductor device under test, a part of the semiconductor devices under test are selected by a selection signal. Select and inspect all the inputs and outputs of the selected semiconductor device under test, and select all of the semiconductor devices under test by the selection signal during the input and output compression test that inspects part of the input and output of the semiconductor device under test. The semiconductor device is characterized by using a part of input / output of the selected semiconductor device to be tested.

  The measuring method of the present invention is characterized in that the input / output of the semiconductor device under test that has not been selected by the selection signal during the normal operation test is in a high impedance state.

  The measurement method of the present invention is characterized in that, during the input / output compression test, the input / output not used by the semiconductor device under test is in a high impedance state.

  The measuring method of the present invention is a measuring method using the above-described jig for wafer inspection, and selects all semiconductor devices under test by a selection signal during a normal operation test in which all inputs / outputs of the semiconductor devices under test are inspected. After inputting the input signals simultaneously, select only a part of the semiconductor device under test by the selection signal, inspect the output signal, and select the input signal during the input / output compression test that inspects the part of the input / output of the semiconductor device under test. After selecting all the semiconductor devices under test and inputting the input signals simultaneously, only some of the semiconductor devices under test are selected by the selection signals and the output signals are inspected.

  The measuring method of the present invention is characterized in that the input / output of the semiconductor device under test not selected by the selection signal is in a high impedance state during the normal operation test and the input / output compression test.

  The wafer inspection tool of the present invention can be connected to a plurality of semiconductor devices under test using input / output signal lines from a test apparatus (tester) as branch wirings. In the case of the input / output compression test, a plurality of semiconductor devices under test are measured simultaneously. In the case of a normal operation test, simultaneous measurement or measurement of each semiconductor device under test is performed. According to the present invention, an input / output compression test and a normal operation test can be performed with a single wafer inspection jig. Therefore, it is not necessary to prepare the respective wafer inspection jigs for the input / output compression test and the normal operation test, and the effect of reducing the jig production cost can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. FIG. 1 shows a measurement method for the first wafer inspection tool, and FIG. 2 shows a block diagram for explaining the measurement method for the second wafer inspection tool. In the inspection of a semiconductor device having a large number of input / output terminals (hereinafter referred to as input / output pads), the present invention simultaneously inspects a plurality of semiconductor devices by using a test jig for connecting the input / output pads of the plurality of semiconductor devices. It is possible to do.

  In wafer inspection, a wafer is set on a stage, and a probe (probe) of a wafer inspection jig is brought into contact with a pad of each semiconductor device. A test signal is supplied from the test apparatus to inspect the semiconductor device. When one inspection is completed, the stage steps and repeats, and the next inspection is performed. By step-and-repeat, all semiconductor devices on the wafer are inspected sequentially. Therefore, the wafer inspection tool includes a plurality of signal wires from the test apparatus and probes (probes) that are brought into contact with pads of the semiconductor device.

  In the present invention, in order to simplify the description, the following state will be described. The semiconductor device under test 20 is a semiconductor device including 16 input / output pads 1 to 16 and a semiconductor device selection signal pad CS. Of the 16 input / output pads 1 to 16, input / output pads 1 to 8 are input / output pads A to H used for an input / output compression test, and input / output pads 1 to 8 and 9 to 16 are used for a normal operation test. I / O pad to be used. The semiconductor device selection signal CS is a signal that allows the semiconductor device to perform a selection operation. For example, the semiconductor device selection signal CS is a signal having the same function as the selection signal of the semiconductor device or the input / output mask signal DQM that selects the input / output operation. Assume that two semiconductor devices 20A and 20B are simultaneously measured.

  Therefore, the jigs and tools used during the input / output compression test are 8 input / output probes for the semiconductor device under test, and the jigs and tools used during the normal operation test are equipped with 16 input / output probes. In the conventional jig / tool, the signal wiring from the test apparatus is connected to the probe at 1: 1. However, these numbers are not particularly limited, and the number of input / output pads and the number of semiconductor devices under test to be simultaneously measured can be appropriately selected. Further, the test apparatus 40 has a large number of input / output signal lines, and a wafer inspection jig also includes a plurality of sets of wirings and probes shown in the drawing. However, since each wiring and probe have the same functional operation, only one set is shown in the figure. Although not shown, the semiconductor device includes a power supply line and other control signals.

  A measuring method in the first wafer inspection jig 31 shown in FIG. 1 will be described. The wafer inspection jig 31 connects each semiconductor device selection signal CS from the test apparatus (tester) 40 to each probe 30 for the semiconductor devices 20A and 20B to be tested. The input / output signals are branched and connected to the probes corresponding to the input / output pads 1 to 16 of the semiconductor device under test 20A and the same probes corresponding to the input / output pads 1 to 16 of the semiconductor device under test 20B, respectively. Accordingly, the input / output signals are connected to the same numbered pads of the semiconductor devices 20A and 20B to be tested.

  When the wafer inspection jig 31 is used, outputs are simultaneously output from the input / output pads 1 to 16 of the semiconductor devices under test 20A and 20B. The two outputs of the test semiconductor devices 20A and 20B collide, and the test device 40 cannot determine PASS and FAIL. Therefore, input signals can be input simultaneously, but output signals are individually inspected without being output simultaneously.

  When the normal operation test is performed, the semiconductor device selection signal CS is input to the semiconductor devices 20A and 20B to be simultaneously measured, and the respective input signals are further input. Since the input wirings of the semiconductor devices 20A and 20B are both connected in common, the input signals are input simultaneously. Thereafter, the output signal of the semiconductor device 20A is first inspected. Therefore, the semiconductor device selection signal CS of the semiconductor device 20A is left in the selected state, and the semiconductor device selection signal CS of the semiconductor device 20B is in the non-selected state. By doing so, since no output is made from the semiconductor device 20B, only the semiconductor device 20A can be inspected. The semiconductor test apparatus may perform normal output determination. The input / output in the non-selected state is in a high impedance state and does not adversely affect the partner pads connected in common.

  Next, the semiconductor device selection signal CS of the semiconductor device 20A is set to a non-selected state, and the semiconductor device selection signal CS of the semiconductor device 20B is set to a selected state. The semiconductor device 20B inspects its output in the selected state. When inspecting by this method, the output signal must be inspected twice for each semiconductor device, but there is no problem in the semiconductor device even if the input signal is inspected once. In this way, the input signals can be input simultaneously by commonly connecting the input / output signals. As a result, it is possible to increase the number of simultaneous measurements without performing input / output compression, and thus it is possible to cope with a normal operation test. Therefore, the inspection time per semiconductor device can be shortened.

  The effect of shortening the inspection time in this case will be described. When the normal operation test is performed, for example, the input / output data bus width of the existing semiconductor inspection apparatus is 160, and the input / output of the semiconductor apparatus is 16. In this case, 10 semiconductor devices can be measured at a time. In the present invention, since one input / output data bus of the semiconductor inspection apparatus is supplied to two semiconductor devices, the number of semiconductor devices that can be measured at one time is doubled to 20.

  The test time in this case is as follows. For example, the inspection time in the semiconductor device is 100 seconds, of which the time related to input / output is 50 seconds, and the others are 50 seconds. Of these, the test time is different in terms of input / output. Of these, the input signals can be simultaneously input to the semiconductor device at the same time. Therefore, the time is different only in the time related to the output. If the ratio of input to output is halved, the time related to output is 25 seconds. In this method, since the output is one semiconductor device at a time, it takes twice as much time 50 seconds to output all the semiconductor devices. The time required for input / output is 75 seconds. Another test time of 50 s is added, resulting in a total test time of 125 seconds in this method.

  When 1000 semiconductor devices are mounted per wafer, the total time required for one wafer is 100 seconds × 100 = 10000 because the conventional method requires 100 measurements. It takes seconds. In this method, it is sufficient to perform 50 measurements, and 125 seconds × 50 = 6250 seconds, and there is an effect of time reduction of 10,000-6250 = 3750 seconds per wafer. A time reduction effect of 37% is obtained.

  Next, the case of the input / output compression test will be described. Also in this case, since the semiconductor devices are connected to the same pad, the normal operation test is performed in the same manner. Therefore, input signals are input simultaneously, and output signals are individually inspected. Consider the efficiency of the I / O compression test. In the case of the input / output compression test, 8 inputs and outputs are used, and 20 simultaneous measurements are performed. In the case of this wafer inspection tool, it is necessary to select which semiconductor device 20A or 20B at the time of output. Therefore, since the output time is doubled, the inspection efficiency is lowered with respect to the jig dedicated to the input / output compression test.

  In the case of the wafer inspection jig 31, the efficiency is improved when the wafer inspection is performed by a normal operation test. On the other hand, in the case of the input / output compression test, the efficiency decreases. Therefore, the effect is great if it is applied to the case where there are many wafer inspections in the normal operation test. In this case, the normal operation test and the input / output compression test can be performed by using one type of wafer inspection jig 31 and the efficiency of wafer inspection can be improved.

  Next, FIG. 2 shows a wafer inspection jig that can obtain the same inspection efficiency by replacing the two types of wafer inspection jigs for the input / output compression test and the normal operation test with one wafer inspection jig. In the second wafer inspection tool 32 shown in FIG. 2, each semiconductor device selection signal CS from the test apparatus 40 is connected to each probe 30 for the semiconductor devices 20A and 20B to be tested. The input / output signal connects the probes for the input / output pads 1 to 8 of the semiconductor device 20A to be tested and the probes for the input / output pads 9 to 16 of the semiconductor device 20B by branch wiring. The probes for the input / output pads 9 to 16 of the remaining semiconductor device 20A to be tested are connected to the probes for the input / output pads 1 to 8 of the semiconductor device 20B. Thus, the connections between the probes of the wafer inspection jig 32 are connected to different terminals.

  Probes for pads (A, B, C, D, E, F, G, H) used for the input / output compression test of the semiconductor device 20A, and pads (9, 10,. 11, 12, 13, 14, 15, 16) are connected in numerical order as shown in the figure. Probes for pads (A, B, C, D, E, F, G, H) used for the input / output compression test of the semiconductor device 20B, and pads (9, 10,. 11, 12, 13, 14, 15, 16) are connected in order of numbers.

  The normal operation test using the wafer inspection jig 32 is not individual measurement but individual measurement because the terminal connections are different. The normal operation test of the semiconductor device 20A is performed with the semiconductor device selection signal CS of the semiconductor device 20A in a selected state and the semiconductor device selection signal CS of the semiconductor device 20B in a non-selected state. The semiconductor device 20A is selected, and only the semiconductor device 20A is inspected. At this time, the semiconductor device 20B is not selected, and its input / output pad is in a high impedance (Hi-Z) state, and does not affect the operation of the semiconductor device 20A.

  Conversely, the normal operation test of the semiconductor device 20B is performed with the semiconductor device selection signal CS of the semiconductor device 20A set to the non-selected state and the semiconductor device selection signal CS of the semiconductor device 20B set to the selected state. The semiconductor device 20B is selected, and only the semiconductor device 20B is inspected. At this time, the semiconductor device 20A is not selected, and its input / output pad is in a high impedance (Hi-Z) state, and does not affect the operation of the semiconductor device 20B.

  The input / output compression test using the wafer inspection jig 32 has different terminal connections, so that the semiconductor devices 20A and 20B can perform simultaneous measurement. The input / output compression test is performed with both the semiconductor device selection signals CS of the semiconductor devices 20A and 20B selected. The input / output signals at the time of each input / output compression test are simultaneously measured using eight halves of the 16 signal lines. At this time, the pads (9 to 16) that are not used in the input / output compression test are set to a high impedance (Hi-Z) state. Since it is in a high impedance state, the operation of each of the semiconductor devices 20A and 20B is not affected.

  Consider the inspection efficiency when the wafer inspection jig 32 is used. For example, the input / output data bus width of the existing semiconductor inspection apparatus is 160, and the input / output of the semiconductor apparatus is 16. When performing a normal operation test, 10 semiconductor devices can be measured at a time. In the present invention, the 16 input / output data buses of the semiconductor inspection apparatus are supplied to two semiconductor devices, respectively. However, since the two semiconductor devices are inspected separately, the number of semiconductor devices that can be measured at one time is also ten. Therefore, the inspection efficiency equivalent to the case of using the wafer inspection jig dedicated for the normal operation test can be obtained.

  When the input / output compression test is performed, the number of inputs / outputs to be inspected for one semiconductor device is eight, and 20 semiconductor devices can be measured at one time. In the present invention, the 16 input / output data buses of the inspection apparatus are supplied to two semiconductor devices, respectively. The eight inputs / outputs to be inspected in the input / output compression test of the two semiconductor devices are connected to the respective separate input / output data buses and can be measured simultaneously. Similarly, the number of semiconductor devices that can be measured at one time is 20. Accordingly, the inspection efficiency equivalent to the case of using the wafer inspection jig dedicated to the input / output compression test can be obtained.

  In the case of the wafer inspection jig 32, both the normal operation test and the input / output compression test have the same inspection efficiency as the wafer inspection performed using the wafer inspection jig dedicated to the normal operation test and the input / output compression test. Therefore, one type of wafer inspection tool may be created instead of two types of wafer inspection tool, and the number of steps and cost for creating the wafer inspection tool can be reduced. Furthermore, since a normal operation test and an input / output compression test can be performed with one type of wafer inspection tool, work time for exchanging the wafer inspection tool becomes unnecessary, and the efficiency of wafer inspection can be improved.

  The wafer inspection tool of the present invention branches input / output signal lines from a test apparatus (tester) and connects them to a plurality of probes. By making the wiring of the wafer inspection jig a branch wiring, it is possible to connect to a plurality of semiconductor devices under test. In the case of the input / output compression test, a plurality of semiconductor devices under test are measured simultaneously. In the normal operation test, the semiconductor devices under test are measured simultaneously or individually. According to the present invention, both an input / output compression test and a normal operation test can be performed with a single wafer inspection jig. Therefore, it is not necessary to prepare the respective wafer inspection jigs for the input / output compression test and the normal operation test, and the effect of reducing the jig production cost can be obtained.

  Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. Needless to say, this is also included in the present application.

It is a block diagram explaining a measuring method using the 1st inspection device jig in the present invention. It is a block diagram explaining a measuring method using the 2nd inspection device jig in the present invention.

Explanation of symbols

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 Input / output pads A, B, C, D, E, F, G, H Input Input / output pad CS used for output compression test Semiconductor device selection signal (pad)
20A, 20B Semiconductor device under test 30 Probe 31, 32 Wafer inspection tool 40 Test device (tester)

Claims (9)

  In a wafer inspection jig equipped with a wiring and a probe for connecting a signal from a test device (tester) to a pad of a semiconductor device under test, an input / output signal from the test device is branched to provide a plurality of devices under test. A jig for wafer inspection, comprising an input / output branch wiring connected to each input / output probe for a test semiconductor device.   2. The jig for wafer inspection according to claim 1, further comprising a selection signal wiring for connecting a selection signal for selecting any one of a plurality of semiconductor devices to be tested, and a selection signal probe. .   The input / output branch wiring includes an input / output probe used for an input / output compression test of one semiconductor device under test, and an input / output probe not used for an input / output compression test of a semiconductor device under test other than the semiconductor device under test The jig for wafer inspection according to claim 2, wherein:   The jig for wafer inspection according to claim 2, wherein the branch wiring connects the same input / output probes of a plurality of semiconductor devices under test. 4. A measurement method using the jig for wafer inspection according to claim 3, wherein a part of the semiconductor device under test is selected by a selection signal during a normal operation test in which all inputs and outputs of the semiconductor device under test are inspected. Inspect all inputs and outputs of the selected semiconductor device under test,
During an input / output compression test in which a part of the input / output of the semiconductor device under test is inspected, all the semiconductor devices under test are selected by the selection signal, and a part of the input / output of the selected semiconductor device under test is used for the inspection. A measuring method characterized by the above.   6. The measuring method according to claim 5, wherein the input / output of the semiconductor device under test that is not selected by the selection signal is set to a high impedance state during the normal operation test.   6. The measuring method according to claim 5, wherein in the input / output compression test, the unused input / output of the semiconductor device under test is in a high impedance state. 5. A measuring method using the jig for wafer inspection according to claim 4, wherein during a normal operation test for inspecting all inputs and outputs of the semiconductor device under test, all the semiconductor devices under test are selected and inputted by a selection signal. After inputting the signals at the same time, select only a part of the semiconductor device under test by the selection signal and inspect the output signal,
During an input / output compression test that tests part of the input / output of the semiconductor device under test, after selecting all the semiconductor devices under test using the selection signal and inputting the input signals simultaneously, only some of the semiconductor devices under test using the selection signal And measuring an output signal.   6. The measuring method according to claim 5, wherein the input / output of the semiconductor device under test not selected by the selection signal is in a high impedance state during the normal operation test and the input / output compression test.

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