JP2005191341A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having an oxide high dielectric constant insulating film having a small hysteresis and a small flat band voltage change ΔVfb as a gate insulating film.
A semiconductor device includes a silicon substrate, a silicon oxide layer formed on the surface of the silicon substrate, a first oxide layer formed on the silicon oxide layer, and a second oxide formed thereon. And a high dielectric constant insulating layer including a third oxide layer formed thereon, wherein the first oxide layer and the third oxide layer have a smaller oxygen diffusion coefficient than the second oxide layer. A high dielectric constant insulating layer, and a gate electrode formed on the high dielectric constant insulating layer.
[Selection] Figure 1

Description

    The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a high dielectric constant insulating film and a manufacturing method thereof.

  As a typical semiconductor element used in a semiconductor integrated circuit device, an insulated gate (IG) field effect transistor (FET) typified by a MOS transistor is widely used. In order to achieve high integration of semiconductor integrated circuit devices, IG-FETs have been miniaturized according to scaling rules. Miniaturization makes it possible to reduce the dimensions of the IG-FET, such as reducing the thickness of the gate insulating film, shortening the gate length, etc., maintaining the performance of the miniaturized element normally, and improving the performance.

  The thickness of the gate oxide film of the next generation MOS transistor is required to be reduced to 2 nm or less. This film thickness is the thickness at which the tunnel current starts to flow directly, and the gate leakage current increases and the power consumption increases. As long as silicon oxide is used as the gate insulating film, there is a limit to miniaturization. In order to suppress a tunnel current passing through the gate insulating film, it is desirable to use a thick gate insulating film.

  In order to increase the physical film thickness while reducing the equivalent film thickness of the gate insulating film to 2 nm or less, a proposal has been made to use a high dielectric constant insulating material having a dielectric constant higher than that of silicon oxide for the gate insulating film. The relative dielectric constant of silicon oxide is said to be about 3.5 to 4.5 (for example, 3.9) depending on the film forming method. Silicon nitride has a higher dielectric constant than silicon oxide, and the relative dielectric constant is said to be about 7-8 (for example, 7.5).

JP 2001-274378 A has a dielectric constant higher than that of silicon oxide as a gate insulating film (barium titanate (Ba (Sr) TiO ₃ ) having a relative dielectric constant of 200 to 300); ) Titanium oxide (TiO ₂ ); (dielectric constant is around 25) Tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ); (dielectric constant is about 7.5) It is proposed to use silicon nitride (Si ₃ N ₄ ); alumina (Al ₂ O ₃ ) (with a relative dielectric constant of about 7.8). In addition, a structure in which a silicon oxide film is interposed between the high dielectric constant insulating material film and the silicon substrate is also proposed.

JP, 2001-274378, A When a new material with a high dielectric constant is adopted as a gate insulating film of IG-FET, a new problem will also arise. Zirconium oxide and hafnium oxide are crystallized by high-temperature treatment, and leakage current increases due to electric conduction through crystal grain boundaries and defect levels. In order to promote the practical application of new materials, it is desirable to solve new problems.

  Japanese Patent Laid-Open No. 2001-77111 proposes that the addition of aluminum oxide to zirconium oxide or hafnium oxide inhibits the formation of a crystal structure and maintains an amorphous phase.

  JP 2003-8011 proposes to increase the thermal stability by adding silicon oxide to hafnium oxide.

JP 2001-77111 A JP 2003-8011 A

  In Japanese Patent Laid-Open No. 2003-23005, when a high dielectric constant material (High-k material) layer made of a metal oxide film is formed on a silicon substrate, a silicon oxide layer is formed at the interface between the metal oxide film and the silicon substrate. It is pointed out that the dielectric constant is lowered, and it is proposed to flow hydrogen instead of oxygen before forming the metal oxide film.

Japanese Patent Laid-Open No. 2002-359370 discloses nitrogen atoms on both surfaces of a high dielectric constant gate insulating film in order to suppress impurity diffusion from the gate electrode to the silicon substrate and diffusion of metal elements and oxygen from the gate insulating film to the gate electrode or silicon substrate. It is proposed to form a layer.
JP 2003-23005 A JP 2002-359370 A

An object of the present invention is to provide a semiconductor device having a gate insulating film using a high dielectric constant insulating material having a dielectric constant higher than that of silicon oxide.
Another object of the present invention is to provide a method for manufacturing a semiconductor device, in which a high dielectric constant insulating material having a dielectric constant higher than that of silicon oxide can be formed as a gate insulating film.

Still another object of the present invention is to provide a semiconductor device using a high dielectric constant oxide film with reduced flat band voltage change and hysteresis as a gate insulating film.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a high dielectric constant oxide film with reduced flat band voltage change and hysteresis as a gate insulating film.

  According to one aspect of the present invention, a silicon substrate, a silicon oxide layer formed on the surface of the silicon substrate, a first oxide layer formed on the silicon oxide layer, and a second oxide formed thereon A high dielectric constant insulating layer including a physical layer and a third oxide layer formed thereon, wherein the first oxide layer and the third oxide layer have a smaller oxygen diffusion coefficient than the second oxide layer There is provided a semiconductor device having a high dielectric constant insulating layer and a gate electrode formed of an oxidizable material on the high dielectric constant insulating layer.

  According to another aspect of the present invention, (a) a step of removing the natural oxide film on the surface of the silicon substrate by wet etching, and (b) a base silicon oxide layer is formed on the silicon substrate surface from which the natural oxide film has been removed by chemical treatment. And (c) forming a first high dielectric constant oxide layer by CVD on the underlying silicon oxide layer at a first oxygen supply rate, and (d) the first high dielectric constant oxide. Forming a second high dielectric constant oxide layer by CVD on the layer at a second oxygen supply rate higher than the first oxygen supply rate; and (e) the second high dielectric constant oxide layer Forming a third high dielectric constant oxide layer by CVD at a third oxygen supply rate lower than the second oxygen supply rate; and (f) on the third high dielectric constant oxide layer. Forming a gate electrode with an oxidizable material.

  When a high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide is formed on the underlying silicon oxide layer by thermal CVD, the amount of oxygen in the deposition gas is suppressed at the initial growth stage and the final growth stage. It has been found that when a sufficient amount of oxygen is supplied, the change in the flat band voltage is reduced and a gate insulating film with little hysteresis can be formed.

  The flat band voltage is said to change according to the fixed charge, and the hysteresis is said to change according to the trap level. In the initial and final stages of growth, by suppressing the amount of oxygen supplied in the deposition gas, a reaction layer is formed at the interface between the high-dielectric-constant insulating layer and the adjacent layer, and fixed charges are generated. It is considered that by supplying a sufficient amount of oxygen during the period, the formation of trap levels in the film was suppressed and the hysteresis was reduced.

  Hafnium oxide (hafnia) is an insulator that can exhibit a dielectric constant several to ten times higher than that of silicon oxide, and has a high possibility as a gate insulating film of an IG-FET. Hafnium oxide is a substance that easily crystallizes, and it is not easy to form a thin and dense film having a uniform thickness. When a gate insulating film is formed using only hafnium oxide on a silicon substrate, a crystalline insulating film with a lot of leakage is easily formed.

When hafnium oxide (HfO ₂ ) is mixed with aluminum oxide (alumina) (Al ₂ O ₃ ), crystallization can be suppressed, and when crystallization is suppressed, leakage current is reduced. In order to obtain a dielectric constant as high as possible, the amount of aluminum oxide mixed with hafnium oxide is preferably limited to Hf _1-x Al _x O (0 <x <0.3). Hf _1-x Al _x O (0.1 <x <0.3) is preferable for the purpose of suppressing the oxidation.

Thermal chemical vapor deposition (CVD) is a method by which such a high dielectric constant insulating film can be formed with good film quality without adversely affecting the substrate.
When the HfAlO film is formed by thermal CVD, the flat band voltage deviates from the value (ideal value) obtained from the physical properties of the substance itself. The change in the flat band voltage is considered to be due to a fixed charge. For example, when a silicon oxide layer having a limited thickness is formed on the surface of a silicon substrate and a sufficient amount of oxygen is supplied thereon to form a high quality HfAlO film, the underlying silicon oxide layer or reaction layer is formed. Grows unnecessarily. A fixed charge is present in the reaction layer, which is thought to shift the flat band voltage. When a gate electrode of a polycrystalline silicon layer is formed on the HfAlO film, it is considered that a silicon oxide layer or a reaction layer grows also at the interface between the HfAlO film and the polycrystalline silicon layer to generate a fixed charge.

  When the amount of oxygen supply during the formation of the HfAlO film is suppressed as much as possible, formation of the reaction layer can be suppressed and generation of fixed charges can be suppressed. In this case, it is considered that the grown HfAlO film is in an oxygen deficient state, traps are generated, and hysteresis is generated in the relationship between capacitance (C) and voltage (V).

  The present inventor has studied a configuration that has the advantages of the above two types of HfAlO films and compensates for the disadvantages of both. In order to suppress the hysteresis, it is preferable to deposit a high dielectric constant oxide layer with a sufficient oxygen supply amount. In order to form a high dielectric constant insulating film with a small amount of change in flat band voltage, it is preferable to suppress diffusion of oxygen or the like from the high dielectric constant insulating layer to the interface with the adjacent layer. An HfAlO film having a low oxygen concentration is effective for suppressing diffusion. An AlO film will have a low oxygen diffusion coefficient and will be more effective. HfAlO with a high Al concentration will also be more effective in preventing oxygen diffusion than HfAlO with a low Al concentration. In the following, description will be made along with experiments conducted by the present inventors.

  As shown in FIG. 1A, the surface of the silicon substrate 1 was cleaned with sulfuric acid hydrogen peroxide (SPM). A natural oxide film 2 is formed on the surface of the silicon substrate 1. Organic contamination adhering to the surface of the natural oxide film 2 is cleaned.

As shown in FIG. 1B, the silicon substrate was washed with pure water for 10 minutes. The residue of the sulfuric acid hydrogen peroxide cleaning is rinsed with pure water.
As shown in FIG. 1C, the silicon substrate 1 was immersed in a dilute HF aqueous solution, and the natural oxide film 2 on the surface of the silicon substrate was removed.

As shown in FIG. 1D, the silicon substrate was washed with running pure water for 10 minutes. The remainder of the HF + H ₂ O oxide film removal step is rinsed with pure water.
As shown in FIG. 1E, the silicon substrate was washed with SC2 (hydrochloric acid hydrogen peroxide solution), and a chemical oxide film 3 made of SC2 was formed on the silicon surface to a thickness of about 0.3 nm. A thin silicon oxide film 3 that is cleaner than the natural oxide film 2 is formed. By forming the silicon oxide film on the surface that is exposed to water and becomes water-repellent, the surface becomes hydrophilic and the generation of watermarks is prevented.

  As shown in FIG. 1F, the silicon substrate was washed with running pure water for 10 minutes. The remainder of the silicon oxide film formation step by SC2 is rinsed with pure water. Subsequently, the substrate surface was dried by thermal drying (nitrogen atmosphere). This process is common to all samples. Thereafter, the silicon substrate was carried into a CVD film forming apparatus. Prior to the description of the next step of FIG. 1G, an embodiment of a CVD film forming apparatus will be described.

FIG. 2 schematically shows the configuration of a thermal CVD film forming apparatus. A shower head 8 is disposed in the reaction chamber 6, and a susceptor 7 having a heater H is disposed below the shower head 8. The shower head 8 is provided with independent pipes 9A and 9B. A hafnium source gas bubbler 10a, an aluminum source gas bubbler 10b, a nitrogen gas supply pipe 10c, and an oxygen gas supply pipe 10d are connected to the pipe 9A via a mass flow controller MFC. The hafnium source gas bubbler 10a contains nitrogen gas as a bubbling gas and contains tetrakisdimethylaminohafnium (Hf [N (CH ₃ ) ₂ ] ₄ ). The aluminum source gas bubbler 10b contains nitrogen gas as a bubbling gas and contains tritertiary butyl aluminum (Al (t-C ₄ H ₉ ) ₃ .

  The mass flow controller MFC supplies Hf, Al source gas, nitrogen gas, and oxygen gas at a predetermined flow rate. This film forming gas is supplied onto the susceptor 7 from the pipe 9 </ b> A via the shower head 8. Other piping 9B is also connected to the shower head 8, and other film-forming gas can also be supplied independently. The susceptor 7 is kept at 500 ° C., and the silicon wafer 1 placed thereon is also 500 ° C.

  As shown in FIG. 1G, an AlO film 4a having a thickness of 0.5 nm is formed on the chemical oxide film 3 of the silicon substrate 1 by thermal CVD at a substrate temperature of 500 ° C., an atmospheric pressure of 65 Pa, and a total flow rate of 1100 sccm. A 2.5-nm thick HfAlO film 4b and a 0.5-nm thick AlO film 4c were stacked thereon to form a high dielectric constant insulating film 4 having a stacked structure. Before describing the next comparative sample of FIG. 1H, the film forming gas of each sample obtained as one embodiment will be described.

FIG. 2B is a table showing the flow rate ratio of the deposition gas when depositing the high dielectric constant insulating layer of each sample. The source gas for forming the AlO film 4a on the silicon oxide film 3 is 300 sccm nitrogen gas containing (Al (t-C ₄ H ₉ ) ₃ bubbling), 30 sccm oxygen gas, and the balance (770 sccm) of nitrogen gas, the total flow rate is 1100 sccm, and the oxygen gas 30 sccm is a minimum flow rate for growing an oxide layer. A film is formed.

The source gas for forming the HfAlO film on the AlO film 4a is 300 sccm of nitrogen gas containing (Hf [N (CH ₃ ) ₂ ] ₄ ) and (Al (t-C _4). 30 sccm of nitrogen gas bubbling H ₉ ) ₃ , 100 sccm of oxygen gas, and the remainder (670 sccm) of nitrogen gas, the total flow rate is the same 1100 sccm, and the composition of HfAlO is Hf _0.8 Al _0.2 O was prepared, and 100 sccm of oxygen is a sufficient amount of oxygen to prevent oxygen deficiency and a sufficient oxygen concentration is imparted.

The source gas for forming the AlO film 4c on the HfAlO film 4b is the same as that for forming the AlO film 4a, that is, 300 sccm of nitrogen gas obtained by bubbling (Al (t-C ₄ H ₉ ) ₃ , and 30 sccm. Oxygen gas and the remainder (770 sccm) of nitrogen gas (total flow rate is 1100 sccm).

  Referring again to FIG. 1G, the upper and lower sides of the HfAlO film 4b formed by supplying sufficient oxygen are sandwiched by the AlO films 4a and 4c formed under the condition that the oxygen supply amount is significantly reduced. A dielectric constant insulating film 4 is formed. The chemical oxide film 3 and the laminated high dielectric constant insulating film 4 form a composite insulating film 5. An insulating gate electrode can be formed by forming a doped silicon film on the insulating film 5.

  As shown in FIG. 1H, a comparative sample in which a single-layer HfAlO film 4 was formed on the chemical oxide film 3 by thermal CVD at a substrate temperature of 500 ° C., an atmospheric pressure of 65 Pa, and a total flow rate of 1100 sccm was also prepared. A case where a sufficient amount of oxygen was supplied (HfAlO film 4x) and a case where the oxygen supply amount was limited as much as possible (HfAlO film 4y) were prepared.

The HfAlO film 4x is similar to the HfAlO film 4b by bubbling 300 sccm of nitrogen gas containing (Hf [N (CH ₃ ) ₂ ] ₄ ) and (Al (t-C ₄ H ₉ ) ₃ ). A total thickness of 3.5 nm was formed using 30 sccm of nitrogen gas, 100 sccm of oxygen gas, and the remaining (670 sccm) of nitrogen gas, with sufficient oxygen supply.

The HfAlO film 4y includes a 300 sccm nitrogen gas containing (Hf [N (CH ₃ ) ₂ ] ₄ ), a 30 sccm nitrogen gas containing (Al (t-C ₄ H ₉ ) ₃ , and 30 sccm. A total thickness of 3.5 nm was formed using the remaining oxygen gas and the remainder (740 sccm) of nitrogen gas under the condition that the oxygen supply amount was significantly reduced.

  After the high dielectric constant insulating layer 4 is formed, post-deposition annealing is performed in a nitrogen atmosphere at 800 ° C. for 30 seconds, and then a polycrystalline silicon layer doped by low pressure CVD (LPCVD) using silane as a raw material is deposited, and MOS A diode structure was formed. Instead of the polycrystalline silicon layer, a silicide layer or a metal gate structure containing Ti, W, and Al may be used, and a material that lowers the contact resistance with the contact plug in contact with the gate electrode can be selected.

  3A, 3B, and 3C show the results of making a MOS diode structure using these three types of samples and performing CV measurement. FIG. 3A shows a sample Sx obtained by growing the HfAlO film 4x under a sufficient oxygen supply (100 sccm), and the hysteresis is very small as about −3.5 mV. However, the shift amount of the flat band voltage is as large as about 0.65V. FIG. 3B shows a sample Sy of the HfAlO film 4y grown with a very low oxygen supply amount (30 sccm), and the hysteresis is very large at about −56 mV. The shift amount of the flat band voltage is reduced to about 0.57V. FIG. 3C is a sample So of the laminated high dielectric film 4, and the hysteresis is about −26 mV and within the allowable range. The shift amount of the flat band voltage is as small as about 0.57V.

  FIG. 4 summarizes these results. The horizontal axis indicates the shift amount ΔVfb of the flat band voltage in the unit V, and the vertical axis indicates the hysteresis in the unit mV. The upper left is better. It is clear that the characteristics of the sample So are superior as compared with the comparative samples Sx and Sy.

  In the comparative sample Sx, since sufficient oxygen was supplied, no oxygen deficiency occurred in the film, but oxygen was supplied to the interface between the underlying silicon oxide film 3 and the polycrystalline silicon gate electrode, and a reaction layer was generated. It is thought that a fixed charge was generated.

  In the comparative sample Sy, the film was formed by significantly reducing the oxygen supply amount, so that the oxygen supply amount to the interface with the underlying silicon oxide film and the polycrystalline silicon gate electrode was suppressed, and the formation of the reaction layer and hence the generation of fixed charges was suppressed. As a result, the shift amount of the flat band voltage is reduced. However, since oxygen supply is extremely small, oxygen deficiency occurs and traps are considered to increase.

  In the laminated sample So (see FIG. 1G again), the surface portion of the high dielectric constant insulating layer was formed of an AlO film having an oxygen diffusion coefficient smaller than that of HfAlO. Oxygen diffusion from the HfAlO film sandwiched between AlO films having a small oxygen diffusion coefficient is suppressed. Further, when the AlO films 4a and 4c are formed, the oxygen supply amount is set low. Like the comparative sample Sy, since the oxygen supply amount is low, it is considered that oxygen supplied to the interface with the underlying silicon oxide layer and the polycrystalline silicon layer is suppressed. Since the AlO film 4a is formed first, even if a sufficient amount of oxygen is supplied during the formation of the HfAlO film 4b, the oxygen is supplied to the interface with the underlying silicon oxide layer and the subsequently formed polycrystalline silicon layer. It is thought to suppress It will suppress the formation of the reaction layer and suppress changes in the flat band voltage. Since the HfAlO film, which is the main part of the high dielectric constant insulating film, is formed by supplying sufficient oxygen, there will be few traps and hysteresis will be suppressed. In this way, the gate electrode material that causes oxidation can be used depending on the conditions during the fabrication of the gate electrode structure, such as a polysilicon layer, thereby increasing the tolerance of the semiconductor device structure design. The oxygen diffusion coefficient does not depend on the oxygen concentration.

  The oxide high dielectric constant insulating film is divided into a central part and both side surface parts, and the central part supplies sufficient oxygen for good film quality with few traps, and both surface parts have a composition to select the oxygen diffusion coefficient. An oxide with low flat band voltage shift and low hysteresis by suppressing the formation of the reaction layer and suppressing the generation of fixed charges by reducing the oxygen supply amount during film formation It is considered that a high dielectric constant insulating film could be formed.

  Although the case where a silicon oxide layer made of chemical oxide is formed on a silicon substrate as the base of the oxide high dielectric constant insulating layer has been described, the surface thereof may be nitrided. Nitrogen may be introduced by other methods. Further, the method of forming a thin silicon oxide layer is not limited to SC2 cleaning.

  HfAlO is used as the central portion of the high dielectric constant insulating film whose properties change in the thickness direction, but Al is an additive for suppressing crystallization. HfO has the property of being easily crystallized, but in order to suppress crystallization, Si or the like may be added in addition to Al. In addition, if conditions for suppressing crystallization, such as a thin film thickness, are added, it will be possible to use HfO as the high dielectric constant insulating film in the center. It is possible to use not only HfO but also TiO, TaO, ZrO, YO, WO, AlO, and LaO, which are oxides having a high dielectric constant, as the oxide high dielectric constant insulating film.

  AlO is used as both surface portions of the high dielectric constant insulating film whose properties change in the thickness direction and has an effect of suppressing the diffusion of oxygen. However, the present invention is not limited to AlO. The oxide having a low oxygen diffusion coefficient is typically AlO. However, other elements may be added to AlO, or a mixture of another insulating material and AlO may be used. For example, AlON in which N is added to AlO, HfAlO having a higher Al composition than HfAlO in the central portion, and the like may be used. Moreover, since AlO has a lower dielectric constant than HfO or the like, HfO, TiO, TaO, ZrO, YO, and WO may be added to increase the dielectric constant. Even if the composition of Hf and Al is the same as that of the central portion, HfAlO having a low oxygen concentration may be used. It can be inferred from the result of the sample 4y that the HfAlO film having a low oxygen concentration has a low oxygen diffusion coefficient. Even when the composition is adjusted, it may be preferable to suppress the oxygen supply amount. For example, in the CVD of the stacked oxide high dielectric constant insulating layer, the total flow rate is constant, and the oxygen supply amount at the beginning and the end of growth is set to be less than half of the oxygen supply amount at the middle stage of growth.

  The thickness of both surface portions 4a and 4c having an oxygen diffusion suppressing effect is preferably 0.3 nm to 1 nm. If it is less than 0.3 nm, it is difficult to obtain a sufficient oxygen diffusion suppressing effect. If it exceeds 1 nm, the silicon oxide equivalent film thickness is excessively increased. The thickness of the high dielectric constant insulating layer 4b having a high dielectric constant is preferably about 1 nm to 5 nm, and about 1 nm to 3 nm in a miniaturized transistor. The sum of the thicknesses of both surface portions 4a and 4c is preferably thinner than the thickness of the central high dielectric constant insulating layer 4b.

  Instead of changing the composition of the central portion and the surface portion stepwise, it may be changed continuously or gradually. The oxygen diffusion coefficient will also change continuously or gradually.

Although CVD film formation was performed at a substrate temperature of 500 ° C., the film formation temperature is not limited to 500 ° C. An HfAlO film will be able to grow well at a deposition temperature of 400 ° C.-600 ° C.
The source gas for Hf is not limited to (Hf [N (CH ₃ ) ₂ ] ₄ ). Hf (OtC ₄ H ₉ ) ₄ , Hf {N (C ₂ H ₅ ) ₂ } ₄ , Hf {N (CH ₃ ) (C ₂ H ₅ )} _4, etc. may be used. Al source gas is also not limited to _{Al (t-C 4 H 9} ) 3. Al (C ₂ H ₅ ) ₃ , Al (CH ₃ ) ₃ or the like may be used.

  Although the case where HfAlO is thermally CVD has been described, a high dielectric constant insulating layer having a low oxygen diffusion coefficient is formed at the initial growth stage and at the end of growth even when another high dielectric constant insulating film is grown by thermal CVD. As a result, it will be possible to suppress hysteresis and suppress changes in the flat band voltage. The source gas is not limited to an organic metal, but will likely be high when an organic metal source is used.

  FIG. 5A shows the configuration of an n-channel IG-FET. An element isolation region 12 by shallow trench isolation (STI) is formed in the silicon substrate 11, and a p-type well 13p is formed in the active region. N-type wells are also created elsewhere. The above-described high dielectric constant laminated gate insulating film 4 is formed on the active region surface via the silicon oxide layer 3. The gate insulating film 4 is an oxide high dielectric constant insulating film grown by supplying a sufficient amount of oxygen with the oxide high dielectric constant insulating films 4a and 4c having a low oxygen diffusion coefficient formed under the condition that the oxygen supply amount is reduced. It has a laminated structure sandwiching 4b.

  On the gate insulating film 4, an n-type polycrystalline silicon gate electrode 15 n doped with phosphorus (P) or arsenic (As) is formed. N-type extension regions 16n are formed on the substrate surface on both sides of the gate electrode. Sidewall spacers 17 such as silicon oxide are formed on the side walls of the gate electrode, and high-concentration n-type source / drain regions 18n are formed in the substrate outside the sidewall spacers 17. A silicide layer 19 such as CoSi is formed on the gate electrode 15n and the source / drain regions 18n. In this way, the n-channel IG-FET 20n is formed.

  According to the above configuration, since the gate insulating film is formed using the high dielectric constant insulating film, even if the equivalent silicon oxide film thickness is reduced, the physical film thickness can be increased and the tunnel current can be suppressed. With the structure of the stacked gate insulating film, hysteresis can be suppressed and a change in flat band voltage can be suppressed. Note that the gate electrode can be formed of aluminum instead of silicon. The aluminum electrode can be formed by sputtering aluminum or replacing silicon with aluminum.

  FIG. 5B shows a configuration example of a semiconductor integrated circuit device. In the silicon substrate 11, an n-type well 13n and a p-type well 13p are formed. The n-channel IG-FET 20n is formed in the p-type well 13p. A p-channel IG-FET 20p is formed in the n-type well 13n. P and n after the reference symbol indicate the conductivity type. The p-channel IG-FET 20p has a configuration in which the conductivity type of each semiconductor region of the n-channel IG-FET is inverted.

As for the gate insulating film, both the n-channel IG-FET and the p-channel IG-FET have an Hf _0.8 Al _0.2 O high dielectric constant insulating film 4b formed on the silicon oxide layer 3 whose thickness is limited. It is formed using a stack sandwiched between low AlO films 4a and 4c. The high dielectric constant insulating film has a small hysteresis and suppresses a flat band voltage change ΔVfb.

An interlayer insulating film 21 is formed so as to cover the gate electrode, and a multilayer wiring 24 is formed in the interlayer insulating film. Each wiring 24 is configured using a barrier metal layer 22 and a main wiring layer 23 such as copper.
FIG. 6 shows a configuration example of a semiconductor integrated circuit device having a multilayer wiring structure. An element isolation region 102 by shallow trench isolation (STI) is formed on the silicon substrate 101. In order to form a MOS transistor in the active region surrounded by the element isolation region 102, a p-type well 103 and an n-type well 104 are formed.

  A gate insulating film 105, a polycrystalline silicon gate electrode 106, and sidewall spacers 107 are formed on the p-type well region 103, and extension-type n-type source / drain regions 108 are formed on both sides of the gate electrode 106. In the n-type well region 104, a p-type source / drain region 109 is formed.

  A silicon nitride layer 111 is formed on the semiconductor substrate so as to cover the gate electrode, and a phosphosilicate glass (PSG, phosphorus-doped silicon oxide) layer 112 is formed thereon. A via conductor formed of the TiN barrier metal layer B11 and the tungsten layer V1 is formed through the PSG layer 112 and the silicon nitride layer 111.

  An organic insulating layer 113 and a silicon oxide layer 114 are stacked on the PSG layer 112. A wiring pattern formed of the barrier metal layer B1, the copper wiring layer W1, the auxiliary barrier metal layer B1x, and the auxiliary copper wiring layer W1x is embedded in this stack. In this way, the first wiring layer WL1 is formed.

  A stack of a silicon nitride layer 121, a silicon oxide layer 122, an organic insulating layer 123, and a silicon oxide layer 124 is formed on the first wiring layer WL1, and an interlayer insulating film for the second wiring WL2 is formed. The second wiring layer WL2 formed of the barrier metal layer B2, the copper wiring layer W2, the auxiliary barrier metal layer B2x, and the auxiliary copper wiring layer W2x is embedded in the second wiring interlayer insulating film.

  Similar to the interlayer insulating film for the second wiring WL2, the interlayer insulating films for the third wiring layer WL3 and the fourth wiring layer WL4 are silicon nitride layers 131 and 141, silicon oxide layers 132 and 142, organic insulating layers 133 and 143, A stack of silicon oxide layers 134 and 144 is formed.

  The damascene wiring structure of the third wiring layer WL3 and the fourth wiring layer WL4 is the same as that of the second wiring layer. A wiring pattern is formed by the barrier metal layer Bn, the copper wiring layer Wn, the auxiliary barrier metal layer Bnx, and the auxiliary copper wiring layer Wnx.

  The fifth wiring layer WL5 to the seventh wiring layer WL7 have different configurations from the second wiring layer WL2 to the fourth wiring layer WL4. The interlayer insulating film of the fifth wiring layer WL5 is formed by stacking a silicon nitride layer 151, a silicon oxide layer 152, a silicon nitride layer 153, and a silicon oxide layer 154. The configuration of the wiring pattern is the same as that of the second to fourth wirings WL4.

  Similarly to the fifth wiring layer WL5, an interlayer insulating film for the sixth wiring layer and the seventh wiring layer is formed of silicon nitride layers 161 and 171, silicon oxide layers 162 and 172, silicon nitride layers 163 and 173, and silicon oxide layers 164 and 174. Has been. The configuration of the wiring pattern is the same as that of the fifth wiring WL5.

  In the upper layer wiring, the pitch between the wirings becomes wider and the wiring density becomes lower. For this reason, in order to reduce the stray capacitance between wirings, the necessity of using a low dielectric constant insulating layer is reduced. Therefore, in the fifth to seventh wiring layers, the organic insulating layer is not used, and the reliability of the interlayer insulating layer is enhanced.

  The uppermost eighth wiring layer WL8 has a unique configuration. A lower insulating layer is formed by the silicon nitride layer 181 and the silicon oxide layer 182, and a via portion is formed by the barrier metal layer B81 and the tungsten layer V8.

  A wiring layer also serving as a pad is formed of the TiN layer B82, the aluminum layer W8, and the TiN layer B83 on the via portion. Cu can also be used in place of aluminum. A silicon oxide layer 183 and a silicon nitride layer 190 are formed so as to cover the uppermost wiring.

  In the configuration of FIG. 6, the auxiliary barrier metal layer is embedded in the wiring pattern in all of the first wiring layer WL1 to the seventh wiring layer WL7 to suppress the generation of voids. The structure of the interlayer insulating film is different between the lower wiring layer and the upper wiring layer except the uppermost layer.

  FIG. 7 shows another configuration example of a semiconductor integrated circuit device having a multilayer wiring structure. The structure of the MOS transistor structure and the source / drain lead conductive plug formed in the semiconductor substrate is the same as that shown in FIG.

  A stack of a SiC layer 116, an organic insulating layer 117, and a SiC layer 118 is formed on the PSG layer 112, and a first wiring layer WL1 is formed of a barrier metal layer B1 and a copper wiring layer W1. No auxiliary barrier metal layer is used.

  The second wiring layer WL2 to the fourth wiring layer WL4 have the same configuration as the first wiring layer WL1. Taking the fourth wiring layer WL4 as an example, the interlayer insulating film is formed of a SiC layer 141, an organic insulating layer 142, and a SiC layer 143. The dual damascene wiring is formed of a barrier metal layer B4 and a copper layer W4, and no auxiliary barrier metal layer is disposed.

  The fifth wiring layer WL5 to the eighth wiring layer WL8 have the same configuration. Taking the fifth wiring layer WL5 as an example, the interlayer insulating film is formed of an SiC layer 151, a silicon oxide carbide (SiOC) layer 152, an SiC layer 153, and a silicon oxide carbide layer 154. The dual damascene wiring is formed of a barrier metal layer B and a copper wiring layer W, and no auxiliary barrier metal layer is disposed.

  The ninth wiring layer WL9 includes a barrier metal layer B9, a copper wiring layer W9, an auxiliary barrier metal layer B9x, and an auxiliary insulating film formed on an interlayer insulating film formed of the SiC layer 191, the silicon oxide layer 192, the SiC layer 193, and the silicon oxide layer 194. A dual damascene wiring formed of the copper wiring layer W9x is embedded.

  The tenth wiring WL10 has a configuration similar to that of the ninth wiring WL9. The SiC layer 201, the silicon oxide layer 202, the SiC layer 203, and the silicon oxide layer 204 are formed, and the interlayer insulating film is formed of the barrier metal layer B10, the copper wiring layer W10, the auxiliary barrier metal layer B10x, and the auxiliary copper wiring layer W10x. Dual damascene wiring is embedded.

  The uppermost wiring layer WL11 has a configuration similar to that of the uppermost wiring in FIG. A SiC layer 211 and a silicon oxide layer 212 are laminated, and a via conductor formed of a TiN barrier metal layer B11 and a W wiring layer W11 is embedded therein. On the via conductor, a TiN layer B111, a main wiring layer W12 formed of aluminum or an aluminum alloy containing copper, and a bonding pad combined uppermost wiring layer formed of an upper barrier metal layer B112 of TiN are formed. A silicon oxide layer 213 and a silicon nitride layer 220 are formed to cover this wiring layer.

  In the configuration of FIG. 7, the laminated configuration of the interlayer insulating layer changes in three stages from the lower layer to the upper layer, and the substantial dielectric constant is lowered as the lower layer. The lower layer wiring has a high density, and it is preferable to reduce the dielectric constant of the interlayer insulating layer in order to reduce the accompanying capacitance of the wiring.

Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, the composition of HfAlO is not limited to Hf _0.8 Al _0.2 O. In addition, other metal oxides could be used.

It will be apparent to those skilled in the art that other various modifications, improvements, and combinations can be made.
The features of the present invention will be described below.
(Appendix 1) (1) A silicon substrate,
A silicon oxide layer formed on the surface of the silicon substrate;
A high dielectric constant insulating layer including a first oxide layer formed on the silicon oxide layer, a second oxide layer formed thereon, and a third oxide layer formed thereon; The first oxide layer and the third oxide layer have a high dielectric constant insulating layer having a smaller oxygen diffusion coefficient than the second oxide layer;
A gate electrode formed on the high dielectric constant insulating layer;
A semiconductor device.

(Supplementary Note 2) (2) The semiconductor device according to claim 1, wherein the second oxide layer includes any one of HfO, TiO, TaO, ZrO, YO, WO, AlO, and LaO.
(Supplementary Note 3) (3) The semiconductor device according to claim 2, wherein the second oxide layer is formed of any one of HfO, HfAlO, HfSiO, HfAlSiO, HfAlON, HfSiON, and HfAlSiON.

(Appendix 4) (4) The semiconductor device according to any one of claims 1 to 3, wherein the first oxide layer and the third oxide layer contain AlO.
(Supplementary Note 5) (5) The semiconductor device according to Supplementary Note 4, wherein the first oxide layer and the third oxide layer further include any one of HfO, TiO, TaO, ZrO, YO, and WO.

(Appendix 6) (6) The semiconductor device according to any one of appendices 1 to 5, wherein the second oxide layer has a trap level lower than that of the first oxide layer and the third oxide layer.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein the second oxide layer is an HfAlO layer, and the first oxide layer and the third oxide layer are AlO layers.

(Supplementary note 8) The semiconductor device according to any one of supplementary notes 1 to 7, wherein the thickness of the second oxide layer is 1 nm to 5 nm.
(Supplementary note 9) The semiconductor device according to any one of supplementary notes 1 to 8, wherein a thickness of the first oxide layer or the third oxide layer is 0.3 nm to 1 nm.

    (Appendix 10) (7) The thickness of the second oxide layer is in the range of 1 nm to 5 nm, and the thickness of the first oxide layer and the third oxide layer is in the range of 0.3 nm to 1 nm. The semiconductor device according to any one of appendices 1 to 7.

(Additional remark 11) (8) (a) The process of removing the natural oxide film of the silicon substrate surface by wet etching,
(B) forming a base silicon oxide layer by chemical treatment on the surface of the silicon substrate from which the natural oxide film has been removed;
(C) forming a first high dielectric constant oxide layer by CVD on the underlying silicon oxide layer at a first oxygen supply rate;
(D) forming a second high dielectric constant oxide layer on the first high dielectric constant oxide layer by CVD at a second oxygen supply rate higher than the first oxygen supply rate;
(E) forming a third high dielectric constant oxide layer on the second high dielectric constant oxide layer by CVD at a third oxygen supply rate lower than the second oxygen supply rate;
(F) forming a gate electrode with an oxidizable material on the third high dielectric constant oxide layer;
A method of manufacturing a semiconductor device including:

(Additional remark 12) The said process (b) is a manufacturing method of the semiconductor device of Additional remark 11 which performs the process by hydrochloric acid and hydrogen peroxide aqueous solution.
(Additional remark 13) At least one of the said process (c) and (e) is a manufacturing method of the semiconductor device of Additional remark 11 or 12 which deposits the layer containing AlO.

    (Additional remark 14) The said process (d) deposits a HfAlO layer, At least one of the said process (C) (e) deposits an HfAlO layer with a high Alf layer or Al composition any one of Additional remarks 11-13 The manufacturing method of the semiconductor device of description.

    (Appendix 15) (9) The process according to any one of appendices 11 to 14, wherein the step (d) is performed without growing a new reaction layer under the first high dielectric constant oxide layer. A method for manufacturing a semiconductor device.

    (Additional remark 16) (10) The said process (f) is any one of Additional remarks 11-15 performed without growing a new reaction layer on the said 3rd high dielectric constant oxide layer substantially. Semiconductor device manufacturing method.

(Additional remark 17) The said process (f) is a manufacturing method of the semiconductor device of Additional remark 16 which deposits a silicon layer or an aluminum layer.
(Supplementary note 18) The semiconductor according to any one of supplementary notes 11 to 17, wherein the steps (c) and (e) are the same as the step (d) in that the total flow rate of the growth gas is the same and the oxygen supply amount is half or less. Device manufacturing method.
Industrial applicability It can be used for semiconductor integrated circuit devices including miniaturized IG-FETs.

It is sectional drawing for demonstrating the method of forming a high dielectric constant insulating film on a silicon substrate by chemical vapor deposition (CVD). It is the table | surface which shows the block diagram which shows the structure of a thermal CVD apparatus roughly, and experimental conditions collectively. It is a graph which shows the CV characteristic of the produced MOS structure. It is a graph which shows collectively flat band voltage variation | change_quantity (DELTA) Vfb and hysteresis. It is sectional drawing which shows the structure of the MOS transistor by an Example. It is sectional drawing which shows the structure of a semiconductor integrated circuit device. It is sectional drawing which shows the structure of a semiconductor integrated circuit device.

Explanation of symbols

1 Silicon substrate 2 Natural oxide film 3 Chemical oxide film (silicon oxide film)
4 High dielectric constant insulating layer 4x High dielectric constant insulating layer with sufficient oxygen supply amount 4y High dielectric constant insulating layer with low oxygen supply amount 4a AlO layer with low oxygen supply amount 4b HfAlO layer with sufficient oxygen supply amount 4c Oxygen supply layer AlO layer with low supply 5 Gate insulating layer 6 Reaction chamber 7 Susceptor 8 Shower head 9 Piping

Claims (10)

A silicon substrate;
A silicon oxide layer formed on the surface of the silicon substrate;
A high dielectric constant insulating layer including a first oxide layer formed on the silicon oxide layer, a second oxide layer formed thereon, and a third oxide layer formed thereon; The first oxide layer and the third oxide layer have a high dielectric constant insulating layer having a smaller oxygen diffusion coefficient than the second oxide layer;
A gate electrode formed on the high dielectric constant insulating layer;
A semiconductor device. The semiconductor device according to claim 1, wherein the second oxide layer includes any one of HfO, TiO, TaO, ZrO, YO, WO, AlO, and LaO. The semiconductor device according to claim 2, wherein the second oxide layer is formed of any one of HfO, HfAlO, HfSiO, HfAlSiO, HfAlON, HfSiON, and HfAlSiON. The semiconductor device according to claim 1, wherein the first oxide layer and the third oxide layer contain AlO. The semiconductor device according to claim 4, wherein the first oxide layer and the third oxide layer further include any one of HfO, TiO, TaO, ZrO, YO, and WO. The semiconductor device according to claim 1, wherein the second oxide layer has a lower trap level than the first oxide layer and the third oxide layer. The thickness of the second oxide layer is in the range of 1 nm to 5 nm, and the thickness of the first oxide layer and the third oxide layer is in the range of 0.3 nm to 1 nm. The semiconductor device according to claim 1. (A) removing a natural oxide film on the surface of the silicon substrate by wet etching;
(B) forming a base silicon oxide layer by chemical treatment on the surface of the silicon substrate from which the natural oxide film has been removed;
(C) forming a first high dielectric constant oxide layer by CVD on the underlying silicon oxide layer at a first oxygen supply rate;
(D) forming a second high dielectric constant oxide layer on the first high dielectric constant oxide layer by CVD at a second oxygen supply rate higher than the first oxygen supply rate;
(E) forming a third high dielectric constant oxide layer on the second high dielectric constant oxide layer by CVD at a third oxygen supply rate lower than the second oxygen supply rate;
(F) forming a gate electrode with an oxidizable material on the third high dielectric constant oxide layer;
A method of manufacturing a semiconductor device including: 9. The method of manufacturing a semiconductor device according to claim 8, wherein the step (d) is performed without growing a new reaction layer under the first high dielectric constant oxide layer. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the step (f) is performed without growing a new reaction layer on the third high dielectric constant oxide layer.

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