TWI866701B - Method of forming semiconductor structure and processing system - Google Patents

Abstract

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

Description

Method and processing system for forming a semiconductor structure

Various embodiments described herein relate generally to semiconductor device manufacturing, and more particularly, to systems and methods for forming high-quality high-κ dielectric material layers and metal gate structures in semiconductor structures.

As metal oxide semiconductor field effect transistors (MOSFETs) have been reduced in size to achieve high device performance and low power consumption, the thickness of traditional silicon dioxide (SiO ₂ ) gate dielectrics has been reduced to its physical limit. Therefore, in order to achieve further scaling, it is inevitable to replace the silicon dioxide gate dielectric with high-κ dielectric materials. Among various high-κ dielectric materials, ferrite (HfO ₂ ) has been used since the 45nm MOSFET technology node because ferrite (HfO ₂ ) has a high dielectric constant and excellent thermal stability on silicon substrates. However, for further reduction of the equivalent oxide thickness (EOT) at the 32nm MOSFET technology node and beyond, simply reducing the thickness of the high-κ dielectric material layer is problematic because leakage current flowing through the high-κ dielectric material layer increases.

In addition, conventional polycrystalline silicon (polysilicon) gates have been replaced by metal gates formed of metal layers (e.g., titanium (Ti), tantalum (Ta), tungsten (W)) and metal-containing conductive compound layers (e.g., titanium nitride (TiN), tantalum nitride (TaN)) to reduce the undesirable voltage drop associated with the polysilicon depletion effect and improve the driving current performance and operating speed of MOSFETs. However, such metal gates are usually formed by a furnace-based process that uses a metal-containing precursor (e.g., titanium chloride, TiCl ₄ ) and a nitrogen-containing precursor (e.g., ammonia, NH ₃ ). Such processes may include high concentrations of oxygen content and therefore may not be ideal for future scalability.

Therefore, there is a need for systems and methods for forming thin (e.g., EOT less than 1 nm) high-κ dielectric material layers and for forming metal gates without high concentrations of oxygen content, such material layers having chemical structures that can be controlled to ensure desired structural and electrical properties.

Multiple embodiments of the present disclosure provide a method for forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate. The method includes the following steps: depositing the high-κ dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer; performing a post cap anneal process to harden and densify the deposited high-κ dielectric cap layer; and removing the sacrificial silicon cap layer.

Various embodiments of the present disclosure also provide a method for forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate. The method includes the following steps: depositing the high-κ dielectric cap layer on the semiconductor structure; Depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer; performing a post-cap annealing process to harden and densify the deposited high-κ dielectric cap layer; and removing the sacrificial silicon cap layer.

Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, and a system controller. The system controller is configured to: deposit a high-κ dielectric cap layer on the high-κ gate dielectric layer in the first processing chamber; deposit a sacrificial silicon cap layer on the high-κ dielectric cap layer in the second processing chamber; perform a post-cap anneal process in the third processing chamber to harden and densify the deposited high-κ dielectric cap layer; and remove the sacrificial silicon cap layer in the fourth processing chamber. The substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber, and the fourth processing chamber without destroying a vacuum environment in the processing system.

As gate structures shrink to smaller dimensions, new material structures are sought to provide improvements. The use of high-κ dielectric materials increases the dielectric constant of the gate structure compared to traditional gate structures utilizing materials such as silicon oxide. However, similar to silicon oxide, as the thickness of the gate structure decreases, the leakage current increases. For example, gate leakage increases as the effective oxide thickness decreases. Therefore, the inverse relationship between gate leakage and effective oxide thickness can form a limitation on the performance of the components and transistors produced.

High-κ dielectric materials can provide greater electrostatic control over the channel than silicon oxide of similar physical thickness. As the industry continues to seek lower effective oxide thickness without increasing gate leakage, efforts to maximize the dielectric constant (also known as the "κ value") of known high-κ materials are reaching their limits due to morphological characteristics. Traditional techniques have struggled to overcome the inherent properties of high-κ materials (which may set an upper limit on the κ value), and subsequent device modifications have attempted to incorporate new films.

Additionally, typical furnace-based processes for forming metal gates replacing polysilicon from metal layers and metal-containing conductive compounds may contain high concentrations of oxygen during the process and thus may not be ideal for future scalability.

The various embodiments described herein provide systems and methods for forming thin (e.g., EOT less than 1 nm) high-κ dielectric material layers and forming metal gates. By producing high-κ dielectric materials that exhibit a specific morphology or grain structure, higher dielectric constants and improved device performance can be achieved. In order to control the in-film morphology in the exemplary device, treatment can be performed to provide an activated substrate surface that can induce a specific film morphology, and stabilize the film after formation, which can result in a higher dielectric constant. Forming a metal gate without a high concentration of oxygen content enables further reduction in equivalent oxide thickness (EOT).

1 is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes: a factory interface 102; load gate chambers 104, 106; transfer chambers 108, 110 with corresponding transfer robots 112, 114; holding chambers 116, 118; and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, wafers in the processing system 100 can be processed in the various chambers and transferred between the various chambers without exposing the wafers to an ambient environment external to the processing system 100 (e.g., an atmospheric environment such as may exist in a wafer fab). For example, the wafers may be processed in various chambers and transferred between the various chambers in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment between various processes performed on the wafers in the processing system 100. Thus, the processing system 100 may provide an integrated solution for some processing of wafers.

Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura® ^, Producer® ^, or ^Centura® integrated processing systems commercially available from Applied Materials, Inc., located in Santa Clara, Calif., or other suitable processing systems. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the various aspects described herein.

1 , the fab 102 includes a docking station 140 and a fab robot 142 to facilitate wafer transfer. The docking station 140 is configured to receive one or more front opening unmanned units (FOUPs) 144. In some examples, each fab robot 142 generally includes a blade 148 disposed on one end of the corresponding fab robot 142 and configured to transfer wafers from the fab 102 to the load gate chambers 104, 106.

The load gate chambers 104, 106 have corresponding ports 150, 152 coupled to the factory interface 102 and corresponding ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 also has corresponding ports 158, 160 coupled to the holding chambers 116, 118 and corresponding ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has corresponding ports 166, 168 coupled to the holding chambers 116, 118 and corresponding ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 may be, for example, slit valve openings with slit valves for passing wafers therethrough by means of transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing between the chambers. Typically, any port is open for passing a wafer therethrough. Otherwise, the port is closed.

The load gate chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., a turbo pump, a cryo-pump, a roughing pump), gas sources, various valves, and conduits that fluidly couple to the various chambers. In operation, the factory interface robot 142 transfers wafers from the FOUP 144 to the load gate chamber 104 or 106 via port 150 or 152. The gas and pressure control system then pumps down the load gate chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at internal low pressure or vacuum environments (which may include an inert gas). Thus, pumping of the load gate chamber 104 or 106 facilitates the transfer of wafers between, for example, the atmospheric environment of the fab interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

With the wafer in the load gate chamber 104 or 106 that has been pumped empty, the transfer robot 112 transfers the wafer from the load gate chamber 104 or 106 to the transfer chamber 108 via the port 154 or 156. The transfer robot 112 can then transfer the wafer to any of the processing chambers 120, 122 and the holding chambers 116, 118 and/or between any of these chambers, transferring the wafer to the processing chamber 120, 122 for processing via the corresponding port 162, 164, and transferring the wafer to the holding chamber 116, 118 for holding to await further transfer via the corresponding port 158, 160. Similarly, the transfer robot 114 can access the wafer in the holding chamber 116 or 118 through the port 166 or 168, and can transfer the wafer to any of the processing chambers 124, 126, 128, 130 and the holding chambers 116, 118 and/or transfer the wafer between any of these chambers, transfer the wafer to the processing chamber 124, 126, 128, 130 for processing through the corresponding port 170, 172, 174, 176, and transfer the wafer to the holding chamber 116, 118 for holding to await further transfer through the corresponding port 166, 168. The transfer and holding of the wafers within and between the various chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

Processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chamber for processing wafers. In some examples, processing chamber 122 may be capable of performing a cleaning process, processing chamber 120 may be capable of performing an etching process, and processing chambers 124, 126, 128, 130 may be capable of performing a corresponding epitaxial growth process. Processing chamber 122 may be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc. of Santa Clara, California, USA. Processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials, Inc. of Santa Clara, California, USA.

The system controller 190 is coupled to the processing system 100 for controlling the processing system 100 or components of the processing system 100. For example, the system controller 190 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. In operation, the system controller 190 can enable data collection and feedback from the corresponding chambers to coordinate the operation of the processing system 100.

The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 can be one of any form of general purpose processor that can be used in an industrial setting. The memory 194 or non-transitory computer readable medium can be accessed by the CPU 192 and can be one or more memories such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage device. The support circuits 196 are coupled to the CPU 192 and can include cache memory, clock circuits, input/output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented by CPU 192 executing computer instruction codes stored in memory 194 (or the memory of a particular process chamber) as, for example, software routines, under the control of CPU 192. When the computer instruction codes are executed by CPU 192, CPU 192 controls the chambers to perform processes according to the various methods.

Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and/or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer device in a processing system.

FIG. 2 is a process flow chart of a method 200 for forming a semiconductor structure 300 according to one or more embodiments of the present disclosure. FIG. 3A and FIG. 3B are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of the method 200. It should be understood that FIG. 3A and FIG. 3B only show partial schematic views of the semiconductor structure 300, and the semiconductor structure 300 may include any number of transistor portions and additional materials having multiple states as shown. It should also be noted that although the method steps shown in FIG. 2 are described in sequence, other process sequences including one or more method steps that have been omitted and/or added, and/or rearranged in another desired order also fall within the scope of the multiple embodiments of the present disclosure provided herein.

The method 200 begins with a pre-cleaning process in block 210 to pre-clean the surface of the substrate 302. The pre-cleaning process may include etching the surface of the substrate 302 by a dry etching process or a wet etching process using an etching solution, such as a Standard Clean 1 (SC1) etching solution containing _NH4OH (ammonium hydroxide), _{H2O2 (} hydrogen peroxide), and _H2O (water), the dry etching process being, for example, a SiConi™ remote plasma assisted dry etching process, in which the surface of the substrate 302 is exposed to _N2 , _NF3 , and _NH3 plasma byproducts. The pre-clean process may be performed in a pre-clean chamber such as the processing chamber 122 or 120 shown in FIG. 1 .

In block 220, an interface formation process is performed to form an interfacial layer 304 on the pre-cleaned surface of the substrate 302, as shown in FIG3A. The interface formation process may include a suitable thermal oxidation process, such as an enhanced in-situ steam generation (eISSG) process using nitrous oxide ( _N2O ) gas. The interfacial layer 304 formed in block 220 is a thin amorphous silicon oxide ( _SiO2 ) layer having a thickness between about 3Å and about 10Å, such as about 5Å, corresponding to one or more monolayers of silicon oxide. In some embodiments, the interface layer 304 may be formed by an in-situ steam generation (ISSG) process using H ₂ and O ₂ gases or by a rapid thermal oxidation (RTO) process using NH ₃ and O ₂ gases. The interface layer 304 may serve as a nucleation layer for a high-κ dielectric material layer to be deposited on the interface layer 304 and improve the quality of the interface between the substrate 302 and the high-κ dielectric material layer (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current). The interface formation process may be performed in a processing chamber such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG. 1 .

In some embodiments, the interface formation process in block 220 is omitted, and the interface layer 304 is not formed before the high-κ dielectric material layer is deposited on the substrate 302. In this case, the interface layer 304 is formed by a thermal oxidation process in block 250 or block 290 described below, which thermally oxidizes the substrate 302 via the high-κ dielectric material layer deposited on the substrate 302. Having a thickness between about 0.3 nm and about 1 nm, for example, about 0.5 nm, the interface layer 304 formed by the thermal oxidation process in box 250 or box 290 can be thick enough to ensure reliable device characteristics (e.g., such as interface state density, cumulative capacitance, dispersion and leakage current) and reduce atomic diffusion from the high-κ dielectric material layer to the substrate 302.

In block 230, a deposition process is performed to deposit a high-κ gate dielectric layer 306 on the exposed surface of the semiconductor structure 300 (i.e., on the interface layer 304 if the interface layer 304 is formed in block 220, as shown in FIG. 3B, and on the substrate 302 if the interface layer 304 is not formed in block 220). The high-κ gate dielectric layer 306 may be formed of a high-κ dielectric material (such as materials such as HfO ₂ , ZrO ₂ , ytterbium oxide (Y ₂ O ₃ ), and aluminum oxide (Al ₂ O ₃ )), a ternary high-κ dielectric film (such as HfZrO, HfLaOx, and HfTiO) having a third element doped into an existing metal oxide high-κ dielectric host material. The deposition process may include an atomic layer deposition (ALD) process, in which a metal-containing precursor and an oxygen-containing precursor are alternately delivered to the exposed surface of the semiconductor structure 300. In some embodiments, the metal-containing precursor is purged before the oxygen-containing precursor is delivered. The metal may be a transition metal such as halogen (Hf), zirconium (Zr), or titanium (Ti), a rare earth metal such as yttrium (La), yttrium (Yb), or yttrium (Y), an alkali earth metal such as strontium (Sr), or other metals such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor may be or contain water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen and oxygen-containing precursor, plasma-enhanced oxygen containing local or remote enhanced oxygen, or any other material containing oxygen that can combine with the metal to produce a layer of metal oxide on the substrate 302. In one example, the metal-containing precursor is hafnium tetrachloride (HfCl ₄ ) and the oxidant is water (H ₂ O) to form a hafnium dioxide (HfO ₂ ) layer. The ALD process can be performed at a temperature between 200° C. and about 400° C., for example, about 270° C. As deposited by the ALD process, the high-κ gate dielectric layer 306 can be amorphous and have a thickness between about 10 Å and about 30 Å. The deposition process can be performed in a processing chamber such as the processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1 .

In block 240, an optional post-deposition annealing process is performed to harden and densify the deposited high-κ gate dielectric layer 306. Crystallization of the deposited amorphous high-κ gate dielectric layer 306 may occur. The post-deposition annealing process may include a thermal annealing process in an inert environment (e.g., a nitrogen ( _N2 ) and argon (Ar) environment) performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California, USA. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG1. The post-deposition annealing process may thermally harden and densify the interface layer 304 and the high-κ dielectric layer 306.

The post-deposition annealing process may be performed at a temperature between about 500° C. and about 800° C. and a pressure between about 0.01 Torr and 100 Torr for a time between about 1 second and about 60 seconds.

In block 250, an optional reoxidation process is performed to thermally oxidize the substrate 302 in place of the post-deposition anneal process in block 240. The reoxidation process may include a thermal annealing process in an oxygen ( _O2 ), nitrous oxide ( _N2O ), and _H2 environment performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The reoxidation process in box 250 can thermally oxidize the underlying layers through the high-κ gate dielectric layer 306, thereby thickening the interface layer 304 to a thickness between about 3Å and about 10Å if the interface layer 304 is formed in box 220, and forming the interface layer 304 in the substrate 302 near the junction with the high-κ dielectric layer 306 if the interface layer 304 is not formed in box 220.

The reoxidation process may be performed at a temperature between about 400° C. and about 900° C. and a pressure between about 0.01 Torr and 100 Torr for a time between about 1 second and about 30 seconds.

In block 260, a plasma nitridation process is performed to insert nitrogen atoms into pores and defects in the high-κ gate dielectric layer 306. The plasma nitridation process may be a decoupled plasma nitridation (DPN) process performed in a DPN chamber, such as a CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, California. The DPN chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The plasma nitridation process exposes the high-κ gate dielectric layer 306 to nitrogen plasma, which can enable nitrogen radicals or nitrogen atoms to be bonded into the high-κ gate dielectric layer 306 throughout the thickness of the high-κ gate dielectric layer 306. During the plasma nitridation process, the nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in the plasma process include nitrogen-containing gases, such as nitrogen ( _N2 ), ammonia ( _NH3 ), or mixtures of these gases. In one example, the nitrogen-containing gas is ammonia ( _NH3 ) mixed with about 3% to about 8% nitrogen ( _N2 ). As a result of the incorporation of nitrogen into the pores and defects of the deposited high-κ gate dielectric layer 306 , the plasma nitridation process may not change the thickness of the high-κ gate dielectric layer 306 .

The nitridation process may be performed at a temperature between about 0°C and about 500°C for a time between about 10 seconds and about 300 seconds.

In block 270, an optional thermal nitridation process is performed to further insert nitrogen atoms into the pores and defects in the plasma nitrided high-κ gate dielectric layer 306. The thermal nitridation process may include a thermal annealing process in an ammonia (NH ₃ ) environment performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California, USA. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 .

The thermal nitridation process may be performed at a temperature between about 700° C. and about 900° C. and a pressure between about 10 Torr and 740 Torr for a time between about 10 seconds and about 300 seconds.

In block 280, a post-nitridation anneal process is performed to passivate the chemical bonds remaining in the high-κ gate dielectric layer 306 after the plasma nitridation. The post-nitridation anneal process may include a spike thermal anneal process in a nitrogen ( _N2 ) and argon (Ar) environment performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The post-nitridation annealing process may passivate the metastable nitrogen bonds formed during the plasma nitridation process in block 240 and may cause crystallization of the amorphous high-κ gate dielectric layer 306 to occur.

The spike thermal annealing process may be performed at a temperature between about 700° C. and about 850° C. and a pressure between about 10 Torr and 740 Torr for a time between about 1 second and about 30 seconds.

In block 290, instead of the post-nitridation annealing process in block 280, a post-nitridation annealing and reoxidation process is performed to simultaneously passivate the remaining chemical bonds in the high-κ gate dielectric layer 306 as in block 280 and thermally oxidize the substrate 302 as in block 250. The post-nitridation annealing and reoxidation process in block 290 is the same as the reoxidation process in block 250. Therefore, the details of the post-nitridation annealing and reoxidation process in block 290 are omitted here.

4 is a process flow diagram of a method 400 for forming a metal gate structure 500 on a high-κ gate dielectric layer 306 in a semiconductor structure 300 according to one or more embodiments of the present disclosure. FIGS. 5A, 5B, and 5C are cross-sectional views of a portion of the metal gate structure 500 in the semiconductor structure 300 corresponding to various states of the method 400. It should be understood that FIGS. 5A, 5B, and 5C are only partial schematic views of the semiconductor structure 300, and the semiconductor structure 300 may include any number of transistor portions and additional materials having multiple states as shown. It should also be noted that, although the method steps shown in FIG. 4 are described in sequence, other process sequences including one or more method steps that have been omitted and/or added, and/or rearranged in another desired sequence also fall within the scope of the various embodiments of the present disclosure provided herein.

The method 400 begins with a deposition process in block 410 to deposit a high-κ dielectric cap layer 502 on the high-κ gate dielectric layer 306 of the semiconductor structure 300, as shown in FIG5A. The high-κ dielectric cap layer 502 may be formed of a metal nitride material including titanium (Ti) or tantalum (Ta) doped with silicon (Si), aluminum (Al), gallium (Ga), germanium (Ge), indium (In), or tantalum (Hf), such as TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN, or TaHfN. The high-κ dielectric cap layer 502 formed of such doped metal nitride material can prevent silicon (Si) migration during the subsequent silicon deposition process in block 430. The deposition process in block 410 may include an atomic layer deposition (ALD) process, in which a metal-containing precursor containing titanium (Ti) or tantalum (Ta), a nitrogen-containing precursor, and a dopant-containing precursor are delivered to the surface of the high-κ gate dielectric layer 306. Examples of metal-containing precursors containing titanium (Ti) or tantalum (Ta) and examples of nitrogen-containing precursors are listed in the description of block 420. The doped precursor includes aluminum (Al), gallium (Ga), germanium (Ge), halogen (Hf), indium (In), or silicon (Si). Examples of the dopant-containing precursor containing aluminum (Al) include inorganic compounds of aluminum (Al) such as aluminum chloride (AlCl ₃ ) and aluminum bromide (AlBr ₃ ), and organometallic compounds of aluminum (Al) such as trimethylaluminum (TMA, (CH ₃ ) ₃ Al), dimethylaluminum hydride (DMAH, (CH ₃ ) ₂ AlH), tris(diethylamino)aluminum (TDEAA, Al(N(C ₂ H ₅ ) ₂ ) ₃ ), trimethylamine alane (TMAA, AlH ₃ -N(CH ₃ ) ₃ ), triethylamine alane (TEAA, AlH ₃ -N(C ₂ H ₃ ) ₃ ), dimethylethylamine alane ((AlH ₃ -C ₂ H ₅ N(CH ₃ ) ₂ ), triisobutylaluminum (TiBA, [Al(CH ₃ ) ₂ CHCH ₂ ] ₃ )), triethylaluminum (TEAl, Al(C ₂ H ₅ ) ₃ ), dimethylaluminum hydride (DMAH, (CH ₃ ) ₂ AlH) and diethylaluminum chloride (DEAC, (C ₂ H ₅ ) ₂ AlCl). Examples of the dopant-containing precursor containing gallium (Ga) include inorganic compounds of gallium (Ga), such as gallium tribromide (GaBr ₃ ) and gallium trichloride (GaCl ₃ ), and organic metal compounds of gallium (Ga), such as trimethyl gallium (Ga(CH ₃ ) ₃ ), triethyl gallium (Ga(C ₂ H ₅ ) ₃ ), triisopropyl gallium (Ga(CH(CH ₃ ) ₂ ) ₃ ), tris(dimethylamido) gallium (Ga(N(CH ₃ ) ₂ ) ₃ ). ) and tri-tert-butylgallium (Ga(C(CH ₃ ) ₃ ) ₃ ). Examples of the dopant-containing precursor containing germanium (Ge) include inorganic compounds of germanium (Ge) such as digermane (Ge ₂ H ₆ ) and germanium (GeH ₄ ), and organometallic compounds of germanium (Ge) such as tetramethylgermanium ((CH ₃ ) ₄ Ge). Examples of the dopant-containing precursor containing ibnium (Hf) include inorganic compounds of ibnium (Hf), such as hafnium (IV) chloride (HfCl ₄ ), and organometallic compounds of ibnium (Hf), such as hafnium (IV) tert-butoxide (Hf[OC(CH ₃ ) ₃ ] ₄ ), tetrakis(diethylamido)hafnium(IV), [(CH ₂ CH ₃ ) ₂ N] ₄ Hf, and tetrakis(dimethylamido)hafnium(IV), [(CH ₃ ) ₂ N] ₄ Hf) and tetrakis(ethylmethylamido)hafnium(IV),TEMAH, [(CH ₃ )(C ₂ H ₅ )N] ₄ Hf). Examples of the dopant-containing precursor containing indium (In) include inorganic compounds of indium (In), such as indium trichloride (InCl ₃ ) and indium (I) iodide (InI), and organic metal compounds of indium (In), such as triethylindium (In(CH ₂ CH ₃ ) ₃ ) and indium (III) acetylacetonate (In(OCCH ₃ CHOCCH ₃ ) ₃ ). Examples of the dopant-containing precursor containing silicon (Si) include inorganic compounds of silicon (Si), such as silane (SiH ₄ ) and disilane (Si ₂ H ₆ ), and organometallic compounds of silicon (Si), such as trimethylsilane ((CH ₃ ) ₃ SiH) and neopentasilane ((SiH ₃ ) ₄ Si).

The order of delivering the metal-containing precursor, the nitrogen-containing precursor, and the dopant-containing precursor can be changed. In some embodiments, the metal-containing precursor, the nitrogen-containing precursor, and the dopant-containing precursor are delivered alternately. In some embodiments, the metal-containing precursor and the dopant-containing precursor are delivered simultaneously, and after purification, the nitrogen-containing precursor is delivered. Table 1 below shows several non-limiting sequence variations.

Table 1 Exemplary Deposition Sequence Options Sequence 1 Metal-containing precursor → purification → nitrogen-containing precursor → purification → precursor containing dopants → purification → nitrogen-containing precursor → purification → repeat 2 Precursor containing impurities → purification → nitrogen-containing precursor → purification → metal-containing precursor → purification → nitrogen-containing precursor → purification → repeat 3 Metal-containing precursor → purification → (nitrogen-containing precursor + precursor containing dopants) → purification → repeat 4 (Metal-containing precursor + dopant-containing precursor) → purification → nitrogen-containing precursor → purification → repeat 5 Metal-containing precursor → dopant-containing precursor → purification → nitrogen-containing precursor → purification → repeat 6 Precursor containing dopants → Precursor containing metal → Purification → Precursor containing nitrogen → Purification → Repeat

The ALD process in block 410 may be performed at a temperature between about 200° C. and about 700° C. (e.g., between about 300° C. and about 600° C.). As deposited by the ALD process in block 410, the high-κ dielectric cap layer 502 may be amorphous and have a thickness between about 2 Å and about 200 Å (e.g., between about 10 Å and about 15 Å). The deposition process may be performed in a processing chamber such as the processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1 .

In block 420, an optional metal cap anneal process is performed to harden and densify the deposited high-κ dielectric cap layer 502. Crystallization of the deposited high-κ dielectric cap layer 502 may occur. The optional metal cap anneal process in block 420 may include a thermal anneal process in an inert environment, such as a nitrogen ( _N2 ) and argon (Ar) environment, performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, California. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1.

The optional metal cap anneal process in block 420 may be performed at a temperature between about 700° C. and about 850° C. and a pressure between about 0.1 Torr and 100 Torr for a time between about 1 second and about 10 seconds.

In block 430, a deposition process is performed to deposit a sacrificial silicon cap layer 504 on the high-κ dielectric cap layer 502, as shown in FIG5B. The sacrificial silicon cap layer 504 can physically and chemically protect the underlying high-κ gate dielectric layer 306 and the high-κ dielectric cap layer 502 during a subsequent annealing process in block 440. The sacrificial silicon cap layer 504 is formed of amorphous silicon, such as hydrogenated amorphous silicon (a-Si:H). Compared to polycrystalline silicon containing grain boundaries leading path for diffusion, amorphous silicon can provide less atomic diffusion. The deposition process in block 430 may be an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process, wherein the semiconductor structure 300 with _the high-κ dielectric cap layer 502 formed thereon is exposed to a silicon precursor. An example of a silicon precursor is poly-silane ( _SixHy ). For example, polysilanes include disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), tetrasilane (Si ₄ H ₁₀ ), isotetrasilane, neopentasilane (Si ₅ H ₁₂ ), cyclopentasilane (Si ₅ H ₁₀ ), hexasilane ( _{C 6} H ₁₄ ), cyclohexasilane (Si ₆ H ₁₂ ) or generally _SixHy (where x=2 or greater), and combinations thereof.

The sacrificial silicon cap layer 504 may have a thickness between about 30 Å and about 50 Å. The deposition process in block 430 may be performed in a processing chamber such as the processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1 .

In block 440, a post cap anneal (PCA) process is performed to harden and densify the deposited high-κ dielectric cap layer 502. Crystallization of the deposited high-κ dielectric cap layer 502 and the deposited sacrificial silicon cap layer 504 may occur. The PCA process in block 440 may include a thermal annealing process in an inert environment (such as a nitrogen ( _N2 ) and argon (Ar) environment) performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, California, USA. Such an RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1.

The PCA process in block 440 may be performed at a temperature between about 900° C. and about 1000° C. (e.g., about 900° C.) and a pressure between about 0.1 Torr and 100 Torr for a time between about 1 second and about 10 seconds.

In block 450, a removal process is performed to strip the sacrificial silicon cap layer 504. The removal process may include a dry plasma etching process.

Following the removal process in block 460, a deposition process is performed in block 460 to deposit a metal layer 506 on the hardened and densified high-κ dielectric cap layer 502, as shown in FIG. 5C. The metal layer 506 may be formed of tungsten (W) or cobalt (Co). The metal layer 506 may be p-type doped or n-type doped. The deposition process in block 450 may include a chemical vapor deposition process (CVD) using a cobalt-containing precursor or a tungsten-containing precursor such as WF ₆ .

The high-κ dielectric cap layer 502 formed of a doped metal nitride material described herein can be effective as a fluorine barrier, for example, in a deposition process using a fluorine-containing precursor such as WF ₆ in block 460. The high-κ dielectric cap layer 502 formed of a doped metal nitride material described herein can also prevent aluminum (Al) migration, thereby alleviating the need for an aluminum barrier, whereas conventional high-κ dielectric cap layers formed of metal nitride materials such as titanium nitride (TiN) allow aluminum migration. The high-κ dielectric cap layer 502 formed of a doped metal nitride material described herein may also be used as a work function layer to increase the effective work function at the interface between the high-κ dielectric cap layer 502 and the metal layer 506 .

In some implementations, the deposition process for depositing the high-κ dielectric cap layer 502 in block 410 and the deposition process for depositing the sacrificial silicon cap layer 504 in block 430 are performed without disrupting a low pressure or vacuum environment in a processing system such as the processing system 100. Processes that do not disrupt a low pressure or vacuum environment can reduce contamination caused by moisture introduced from the atmospheric environment.

In some embodiments, the deposition process for depositing the high-κ dielectric cap layer 502 in block 410, the deposition process for depositing the sacrificial silicon cap layer 504 in block 430, and the post-cap anneal (PCA) process in block 440 are performed without destroying the low pressure or vacuum environment in a processing system such as the processing system 100. Processes that do not destroy the low pressure or vacuum environment can reduce contamination caused by moisture introduced from the atmospheric environment and further prevent thickening of the high-κ gate dielectric layer 306.

In the various embodiments described herein, systems and methods for forming high-quality thin high-κ dielectric material layers and metal gate structures are provided. The characteristics of such high-κ dielectric material layers can be well controlled. For example, the nitridation process in blocks 260 and 270 can be controlled to provide nitrogen incorporation in the high-κ gate dielectric layer 306 between about 3 atomic % and about 20 atomic %, thereby achieving a higher κ value compared to a higher nitrogen incorporation, and better structural stability compared to a lower nitrogen incorporation. The annealing process in blocks 240, 270, 280, and 290 can also be controlled to provide grains having a size greater than about 20Å in the high-κ gate dielectric layer 306, thereby reducing leakage current flowing through the high-κ gate dielectric layer 306.

The metal gate structure described herein can exhibit reduced equivalent oxide thickness (EOT), reduced leakage current therethrough, and increased effective work function. The metal gate structure described herein can also exhibit aluminum (A) barrier properties, which enables the formation of an aluminum layer directly on the metal gate structure. Such a metal gate structure can be advantageously used in any barrier application and/or any metal gate application in flash memory, dynamic random access memory (DRAM), and MOSFET.

Although the foregoing relates to multiple implementations of the present disclosure, other and further implementations of the present disclosure may be designed without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the scope of the accompanying patent applications.

100: Multi-chamber processing system 102: Factory interface 104: Load gate chamber 106: Load gate chamber 108: Transfer chamber 110: Transfer chamber 112: Transfer robot 114: Transfer robot 116: Holding chamber 118: Holding chamber 120: Processing chamber 122: Processing chamber 124: Processing chamber 126: Processing chamber 128: Processing chamber 130: Processing chamber 140: Dockyard 142: Factory interface robot 144: Front-opening standard cabin 148: Blade 150: Port 152: Port 154: Port 156: Port 158: port 160: port 162: port 164: port 166: port 168: port 170: port 172: port 174: port 176: port 190: system controller 192: central processing unit 194: memory 196: support circuit 200: method 210: box 220: box 230: box 240: box 250: box 260: box 270: box 280: box 290: box 300: semiconductor structure 302: substrate 304: interface layer 306: high-κ gate dielectric layer 400: method 410: box 420: box 430: box 440: box 450: box 460: box 480: box 500: metal gate structure 502: high-κ dielectric cap layer 504: sacrificial silicon cap layer 506: metal layer

In order to understand the above-mentioned features of the present disclosure in detail, the present disclosure briefly summarized above can be described in more detail by referring to a plurality of implementations, some of which are illustrated in the attached figures. However, it should be noted that the attached figures only illustrate typical implementations of the present disclosure and should not be regarded as limiting the scope of the present disclosure, as the present disclosure may allow for other equivalent implementations.

FIG. 1 is a schematic top view of an example multi-chamber processing system according to one embodiment.

FIG. 2 is a process flow diagram of a method for forming a semiconductor structure according to an embodiment.

3A and 3B are schematic diagrams of a semiconductor structure according to an embodiment.

FIG. 4 is a process flow diagram of a method for forming a semiconductor structure according to an embodiment.

5A, 5B and 5C are schematic diagrams of a semiconductor structure according to an embodiment.

To facilitate understanding, identical reference numerals have been used, wherever possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

400:Method

410: Box

420: Box

430: Box

440: Box

450: Box

460: Box

480: Box

Claims (39)

A method for forming a semiconductor structure, the method comprising: forming a high-κ dielectric cap layer on the semiconductor structure, the semiconductor structure being formed on a substrate, comprising: depositing the high-κ dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer; performing a post-cap annealing process to harden and densify the deposited high-κ dielectric cap layer; and removing the sacrificial silicon cap layer. A method as claimed in claim 1, wherein the step of forming the high-κ dielectric cap layer is performed in a processing system without breaking the vacuum. The method as described in claim 1 further includes: performing a post-nitridation annealing process to passivate the chemical bonds in the high-κ dielectric cap layer. The method as described in claim 3 further includes: forming an interface layer on the substrate, the step of forming the interface layer includes thermally oxidizing the substrate using nitrous oxide gas, and the interface layer includes silicon oxide. The method of claim 4 further comprises: depositing a high-κ gate dielectric layer on the interface layer, wherein the high-κ gate dielectric layer comprises HfO ₂ . The method as claimed in claim 5 further comprises: Performing a plasma nitridation process, wherein the plasma nitridation process comprises exposing the deposited high-κ gate dielectric layer to a nitrogen-containing plasma. The method of claim 6 further comprises: performing a post-deposition annealing process before the plasma nitridation process to harden and densify the deposited high-κ gate dielectric layer, wherein the post-deposition annealing process comprises annealing the deposited high-κ gate dielectric layer at a temperature between 500°C and 800°C. The method as claimed in claim 7 further comprises: performing a thermal nitridation process before the post-nitridation annealing process, wherein the thermal nitridation process comprises annealing the plasma nitrided high-κ gate dielectric layer at a temperature between 700°C and 900°C. A method as claimed in claim 3, wherein the post-nitridation annealing process includes spike annealing the deposited high-κ gate dielectric layer at a temperature between 700°C and 850°C. A method as claimed in claim 1, wherein the high-κ dielectric cap layer comprises TiSiN. The method of claim 1, further comprising: performing a metal cap annealing process to harden and densify the high-κ dielectric cap layer at a temperature between 700° C. and 850° C. in a nitrogen (N ₂ ) environment before the deposition of the sacrificial silicon cap layer. The method of claim 1, wherein the post cap annealing process comprises annealing the high-κ dielectric cap layer at a temperature between 900° C. and 1000° C. in a nitrogen (N ₂ ) environment. A method for forming a semiconductor structure, the method comprising: forming the semiconductor structure on a substrate, including: pre-cleaning a surface of the substrate; depositing a high- κ gate dielectric layer on the substrate; and performing a plasma nitridation process to insert nitrogen atoms in the deposited high -κ gate dielectric layer; forming a high-κ dielectric cap layer on the semiconductor structure, the semiconductor structure is formed on the substrate, including: depositing the high-κ dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer; performing a post-cap annealing process to harden and densify the high-κ dielectric cap layer; and removing the sacrificial silicon cap layer. The method of claim 13, wherein the step of forming the high-κ dielectric cap layer is performed in a processing system without breaking the vacuum. The method of claim 13 further comprises: forming an interface layer on the pre-cleaned surface of the substrate, comprising thermally oxidizing the substrate using nitrous oxide (N ₂ O) gas, wherein the interface layer comprises silicon oxide (SiO ₂ ). The method of claim 13, wherein the high-κ gate dielectric layer comprises helium oxide (HfO ₂ ). The method of claim 13, wherein the plasma nitridation process comprises exposing the deposited high-κ gate dielectric layer to a nitrogen plasma using a mixture of nitrogen (N ₂ ) and ammonia (NH ₃ ). The method of claim 13, further comprising: performing a metal cap annealing process to harden and densify the high-κ dielectric cap layer at a temperature between 700° C. and 850° C. in a nitrogen (N ₂ ) environment prior to the deposition of the sacrificial silicon cap layer. The method of claim 13, wherein the post cap anneal process comprises annealing the high-κ dielectric cap layer at a temperature between 900° C. and 1000° C. in a nitrogen (N ₂ ) environment. A processing system includes: a first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; a fifth processing chamber; and a system controller, wherein the system controller is configured to cause the processing system to: pre-clean a surface of a substrate in the first processing chamber; form an interface layer on the substrate in the second processing chamber; on the surface after pre-cleaning; in the third processing chamber, a high-κ gate dielectric layer is deposited on the interface layer; in the fourth processing chamber, a plasma nitridation process is performed to insert nitrogen atoms in the deposited high-κ gate dielectric layer; and in the fifth processing chamber, a post-nitridation annealing process is performed to passivate the chemical bonds in the high-κ gate dielectric layer after plasma nitridation. The processing system of claim 20 further comprises: one or more transfer chambers, wherein the system controller is further configured to cause the processing system to transfer the substrate between the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber, and the fifth processing chamber through the one or more transfer chambers without destroying the vacuum environment in the processing system. The processing system of claim 20, wherein the interface layer comprises silicon oxide (SiO ₂ ), and the step of forming the interface layer comprises thermally oxidizing the substrate using nitrous oxide (N ₂ O) gas. The processing system of claim 20, wherein the high-κ gate dielectric layer comprises helium oxide (HfO ₂ ). The processing system of claim 20, wherein the plasma nitridation process comprises exposing the deposited high-κ gate dielectric layer to a nitrogen plasma using a mixture of nitrogen (N ₂ ) and ammonia (NH ₃ ). The processing system of claim 20, wherein the post-nitridation annealing process comprises spike annealing the deposited high-κ gate dielectric layer at a temperature between 700° C. and 850° C. in a nitrogen (N ₂ ) and argon (Ar) environment. The processing system as described in claim 20 further includes: a sixth processing chamber, wherein the system controller is further configured to cause the processing system to perform a post-deposition annealing process in the sixth processing chamber before the plasma nitridation process to harden and densify the deposited high-κ gate dielectric layer, the post-deposition annealing process comprising annealing the deposited high-κ gate dielectric layer at a temperature between 500°C and 800°C and in a nitrogen ( _N2 ) and argon (Ar) environment. The processing system as described in claim 20 further includes: a sixth processing chamber, wherein the system controller is further configured to cause the processing system to perform a thermal nitridation process in the sixth processing chamber before the post-nitridation annealing process to further insert nitrogen atoms into the high-κ gate dielectric layer after plasma nitridation, the thermal nitridation process comprising annealing the high-κ gate dielectric layer after plasma nitridation at a temperature between 700°C and 900°C and in an ammonia (NH ₃ ) environment. A processing system includes: a first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; a fifth processing chamber; and a system controller, wherein the system controller is configured to cause the processing system to: pre-clean a surface of a substrate in the first processing chamber; deposit a high-κ gate dielectric layer in the second processing chamber; on the substrate; in the third processing chamber, performing a reoxidation process to thermally oxidize the substrate; in the fourth processing chamber, performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ gate dielectric layer; and in the fifth processing chamber, performing a post-nitridation annealing process to passivate chemical bonds in the high-κ gate dielectric layer after plasma nitridation. The processing system of claim 28 further comprises: one or more transfer chambers, wherein the system controller is further configured to cause the processing system to transfer the substrate between the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber, and the fifth processing chamber through the one or more transfer chambers without destroying the vacuum environment in the processing system. The processing system of claim 28 further comprises: a sixth processing chamber, wherein the system controller is further configured to cause the processing system to form an interface layer on the pre-cleaned surface of the substrate by thermally oxidizing the substrate using nitrous oxide ( _N2O ) gas in the sixth processing chamber, wherein the interface layer comprises silicon oxide ( _SiO2 ). The processing system of claim 28, wherein the high-κ gate dielectric layer comprises helium oxide (HfO ₂ ). The processing system of claim 28, wherein the plasma nitridation process comprises exposing the deposited high-κ gate dielectric layer to a nitrogen plasma using a mixture of nitrogen ( _N2 ) and ammonia ( _NH3 ). A processing system as described in claim 28, wherein the reoxidation process includes annealing the high-κ gate dielectric layer at a temperature between 400°C and 900°C in an environment of oxygen ( _O2 ), nitrous oxide ( _N2O ) and _H2 ; and the post-nitridation annealing process includes spike annealing the high-κ gate dielectric layer after plasma nitridation at a temperature between 700°C and 850°C in an environment of nitrogen ( _N2 ) and argon (Ar). A processing system includes: a first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; and a system controller, wherein the system controller is configured to cause the processing system to: pre-clean a surface of a substrate in the first processing chamber; deposit a high-κ gate dielectric layer on the substrate in the second processing chamber; perform a plasma nitridation process in the third processing chamber to insert nitrogen atoms in the deposited high-κ gate dielectric layer; and perform a re-oxidation process in the fourth processing chamber to passivate the remaining chemical bonds in the plasma nitrided high-κ gate dielectric layer and thermally oxidize the substrate. The processing system of claim 34 further comprises: one or more transfer chambers, wherein the system controller is further configured to cause the processing system to transfer the substrate between the first processing chamber, the second processing chamber, the third processing chamber, and the fourth processing chamber through the one or more transfer chambers without destroying the vacuum environment in the processing system. The processing system of claim 34 further comprises: a fifth processing chamber, wherein the system controller is further configured to cause the processing system to form an interface layer on the pre-cleaned surface of the substrate by thermally oxidizing the substrate using nitrous oxide ( _N2O ) gas in the fifth processing chamber, wherein the interface layer comprises silicon oxide ( _SiO2 ). The processing system of claim 34, wherein the high-κ gate dielectric layer comprises helium oxide (HfO ₂ ). The processing system of claim 34, wherein the plasma nitridation process includes exposing the deposited high-κ gate dielectric layer to a nitrogen plasma using a mixture of nitrogen ( _N2 ) and ammonia ( _NH3 ). The processing system of claim 34, wherein the reoxidation process comprises annealing the high-κ gate dielectric layer at a temperature between 400° C. and 900° C. in an ambient of oxygen (O ₂ ), nitrous oxide (N ₂ O), and H ₂ .