JP2004504751A - High-speed switching input buffer - Google Patents

Abstract

The input buffer circuit (300) for a semiconductor device includes a PMOS transistor (306), an NMOS transistor (308), and a pull-up circuit (314). The pull-up circuit (314) applies a voltage to the bulk region of the PMOS transistor (306) to cause a positive body effect, which temporarily inputs the absolute value of the threshold voltage of the PMOS transistor (306). Reduce if buffer (300) is switched. This allows the input buffer (300) to switch faster than conventional input buffers. The input buffer (300) is an inverter, NOR, NAND, or other input buffer.

Description

[0001]
【Technical field】
The present invention relates generally to CMOS input buffers for semiconductor devices.
[0002]
[Background Art]
Complementary metal oxide semiconductor (CMOS) input buffers have been used for semiconductor devices for many years. An important feature of the input buffer is the switching time, which is the time required for a high-to-low transition or vice versa.
[0003]
FIG. 1 shows an example of a conventional CMOS inverter input buffer 100 for a semiconductor device. CMOS inverter input buffer 100 includes a P-channel MOSFET transistor 106, also called a PMOS transistor, and an N-channel MOSFET transistor 108, also called an NMOS transistor, in a complementary configuration. The gates of the PMOS and NMOS transistors 106, 108 are connected to an input node 102, also called an input terminal. Since both gates are connected to input node 102, the input signal is also referred to as gate voltage Vg. The output signal is transmitted from an output node 110, also called an output terminal. Output node 110 is connected to the drains of PMOS and NMOS transistors 106,108. When a low signal of substantially 0 volts is applied to input node 102, PMOS transistor 106 turns on and NMOS transistor 108 turns off, driving output node 110 high. When a high signal, which is substantially a power supply voltage, is applied to the input terminal 102, the PMOS transistor 106 turns off and the NMOS transistor 108 turns on, driving the output node low. Since one of the PMOS and NMOS transistors is off, little DC current is consumed.
[0004]
FIG. 2 shows an example of a conventional CMOS NOR input buffer 200. The CMOS NOR input buffer 200 includes first and second PMOS transistors 210 and 212, and first and second NMOS transistors 214 and 216. The gate of the second PMOS transistor 212 and the gate of the first NMOS transistor 214 are connected to the input node 202. The output signal is transmitted from an output node 210 connected to the drain of the second PMOS transistor 212 and the drains of the first and second NMOS transistors 214, 216. The control signal “power down” is received at control node 218. Control node 218 is connected to the gate of first PMOS transistor 210 and the gate of second NMOS transistor 216.
[0005]
DISCLOSURE OF THE INVENTION
An input buffer circuit for a semiconductor device including a PMOS transistor, an NMOS transistor, and a pull-up circuit. The pull-up circuit applies a voltage to the bulk region of the PMOS transistor, causing a positive body effect that temporarily reduces the absolute value of the voltage threshold of the PMOS transistor when the input buffer switches. This causes the input buffer to switch faster than a conventional input buffer. The input buffer is an inverter, NOR, NAND, or other input buffer.
[0006]
The present invention will be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Further, the left-most digit (s) of a reference number identifies the drawing in which the reference number first appears.
[0007]
Mode for carrying out the invention
Input devices for semiconductor devices, such as memory devices such as SRAMs and DRAMs, provide fast switching between a high output state and a low output state. The input device operates with low current leakage and low power supply voltage. The present invention temporarily lowers the absolute value of the threshold voltage to reduce switching time without substantial current leakage.
[0008]
The input buffer monitors the input node for signals and switches the output node based on the input node. While the input buffer and circuitry beyond the output node operate between the power supply voltage Vcc and ground, the signals received at the inputs may be in a smaller range, for example, Vih and Vil. Vih represents a "high" signal and Vil represents a "low" signal. As a result of wiring capacitance and other factors, Vil is often higher than ground and Vih is often lower than the power supply voltage.
[0009]
PMOS transistors tend to switch at a slower speed when operating at lower power supply voltages. A low power supply voltage is a power supply voltage lower than 3.3 volts, such as 1.8 volts or 1.6 volts. In many applications, it is desirable to have a switch that operates as fast as possible.
[0010]
The principle of CMOS design is that PMOS transistors are "weaker" than NMOS transistors. This is due to mobility factors. Since the absolute value | V _t | of the threshold voltage of the PMOS transistor is often very high relative to the threshold voltage of the NMOS transistor, the switching time from “high” to “low” of the input buffer is generally Faster than the switching time from "low" to "high". The threshold voltage is used to determine whether the signal on the input line is high or low. If the absolute value of the threshold voltage of the PMOS transistor is reduced in an attempt to reduce the switching speed, the current leakage in the PMOS transistor increases, which is undesirable. The present invention temporarily reduces the absolute value of the threshold voltage to reduce switching time without causing substantial current leakage, as shown in FIGS.
[0011]
FIG. 3 shows an example of a CMOS inverter input buffer 300 with fast switching and low current leakage. CMOS inverter input buffer 300 includes PMOS transistor 306, NMOS transistor 308 in a complementary configuration, pull-up device 314, and optional capacitor 312. The gates of the PMOS and NMOS transistors 306, 308 are connected to the input node 302. The output signal is transmitted from output node 310, which is connected to the drains of PMOS and NMOS transistors 306,308. The pull-up device 314, for example, a register, is connected to the power supply voltage and the bulk of the PMOS transistor 306.
[0012]
The resistance of the pull-up device 314 depends on the characteristics of the input buffer 300, and particularly on the characteristics of the PMOS transistor 306. For example, the resistance can be from 1 kOhm to 3000 kOhm. Other pull-up devices 314 may be used, as long as they provide a voltage to the bulk region of the PMOS transistor, but these are, for example, RL circuits, diodes, or other devices. The pull-up device 314 acts as a charging mechanism for supplying a voltage to the bulk of the PMOS transistor 306.
[0013]
Optional capacitor 312 is connected to the gate and bulk of the PMOS transistor. Capacitor 312 adds gate capacitance to input buffer 300 when PMOS and NMOS transistors 306, 308 do not provide enough input capacitance to increase the switching time of the buffer.
[0014]
When the input signal goes low, ie, when Vil is received at input node 302, the gate capacitance momentarily pulls the bulk region of PMOS transistor 306 low. This reduces the absolute value | V _t | of the threshold voltage. Thus, PMOS transistor 306 becomes "stronger" and current flows faster through the P-channel. The pull-up device 314 charges the bulk region of the PMOS transistor 306 again toward the power supply voltage after the output has switched to high. Optionally, PMOS transistor 306 and pull-up device 314 are connected to different power supply voltages.
[0015]
FIG. 4 shows an example of a CMOS NOR input buffer 400 with fast switching and low current leakage. The CMOS NOR input buffer 400 includes first and second PMOS transistors 410 and 412, first and second NMOS transistors 414 and 416, first and second pull-up devices 406 and 408, and an optional capacitor. 422. The gate of the second PMOS transistor 412 and the gate of the first NMOS transistor 414 are connected to the input node 402. The output signal is transmitted from output node 420, which is connected to the drain of second PMOS transistor 412 and the drains of first and second NMOS transistors 414, 416. The sources of the first and second NMOS transistors 414, 416 are connected to ground. The source of the second PMOS transistor 412 is connected to the drain of the first PMOS transistor 410. The source of the first PMOS transistor 410 is connected to the power supply voltage 404. A control signal labeled “power down” is received at control node 418. The control signal is connected to the gate of the first PMOS transistor 410 and the gate of the second NMOS transistor 416. Control node 418 and input node 402 are inputs to a NOR circuit, and output nodes are outputs of the NOR circuit.
[0016]
The first pull-up device 406 is connected to the power supply voltage and the bulk of the first PMOS transistor 410. A second pull-up device 408, also called a pull-up circuit, is connected to the power supply voltage 404 and the bulk of the second PMOS transistor 412. The resistance of the pull-up devices 406 and 408 depends on the characteristics of the input buffer 400, and particularly on the characteristics of the connected PMOS transistor. For example, the resistance of the pull-up devices 406, 408 can be from 1 kOhm to 3000 kOhm. Other values are also acceptable depending on the characteristics of the input buffer 400. The pull-up devices 406, 408 may include other circuits as long as they supply a voltage to the bulk region of the PMOS transistors 410, 412, such as RL circuits, RLC circuits, diode circuits, or other devices. . The pull-up devices 406 and 408 in this embodiment act as charging means for supplying a voltage to the bulk of the PMOS transistors 410 and 412. In other embodiments, only one of the two pull-up devices 406, 408 is used.
[0017]
An optional capacitor 422 may be added to increase the gate capacitance. Optional capacitor 422 is connected to the gate and bulk of second PMOS transistor 412.
[0018]
Optionally, the first PMOS transistor 410 and the pull-up devices 406, 408 are connected to different supply voltages. Conventional power supply voltages are 5.0 volts and 3.3 volts. The invention is preferably used with low power input buffers. The low power input buffer has a supply voltage of 3.3 volts or less. For example, the power supply voltage may be about 2.0 volts to 1.0 volt. The invention can also be used in other power supply voltage ranges.
[0019]
FIG. 5 is a cross-sectional view of a PMOS transistor 500 that implements the elements of the present invention. PMOS transistor 500 includes an N-type substrate region 526, a dielectric region 524, two P-type regions 518, 522, and a P-channel region 520, also referred to as an N-well region. The external interface of the PMOS transistor 500 includes a source 512, a gate 514, a drain 516, and a bulk 528. PMOS transistor 500 has a pull-up device 506 that connects bulk 528 to a power supply voltage at source node 504. Optional capacitor 508 connects bulk 528 to gate 514. Gate 514 is connected to gate node 502 that receives a gate signal. Drain 516 is connected to drain node 510 that transmits the output from PMOS transistor 500. If substantially zero volts of ground is applied to gate node 502, no P-channel 520 is created and drain 516 provides minimal current. When a negative voltage is applied to gate node 502, electrons are driven off the surface, creating a P-channel 520, a conductive region, providing a positive current from source 512 to drain 516.
[0020]
The body effect phenomenon in the NMOS transistor occurs when a potential difference called Vbs between the back gate voltage Vb and the source potential Vs is changed negatively by the voltage of the input signal, and the absolute value of the threshold voltage of the NMOS transistor Increase. For PMOS transistors, the potential difference Vbs is changed positively to increase the absolute value of the threshold voltage. When this phenomenon occurs in the NMOS transistor, the voltage Vgs from the gate to the source decreases, the driving force of the NMOS transistor decreases, and the signal transfer resistance increases. This is known as the "negative" substrate effect. The present invention uses a complementary phenomenon called the "positive" body effect to temporarily lower the absolute value of the threshold voltage of a PMOS transistor.
[0021]
The input buffers 300 (FIG. 3), 400 (FIG. 4) described above have a high DC threshold voltage that results in a low leakage voltage. Further, the input buffers 300, 400 have a low AC threshold voltage which results in faster switching and lower leakage voltage. It is estimated that such an input buffer can switch from high to low in 50% to 60% of the time of a conventional low voltage input buffer.
[0022]
Input buffer 500 may be used in a variety of devices, including computers, cell phone flash memory, semiconductor memory used in logic and other circuits. In the preferred embodiment, input buffer 500 is used in a low voltage semiconductor memory.
[0023]
As the input line transitions from high to low and from logic one to logic zero, the gate capacitance is momentarily pulled down. This reduces the absolute value of the threshold voltage. The current then travels faster through the P-channel. This quickly switches the output voltage Vo from low to high. The voltage Vbulk at the bulk layer is recharged to the full supply voltage through pull-up device 506 after output node 510 is switched high. Optionally, a capacitor 508 is added to increase the gate-bulk capacitance.
[0024]
The following equation describes the effect on the absolute value of the threshold voltage.
_{| V t | = V t0 +} δ * [sqrt (2Φ F + V bs) -sqrt (2Φ F)] Equation 1
here:
| V _t | is the absolute value of the threshold voltage of the PMOS transistor.
[0025]
V _t0 is a threshold voltage when V _bs = 0.
δ is a bias effect constant of the substrate. This constant is a function of the fabrication process and can vary from device to device.
[0026]
Φ _F is the bulk potential. Bulk potential is a function of the fabrication process and can vary from device to device.
[0027]
_Vbs is the voltage difference between the bulk and the source.
In order to temporarily lower the absolute value | V _t | of the threshold voltage when the gate voltage goes from high to low, | V _bs | is lowered, and the bulk voltage V _b is reduced to the source voltage V _s . , Which means that the bulk-source voltage _Vbs is negative. When the gate voltage switches low, the bulk voltage is combined with the gate voltage and is lower than the power supply voltage. This temporarily lowers the absolute value | V _t | of the threshold voltage of the PMOS transistor, and accelerates the switching of the output voltage V _out .
[0028]
The RC circuits, for example 506 and 508 (FIG. 5), are preferably scaled to avoid a latch-up condition when the bulk voltage is lower than the source voltage.
[0029]
Although FIGS. 3-5 illustrate an inverter and a NOR input buffer, the invention can be implemented with other input buffers used for semiconductor devices such as memory devices. For example, the present invention may be used in a NAND input buffer.
[0030]
While preferred embodiments have been shown and described, they are not intended to limit this disclosure, and all methods and apparatus modifications and alternatives are defined in the following claims and equivalents thereof. It will be understood that the invention is intended to be within the spirit and scope of the invention.
[Brief description of the drawings]
FIG. 1 is a diagram showing a conventional CMOS inverter input buffer.
FIG. 2 is a diagram showing a conventional CMOS NOR input buffer.
FIG. 3 illustrates an embodiment of the invention relating to a CMOS inverter input buffer.
FIG. 4 illustrates an embodiment of the present invention relating to a CMOS NOR input buffer.
FIG. 5 is a cross-sectional view of a PMOS transistor realizing the elements of the present invention.

Claims (10)

An input buffer circuit (300) for a semiconductor device,
(A) an input node (302);
(B) an output node (310);
(C) a PMOS transistor (306) having a source node, a gate node, a drain node, and a bulk node, wherein the source node of the PMOS transistor (306) is connected to a first power supply voltage (304); And (d) an NMOS transistor (308) having a source node, a gate node, and a drain node, wherein the source node is connected to ground;
The gate nodes of the PMOS and NMOS transistors (306, 308) are connected to the input node (302), and the drain nodes of the PMOS and NMOS transistors (306, 308) are connected to the output node (310). And (e) an input buffer circuit (300) including a pull-up circuit (314) connected to the bulk node of the PMOS transistor (306) and a second power supply voltage. The input buffer circuit (300) of claim 1, wherein the input buffer circuit (300) comprises a low power input buffer circuit. The input buffer circuit (300) of claim 1, wherein the first (304) and second power supply voltages provide substantially the same voltage. The input buffer circuit (300) according to claim 1, wherein the first power supply voltage (304) is less than or equal to 1.9 volts. The input buffer circuit (300) of claim 1, wherein the pull-up circuit (314) includes a register. The input buffer circuit (300) of claim 1, further comprising a capacitor circuit (312) connected to a source node and a bulk node of said PMOS transistor (306). The input buffer circuit (300) of claim 1, wherein the pull-up circuit (314) reduces a threshold voltage of the PMOS transistor (306) and reduces a switching time of the input buffer circuit (300). The input buffer circuit (300) according to claim 1, wherein the input buffer circuit (300) includes a CMOS inverter circuit. An input buffer circuit (400),
An input node (402);
An output node (420);
A selection node (418);
A first and a second PMOS transistor each comprising a source node, a gate node, a drain node and a bulk node, wherein the source node of the second PMOS transistor is a first power supply. A first and second NMOS transistor (414, 416) connected to a voltage (404) and each having a source node, a gate node, and a drain node; A source node of the first NMOS transistor (414) is connected to the ground, a drain node of the first and second NMOS transistors (414, 416) is connected to an output node (420), and a gate node of the first NMOS transistor (414). Is connected to an input node (402) and the second NMO The gate node of the transistor (416) is connected to the selection node (418), the drain node of the first PMOS transistor (410) is connected to the output node (420), and the gate of the first PMOS transistor (410). A node connected to an input node (402), a gate node of the second PMOS transistor (412) connected to a selection node (418),
A first pull-up circuit (406) is connected to a bulk node of the first PMOS transistor (410) and a second power supply voltage, and a second pull-up circuit (408) is connected to the second PMOS transistor (412). An input buffer circuit (400), wherein the input buffer circuit (400) is connected to the bulk node of (3) and a third power supply voltage. A memory device,
(A) including a CMOS input buffer (300), wherein the CMOS input buffer (300) includes at least one NMOS transistor (308) and at least one PMOS transistor (306) connected to the NMOS transistor (308); A pull-up circuit (314) for connecting a bulk node of the PMOS transistor (306) to a power supply voltage (304); and (b) an array of memories connected to a CMOS input buffer (300). apparatus.