JP2003298150A - Method for manufacturing magnetic tunnel junction element and magnetic tunnel junction device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a magnetic tunnel junction element (TMR element) to enhance a production yield. <P>SOLUTION: A laminated layer composed of a first conductive material layer, an antiferromagnetic layer, a first ferromagnetic layer, a tunnel barrier layer, a second ferromagnetic layer and a second conductive material layer in this order from below is formed on an insulating film 22 coating a substrate 20. Thereafter, the second conductive material layer is subjected to a selective etching process to form a hard mask, and an isolated trench 38 is formed in a laminated layer by an ion milling process with this mask as a selective mask. After the residual hard mask is subjected to the selective etching process to form hard masks 34a to 34c, a residual part of the laminated layer is etched until reaching the antiferromagnetic layer (or the first conductive material layer) by the ion milling process with the masks 34a to 34c as the selective mask to form an isolated trench 42 to obtain TMR elements Ta to Tc. An assembly in a side wall of the isolated trenches 38, 42 is removed. An end of the tunnel barrier layer is cleaned, thereby preventing an electric short-circuit or a leak. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a magnetic tunnel junction element used for a magnetic sensor and the like, and a magnetic tunnel junction device such as a magnetic sensor and a magnetic memory suitable for manufacturing by this method. In the following description, the magnetic tunnel junction element will be abbreviated as a TMR element.

[0002]

2. Description of the Related Art Conventionally, as a method of manufacturing a magnetic sensor having a plurality of TMR elements, those shown in FIGS. 38 to 43 have been proposed (for example, Japanese Patent Application No. 11- 368767).

In the process of FIG. 38, a Cr layer 3 as a lower electrode layer, a Rh-Mn alloy layer 4 as an antiferromagnetic layer, and a lower ferromagnetic layer are formed on a silicon oxide film 2 covering the surface of a silicon substrate 1. After the Ni-Fe alloy layer 5 as a layer is sequentially stacked and formed by the sputtering method, Al is formed on the Ni-Fe alloy layer 5.
A layer is formed and oxidized to form an alumina layer 6 as a tunnel barrier layer, and a Ni—Fe alloy / Co laminated layer (Co is a lower layer) as an upper ferromagnetic layer is formed on the alumina layer 6.
7 and a Mo layer 8 as an upper electrode layer are sequentially stacked to form a sputtering method. The Mo layer 8 has a structure shown in FIG.
26A and 26B, the resist layers 9a and 9b having a quadrilateral pattern are formed by a well-known photolithography process.

Next, in the step of FIG. 39, the resist layer 9
By forming the isolation trench 10 in the stack of layers 3 to 8 so as to reach the silicon oxide film 2 by selective ion milling using a and 9b as a mask, the stack is formed of portions 3a to 8a of layers 3 to 8. First laminated part and part 3 of layers 3-8
It is separated into a second laminated portion composed of b to 8b. After that, the resist layers 9a and 9b are removed.

In the ion milling process of FIG. 39, the process shown in FIG.
As shown in, the sidewall deposition film DP ₁ is formed on the sidewall of the isolation trench 10. The sidewall deposited film DP ₁ is formed of the resist layers 9a, 9
b contains a large amount of a resist modifying component (organic substance) generated by being abraded by ion milling, and the layer 3a is also included.
.About.5a, 7a, 8a, and the constituents of the silicon oxide film 2.

In the resist removing step of FIG. 39, the resist layers 9a and 9b are subjected to an ashing treatment with O ₂ plasma, and then a stripping treatment is carried out using an organic stripping solution. However, even if such a treatment is performed, it is difficult to completely remove the sidewall deposition film DP ₁ , and the resist residue R
₁ , R ₂ remains. The resist residues R ₁ and R ₂ are, in addition to the resist modifying components derived from the resist layers 9a and 9b,
Since it contains a metal component and a component such as SiO ₂ , it is difficult to completely remove it by a resist removing process using an organic solvent or the like.

In the step of FIG. 40, a resist layer 9 is formed on each of the first and second laminated portions obtained in the step of FIG.
c, 9d and the resist layer 9e are formed by photolithography. The patterns of the resist layers 9c, 9d and 9e are quadrangular patterns as shown in Ta, Tb and Tc of FIG.

In the process of FIG. 41, the resist layers 9c-9e are formed.
By forming the isolation groove 12 in the first and second laminated portions so as to reach the layer portions 4a and 4b by the selective ion milling treatment (or the selective wet etching treatment) using the mask as the TMR element Ta, Tb, Obtain Tc. T
The MR element Ta includes portions 3 a and 4 a of the layers 3 and 4 surrounded by the separation groove 10 and portions 5 a of layers 5 to 8 surrounded by the separation groove 12.
_{1 to} 8a ₁ and the TMR element Tb is composed of the portions 3a and 4a of the layers 3 and 4 surrounded by the separation groove 10 and the separation groove 1.
The layers 5 to 8 surrounded by ₂ are laminated with the portions 5a _{2 to} 8a ₂ . The layer portions 3a and 4a are laminated so that the TMR element Ta,
It is an electrode layer common to Tb and interconnects the TMR elements Ta and Tb. The TMR element Tc includes portions 3b and 4b of the layers 3 and 4 separated from the layer portions 3a and 4a by the separation groove 10.
And portions 5b to 8b of layers 5 to 8 surrounded by the separation groove 12 are laminated. After the ion milling process, the resist layer 9
Remove c-9e.

In the ion milling process of FIG. 41, the process of FIG.
45, the sidewall deposition films DP ₂ and DP _{3 are} formed on the sidewalls of the isolation trenches 10 and 12 in the same manner as described above.
Is formed. Then, in the resist removing step of FIG. 41, the ashing process and the organic stripping solution process are performed in the same manner as described above with respect to the process of FIG. 39. Even in this case, the sidewall deposition films DP ₂ and DP ₃ are completely removed. It is difficult to do so, and the resist residues R _{3 to} R ₆ remain. The sidewall deposited films DP ₂ and DP ₃ are formed of the resist layers 9c to 9c.
e is a layer containing a large amount of a resist modifying component (organic substance) generated by being scraped by ion milling.
.About.5a, 7a, 8a, and the constituent components of the silicon oxide film 2. The resist residues R _{3 to} R ₆ are
It is mainly composed of a resist modifying component derived from the resist layers 9c to 9e. Note that, in the resist removing step of FIG. 41, the resist residue may remain on the side wall of the separation groove 12 at a place where the side wall deposited film DP ₂ is not present.

In the process of FIG. 42, TMR elements Ta to Tc are used.
Then, a silicon oxide film 13 as an interlayer insulating film is formed on the upper surface of the substrate by covering the isolation trenches 10 and 12 by a sputtering method. Then, by the selective ion milling process, connection holes 13a to 13c corresponding to the Mo layers 8a ₁ , 8a ₂ and 8b of the TMR elements Ta to Tc are formed in the silicon oxide film 13.

In the process of FIG. 43, after the connection holes 13a to 13c are covered on the silicon oxide film 13 by depositing Al by the sputtering method, the deposit layer is patterned by the selective ion milling process to form the wiring layer. Layers 14a, 1 as
4b is formed. The Al layer 14a is connected to the Mo layer 8a ₁ of the TMR element Ta through the connection hole 13a, and the Al layer 1a
4b is the TMR element T via the connection holes 13b and 13c.
The Mo layers 8a ₂ and 8b of b and Tc are interconnected. As a result, the TMR elements Ta to Tc are connected in series.

[0012]

According to the above-mentioned prior art, there are the following problems (a) to (c).

(A) The resist layer as a selective mask is
Since it is easily scraped by ion milling,
In the step of, the resist layers 9a to 9e are set to 0.6 to 2.0 μm.
It is necessary to form it to a thickness of about m, which is not suitable for fine processing. That is, with a thick resist layer, it is difficult to form a fine pattern, and pattern collapse easily occurs,
In addition, since the shadowed portion is generated during the processing by the angle milling, the processing accuracy is lowered.

(B) Side wall deposited film DP on the side wall of the separation groove 12
₂ and the resist residue remain, the tunnel barrier layer 6a
This may cause an electrical short circuit or a leak between the upper and lower metal layers, leading to a decrease in yield and deterioration of element characteristics. Also,
As shown in FIGS. 44 and 45, if the resist residues R _{1 to} R ₆ remain, they cause the generation of particles, leading to a decrease in yield.

(C) Since the silicon oxide film is etched at the bottom of the isolation trench 10 when the isolation trench 12 is formed in the ion milling process of FIG. 41, the depth D of the isolation trench 10 is increased by the amount of etching. The step of the separation groove 10 becomes steep.
Therefore, when the silicon oxide film 13 is formed by the sputtering method in the step of FIG. 42, a film defect is likely to occur near the opening end of the isolation trench 10, and when the Al layer 14b is formed in the step of FIG. A defect may occur in which the portion 4a is short-circuited via a film defect. It should be noted that CVD (Chemical Vapor
The deposition method does not cause film defects, but 400
Since the TMR element is processed at a temperature of about 0 ° C. and is vulnerable to high temperatures, it is not suitable for forming the silicon oxide film 13.

As a method of coping with the problem (b), a treatment of removing the side wall deposited film and the resist residue with a solution of acid or alkali can be considered. However, such a treatment may damage the extremely thin tunnel barrier layer or may cause the deterioration of the shape by etching the metal layers above and below the tunnel barrier layer. Also,
In the process of removing the side wall deposited film containing the resist modifying component using an organic solvent or the like, a substance harmful to the human body and the environment must be used, and the cost of the organic waste liquid increases.

Regarding the problem (b), as a method for reducing the leakage current of the TMR element, an oxidizing or nitriding atmosphere is used when the magnetic tunnel junction stack is patterned by selective ion milling to form the TMR element. It is known to form an insulating layer made of an oxide or a nitride on the sidewall of a TMR element by performing ion milling therein (for example, see Japanese Patent Laid-Open No. 2001-52316). When such an ion milling process is adopted in the process of FIG. 41, there is a problem in that it is difficult to detect the etching end point. That is, in the ion milling process of FIG. 41, the plasma emission measurement method is often used as the etching end point detection method. When this method is used, the ion milling is stopped by detecting the light emission based on the constituent atoms of the Rh-Mn alloy layers 4a and 4b as the antiferromagnetic layer. When performing ion milling in an oxidizing or nitriding atmosphere, the etching rate is lower than when performing ion milling in an atmosphere that does not contain oxygen or nitrogen, so the amount of excited atoms generated per unit time decreases. , The signal intensity required for light emission detection decreases. Therefore, the detection accuracy of the etching end point is lowered, and the under etching causes T
This may cause a short circuit between the MR elements Tb and Tc, or increase in connection resistance (and further disconnection) between the TMR elements Ta and Tb due to overetching. In addition, if the separation groove 10 is formed before the step of FIG. 41, the exposed area of the Rh—Mn alloy layers 4a and 4b becomes smaller than the separation groove 1 in the step of FIG.
Since it is reduced by the amount corresponding to 0, the signal intensity required for light emission detection is further reduced. Therefore, it becomes more difficult to detect the etching end point, and under-etching or over-etching is more likely to occur.

As a method for dealing with the problem (c) above, there has been proposed a method of performing an ion milling step corresponding to FIG. 39 after the ion milling step corresponding to FIG. 41 (for example, the same application as the present application). Japanese Patent Application 2001 for a person's application
288809). According to this method, the separation groove 1
Since the separation groove 10 is formed after forming 2, the step difference of the separation groove 10 can be reduced, and the short circuit failure of the wiring due to the film defect of the interlayer insulating film (corresponding to the silicon oxide film 13) can be prevented. Can be prevented. Further, in the ion milling process corresponding to FIG. 41, the signal intensity necessary for light emission detection can be increased by the amount of the separation groove 10 not provided.

However, since the resist layer (corresponding to the resist layers 9a to 9e) is used as a selective mask for ion milling, the same problems as those in the above (a) and (b) cannot be avoided. For example, regarding the problem (b) above, FIG.
In the ion milling process corresponding to 1, as shown in FIG. 45, the sidewall deposition film DP ₂ is formed on the sidewall of the isolation trench 12,
In the resist removal process corresponding to FIG. 41, the sidewall deposition film DP ₂
The resist residues R _{3 to} R ₅ may remain. Further, in the step of forming the resist layer as the selective mask prior to the ion milling step corresponding to FIG. 39, the resist or the like may adhere to the sidewall of the separation groove 12 to cause contamination. Further, in the ion milling process corresponding to FIG. 39, the sidewall deposition film DP ₃ is formed on the sidewall of the isolation trench 10 as shown in FIG. 45, and in the resist removing process corresponding to FIG. 39, the sidewall deposition film DP ₃ and the resist residue are deposited. R ₆ remains or separation groove 12
A resist residue may remain on the side wall of the substrate where there is no side wall deposition film DP ₂ . Therefore, the tunnel barrier layer 6a
Electrical shorts and leaks tend to occur between the upper and lower metal layers.

The object of the present invention is to solve the above problems and to obtain a high production yield with a novel TM.
It is to provide a manufacturing method of an R element.

Another object of the present invention is to provide a novel magnetic tunnel junction device with improved flexibility in wiring design for TMR elements or other circuit elements.

Still another object of the present invention is to provide a novel magnetic tunnel junction device in which the flatness or stability of the insulating film covering the TMR element is improved.

[0023]

Means for Solving the Problems The first T according to the present invention
The manufacturing method of the MR element is a step of forming a magnetic tunnel junction laminated layer on the insulative main surface of the substrate through a first conductive material layer. Stacking a ferromagnetic layer, a first magnetic layer, a tunnel barrier layer and a second magnetic layer to form the magnetic tunnel junction stack;
Forming a second conductive material layer over the magnetic tunnel junction stack; and the second conductive layer for leaving the second conductive material layer over the magnetic tunnel junction stack according to a desired electrode pattern. Forming a first hard mask composed of the remaining portion of the second conductive material layer by performing a first selective etching process on the material layer; and forming the first hard mask on the magnetic tunnel junction stack. A step of leaving the magnetic tunnel junction stack according to the electrode pattern by performing a second selective etching process using a selective mask; and the first part so as to cover the remaining part of the magnetic tunnel junction stack according to a desired element pattern. A third selective etching process is performed on the first hard mask to leave the hard mask, thereby leaving the first hard mask remaining. A step of forming a second hard mask consisting of a portion, and a remaining portion of the magnetic tunnel junction stack is subjected to a fourth selective etching process using the second hard mask as a selective mask to leave the magnetic tunnel junction stack. Part is etched until it reaches the antiferromagnetic layer to form a magnetic tunnel junction consisting of the remaining portions of the first magnetic layer, the tunnel barrier layer and the second magnetic layer, and the magnetic tunnel. The first electrode layer composed of the remaining portions of the first conductive material layer and the antiferromagnetic layer is left under the junction, and the second hard mask is left as the second electrode layer. Process,
And a step of removing deposits deposited at the end of the tunnel barrier layer in the magnetic tunnel junction portion during the fourth selective etching process.

According to the first TMR element manufacturing method, since the second hard mask made of a conductive material is used as the selective mask in the fourth selective etching process, the side wall of the magnetic tunnel junction (especially the end of the tunnel barrier layer) is formed. The deposit as an etching product adhering to (part) does not contain organic substances such as resist modifying components. Therefore, in the step of removing the deposit, the deposit can be easily removed without using an organic solvent or the like. Therefore, the metal layers above and below the tunnel barrier layer are not connected to each other by deposits or the like on the side wall of the magnetic tunnel junction, and electrical short circuit and leakage can be prevented. Further, since it is not necessary to use an organic solvent or the like, the amount of a substance harmful to the human body and the environment can be reduced, and the process can be simplified and the cost can be reduced.

Moreover, in the first selective etching process for forming the first hard mask or the third selective etching process for forming the second hard mask, the conductive material layer for the hard mask (second As the conductive material of the conductive material layer), a material such as W (tungsten) having an ion milling rate (etching rate) slower than those of the first and second magnetic layers and the first conductive material layer can be selected. The conductive material layer can be thinned. Therefore, the resist layer used as a selective mask when patterning the mask conductive material layer can be thinned. Therefore, it is easy to form a fine pattern, the pattern does not easily fall, and the processing accuracy is improved because there are few shadowed portions during processing by angle milling.

In the method of manufacturing the first TMR element, the first
As a modified example of, the following changes may be added. That is, in the step of forming the magnetic tunnel junction portion, the remaining portion of the magnetic tunnel junction stack is etched by the fourth selective etching process until it reaches the first conductive material layer, whereby the antiferromagnetic layer and the first magnetic layer are etched. Forming a magnetic tunnel junction consisting of the remaining portion of each of the tunnel barrier layer and the second magnetic layer, and forming a first electrode layer consisting of the remaining portion of the first conductive material layer under the magnetic tunnel junction. Let it remain. Even in this case, the same effects as those described above regarding the method of manufacturing the first TMR element can be obtained.

When the first modification is adopted in the manufacturing method of the first TMR element, the following modifications may be made as the second modification. That is, in the step of forming the magnetic tunnel junction stack, the first magnetic layer, the tunnel barrier layer, the second magnetic layer, and the antiferromagnetic layer are stacked in this order from the bottom on the first conductive material layer to form the magnetic tunnel junction. Laminates may be formed. In this case, the other steps are performed in the same manner as described above regarding the manufacturing method of the first TMR element and the first modification. By doing so, the same operational effect as described above regarding the manufacturing method of the first TMR element can be obtained.

A second method of manufacturing a TMR element according to the present invention is a step of forming a magnetic tunnel junction stack on a first insulating main surface of a substrate via a first conductive material layer.
An antiferromagnetic layer, a first magnetic layer, a tunnel barrier layer, and a second magnetic layer are stacked in this order from the bottom on the conductive material layer to form the magnetic tunnel junction stack; Covering and forming a second conductive material layer;
The second conductive material layer is subjected to a first selective etching treatment so as to leave the second conductive material layer so as to cover the magnetic tunnel junction stack according to a desired electrode pattern. A step of forming a first hard mask formed of the remaining part of the magnetic tunnel junction, and a second step of using the first hard mask as a selective mask in the magnetic tunnel junction stack.
Forming a third conductive material layer by covering the first hard mask and the remaining portion of the magnetic tunnel junction stack by leaving the magnetic tunnel junction stack according to the electrode pattern. And a step of leaving the first hard mask and the third conductive material layer so as to cover the remaining portion of the magnetic tunnel junction stack according to a desired element pattern. Forming a second hard mask composed of the remaining portions of the first hard mask and the third conductive material layer by subjecting the conductive material layer to a third selective etching treatment; and the magnetic tunnel junction. A fourth selective etching process using the second hard mask as a selective mask is performed on the remaining portion of the stack to remove the remaining portion of the magnetic tunnel junction stack. By etching until reaching the ferromagnetic layer, a magnetic tunnel junction consisting of the remaining portions of each of the first magnetic layer, the tunnel barrier layer and the second magnetic layer is formed, and under the magnetic tunnel junction. To leave the first electrode layer composed of the remaining portions of the first conductive material layer and the antiferromagnetic layer, and at least the remaining portion of the first hard mask of the second hard mask. It includes a step of remaining as a second electrode layer, and a step of removing a deposit deposited at the end of the tunnel barrier layer in the magnetic tunnel junction portion during the fourth selective etching process.

In the method of manufacturing the second TMR element, the second hard mask is formed not only on the basis of the first hard mask but on the second hard mask using the first hard mask and the third conductive material. This is different from the manufacturing method of the first TMR element in that it is formed on the basis of laminated layers. Second TM
According to the method of manufacturing the R element, the following function and effect are obtained in addition to the function and effect described above regarding the method of manufacturing the first TMR element. That is, since the first hard mask is formed on the basis of the second conductive material layer and the second hard mask is formed on the basis of the lamination in which the third conductive material layer is laminated on the first hard mask, As the second conductive material layer, the optimum material and thickness for the second selective etching process using the first hard mask can be set, and as the third conductive material layer, the second hard mask using the second hard mask is used. The optimum material and thickness for the selective etching process of No. 4 can be set. In particular, the second conductive material layer constitutes the second hard mask together with the third conductive material layer, so that the thickness can be set thin and fine processing becomes easy.

As the third conductive material layer forming the second hard mask, one having a thickness which disappears by the fourth selective etching process may be used. In this case, the remaining portion of the first hard mask (second conductive material layer) remains as the second electrode layer. Further, as the third conductive material layer,
You may use the thing of the thickness which does not disappear by a 4th selective etching process. In this case, as the second electrode layer,
Remaining portions of each of the first and second hard masks are left.

In the method of manufacturing the second TMR element, the same modifications as those of the first modification described above may be added. When the first modification is adopted, the same modification as that of the second modification described above is performed. Similar changes may be made. Even in this way, the second T
The same effects as those described above with respect to the manufacturing method of the MR element can be obtained.

A third method of manufacturing a TMR element according to the present invention is a step of forming a magnetic tunnel junction stack on a first insulating main surface of a substrate via a first conductive material layer.
An antiferromagnetic layer, a first magnetic layer, a tunnel barrier layer, and a second magnetic layer are stacked in this order from the bottom on the conductive material layer to form the magnetic tunnel junction stack; Covering and forming a second conductive material layer;
The second conductive material layer is formed by performing a first selective etching process on the second conductive material layer so as to leave the second conductive material layer so as to cover the magnetic tunnel junction stack according to a desired element pattern. A step of forming a first hard mask formed of the remaining part of the magnetic tunnel junction, and a second step of using the first hard mask as a selective mask in the magnetic tunnel junction stack.
Of the remaining portions of the first magnetic layer, the tunnel barrier layer, and the second magnetic layer by subjecting the magnetic tunnel junction stack to the antiferromagnetic layer by performing the selective etching process of 1. Forming a magnetic tunnel junction, forming a third conductive material layer covering the first hard mask, the magnetic tunnel junction, and the exposed portion of the antiferromagnetic layer; Of the third conductive material layer so as to leave the third conductive material layer so as to cover the hard mask, the magnetic tunnel junction, and the exposed portion of the antiferromagnetic layer according to a desired electrode pattern. A step of forming a second hard mask made of the remaining portion of the third conductive material layer by performing a selective etching process; and a step of stacking the first conductive material layer and the antiferromagnetic layer with the second hard mask. Ha Forming a first electrode layer consisting of the remaining portion of the stacked layer under the magnetic tunnel junction by performing a fourth selective etching process using a mask as a selective mask; and forming the first electrode layer. Removing the second hard mask from the end of the tunnel barrier layer in the magnetic tunnel junction portion after or during formation and leaving at least the first hard mask as a second electrode layer.

According to the third manufacturing method of the TMR element, when the second hard mask is formed on the basis of the third conductive material layer by the third selective etching process, the magnetic tunnel junction portion has the third surface. Since it is covered with the conductive material layer, it is possible to prevent the resist or the like from adhering to the side wall of the magnetic tunnel junction. In addition, a fourth hard mask using the second hard mask as a selection mask
When the first electrode layer is formed by the selective etching process of step 1, since the magnetic tunnel junction is covered with the second hard mask, deposits are formed on the side wall of the magnetic tunnel junction (particularly at the end of the tunnel barrier layer). Etc. can be prevented from directly adhering. Further, the second hard mask is removed from the sidewall of the magnetic tunnel junction (particularly the end of the tunnel barrier layer) during or after the formation of the first electrode layer. Therefore,
The metal layers above and below the tunnel barrier layer are not connected to each other by deposits or the like on the side wall of the magnetic tunnel junction, so that an electrical short circuit or leakage can be prevented. The deposits deposited on the sidewalls of the magnetic tunnel junction portion during the second selective etching process may be removed after the second selective etching process, but if they are left, they may be removed by the second hard etching process. It is removed as the mask is removed.

According to the manufacturing method of the third TMR element, since the first and second hard masks each made of a conductive material are used, it is easy to form a fine pattern as described above for the first TMR element. In addition, the processing accuracy is improved. Further, since the first hard mask is formed based on the second conductive material layer and the second hard mask is formed based on the third conductive material layer, materials and materials for the first and second hard masks are formed. The thickness can be optimized and fine processing becomes easy.

Moreover, after the magnetic tunnel junction is formed by the second selective etching treatment, the first electrode layer is formed under the magnetic tunnel junction by the fourth selective etching treatment. The base film of the conductive material layer 1 is
Since the etching is performed only during the fourth selective etching process, the step difference at the end portion of the electrode layer can be reduced as compared with the method of manufacturing the first or second TMR element.

In the third manufacturing method of the TMR element,
As a modified example of, the following changes may be added. That is, in the step of forming the magnetic tunnel junction part, the magnetic tunnel junction stack is first processed by the second selective etching process.
By etching until the conductive material layer is reached to form a magnetic tunnel junction formed of the remaining portion of the magnetic tunnel junction stack. In this case, the second hard mask is the first
In the step of forming the first electrode layer by covering the hard mask, the magnetic tunnel junction, and the exposed portion of the first conductive material layer, a second hard mask is formed on the first conductive material layer. By performing a fourth selective etching process as a selective mask, the first electrode layer made of the remaining portion of the first conductive material layer is left under the magnetic tunnel junction. Even in this case, the same operational effects as those described above regarding the method of manufacturing the third TMR element can be obtained.

When the third modification is adopted in the method of manufacturing the third TMR element, the following modifications may be made as the fourth modification. That is, in the step of forming the magnetic tunnel junction stack, the first magnetic layer, the tunnel barrier layer, the second magnetic layer, and the antiferromagnetic layer are stacked in this order from the bottom on the first conductive material layer to form the magnetic tunnel junction. Laminates may be formed. In this case, the other steps are performed in the same manner as described above regarding the manufacturing method of the third TMR element and the third modification. By doing so, the same operational effects as those described above regarding the method of manufacturing the third TMR element can be obtained.

A first magnetic tunnel junction device according to the present invention is a substrate having an insulative main surface and a magnetic tunnel junction element formed on the one main surface. A first conductive material layer, an antiferromagnetic layer, a first magnetic layer, a tunnel barrier layer, a second magnetic layer and a second conductive material layer are stacked in this order, or the first main surface is provided with a first conductive layer in order from the bottom. A conductive material layer, a first magnetic layer, a tunnel barrier layer, a second magnetic layer,
A wiring layer formed by stacking an antiferromagnetic layer and a second conductive material layer, and a wiring layer formed on the one main surface and having a laminated structure having substantially the same laminated structure as the magnetic tunnel junction element. And using the wiring layer as a wiring layer for the magnetic tunnel junction element or a wiring layer for a circuit element formed on the substrate.

The first magnetic tunnel junction device can be easily manufactured by the manufacturing method of the TMR element of the present invention because the TMR element and the wiring layer have substantially the same laminated structure. Further, since the wiring layer is used as a wiring layer for the TMR element or another circuit element, the degree of freedom in wiring design is improved.

In the first magnetic tunnel junction device,
A conductive layer may be formed to cover at least a side portion of the laminated structure so as to short-circuit two magnetic layers sandwiching the tunnel barrier layer in the laminated structure. In this way, in the wiring layer, the stack including the magnetic layer and the conductive material layer below the tunnel barrier layer and the stack including the magnetic layer and the conductive material layer above the tunnel barrier layer are formed by the conductive layers formed on the side portions. Since it is short-circuited, low resistance wiring can be realized.

A second magnetic tunnel junction device according to the present invention is a substrate having an insulative main surface and a magnetic tunnel junction element formed on the one main surface. A first conductive material layer, an antiferromagnetic layer, a first magnetic layer, a tunnel barrier layer, a second magnetic layer and a second conductive material layer are stacked in this order, or the first main surface is provided with a first conductive layer in order from the bottom. A conductive material layer, a first magnetic layer, a tunnel barrier layer, a second magnetic layer,
A structure formed by stacking an antiferromagnetic layer and a second conductive material layer, an auxiliary stack formed on the one main surface and having a stack structure substantially the same as that of the magnetic tunnel junction element, and the magnetic tunnel. A bonding element and an insulating film formed on the one main surface so as to cover the auxiliary laminated layer, and to prevent the auxiliary laminated layer from peeling a planarizing layer for planarizing the insulating film or the insulating film. Used as a peeling prevention layer.

The second magnetic tunnel junction device can be easily manufactured by the manufacturing method of the TMR element of the present invention because the TMR element and the flattening layer or the peeling prevention layer have substantially the same laminated structure. Further, when the planarizing layer is provided, the insulating film can be planarized, and the wiring layer formed on the insulating film can be planarized. Further, when the peeling prevention layer is provided, the peeling of the insulating film can be prevented, and the stability of the insulating film is improved.

[0043]

1 to 9 show a method of manufacturing a magnetic sensor having a TMR element according to a first embodiment of the present invention, and steps (1) to (9) corresponding to the respective drawings are shown. ) Will be sequentially described.

(1) An insulating film 22 made of silicon oxide is formed on the surface of a semiconductor substrate 20 made of, for example, silicon by a thermal oxidation method. Instead of the semiconductor substrate 20 having the insulating film 22 formed on its surface, an insulating substrate made of glass, quartz or the like may be used. Next, a conductive material layer 24 made of Cr is deposited on the insulating film 22 by sputtering to have a thickness of 10 to 30 nm.
To the thickness of. As the conductive material layer 24, a single layer of Ti or a laminated layer of a Cu layer on a Ti layer may be used, or a conductive non-magnetic metal material such as W, Ta, Au, Mo may be used.

Next, an antiferromagnetic layer 26 made of a Pt-Mn alloy is formed on the conductive material layer 24 by sputtering.
It is formed to a thickness of 50 nm. As the antiferromagnetic layer 26,
Rh-Mn alloy, Fe-Mn alloy, etc. may be used. After that, Ni is sputtered on the antiferromagnetic layer 26.
A ferromagnetic layer 28 made of a —Fe alloy is formed to a thickness of 10 to 30 nm. As the ferromagnetic layer 28, Ni, Fe, C
Any metal of o, an alloy of two or more metals of Ni, Fe, and Co, an intermetallic compound, or the like may be used, or a Co layer is laid under the Ni—Fe alloy layer 28. Then, a laminated structure may be used.

Next, an Al layer having a thickness of 1 to 2 nm is formed on the ferromagnetic layer 28 by the sputtering method. And
The tunnel barrier layer 30 made of alumina (aluminum oxide) is formed by subjecting the Al layer to oxidation treatment.
As the tunnel barrier layer 30, an oxide obtained by modifying a metal or a semiconductor (eg, TiOx, SiO ₂ , MgO, Al) is used.
₂ O ₂ + SiO ₂ [sialon]), nitride (eg A
1N, Si ₃ N ₄ , oxynitride (eg AlN + Al)
₂ O ₃ ) or the like may be used. After that, a ferromagnetic layer 32 made of a Ni—Fe alloy is formed on the tunnel barrier layer 30 by sputtering to have a thickness of 20 to 100 nm.
As the ferromagnetic layer 32, the same ferromagnetic layer as described above regarding the ferromagnetic layer 28 can be used.

Next, a hard mask conductive material layer 34 made of, for example, W or TiW is formed on the ferromagnetic layer 32 by sputtering or CVD to a thickness of 200 to 600 nm (preferably 400 nm). When the conductive material layer 34 is formed by the sputtering method, the processing condition is, for example, Ar gas flow rate: 15 to 100 sccm (preferably 30).
sccm) Pressure: 1-10 mTorr (preferably 3 mTorr) RF power: 0.5-2 kW (preferably 1.15 k)
W) Substrate temperature: 80 to 250 ° C (preferably 150 ° C). In addition, the conductive material layer 3 is formed by the CVD method.
In the case of forming No. 4, the processing condition is, for example, gas flow rate: WF ₆ / H ₂ / Ar = 40/400/225.
0 sccm pressure: 0.5 to 10 × 10 ⁶ Torr (preferably 1 ×)
10 ⁶ Torr) Substrate temperature: 250 to 450 ° C. (preferably 300 ° C.).

Next, resist layers 36a and 36b having quadrilateral electrode patterns as shown in 26A and 26B of FIG. 13 are formed on the conductive material layer 34 by photolithography. The resist thickness at this time is
It can be 200 to 800 nm (preferably 400 nm).

(2) The conductive material layer 34 is patterned by selective ion milling or selective dry etching using the resist layers 36a and 36b as masks to form hard masks 34A and 34B. When patterning is performed by ion milling, the processing conditions are, for example, Ar flow rate: 4 sccm, pressure: 2.0 × 10 ⁻⁴ Torr, angle: 0 to 30 degrees, power: 500 V, 190 mA, milling time: 6.0 to 6. It can be about 5 min. When patterning is performed by dry etching, the processing conditions are, for example, gas flow rate: SF ₆ / Ar = 30 to 140/40 to 140.
sccm (preferably 110/90 sccm) Pressure: 250 mTorr RF power: 450 W can be used.

(3) After forming the hard masks 34A and 34B, the resist layers 36a and 36b are removed. The resist can be removed, for example, by performing an ashing treatment with O ₂ plasma and then performing a chemical treatment using an organic stripping solution. As an example, the processing condition in the ashing processing may be an O ₂ flow rate: 100 sccm pressure: 50 mTorr RF power: 150 W. As another example of the resist removing method, an acetone ultrasonic cleaning method or the like may be used. Instead of providing an independent resist removing step, the resist layers 36a and 36b may be simultaneously removed during the ion milling process.

When the patterning is performed by the ion milling process, the sidewall deposition film DP is formed on the sidewalls of the stack of the hard mask 34A and the resist layer 36a and the sidewalls of the stack of the hard mask 34B and the resist layer 36b, respectively.
₁₀ and DP ₁₁ are formed as etching products. These deposited films DP ₁₀ and DP ₁₁ include a resist modifying component (organic material), a metal component of the layers 32 and 34, and the like, and remain on the sidewalls of the hard masks 34A and 34B even after the resist removing process as described above. easy. However, since the milling time is short, the amount of deposits is small, and the deposits can be completely removed by the ion milling process of FIG. 3 without additional treatment for removing the deposits. When the patterning is performed by the dry etching process, there is almost no problem of the side wall deposited film.

Next, the layers 24 to 32 are subjected to a selective ion milling process using the hard masks 34A and 34B as masks.
By forming the separation groove 38 in the stack of the above so as to reach the insulating film 22, the stack remaining portions Ra and Rb are obtained. The remaining layer portion Ra is formed by stacking the remaining portions 24A to 32A of the layers 24 to 32 surrounded by the separation groove 38, and the remaining portion portion Rb is a remaining portion 24B of the layers 24 to 32 surrounded by the separation groove 38. Three
It consists of a stack of 2B.

The processing conditions in the ion milling processing are as follows:
As an example, Ar flow rate: 4 sccm Pressure: 2.0 × 10 ⁻⁴ Torr Angle: 0-60 degrees Power: 500 V, 190 mA can be used. The hard masks 34A, 34A
Since B is necessary to form the hard masks 34a to 34c in the step of FIG. 5, it is left.

In the ion milling process of FIG. 3, the separation groove 3
Side wall deposited film D as an etching product on the side wall of No. 8
P ₁₂ and DP ₁₃ are formed. Deposition film DP ₁₂ , DP
₁₃ includes the metal components of the layers 24-28, 32, 34, etc., and does not include the resist modifying component (organic substance),
It can be easily removed without an organic solvent.

(4) After the ion milling treatment, a chemical treatment for removing the side wall deposited films DP ₁₂ and DP ₁₃ is performed. This chemical treatment includes (a) dilute hydrofluoric acid (or BH
F) treatment + pure water cleaning treatment, (b) ammonia and hydrogen peroxide solution treatment + pure water cleaning treatment, (c) sulfuric acid and hydrogen peroxide solution treatment + pure water cleaning treatment It is possible to perform processing or processing relating to a combination of a plurality of types. Since such a process is a short-time process, the etching amount on the sidewalls of the remaining laminate portions Ra and Rb is very small, and the tunnel barrier layer is not substantially damaged.

If it is desired to remove the sidewall deposited films DP ₁₂ and DP ₁₃ more surely, a cleaning milling process (milling process for a short time with an angle) may be added.
As an example, the processing conditions in the cleaning milling process may be: Ar flow rate: 4 sccm Pressure: 2.0 × 10 ⁻⁴ Torr Angle: 45-80 degrees (preferably 60 degrees) Power: 500 V, 190 mA By adding such a milling process, the side wall of the separation groove 38 can be further cleaned, and the side wall shape becomes more tapered.

The side wall deposited films DP ₁₂ and DP ₁₃ may be left as long as there is no problem such as generation of particles, and even if left, they are removed by the ion milling process of FIGS. The chemical treatment or the cleaning milling treatment may be omitted.

Next, resist layers 40a and 40b are formed on the remaining hard mask 34A, and a resist layer 40c is formed on the remaining hard mask 34B. The resist layers 40a to 40c are the T layers shown in FIG.
It is formed by photolithography so as to have a quadrilateral element pattern as shown by a to Tc. At this time, the resist thickness is 80 to 500 nm (preferably 25 nm).
0 nm).

(5) The hard masks 34A and 34B are patterned by the selective ion milling process or the selective dry etching process using the resist layers 40a to 40c as masks to form the hard masks 34a to 34c. The hard masks 34a to 34c are the resist layers 40, respectively.
a to 40c, the hard masks 34a and 34b are both hard masks 34A.
And the hard mask 34c is formed of the remaining portion of the hard mask 34B.

When patterning is performed by the ion milling process, the processing conditions can be the same as those described above for the ion milling process of FIG. When patterning by dry etching,
The processing condition is, for example, gas flow rate: CHF ₃ / CF ₄ / Ar = 30/5/100.
The sccm pressure may be 200 mTorr RF power may be 700 W.

(6) After the ion milling treatment or the dry etching treatment, the resist layers 40a-40c are removed. The resist removing process at this time can be performed in the same manner as described above with reference to FIG.

In the ion milling process of FIG. 5, the side wall deposited films DP _{15 to} DP ₁₉ are formed as etching products. The deposited film DP ₁₅ covers the side wall of the stack of the hard mask 34a and the resist layer 40a, and the deposited film DP ₁₆
Covers the side wall of the stack of the hard mask 34b and the resist layer 40b, and the deposited film DP ₁₇ is the hard mask 34.
c and the resist films 40c, which cover the sidewalls of the stacked layers, and the deposited films DP ₁₈ and DP ₁₉ are the remaining stacked portions Ra and R, respectively.
It covers the side wall of b. Deposited films DP _{15 to} DP ₁₉
Is the same as the deposited films DP ₁₀ and DP ₁₁ described above. After the resist removal process described above, the hard mask 34
It is likely to remain on the sidewalls of a to 34c and the sidewalls of the remaining laminated portions Ra and Rb.

In order to remove such a remaining deposited film, the chemical treatment as described in (a) to (c) above may be performed. However, since the remaining deposited film is removed by the ion milling process of FIG. 6 even if it is left, such a chemical solution process can be omitted.

Next, the layer remaining portion R is subjected to a selective ion milling process using the hard masks 34a to 34c as masks.
The TMR elements Ta to Tc are obtained by forming the separation groove 42 in a and Rb so as to reach the antiferromagnetic layers 26A and 26B. The processing conditions in the ion milling process at this time can be the same as those described above regarding the ion milling process in FIG.

The TMR element Ta includes layers 24A and 26A surrounded by the separation groove 38 and layers 28A to 28A surrounded by the separation groove 42.
The hard mask 34a and the portions 28a to 32a of 32A are laminated, and the TMR element Tb has the isolation trench 38.
The layers 24A and 26A surrounded by ???, the portions 28b to 32b of the layers 28A to 32A surrounded by the separation groove 42, and the hard mask 34b are laminated. The stacked layers 24A and 26A are used as one electrode layer of the TMR element Ta, and the hard mask 34a is used as the other electrode layer of the TMR element Ta. The stack of layers 24A and 26A is
The hard mask 34b is used as one electrode layer of the TMR element Tb, and is also used as the other electrode layer of the TMR element Tb. The TMR elements Ta and Tb are interconnected by stacking layers 24A and 26A as wiring layers (common electrode layers).

The TMR element Tc includes the layers 24B and 26B surrounded by the separation groove 38 and the layers 28B to 26B surrounded by the separation groove 42.
32B portions 28c to 32c and a hard mask 34c are laminated. The layers 24B and 26B are the TMR element Tc.
The hard mask 34c is used as one of the electrode layers and the other of the TMR elements Tc is used as the other electrode layer.

In the ion milling process of FIG. 6, the separation groove 4
2 as an etching product on the sidewall of the second sidewall DP _21.
~ DP ₂₃ is formed, and sidewall deposition films DP ₂₄ and DP ₂₅ are formed as etching products on the sidewalls of the isolation trench 38. The deposited films DP _{21 to} DP ₂₅ are the same as the deposited films DP ₁₂ and DP ₁₃ described above, and can be easily removed without an organic solvent.

(7) After the ion milling treatment, a chemical treatment for removing the sidewall deposited films DP _{21 to} DP ₂₅ is performed. As the chemical treatment, sulfuric acid / hydrogen peroxide water treatment + pure water cleaning treatment can be performed. In this case, it is desirable to perform a chemical treatment that does not contain fluorine or alkali (ammonia or the like) so as not to leave damage to the tunnel barrier layers 30a to 30c. Further, if necessary, the cleaning milling process described above with respect to the process of FIG. 3 may be performed. By doing so, the sidewalls of the TMR elements Ta to Tc are further cleaned and the sidewall shape becomes more tapered. At the end of the side wall deposited film removing process as described above, the remaining thickness of each hard mask such as 34a is 50 to 300 n in consideration of use as an electrode layer.
It is desirable to set it to about m. In the process of FIG. 1, the thickness of the conductive material layer 34 can be set so as to have such a remaining thickness.

(8) The hard mask 34a is formed on the upper surface of the substrate.
An interlayer insulating film 46 made of silicon oxide is formed by a sputtering method so as to cover .about. After this, the TMR element Ta is subjected to selective ion milling.
The contact holes 46a to 46c corresponding to the electrode layers 34a to 34c of Tc to Tc are formed in the insulating film 46.

(9) On the insulating film 46, the connection hole 46a is formed.
The wiring layers 48a and 48b are formed by covering wirings 46c to 46c with a wiring metal such as Al by sputtering and patterning the deposited layer by selective ion milling (or selective wet etching). Wiring layer 4
8a is connected to the electrode layer 34a of the TMR element Ta via the connection hole 46a, and the wiring layer 48b is connected to the connection holes 46b and 4b.
The electrode layers 34b, 3 of the TMR elements Tb, Tc via the 6c.
4c are interconnected. As a result, the TMR elements Ta to Tc
Are connected in series. 13 shows a connection state of the TMR elements Ta to Tc, and FIG. 9 corresponds to a cross section taken along the line XX 'of FIG.

According to the manufacturing method of the first embodiment described above,
In the steps of FIGS. 2 and 5, a hard mask can be formed with good dimensional accuracy using a thin resist layer, and in the steps of FIGS.
The reason is that the R element can be formed, and that the sidewall deposited film can be easily removed in the process of FIG. 7 so that an electrical short circuit or a leak can be prevented from occurring at the end portion of the tunnel barrier layer and the generation of particles can be prevented. This improves the manufacturing yield of the magnetic sensor.

In the magnetic sensor shown in FIG. 9, the operations of the TMR elements Ta to Tc are similar, and the element Ta is representative.
The operation of will be described. The antiferromagnetic layer 26A is the ferromagnetic layer 28.
Since it acts to fix the magnetization direction of a, the ferromagnetic layer 2
8a becomes a magnetization fixed layer. On the other hand, the ferromagnetic layer 32a is
The direction of magnetization is free and it becomes a magnetization free layer.

When an external magnetic field is applied to the plane of the substrate 20 while a constant current is applied between the electrode layers 24A and 34a, the ferromagnetic layers 28a and 32 are responsive to the direction and strength of the magnetic field.
The relative angle of magnetization changes between a and the electric resistance value between the electrode layers 24A and 34a changes according to such a change in relative angle. Therefore, the magnetic field can be detected based on such a change in the electric resistance value.

FIGS. 10 to 12 show a step of forming a wiring in the wiring portion by diverting a part of the TMR element forming process in the manufacturing method of the first embodiment, which is similar to FIGS. The same reference numerals are given to the parts of and the detailed description is omitted.

In the step of FIG. 10, the layer 24 is formed on the insulating film 22 covering the surface of the substrate 20 by using the layer forming step of FIG.
3 to 34, a conductive material layer 3 is formed by using a resist mask corresponding to a desired wiring pattern and applying the ion milling process or the dry etching process shown in FIG.
4 is patterned to form a hard mask 34s.
Then, after removing the resist mask by diverting the resist removal process of FIG. 3, the hard mask 34s is used and the ion milling process of FIG. 3 is diverted to pattern the stack of layers 24 to 32 to form the wiring layer Ts. To do. Wiring layer T
s is formed by stacking the portions 24 s to 32 s of the layers 24 to 32 and the hard mask 34 s, and the side wall of the layer Ts includes
Side wall deposited film D similar to the deposited films DP ₁₂ and DP ₁₃ described above
P ₁₄ is formed.

In the process of FIG. 11, the stack of FIG.
Deposition of deposited film DP ₁₄To remove. So
Then, the resist layer forming process of FIG.
A resist layer 40s on the insulating film 22 so as to cover
To do. After that, the ion milling process of FIG. 5 is performed.
It At this time, the wiring layer Ts is covered with the resist layer 40s.
Therefore, there is no change at all, but on the side wall of the layer 40s
Is the above-mentioned deposited film DP₁₅~ DP₁₉Side wall deposition similar to
Membrane DP₂₀Is formed.

In the process of FIG. 12, the resist removal process of FIG. 6 is diverted to remove the resist layer 40s, and then the chemical solution process of FIG. 6 is diverted to remove the deposited film DP ₂₀ if necessary. After that, the ion milling process of FIG. 6 is performed.
At this time, in the wiring layer Ts, the uppermost layer is the hard mask 34s.
Therefore, although the hard mask 34s is slightly thinned, there is almost no change in the constituent layers below the mask 34s. Further, the insulating film 22 is thinned to the same extent as in the case of FIG.

When the ion milling process of FIG. 6 is performed, the above-mentioned deposited films DP _{21 to} D ₂₁ are formed on the sidewalls of the wiring layer Ts.
A sidewall deposited film similar to P ₂₅ is formed. Such a deposited film is removed by diverting the deposited film removing process of FIG. 7, and the hard mask 34s is left as a part of the wiring layer Ts. At the end of the deposited film removal process, the hard mask 3
The remaining thickness of 4 s, considering the use as a wiring layer,
It is desirable to set the thickness to about 50 to 300 nm like the electrode layer such as 34a described above.

The wiring layer Ts shown in FIG. 12 can be used as a wiring layer at the same level as the TMR elements Ta to Tc shown in FIG. 9, and for example, the wiring layer for the TMR element such as Ta or the substrate 20. It can be used as a wiring layer for a circuit element such as a transistor formed on the surface.

In the steps of FIGS. 10 to 12, a part of the TMR element forming process is diverted to form the wiring layer Ts composed of the layers 24s to 34s, but the pattern of FIGS. Layers 24s-3 by the same process as the process
It is also possible to form an insulating film flattening layer or an insulating film peeling prevention layer having a stacked structure of 4 s. The insulating film flattening layer is used to improve the flatness of the insulating film 46 shown in FIG.
6 is disposed below the insulating film peeling prevention layer,
For example, it is arranged under the insulating film 46 to prevent the insulating film 46 from peeling off.

14 and 15 show a modified example of the above-described first embodiment. The same parts as those in FIGS. 1 to 9 are designated by the same reference numerals and detailed description thereof will be omitted.

In FIG. 14, hard masks 34a to 34c made of a conductive material layer are formed on the remaining laminated portions Ra and Rb in the same manner as described above with reference to FIGS. The state where the resist removing process and the deposited film removing process are performed on the upper surface of the substrate is shown.

The step of FIG. 15 is a step of obtaining the TMR elements Ta to Tc by subjecting the upper surface of the substrate to selective ion milling using the hard masks 34a to 34c as a mask after the step of FIG. The ion milling process of this step is different from the ion milling process of FIG. 6 in that the separation groove 42 is deeply formed so as to reach the conductive material layers 24A and 24B. After the ion milling process, as in the case described above with reference to FIG. 7, the sidewall deposited films (etching products) of the separation grooves 38 and 42 are formed.
A deposited film removing process is performed to remove the.

In the TMR element Ta, the conductive material layer 24 A surrounded by the separation groove 38 and the layers 26 A to 3 surrounded by the separation groove 42.
The TMR element Tb includes a conductive material layer 24A surrounded by the separation groove 38 and a layer 2 surrounded by the separation groove 42 while being formed by laminating the portions 26a to 32a of 2A and the hard mask 34a.
6A to 32A portions 26b to 32b and the hard mask 3
4b and laminated. The conductive material layer 24A is used as one electrode layer of the TMR element Ta, and the hard mask 34a is used as the other electrode layer of the TMR element Ta. The conductive material layer 24A is used as one electrode layer of the TMR element Tb, and also serves as the hard mask 34b.
Is used as the other electrode layer of the TMR element Tb.
The TMR elements Ta and Tb are interconnected by a conductive material layer 24A as a wiring layer (common electrode layer).

The TMR element Tc is composed of the conductive material layer 24 B surrounded by the separation groove 38 and the layers 26 B to 3 surrounded by the separation groove 42.
2B portions 26c to 32c and a hard mask 34c are laminated. The conductive material layer 24B is used as one electrode layer of the TMR element Tc, and also the hard mask 34.
c is used as the other electrode layer of the TMR element Tc.

After the step of FIG. 15, the interlayer insulating film 46 is formed on the upper surface of the substrate in the same manner as described above with reference to FIG. Then, after forming the connection holes 46a to 46c in the insulating film 46 in the same manner as described above with reference to FIG. 8, the wiring layers 48a and 48b are formed on the insulating film 46 in the same manner as described above with reference to FIG.
To form.

According to the manufacturing method according to the modified examples of FIGS. 14 and 15, the manufacturing yield of the magnetic sensor is improved similarly to the manufacturing method according to the first embodiment described above. The obtained magnetic sensor operates similarly to the magnetic sensor shown in FIG.

16 and 17 show another modification of the first embodiment described above with reference to FIGS.
The same parts as those in FIG.

In the modification of FIGS. 16 and 17, in the step corresponding to FIG. 1, the conductive material layer 24, the ferromagnetic layer 28, the tunnel barrier layer 30, the ferromagnetic layer 32, and the antireflection layer are formed on the insulating film 22 in this order from the bottom. A ferromagnetic layer and a conductive material layer 34 are formed. here,
The antiferromagnetic layer between the ferromagnetic layer 32 and the conductive material layer 34 is the same as the antiferromagnetic layer 26 described above, and serves to make the ferromagnetic layer 32 a magnetization fixed layer.

In FIG. 16, the hard masks 34a to 34c made of a conductive material are formed on the remaining laminated portions Ra and Rb by performing the same processing as that described above with reference to FIGS. 1 to 5 on the laminated layers formed in the step corresponding to FIG. After the formation, the resist removal process and the deposited film removal process are performed on the upper surface of the substrate in the same manner as described above with reference to FIG. In this state, the remaining laminated portion Ra
Are the conductive material layer 24A, the ferromagnetic layer 28A, the tunnel barrier layer 30A, the ferromagnetic layer 32A, and the antiferromagnetic layer 3 in order from the bottom.
The hard masks 34a and 34b are formed on the antiferromagnetic layer 33A by stacking 3A. In addition, the remaining layer Rb has a conductive material layer 24B and a ferromagnetic layer 28 in order from the bottom.
B, a tunnel barrier layer 30B, a ferromagnetic layer 32B, and an antiferromagnetic layer 33B are stacked to form an antiferromagnetic layer 33B.
A hard mask 34c is disposed on the above.

The step of FIG. 17 is a step of obtaining the TMR elements Ta to Tc by subjecting the upper surface of the substrate to selective ion milling using the hard masks 34a to 34c as a mask after the step of FIG. The ion milling process of this step is different from the ion milling process of FIG. 6 in that the separation groove 42 is deeply formed so as to reach the conductive material layers 24A and 24B. After the ion milling process, as in the case described above with reference to FIG. 7, the sidewall deposited films (etching products) of the separation grooves 38 and 42 are formed.
A deposited film removing process is performed to remove the.

The TMR element Ta is composed of the conductive material layer 24 A surrounded by the separation groove 38 and the layers 28 A to 3 surrounded by the separation groove 42.
The TMR element Tb includes a conductive material layer 24 </ b> A surrounded by the separation groove 38 and a layer 2 surrounded by the separation groove 42 while being formed by stacking the portions 28 a to 33 a of 3 A and the hard mask 34 a.
8A to 33A portions 28b to 33b and the hard mask 3
4b and laminated. The conductive material layer 24A is used as one electrode layer of the TMR element Ta, and the hard mask 34a is used as the other electrode layer of the TMR element Ta. The conductive material layer 24A is used as one electrode layer of the TMR element Tb, and also serves as the hard mask 34b.
Is used as the other electrode layer of the TMR element Tb.
The TMR elements Ta and Tb are interconnected by a conductive material layer 24A as a wiring layer (common electrode layer).

The TMR element Tc is composed of the conductive material layer 24 B surrounded by the separation groove 38 and the layers 28 B to 3 surrounded by the separation groove 42.
3B portions 28c to 33c and a hard mask 34c are laminated. The conductive material layer 24B is used as one electrode layer of the TMR element Tc, and also the hard mask 34.
c is used as the other electrode layer of the TMR element Tc.

After the step of FIG. 17, the interlayer insulating film 46 is formed on the upper surface of the substrate in the same manner as described above with reference to FIG. Then, after forming the connection holes 46a to 46c in the insulating film 46 in the same manner as described above with reference to FIG. 8, the wiring layers 48a and 48b are formed on the insulating film 46 in the same manner as described above with reference to FIG.
To form.

According to the manufacturing method of the modification of FIGS. 16 and 17, the manufacturing yield of the magnetic sensor is improved similarly to the manufacturing method of the first embodiment described above. The obtained magnetic sensor operates similarly to the magnetic sensor shown in FIG.

Next, a method of manufacturing the magnetic sensor according to the second embodiment of the present invention will be described with reference to FIGS.

In the step of FIG. 18, after the substrate 20 whose surface is covered with the insulating film 22 is prepared as described above with reference to FIG. 1, the lower magnetic layer 50 and the tunnel barrier layer are formed on the insulating film 22 in order from the bottom. 52, the upper magnetic layer 54 and the conductive material layer 56 are laminated. The tunnel barrier layer 52 can be formed in the same manner as the tunnel barrier layer 30 described above with reference to FIG.

The lower magnetic layer 50 may be formed by laminating the conductive material layer 24, the antiferromagnetic layer 26 and the ferromagnetic layer 28 in this order from the bottom as described above with reference to FIG. 1. As another example, As described above with reference to FIG. 16, the ferromagnetic layer 28 may be stacked on the conductive material layer 24.

The upper magnetic layer 54 can be composed of the ferromagnetic layer 32 as described above with reference to FIG. 1, and as another example, an antiferromagnetic layer can be added to the ferromagnetic layer 32 as described above with reference to FIG. It may be stacked.

On the upper magnetic layer 54, for example, W or Ti
A conductive material layer 56 made of W is formed. The conductive material layer 56 is
The conductive material layer 34 described above with reference to FIG. 1 can be formed by a sputtering method, a CVD method, or the like, and the film thickness can be 100 to 400 nm (preferably 200 nm).

A resist layer 58 having a quadrilateral electrode pattern as shown at 26A in FIG. 13 is formed on the conductive material layer 56 by photolithography. At this time, the resist thickness is 100 to 700 nm (preferably 3 nm).
50 nm).

In the process of FIG. 19, the hard mask 56A is formed by patterning the conductive material layer 56 by ion milling or dry etching using the resist layer 58 as a selective mask. The hard mask 56A is composed of the remaining portion of the conductive material layer 56 corresponding to the resist layer 58. When the patterning process of the conductive material layer 56 is performed by the ion milling process or the dry etching process, the processing conditions can be the same as those described above with reference to FIG. After that, the resist layer 58 is removed by the same method as described above with reference to FIG. 3 to leave the hard mask 56A.

In the process of FIG. 20, the layers 50 to 5 are formed by ion milling using the hard mask 56A as a selective mask.
The separation groove 59 is formed in the stacked layer of No. 4 so as to reach the insulating film 22, and the stacked layer remaining portion Ra is obtained. The remaining laminated portion Ra is the remaining portions 50A to 54A of the layers 50 to 54 surrounded by the separation groove 59.
Consists of. In the ion milling process, the sidewall deposition film DP ₃₁ is formed on the sidewall of the separation groove 59. Deposition film DP
₃₁ is a metal component of the hard mask 56A, layers 50 and 54
However, the resist modifying component (organic substance) is not included.

The deposited film DP ₃₁ can be easily removed by the chemical treatment described above with reference to FIG. However, the deposited film DP ₃₁ is formed by the mask patterning process of FIG.
Since it is removed by the ion milling treatment of No. 4, it may be left.

In the process of FIG. 21, the hard mask 56A, the remaining laminated portion Ra, and the separation groove 59 are covered with, for example, W or T.
The conductive material layer 60 made of iW is formed by a sputtering method, a CVD method, or the like. The conductive material layer 60 can be formed in the same manner as the conductive material layer 34 described above with reference to FIG. 1, and the film thickness can be 100 to 400 nm (preferably 200 nm).

In the step of FIG. 22, resist layers 62a and 62b having quadrilateral element patterns as shown in Ta and Tb of FIG. 13 are formed on the conductive material layer 60 by photolithography. The resist thickness at this time is 80
It can be ˜500 nm (preferably 300 nm).

In the process of FIG. 23, the resist layers 62a, 6a are formed.
The hard mask 56A and the conductive material layer 60 are patterned by ion milling or dry etching using 2b as a mask to form the hard masks 56a, 56.
b, 60a, 60b are formed. Hard mask 56a,
56b is formed of the first and second remaining portions of the hard mask 56A corresponding to the resist layers 62a and 62b, respectively, and the hard masks 60a and 60b are formed of the first and second conductive material layers 60 corresponding to the resist layers 62a and 62b, respectively. 1,
It consists of a second remaining part. When the patterning process for the lamination of the hard mask 56A and the conductive material layer 60 is performed by the ion milling process or the dry etching process, the processing conditions can be the same as those described above with reference to FIG.

Next, the resist layers 62a and 62b are removed by the same method as described above with reference to FIG. 3, and the hard masks 56a and 60a are laminated and the hard masks 56b and 60b are stacked.
And the stack of layers are left. In addition to such a resist removal process, a deposited film removal process (a process that does not damage the tunnel barrier layer) such as a dilute hydrofluoric acid process + a pure water cleaning process may be performed.

In the process of FIG. 24, the hard masks 56a,
The isolation groove 64 is formed in the remaining layer Ra so as to reach the antiferromagnetic layer (or the conductive material layer) in the layer 50A by an ion milling process using the stack of 60a and the stack of the hard masks 56b and 60b as selective masks. By TMR element T
a, Tb are obtained. The TMR element Ta includes layers 52A and 54A.
Of the TMR element T including the remaining portions 52a and 54a of
b includes the remaining portions 52b and 54b of the layers 52A and 54A, and the layer 50A is in a state of being commonly arranged to the TMR elements Ta and Tb. TMR by the remaining lower magnetic layer 50A
There are three possible connection configurations of the elements Ta and Tb depending on the configuration of the lower magnetic layer 50 in the step of FIG. 18 and the depth of the isolation groove 64 in the step of FIG.

That is, when the lower magnetic layer 50 shown in FIG. 18 has a structure in which the conductive material layer 24, the antiferromagnetic layer 26 and the ferromagnetic layer 28 are laminated in this order from the bottom as shown in FIG. In the step of, the separation groove 64 is formed so as to reach the antiferromagnetic layer 26.
6A, the lower magnetic layer 50A is formed by stacking the remaining portions 24A and 26A of the layers 24 and 26 as shown in FIG. 6, and this stack is left in the form of interconnecting the TMR elements Ta and Tb. . When the separation groove 64 is formed so as to reach the conductive material layer 24 in the process of FIG. 24, the lower magnetic layer 50
As shown in FIG. 15, A is formed by stacking the remaining portions 24A and 26a of the layers 24 and 26 for the TMR element Ta and is formed by stacking the remaining portions 24A and 26b of the layers 24 and 26 for the TMR element Tb. The conductive material layer 24A is T
The MR elements Ta and Tb are left as they are interconnected.

When the lower magnetic layer 50 shown in FIG. 18 has a structure in which the ferromagnetic layer 28 is superposed on the conductive material layer 24 as described above with reference to FIG. 16, the conductive material layer 24 is reached in the step of FIG. When the separation groove 64 is formed, the lower magnetic layer 50A
As shown in FIG. 17, for the TMR element Ta, the remaining portions 24A and 28a of the layers 24 and 28 are laminated, and for the TMR element Tb, the remaining portions 24A and 28b of the layers 24 and 28 are laminated. Material layer 24A is TM
The R elements Ta and Tb are left as they are interconnected.

In the ion milling step of FIG. 24, a sidewall deposition film (not shown) as an etching product is formed on the sidewalls of the isolation trenches 59 and 64. These sidewall deposited films are
Since it does not contain organic substances such as resist modifying components, it can be easily removed. The side wall deposited film causes electrical shorts and leaks between metal layers above and below the tunnel barrier layer such as 52a, and must be removed. Therefore, the sidewalls (particularly the tunnel barrier layers 52a, 52a, 52b) of the isolation trenches 59, 64 are processed by the same method as described above with reference to FIG.
The side wall deposited film is removed from the end b). Hard mask 6
0a and 60b may be left as they are with the hard masks 56a and 56b to be used as a part of the electrode layer or the wiring layer, or may be removed during or after the ion milling process. When the hard masks 60a and 60b are removed, the hard masks 56a and 56b are left as electrode layers.

Thereafter, the processes of forming an interlayer insulating film, forming a connection hole, forming a wiring layer and the like are performed in the same manner as described above with reference to FIGS.

According to the manufacturing method of the second embodiment described above,
In the steps of FIGS. 19 and 23, a hard mask can be formed with good dimensional accuracy using a thin resist layer, and in the steps of FIGS. 20 and 24, the remaining layer and the TMR element can be formed with good dimensional accuracy using a hard mask. Since the sidewall deposited film can be easily removed in the process, the manufacturing yield of the magnetic sensor is improved for the reason that an electrical short circuit or a leak can be prevented between the upper and lower metal layers of the tunnel barrier layer such as 52a. Furthermore, the hard mask 56A can optimize the material and thickness for the ion milling process of FIG. 20, and the hard masks 60a and 60b can optimize the material and thickness for the ion milling process of FIG. There is also an advantage.

25 to 27 show a step of forming wiring in the wiring portion by diverting part of the TMR element forming process in the manufacturing method of the second embodiment described above.
Portions similar to those of 4 are denoted by the same reference numerals and detailed description thereof will be omitted.

In the step of FIG. 25, the lower magnetic layer 50, the tunnel barrier layer 52, the upper magnetic layer 54, and the conductive material layer are formed in this order from the bottom on the insulating film 22 covering the substrate 20 by diverting the film forming process of FIG. While forming 56 in a laminated shape, the photolithography process of FIG. 18 is diverted to form a resist layer corresponding to a desired wiring pattern on the conductive material layer 56. And
This resist layer is used as a selective mask and FIG.
The hard mask 56s is formed by patterning the conductive material layer 56 by diverting the ion milling treatment (or dry etching treatment). After that, the resist layer is removed by utilizing the resist removal process of FIG.

Next, the hard mask 56s is used as a selective mask and the ion milling process of FIG. 20 is applied to pattern the stack of the layers 50 to 54 to pattern the remaining portions 50s, 52s and 54s of the layers 50, 52 and 54. A laminated residual portion Rs including is obtained. In the ion milling process, a sidewall deposition film is formed on the sidewall of the remaining layer Rs. If necessary, a chemical treatment for removing the side wall deposited film is performed.

Next, the conductive material layer 60 is formed on the insulating film 22 by covering the hard mask 56s and the remaining laminated portion Rs by utilizing the film forming process of FIG. Then, by utilizing the photolithography process of FIG. 22, a resist layer 62s is formed on the conductive material layer 60 so as to cover the hard mask 56s and both side surfaces of the remaining layer Rs.

In the process of FIG. 26, the resist layer 62s is used as a selective mask and the ion milling process (or dry etching process) of FIG.
By patterning 0, the hard mask 60s is formed. The hard mask 60s is the hard mask 54s.
And the both side surfaces of the remaining laminated portion Rs.
After that, the resist removal process of FIG. 23 is diverted to remove the resist layer 62s.

In the process of FIG. 27, the ion milling process of FIG. 24 is executed using the hard mask 60s as a selection mask. In this process, the hard mask 60s is the hard mask 5
6 s and both side surfaces of the remaining laminated portion Rs are covered so as to remain. As a result, the wiring layer Ts including the laminated remaining portion Rs and the hard masks 56s and 60s is obtained. In this wiring layer Ts, the lower magnetic layer 50s and the upper magnetic layer 54s sandwiching the tunnel barrier layer 52s are left in the laminated portion R.
Since both sides of s are short-circuited by the hard mask 60s, the wiring resistance is reduced as compared with the case where there is no short circuit.

The wiring layer Ts shown in FIG. 27 can be used as a wiring layer at the same level as the TMR elements Ta and Tb shown in FIG. 24. For example, the wiring layer for the TMR element such as Ta or the substrate 20 is used. It can be used as a wiring layer for a circuit element such as a transistor formed on the surface.

In the steps of FIGS. 25 to 27, a part of the TMR element forming process is diverted to form the wiring layer Ts formed by laminating the layers 50s to 54s and the hard masks 56s and 60s, but the pattern is appropriately changed. Then, the insulating film flattening layer or the insulating film peeling prevention layer formed by stacking the layers 50s to 54s and the hard masks 56s and 60s can be formed by the same processing as the steps of FIGS.

28 to 33 show a method of manufacturing a magnetic sensor according to the third embodiment of the present invention, and FIGS.
The same parts as those in FIG.

In the step of FIG. 28, the lower magnetic layer 50, the tunnel barrier layer 52, the upper magnetic layer 54 and the conductive material layer 56 are formed in this order from the bottom on the insulating film 22 of the substrate 20 in the same manner as described above with reference to FIG. It is formed in a laminated shape.

On the conductive material layer 56, resist layers 70a and 70b having quadrilateral element patterns as shown in Ta and Tb of FIG. 13 are formed by photolithography. At this time, the resist thickness is 100 to 7
It can be set to 00 nm (preferably 350 nm).

In the process of FIG. 29, the resist layers 70a, 7
The conductive material layer 56 is patterned by ion milling or dry etching using 0b as a selective mask to form hard masks 56a and 56b. The hard masks 56a and 56b are resist layers 70a and 70b, respectively.
Corresponding to the first and second remaining portions of the conductive material layer 56. When the patterning process of the conductive material layer 56 is performed by the ion milling process or the dry etching process, the processing conditions can be the same as those described above with reference to FIG.
Then, the resist layers 70a and 70b are removed by the same method as described above with reference to FIG.
56b remains.

In the process of FIG. 30, the hard masks 56a,
The magnetic tunnel junctions ATa and ATb are formed by forming an isolation groove 72 in the stack of layers 50 to 54 so as to reach the antiferromagnetic layer (or conductive material layer) in the layer 50 by ion milling using 56b as a selective mask. To get The magnetic tunnel junction ATa is formed by the remaining portions 52a and 54a of the layers 52 and 54.
And the magnetic tunnel junction ATb includes the layers 52,
The layer 50 including the remaining portions 52b and 54b of 54 is in a state of being commonly arranged in the magnetic tunnel junction portions ATa and ATb. The processing conditions in the ion milling processing can be the same as those described above with reference to FIG. In the ion milling process, a plasma emission measurement method is used as a method for detecting the etching end point, and the light emission based on the constituent atoms of the lower magnetic layer 50 is detected to stop the ion milling. The target of light emission detection as the lower magnetic layer 50 is an antiferromagnetic layer or a conductive material layer.

That is, when the lower magnetic layer 50 has a structure in which the conductive material layer 24, the antiferromagnetic layer 26, and the ferromagnetic layer 28 are laminated in this order from the bottom as shown in FIG. 1, the ion milling treatment shown in FIG. If the milling is performed so as to reach the antiferromagnetic layer 26, the antiferromagnetic layer 26 is the target of light emission detection, and the conductive material layer 2 is subjected to the ion milling process of FIG.
If the milling is performed so as to reach 4, the conductive material layer 24 is the target of light emission detection. In addition, the lower magnetic layer 50 is formed on the conductive material layer 24 as described above with reference to FIG.
In the case of the structure in which eight layers are stacked, the ion milling process of FIG. 30 performs milling so as to reach the conductive material layer 24, so that the conductive material layer 24 is a target for light emission detection. In either case, since the exposed area of the antiferromagnetic layer 26 or the conductive material layer 24 is large, a signal intensity sufficient for light emission detection can be obtained, and the etching end point can be detected with high accuracy.

In the ion milling step of FIG. 30, a sidewall deposition film (not shown) as an etching product is formed on the sidewall of the isolation trench 72. The side wall deposited film is the hard mask 5
6a, 56b metal components, layers 50, 54 metal components, etc., but does not contain the resist modifying component (organic substance),
It can be easily removed.

Next, as described above with reference to FIG. 4, a chemical treatment is applied to the upper surface of the substrate to separate the sidewall deposited film into the separation groove 72.
Sidewalls (especially the ends of the tunnel barrier layers 52a and 52b)
To remove from. Thereafter, a cleaning milling process as described above with reference to FIG. 4 may be added if necessary. This treatment enables further cleaning and the side wall shape becomes more tapered. Since the etching products such as the side wall deposited film are removed in the step of FIG. 30, it is possible to prevent electrical short circuit or leakage between the metal layers above and below the tunnel barrier layer such as 52a.

In the process of FIG. 31, the magnetic tunnel junction A
Covering Ta and ATb and the separation groove 72, for example W or Ti
The conductive material layer 74 made of W is formed by a sputtering method, a CVD method, or the like. The conductive material layer 74 can be formed in the same manner as the conductive material layer 34 described above with reference to FIG. 3, and the film thickness can be 100 to 400 nm (preferably 200 nm).

Next, on the conductive material layer 74, 26A of FIG.
A resist layer 76 having a quadrilateral electrode pattern is formed by photolithography as shown in FIG. The resist layer 76 is formed so as to cover the magnetic tunnel junction portions ATa and ATb. The resist thickness at this time is 80 to 5
It can be set to 00 nm (preferably 300 nm).

In the step of FIG. 32, the hard mask 74A is formed by patterning the conductive material layer 74 by ion milling or dry etching using the resist layer 76 as a selective mask. The patterning process of the conductive material layer 74 can be performed in the same manner as the patterning process of the conductive material layer 34 described above with reference to FIG.

In the step of FIG. 32, the resist layer 76 is removed by the same method as described above with reference to FIG. 2 to leave the hard mask 74A. In addition to such a resist removal process, a deposited film removal process (a process that does not damage the tunnel barrier layer) such as a dilute hydrofluoric acid process + a pure water cleaning process may be performed. By doing so, the resist-removed surface can be further cleaned.

In the step of FIG. 33, the lower magnetic layer 5 is formed by ion milling using the hard mask 74A as a selective mask.
The isolation trench 78 is formed so as to reach the insulating film 22, and the hard mask 74A is removed. Hard mask 7
The thickness of 4A can be set in advance so as to be removed by the ion milling process of FIG. As a result of the ion milling treatment, a part 50A of the lower magnetic layer 50 is separated into the separation groove 78.
Remains in the form surrounded by. The connection form of the TMR elements Ta and Tb by the remaining lower magnetic layer 50A is the structure of the lower magnetic layer 50 in the step of FIG. 28 and the separation groove 72 in the step of FIG.
There are three types depending on the depth of the connection, and the details of each connection form are the same as those described above with reference to FIGS. 6, 15 and 17 in connection with the process of FIG.

In the ion milling step of FIG. 33, a sidewall deposited film (not shown) as an etching product is formed on the sidewalls of the isolation trenches 72 and 78. These sidewall deposited films are
Since it does not contain organic substances such as resist modifying components, it can be easily removed. The side wall deposited film causes electrical shorts and leaks between metal layers above and below the tunnel barrier layer such as 52a, and must be removed. Therefore, the sidewalls of the isolation trenches 72 and 78 (particularly the tunnel barrier layers 52a and 52a) are formed by the same method as described above with reference to FIG.
The side wall deposited film is removed from the end b).

Thereafter, the processes of forming an interlayer insulating film, forming a connection hole, forming a wiring layer and the like are performed in the same manner as described above with reference to FIGS.

According to the manufacturing method of the third embodiment described above,
29 and 32, a hard mask can be formed with good dimensional accuracy using a thin resist layer, and magnetic tunnel junctions and TMR elements can be formed with good dimensional accuracy using a hard mask in the steps of FIGS. 30 and 33. In the step of (3), the side walls of the magnetic tunnel junction portions ATa, ATb are covered with the conductive material layer 74 to avoid resist contamination. In the step of FIG. 33, the side wall deposited film can be easily removed, so that the tunnel barrier layers such as 52a can be formed. The manufacturing yield of the magnetic sensor is improved because of prevention of electrical short circuit and leakage between the upper and lower metal layers. In addition, FIG.
As is clear from comparison with No. 24, the insulating film 22 is scraped only during the ion milling process of FIG.
The step D at the end of the electrode layer 50A is low, and there is an advantage that the short circuit failure of the wiring due to the defect of the interlayer insulating film as described above with reference to FIG. 42 can be prevented.

34 to 36 show a step of forming wiring in the wiring portion by diverting part of the TMR element forming process in the manufacturing method of the third embodiment described above.
The same parts as those in No. 3 are denoted by the same reference numerals and detailed description thereof will be omitted.

In the step of FIG. 34, the lower magnetic layer 50, the tunnel barrier layer 52, the upper magnetic layer 54, and the conductive material layer are formed in order from the bottom on the insulating film 22 covering the substrate 20 by diverting the film forming process of FIG. While forming 56 in a laminated form, the photolithography process of FIG. 28 is diverted to form a resist layer corresponding to a desired wiring pattern on the conductive material layer 56. And
This resist layer is used as a selective mask and FIG.
The hard mask 56s is formed by patterning the conductive material layer 56 by diverting the ion milling treatment (or dry etching treatment). After that, the resist layer is removed by diverting the resist removing process shown in FIG.

Next, the hard mask 56s is used as a selective mask and the ion milling process of FIG. 30 is applied to mill the stacked layers 50 to 54 until the antiferromagnetic layer (or conductive material layer) in the layer 50 is reached. The layers 52,
A magnetic tunnel junction portion ATs including the remaining portions 52s and 54s of 54 is obtained. In the ion milling process, a sidewall deposition film is formed on the sidewall of the magnetic tunnel junction ATs. If necessary, a chemical treatment for removing the side wall deposited film is performed.

Next, the conductive material layer 74 is formed on the lower magnetic layer 50 by covering the hard mask 56s and the magnetic tunnel junction portion ATs by utilizing the film forming process of FIG. Then, by utilizing the photolithography process of FIG. 31, a resist layer 76s is formed on the conductive material layer 74 so as to cover the hard mask 56s and both side surfaces of the magnetic tunnel junction portion ATs.

In the step of FIG. 35, the conductive material layer 7 is formed by using the resist layer 76s as a selective mask and diverting the ion milling process (or dry etching process) of FIG.
By patterning 4, hard mask 74s is formed. The hard mask 74s is the hard mask 54s.
And the both side surfaces of the magnetic tunnel junction portion ATs are formed. After that, the resist removal process of FIG. 32 is applied to remove the resist layer 76s.

In the step of FIG. 36, the hard mask 74s is used as a selective mask to perform the ion milling process of FIG. 33 to leave a part of the lower magnetic layer 50s in a pattern corresponding to the hard mask 74s. This process
The hard mask 74s is left so as to cover the hard mask 56s and both side surfaces of the magnetic tunnel junction portion ATs. As a result, a wiring layer Ts including a stack of the magnetic tunnel junction portion ATs and the hard masks 56s and 74s is obtained. In the wiring layer Ts, the tunnel barrier layer 52
Since the lower magnetic layer 50s and the upper magnetic layer 54s sandwiching s are short-circuited by the hard masks 74s on both sides of the magnetic tunnel junction ATs, the wiring resistance is reduced as compared with the case without no short circuit.

In order to remove the hard mask 74A in the TMR element portion and leave the hard mask 74s in the wiring portion as shown in FIGS. 33 and 36, (a) FIG.
1 and 34, the conductive material layer 74 is made thicker in advance in the wiring portion than the TMR element portion, or (b) in the steps of FIGS. 31 and 34, the thickness of the conductive material layer 74 is set to the TMR element portion. 33 and 36, the hard mask 74A remaining in the first ion milling process in the state where the wiring part is masked is used as the hard mask 74A. A method of removing by the second ion milling treatment or the like can be adopted.

The wiring layer Ts shown in FIG. 36 can be used as a wiring layer at the same level as the TMR elements Ta and Tb shown in FIG. 33. For example, the wiring layer for the TMR element such as Ta or the substrate 20 can be used. It can be used as a wiring layer for a circuit element such as a transistor formed on the surface.

In the steps of FIGS. 34 to 36, a part of the TMR element forming process is diverted to form the wiring layer Ts including the layers 50 s to 54 s and the hard masks 56 s and 74 s, but the pattern is appropriately changed. Then, the insulating film flattening layer or the insulating film peeling prevention layer formed by stacking the layers 50s to 54s and the hard masks 56s and 74s can be formed by the same processing as the steps of FIGS.

In the above description, W and TiW are exemplified as the conductive material for the hard mask, but other various conductive materials can be used. In the ion milling apparatus, the milling rate is the type of gas of the ion source (generally a rare gas such as Ar, but O ₂ , Cl ₂ , SF ₆ , C
F ₄ etc. may be used), ion energy intensity,
The density of the ion beam, the angle of incidence of the ion beam on the work piece, the composition of the work piece, the crystallinity, the crystal orientation, the film formation method, and other factors can significantly change the operation status of the milling equipment (operation time, maintenance status, repairs). / It will also change slightly depending on the state of modification. Therefore, the inventor can use it by setting the milling rate of the reference material SiO ₂ to 100 under a certain constant condition, comparing the milling rate of various conductive materials with this, and evaluating the specific resistance of various conductive materials. Conductive materials were obtained and classified into the following A to D groups.

Group A includes W, WSi _X (x = 1 to
3), Ti, TiW, TiSi _X (x = 1 to 3), V.

The materials in this group have a low milling rate and a low specific resistance. Even if the film thickness is made thin, it is difficult to be milled and the wiring has low resistance, which is advantageous for miniaturization. Resistant to oxidation and stable even if an interlayer insulating film is formed on the upper layer. Since a volatile (low vapor pressure) compound is easily formed, patterning by dry etching is possible, and the film forming method is not limited to the sputtering method, and the CVD method can be used. It should be noted that alloys related to any combination of materials in group A are considered to be fully usable.

Group B includes Mo, MoSi _X (x = 1)
˜3), Ta, TaSi _X (x = 1 to 3), Zr, Zr
It includes Si _X (x = 1 to 3), Si, Al (depending on crystallinity / orientation and dopant). The materials in this group have a milling rate almost equal to that of SiO ₂ and Ni—Fe alloys, and have low specific resistance (however, the specific resistance of Zr is
It is as large as 40 μΩcm). Since it is difficult to remove by milling to some extent, the film thickness can be made moderately thin. Further, the wiring has low resistance, which is advantageous for miniaturization. It is strong against oxidation and stable even if an interlayer insulating film is formed on the upper layer. A volatile (low vapor pressure) compound is easily formed, and patterning by dry etching is possible.

B'group is Fe, Cr, CrSi _X
(X = 1 to 3), Co, CoSi _X (x = 1 to 3), N
i, NiSi _X (x = 1 to 3), Nb, Os, Re, I
Including r. This group of materials has a milling rate of S
It has almost the same level as iO ₂ and Ni-Fe alloy, and has a small specific resistance. Because it is difficult to be milled to some extent,
The film thickness can be made thin. Further, the wiring has low resistance, which is advantageous for miniaturization. The platinum group is resistant to oxidation and is stable even if an interlayer insulating film is formed on the upper layer. Many of the single elements or alloys with other magnetic metals exhibit ferromagnetism, and it is necessary to consider so as not to hinder the characteristics of the TMR element.

Group C includes Cu, Ru, Hf, Pt,
Including Rh and Mn. The materials in this group have a high milling rate and thus are inferior in milling maskability, but have a low specific resistance (however, the specific resistance of Mn is as high as 258 μΩcm). Since it is easily scraped by milling, it is necessary to increase the film thickness. The wiring has low resistance. The hard masks 60a and 60b used in the second embodiment or the hard mask 74A used in the third embodiment are easy to use.

D group includes Y, Pd, Au, Sn, A
Including g and Pb. The materials in this group have a milling rate as large as three times that of SiO ₂ , but have a low specific resistance (however, the specific resistance of Y is as large as 53 μΩcm). Since it is easily scraped by milling, it is necessary to increase the film thickness.
The wiring has low resistance. Similar to the material of the C group, it is easy to use as the hard mask 60a, 60b or 74A.

When a preferable material for the conductive material of the hard mask is selected from the above groups A to D,
A, B, B'group materials and C group Cu, P
t and Mn can be mentioned. The other materials in the C group and the materials in the D group are the hard masks 60a, 60.
It can be used as the material of b or 74A.

FIG. 37 shows an LSI chip equipped with the magnetic sensor according to the present invention. LSI chip LC
Is provided with a P-type semiconductor substrate 80 made of, for example, silicon, and a field insulating film 82 made of silicon oxide is formed on one main surface of the substrate 80 by a selective oxidation method.

A MOS type transistor is formed in the element hole of the insulating film 82 on one main surface of the substrate 80, and 84 is an N ⁺ type drain region of the transistor. An interlayer insulating film 86 is formed so as to cover the insulating film 82 and the MOS transistor, and a first connection hole corresponding to a part of the drain region 84 is formed in this insulating film 86. A wiring layer 88 is formed on the insulating film 86 so as to be connected to the drain region 84 via the first connection hole.

An interlayer insulating film 90 is formed on the insulating film 86 so as to cover the wiring layer 88, and a second connection hole corresponding to a part of the wiring layer 88 is formed in the insulating film 90. Has been done. A lower magnetic layer 50c is formed on the insulating film 90 so as to be connected to the wiring layer 88 via the second connection hole. On the insulating film 90, the lower magnetic layers 50k, 50
A and 50s are also formed. Lower magnetic layer 50c, 50
k, 50A, and 50s are all obtained by sequentially stacking the conductive material layer 24, the antiferromagnetic layer 26, and the ferromagnetic layer 28 from the bottom as described above with reference to FIG. 1, or the conductive material layer 24 as described above with reference to FIG. And the ferromagnetic layer 28 is superposed thereon.

As described above with reference to FIG. 24, the TMR elements Ta and Tb include the upper magnetic layers 54a and 54 on the lower magnetic layer 50A via the tunnel barrier layers 52a and 52b, respectively.
b and electrode layers (hard masks) 56a and 56b are respectively disposed on the upper magnetic layers 54a and 54b. In the TMR element Tc, the upper magnetic layer 54c is arranged on the lower magnetic layer 50c via the tunnel barrier layer 52c, and the electrode layer (hard mask) 56c is arranged on the upper magnetic layer 54c. The insulating film flattening layer Tk disposed between the TMR elements Tb and Tc has an upper magnetic layer 54k disposed on the lower magnetic layer 50k via a tunnel barrier layer 52k and a conductive material disposed on the upper magnetic layer 54k. The layer (hard mask) 56k is arranged. The wiring layer Ts includes the tunnel barrier layer 52s on the upper magnetic layer 50s.
The upper magnetic layer 54s is disposed via the
The conductive material layer (hard mask) 56s is disposed on the s. Upper magnetic layers 54a, 54b, 54c, 54k,
Each of 54s is composed of the ferromagnetic layer 32 as described above with reference to FIG. 1 or is an antiferromagnetic layer stacked on the ferromagnetic layer 32 as described above with reference to FIG.

An insulating film flattening layer Tk is formed on the insulating film 90.
An insulating film peeling prevention layer (not shown) having substantially the same laminated structure as the above may be arranged so as to surround the MOS transistor circuit arrangement region or the TMR element arrangement region, for example. The TMR elements Ta to Tc, the wiring layer Ts, the insulating film flattening layer Tk, and the insulating film peeling prevention layer have the above-mentioned first to third parts.
It can be manufactured by the manufacturing method according to any of the embodiments (including modified examples).

The TMR elements Ta to T are formed on the insulating film 90.
An interlayer insulating film 92 is formed so as to cover the c, the wiring layer Ts, the insulating film flattening layer Tk, and the like.
6c, 56b, 56a respectively corresponding to the third, fourth,
The fifth connection hole is formed, and the sixth and seventh connection holes corresponding to the first portion near one end and the second portion near the other end of the conductive material layer 56s are formed.

A wiring layer 94 is formed on the insulating film 92 so as to interconnect the electrode layers 56c and 56b through the third and fourth connection holes, and the fourth and fifth connection holes are formed. A wiring layer 96 is formed so as to interconnect the first portion of the electrode layer 56a and the first portion of the conductive material layer 56s with each other.
The conductive material layer 5 is formed on the insulating film 92 through the seventh connection hole.
The bonding electrode layer 98 is formed so as to be connected to the second portion of 6s, and the electrode layer 98 constitutes a bonding pad together with a part of the wiring layer Ts therebelow. A bonding wire is connected to the electrode layer 98. A protective insulating film is formed on the insulating film 92 so as to cover the wiring layers 94 and 96 and expose the electrode layer 98, but the illustration is omitted.

The wiring layer Ts includes a first wiring path in which a conductive material layer (hard mask) 56s is arranged on the upper magnetic layer 54s and a second wiring path including a lower magnetic layer 50s including a conductive material layer. And the first and second wiring paths are electrically separated by the tunnel barrier layer 52s. First and second
Since each of the wiring paths includes a conductive material layer, low resistance wiring can be realized. The first wiring path is, for example, TM
Since the wiring is at the same level as that of the electrode layer 56a of the R element Ta, the wiring layer 96 is flattened by flattening the insulating film 92 and the connection hole is shallowed to facilitate the processing and embedding of the connection hole. be able to. The second wiring path can be used as wiring for a circuit element in the substrate 80 by connecting to the wiring layer 88 as shown by a line 88a. Further, as described above with reference to FIGS. 25 to 27 or 34 to 36, the first and second wiring paths are short-circuited by the conductive layers formed on both sides of the wiring layer Ts to thereby form the first or second wiring paths. The wiring resistance can be reduced to about half as compared with the case where it is used alone. Therefore, by providing the wiring layer Ts, the degree of freedom in wiring design in the integrated circuit is improved.

When the insulating film flattening layer Tk is arranged in the space between the TMR elements Tb and Tc, the insulating film 92 can be easily flattened and the wiring layer 94 can be extended in a flat shape. Further, when the insulating film peeling prevention layer is provided as described above, peeling of the insulating film 92 can be prevented and L
It is possible to prevent moisture from entering the inside of the SI chip.

In the structure of FIG. 37, TMR elements Ta to
The Tc, the wiring layer Ts, the insulating film flattening layer Tk, and the insulating film peeling prevention layer may be provided at the same wiring level (on the insulating film 86) as the wiring layer 88, or at any position above the illustrated arrangement position. It may be provided at the wiring level.

The present invention can be applied not only to the magnetic sensor as described above, but also to the manufacture of other TMR element application products (magnetic tunnel junction device) such as magnetic sensors, magnetic memories, and magnetic heads. .

[0167]

As described above, according to the present invention, the remaining portion of the magnetic tunnel junction stack is subjected to the selective etching process using the hard mask made of a conductive material as a selective mask to form the magnetic tunnel junction portion and the electrode layer. After that, the deposit deposited at the end of the tunnel barrier layer at the end of the tunnel barrier layer in the magnetic tunnel junction is removed, or the magnetic tunnel junction is selectively etched using a hard mask made of a conductive material as a selective mask. After forming the electrode layer below, the hard mask is removed from the end of the tunnel barrier layer at the magnetic tunnel junction, so that an electrical short circuit or a leak may occur between the metal layers above and below the tunnel barrier layer. Therefore, it is possible to obtain the effect that the manufacturing yield of the TMR element is improved and the characteristic deterioration of the TMR element can be prevented. Further, in the manufacturing method of the present invention, it is not necessary to perform the ion milling treatment in an oxidizing or nitriding atmosphere, and therefore, there is an advantage that the detection accuracy of the etching end point does not decrease.

Moreover, in the selective etching process using the hard mask made of a conductive material as a selective mask, since the deposit (etching product) does not contain an organic substance such as a resist modifying component, it adheres to the sidewall of the magnetic tunnel junction. The deposit can be easily removed without using an organic solvent or the like, and there is an effect that the cost can be reduced. Further, there is an advantage that a fine pattern can be easily formed and the processing accuracy is high.

Furthermore, since part of the TMR element forming process is diverted to form a wiring layer, an insulating film flattening layer, or an insulating film peeling prevention layer, which has substantially the same laminated structure as the TMR element, the wiring is formed at low cost. The effect that the degree of freedom in design is improved and the flatness or stability of the insulating film is improved can be obtained.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a lamination forming step and a resist layer forming step in a method of manufacturing a magnetic sensor according to a first embodiment of the present invention.

FIG. 2 is a substrate cross-sectional view showing a mask forming process following the process of FIG.

FIG. 3 is a substrate cross-sectional view showing a resist removing step and an ion milling step that follow the step of FIG.

FIG. 4 is a substrate cross-sectional view showing a sidewall deposited film removing step and a resist layer forming step following the step of FIG.

FIG. 5 is a substrate cross-sectional view showing a mask forming step following the step of FIG.

6 is a substrate cross-sectional view showing a resist removing step and an ion milling step that follow the step of FIG.

FIG. 7 is a substrate cross-sectional view showing a sidewall deposited film removing step that follows the step of FIG.

8 is a substrate cross-sectional view showing an insulating film forming step and a connection hole forming step that follow the step of FIG.

9 is a substrate cross-sectional view showing a wiring forming process following the process of FIG.

10 is a substrate cross-sectional view showing a wiring layer forming process corresponding to FIGS. 1 to 3 in a wiring portion. FIG.

11 is a substrate cross-sectional view showing a sidewall deposited film removing step, a resist layer forming step, and an ion milling step corresponding to FIGS. 4 and 5 in the wiring portion.

FIG. 12 is a substrate cross-sectional view showing a resist removing step, an ion milling step, and a sidewall deposited film removing step corresponding to FIGS.

FIG. 13 is a top view showing a connection state of TMR elements.

FIG. 14 is a substrate cross-sectional view showing a mask forming step in a first modification example of the first embodiment.

15 is a substrate cross-sectional view showing an ion milling process and a sidewall deposited film removing process following the process of FIG.

FIG. 16 is a substrate cross-sectional view showing a mask forming step in a second modification example of the first embodiment.

FIG. 17 is a substrate cross-sectional view showing an ion milling process and a sidewall deposited film removing process following the process of FIG.

FIG. 18 is a substrate cross-sectional view showing a lamination forming step and a resist layer forming step in the method of manufacturing the magnetic sensor according to the second embodiment of the invention.

FIG. 19 is a substrate cross-sectional view showing a mask forming step that follows the step of FIG.

20 is a substrate cross-sectional view showing an ion milling process following the process of FIG.

21 is a substrate cross-sectional view showing a sidewall deposited film removing step and a conductive material layer forming step following the step of FIG. 20. FIG.

22 is a substrate cross-sectional view showing a resist layer forming step following the step of FIG. 21. FIG.

23 is a cross-sectional view of the substrate showing a mask forming step following the step of FIG.

FIG. 24 is a substrate cross-sectional view showing an ion milling process and a sidewall deposited film removing process following the process of FIG. 23.

FIG. 25 is a substrate cross-sectional view showing a step corresponding to FIGS. 18 to 22 in the wiring portion.

FIG. 26 is a substrate cross-sectional view showing a step of the wiring portion corresponding to FIG. 23.

FIG. 27 is a substrate cross-sectional view showing a step of the wiring portion corresponding to FIG. 24.

FIG. 28 is a cross-sectional view of a substrate showing a lamination forming step and a resist layer forming step in the method of manufacturing a magnetic sensor according to the third embodiment of the present invention.

FIG. 29 is a substrate cross-sectional view showing a mask forming step following the step of FIG. 28.

FIG. 30 is a substrate cross-sectional view showing an ion milling process and a sidewall deposited film removing process following the process of FIG. 29.

31 is a substrate cross-sectional view showing a resist layer forming step following the step of FIG. 30. FIG.

32 is a substrate cross-sectional view showing a mask forming step following the step of FIG. 31. FIG.

FIG. 33 is a substrate cross-sectional view showing an ion milling process and a sidewall deposited film removing process following the process of FIG. 32.

34 is a substrate cross-sectional view showing a step corresponding to FIGS. 28 to 31 in the wiring portion. FIG.

35 is a substrate cross-sectional view showing a step of the wiring portion corresponding to FIG. 32. FIG.

FIG. 36 is a substrate cross-sectional view showing a step of the wiring portion corresponding to FIG. 33.

FIG. 37 is an LSI provided with a magnetic sensor according to the present invention.
It is sectional drawing which shows a chip.

FIG. 38 is a cross-sectional view of a substrate showing a laminated layer forming step and a resist layer forming step in a conventional magnetic sensor manufacturing method.

FIG. 39 is a substrate cross-sectional view showing an ion milling process and a resist removing process following the process of FIG. 38.

40 is a substrate cross-sectional view showing a resist layer forming step following the step of FIG. 39. FIG.

41 is a substrate cross-sectional view showing an ion milling process and a resist removing process following the process of FIG. 40. FIG.

42 is a substrate cross-sectional view showing an insulating film forming step and a connection hole forming step that follow the step of FIG.

FIG. 43 is a substrate cross-sectional view showing a wiring forming process following the process of FIG. 42.

44 is a cross-sectional view of the substrate showing the state of formation of the sidewall deposited film in the ion milling process of FIG. 39.

45 is a substrate cross-sectional view showing the state of formation of a sidewall deposited film in the ion milling process of FIG. 41.

[Explanation of reference numerals] 20, 80: semiconductor substrate, 22, 46, 82, 86, 9
0, 92: insulating film, 24, 34, 56, 60, 74: conductive material layer, 26, 33A, 33B: antiferromagnetic layer, 28, 3
2: ferromagnetic layer, 30, 52: tunnel barrier layer, 36
a, 36b, 40a-40c, 40s, 58, 62a,
62b, 62s, 70a, 70b, 76, 76s: resist layer, 38, 42, 59, 64, 72, 78: separation groove, 34A, 34B, 34a to 34c, 34s, 56.
A, 56a, 56b, 56s, 60a, 60b, 60
s, 74A, 74s: hard mask, 46a to 46c:
Connection holes, 48a, 48b, 88,94,96, Ts : the wiring layer, 50: lower magnetic layer, 54: upper magnetic layer, 84: drain region, 98: bonding electrode _layer, DP 10 to DP
₂₅ , DP ₃₁ : Side wall deposited film, Ra, Rb, Rs: Laminated remaining portion, Ta to Tc: TMR element, ATa, ATb, A
Ts: magnetic tunnel junction, LC: LSI chip, T
k: insulating film flattening layer.

Claims (9)

[Claims] 1. A step of forming a magnetic tunnel junction stack on an insulating main surface of a substrate through a first conductive material layer,
An antiferromagnetic layer and a first antiferromagnetic layer are formed on the first conductive material layer in order from the bottom.
Forming a magnetic tunnel junction stack by stacking the magnetic layer, the tunnel barrier layer, and a second magnetic layer, and forming a second conductive material layer covering the magnetic tunnel junction stack; The second conductive material layer is subjected to a first selective etching treatment so as to leave the second conductive material layer so as to cover the junction stack according to a desired electrode pattern, and the remaining portion of the second conductive material layer is left. Forming a first hard mask consisting of a portion; and subjecting the magnetic tunnel junction stack to a second selective etching process using the first hard mask as a selective mask to form the magnetic tunnel junction stack according to the electrode pattern. And leaving the first hard mask so as to cover the remaining portion of the magnetic tunnel junction stack according to a desired element pattern. Therefore, a step of forming a second hard mask composed of the remaining portion of the first hard mask by subjecting the first hard mask to a third selective etching treatment, and the step of forming the second hard mask in the remaining portion of the magnetic tunnel junction stack. A fourth selective etching process using the second hard mask as a selective mask is performed to etch the remaining portion of the magnetic tunnel junction stack until it reaches the antiferromagnetic layer, thereby the first magnetic layer and the tunnel barrier. A magnetic tunnel junction consisting of a layer and a remaining portion of each of the second magnetic layers, and below the magnetic tunnel junction from a remaining portion of each of the first conductive material layer and the antiferromagnetic layer. The remaining first electrode layer and the second hard mask as a second electrode layer, and Preparation of the magnetic tunnel junction element and a step of removing the fourth selection deposited sediments during the etching process to the end of the Nerubaria layer. 2. A step of forming a magnetic tunnel junction stack on one insulating main surface of a substrate with a first conductive material layer interposed therebetween,
An antiferromagnetic layer and a first antiferromagnetic layer are formed on the first conductive material layer in order from the bottom.
The magnetic layer, the tunnel barrier layer, and the second magnetic layer, or a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an antiferromagnetic layer in order from the bottom on the first conductive material layer. To form the magnetic tunnel junction stack, a step of forming a second conductive material layer to cover the magnetic tunnel junction stack, and the step of covering the magnetic tunnel junction stack according to a desired electrode pattern. Forming a first hard mask made of the remaining portion of the second conductive material layer by subjecting the second conductive material layer to a first selective etching treatment so that the second conductive material layer remains. A step of leaving the magnetic tunnel junction stack according to the electrode pattern by subjecting the magnetic tunnel junction stack to a second selective etching process using the first hard mask as a selective mask; The first hard mask is formed by performing a third selective etching process on the first hard mask so as to leave the first hard mask so as to cover the remaining portion of the magnetic tunnel junction stack according to a desired element pattern. Forming a second hard mask composed of the remaining portion of the magnetic tunnel junction stack, and subjecting the remaining portion of the magnetic tunnel junction stack to a fourth selective etching process using the second hard mask as a selective mask. By etching the remaining portion of the antiferromagnetic layer, the first magnetic layer, the tunnel barrier layer, and the second magnetic layer until the first conductive material layer is reached. When a magnetic tunnel junction is formed by the remaining portions of the first magnetic layer, the tunnel barrier layer, the second magnetic layer, and the antiferromagnetic layer. A step of leaving a first electrode layer made of a remaining portion of the first conductive material layer under the magnetic tunnel junction, and a step of leaving the second hard mask as a second electrode layer; A method of manufacturing a magnetic tunnel junction element, which comprises a step of removing a deposit deposited at the end of the tunnel barrier layer in the magnetic tunnel junction portion during the fourth selective etching process. 3. A step of forming a magnetic tunnel junction stack on one insulating main surface of a substrate through a first conductive material layer,
An antiferromagnetic layer and a first antiferromagnetic layer are formed on the first conductive material layer in order from the bottom.
Forming a magnetic tunnel junction stack by stacking the magnetic layer, the tunnel barrier layer, and a second magnetic layer, and forming a second conductive material layer covering the magnetic tunnel junction stack; The second conductive material layer is subjected to a first selective etching treatment so as to leave the second conductive material layer so as to cover the junction stack according to a desired electrode pattern, and the remaining portion of the second conductive material layer is left. Forming a first hard mask consisting of a portion; and subjecting the magnetic tunnel junction stack to a second selective etching process using the first hard mask as a selective mask to form the magnetic tunnel junction stack according to the electrode pattern. And a step of forming a third conductive material layer covering the first hard mask and the remaining portion of the magnetic tunnel junction stack. In order to leave the first hard mask and the third conductive material layer so as to cover the remaining portion of the air tunnel junction stack according to a desired element pattern, the first hard mask and the third conductive material layer are provided with a second layer. The first hard mask and the third hard mask
A step of forming a second hard mask made of the remaining portions of the conductive material layers, and a fourth selective etching process using the second hard mask as a selective mask on the remaining portions of the magnetic tunnel junction stack. The remaining portion of the magnetic tunnel junction stack is etched to reach the antiferromagnetic layer, thereby forming a magnetic tunnel junction composed of the remaining portions of the first magnetic layer, the tunnel barrier layer, and the second magnetic layer. And a first electrode layer composed of remaining portions of the first conductive material layer and the antiferromagnetic layer is left under the magnetic tunnel junction, and the second hard mask At least the remaining portion of the first hard mask is
And a step of removing the deposit deposited at the end of the tunnel barrier layer at the end of the tunnel barrier layer in the magnetic tunnel junction, the method for manufacturing a magnetic tunnel junction element. . 4. A step of forming a magnetic tunnel junction stack on one insulating main surface of a substrate through a first conductive material layer,
An antiferromagnetic layer and a first antiferromagnetic layer are formed on the first conductive material layer in order from the bottom.
The magnetic layer, the tunnel barrier layer, and the second magnetic layer, or a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an antiferromagnetic layer in order from the bottom on the first conductive material layer. To form the magnetic tunnel junction stack, a step of forming a second conductive material layer to cover the magnetic tunnel junction stack, and the step of covering the magnetic tunnel junction stack according to a desired electrode pattern. Forming a first hard mask made of the remaining portion of the second conductive material layer by subjecting the second conductive material layer to a first selective etching treatment so that the second conductive material layer remains. A step of leaving the magnetic tunnel junction stack according to the electrode pattern by subjecting the magnetic tunnel junction stack to a second selective etching process using the first hard mask as a selective mask; Forming a third conductive material layer over the first hard mask and the remaining portion of the magnetic tunnel junction stack, and the step of covering the remaining portion of the magnetic tunnel junction stack according to a desired element pattern. The first hard mask and the third conductive material layer are subjected to a third selective etching treatment so that the first hard mask and the third conductive material layer remain. Three
A step of forming a second hard mask made of the remaining portions of the conductive material layers, and a fourth selective etching process using the second hard mask as a selective mask on the remaining portions of the magnetic tunnel junction stack. Each of the antiferromagnetic layer, the first magnetic layer, the tunnel barrier layer, and the second magnetic layer by etching the remaining portion of the magnetic tunnel junction stack until it reaches the first conductive material layer. Or a magnetic tunnel junction formed of the remaining portions of the first magnetic layer, the tunnel barrier layer, the second magnetic layer, and the antiferromagnetic layer is formed under the magnetic tunnel junction. To leave the first electrode layer made of the remaining portion of the first conductive material layer, and at least the remaining portion of the first hard mask in the second hard mask is the second electrode. A method of manufacturing a magnetic tunnel junction device, comprising: a step of remaining as a layer; and a step of removing a deposit deposited at the end of the tunnel barrier layer in the magnetic tunnel junction section during the fourth selective etching treatment. 5. A step of forming a magnetic tunnel junction stack on one insulating main surface of a substrate through a first conductive material layer,
An antiferromagnetic layer and a first antiferromagnetic layer are formed on the first conductive material layer in order from the bottom.
Forming a magnetic tunnel junction stack by stacking the magnetic layer, the tunnel barrier layer, and a second magnetic layer, and forming a second conductive material layer covering the magnetic tunnel junction stack; A remaining portion of the second conductive material layer is formed by performing a first selective etching process on the second conductive material layer so that the second conductive material layer remains so as to cover the junction stack according to a desired element pattern. Forming a first hard mask consisting of a portion; and subjecting the magnetic tunnel junction stack to the antiferromagnetic process by subjecting the magnetic tunnel junction stack to a second selective etching process using the first hard mask as a selective mask. Forming a magnetic tunnel junction consisting of the remaining portions of each of the first magnetic layer, the tunnel barrier layer and the second magnetic layer by etching until the layer is reached. And a step of forming a third conductive material layer to cover the first hard mask, the magnetic tunnel junction, and the exposed portion of the antiferromagnetic layer, the first hard mask and the magnetic layer. Subjecting the third conductive material layer to a third selective etching treatment so as to leave the third conductive material layer so as to cover the tunnel junction portion and the exposed portion of the antiferromagnetic layer according to a desired electrode pattern. A step of forming a second hard mask made of the remaining portion of the third conductive material layer, and a selective mask of the second hard mask in the stack of the first conductive material layer and the antiferromagnetic layer. Forming a first electrode layer consisting of the remaining portion of the laminated layer under the magnetic tunnel junction by performing a fourth selective etching treatment, and during or after the formation of the first electrode layer. The magnetic tunnel junction Preparation of the magnetic tunnel junction element and a step to leave at least the first hard mask as the second electrode layer to remove the second hard mask from the end of the tunnel barrier layer in. 6. A step of forming a magnetic tunnel junction stack on one insulating main surface of a substrate through a first conductive material layer,
An antiferromagnetic layer and a first antiferromagnetic layer are formed on the first conductive material layer in order from the bottom.
The magnetic layer, the tunnel barrier layer, and the second magnetic layer, or a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an antiferromagnetic layer in order from the bottom on the first conductive material layer. To form the magnetic tunnel junction stack, a step of covering the magnetic tunnel junction stack to form a second conductive material layer, and the step of covering the magnetic tunnel junction stack according to a desired element pattern. Forming a first hard mask made of the remaining portion of the second conductive material layer by subjecting the second conductive material layer to a first selective etching treatment so that the second conductive material layer remains. Subjecting the magnetic tunnel junction stack to a second selective etching process using the first hard mask as a selective mask to etch the magnetic tunnel junction stack until reaching the first conductive material layer. A step of forming a magnetic tunnel junction formed of the remaining portion of the magnetic tunnel junction stack; and a third step of covering the first hard mask, the magnetic tunnel junction and the exposed portion of the first conductive material layer. Forming a conductive material layer, and the third conductive material layer so as to cover the first hard mask, the magnetic tunnel junction, and the exposed portion of the first conductive material layer according to a desired electrode pattern. Forming a second hard mask composed of the remaining portion of the third conductive material layer by subjecting the third conductive material layer to a third selective etching treatment so as to leave the first conductive layer. The material layer is subjected to a fourth selective etching process using the second hard mask as a selective mask, so that the first electrode layer made of the remaining portion of the first conductive material layer is formed under the magnetic tunnel junction. Form Removing the second hard mask from the end of the tunnel barrier layer at the magnetic tunnel junction during or after the formation of the first electrode layer, and at least removing the first hard mask from the second hard mask. A method of manufacturing a magnetic tunnel junction element, which comprises a step of remaining as an electrode layer. 7. A substrate having an insulating main surface, and a magnetic tunnel junction element formed on the main surface, wherein a first conductive material layer and an antiferromagnetic layer are formed on the main surface in order from the bottom. Layer, a first magnetic layer, a tunnel barrier layer, a second magnetic layer and a second conductive material layer, or a first conductive material layer, a first magnetic layer, and a tunnel on the one main surface in order from the bottom. Barrier layer,
A layer formed by stacking a second magnetic layer, an antiferromagnetic layer and a second conductive material layer, and a layer formed on the one main surface and having a layer structure substantially the same as that of the magnetic tunnel junction element. A magnetic tunnel junction device comprising a wiring layer made of a structure, wherein the wiring layer is used as a wiring layer for the magnetic tunnel junction element or a wiring layer for a circuit element formed on the substrate. 8. The magnetic according to claim 7, further comprising a conductive layer formed so as to short-circuit two magnetic layers sandwiching a tunnel barrier layer in the laminated structure so as to cover at least a side portion of the laminated structure. Tunnel junction device. 9. A substrate having an insulative main surface, and a magnetic tunnel junction element formed on the one main surface, wherein a first conductive material layer and an antiferromagnetic material are formed on the main surface in order from the bottom. Layer, a first magnetic layer, a tunnel barrier layer, a second magnetic layer and a second conductive material layer, or a first conductive material layer, a first magnetic layer, and a tunnel on the one main surface in order from the bottom. Barrier layer,
An auxiliary layer formed by stacking a second magnetic layer, an antiferromagnetic layer, and a second conductive material layer, and an auxiliary layer formed on the one main surface and having substantially the same laminated structure as the magnetic tunnel junction element. A stacking layer and an insulating film formed on the one main surface so as to cover the magnetic tunnel junction element and the auxiliary stacking layer, and the flattening layer or the insulating film for flattening the insulating film of the auxiliary stacking layer. Magnetic tunnel junction device used as a peeling prevention layer for preventing peeling of the metal.